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path: root/drivers/net/bnx2x.h
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-rw-r--r--drivers/net/bnx2x.h1585
1 files changed, 828 insertions, 757 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 8e68d06510a6..4bf4f7b205f2 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -14,39 +14,46 @@
14#ifndef BNX2X_H 14#ifndef BNX2X_H
15#define BNX2X_H 15#define BNX2X_H
16 16
17/* compilation time flags */
18
19/* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21/* #define BNX2X_STOP_ON_ERROR */
22
17/* error/debug prints */ 23/* error/debug prints */
18 24
19#define DRV_MODULE_NAME "bnx2x" 25#define DRV_MODULE_NAME "bnx2x"
20#define PFX DRV_MODULE_NAME ": " 26#define PFX DRV_MODULE_NAME ": "
21 27
22/* for messages that are currently off */ 28/* for messages that are currently off */
23#define BNX2X_MSG_OFF 0 29#define BNX2X_MSG_OFF 0
24#define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */ 30#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
25#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */ 31#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
26#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */ 32#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
27#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */ 33#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
28#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ 34#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
29#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ 35#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
30 36
31#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ 37#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
32 38
33/* regular debug print */ 39/* regular debug print */
34#define DP(__mask, __fmt, __args...) do { \ 40#define DP(__mask, __fmt, __args...) do { \
35 if (bp->msglevel & (__mask)) \ 41 if (bp->msglevel & (__mask)) \
36 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \ 42 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
37 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ 43 bp->dev?(bp->dev->name):"?", ##__args); \
38 } while (0) 44 } while (0)
39 45
40/* for errors (never masked) */ 46/* errors debug print */
41#define BNX2X_ERR(__fmt, __args...) do { \ 47#define BNX2X_DBG_ERR(__fmt, __args...) do { \
42 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \ 48 if (bp->msglevel & NETIF_MSG_PROBE) \
43 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ 49 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
50 bp->dev?(bp->dev->name):"?", ##__args); \
44 } while (0) 51 } while (0)
45 52
46/* for logging (never masked) */ 53/* for errors (never masked) */
47#define BNX2X_LOG(__fmt, __args...) do { \ 54#define BNX2X_ERR(__fmt, __args...) do { \
48 printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \ 55 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
49 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ 56 bp->dev?(bp->dev->name):"?", ##__args); \
50 } while (0) 57 } while (0)
51 58
52/* before we have a dev->name use dev_info() */ 59/* before we have a dev->name use dev_info() */
@@ -60,7 +67,7 @@
60#define bnx2x_panic() do { \ 67#define bnx2x_panic() do { \
61 bp->panic = 1; \ 68 bp->panic = 1; \
62 BNX2X_ERR("driver assert\n"); \ 69 BNX2X_ERR("driver assert\n"); \
63 bnx2x_disable_int(bp); \ 70 bnx2x_int_disable(bp); \
64 bnx2x_panic_dump(bp); \ 71 bnx2x_panic_dump(bp); \
65 } while (0) 72 } while (0)
66#else 73#else
@@ -71,164 +78,412 @@
71#endif 78#endif
72 79
73 80
74#define U64_LO(x) (((u64)x) & 0xffffffff) 81#ifdef NETIF_F_HW_VLAN_TX
75#define U64_HI(x) (((u64)x) >> 32) 82#define BCM_VLAN 1
76#define HILO_U64(hi, lo) (((u64)hi << 32) + lo) 83#endif
84
77 85
86#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
87#define U64_HI(x) (u32)(((u64)(x)) >> 32)
88#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
78 89
79#define REG_ADDR(bp, offset) (bp->regview + offset)
80 90
81#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 91#define REG_ADDR(bp, offset) (bp->regview + offset)
82#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
83#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
84 92
85#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 93#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
94#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
95#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
96
97#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
86#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 98#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
87#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 99#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
88#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val) 100#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
101
102#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
103#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
89 104
90#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 105#define REG_RD_DMAE(bp, offset, valp, len32) \
91#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 106 do { \
107 bnx2x_read_dmae(bp, offset, len32);\
108 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
109 } while (0)
92 110
93#define REG_WR_DMAE(bp, offset, val, len32) \ 111#define REG_WR_DMAE(bp, offset, valp, len32) \
94 do { \ 112 do { \
95 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \ 113 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
96 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 114 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
97 offset, len32); \ 115 offset, len32); \
98 } while (0) 116 } while (0)
99 117
100#define SHMEM_RD(bp, type) \ 118#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
101 REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type)) 119 offsetof(struct shmem_region, field))
102#define SHMEM_WR(bp, type, val) \ 120#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
103 REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val) 121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
104 122
105#define NIG_WR(reg, val) REG_WR(bp, reg, val) 123#define NIG_WR(reg, val) REG_WR(bp, reg, val)
106#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) 124#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
107#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val) 125#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
108 126
109 127
110#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++) 128#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
111 129
112#define for_each_nondefault_queue(bp, var) \ 130#define for_each_nondefault_queue(bp, var) \
113 for (var = 1; var < bp->num_queues; var++) 131 for (var = 1; var < bp->num_queues; var++)
114#define is_multi(bp) (bp->num_queues > 1) 132#define is_multi(bp) (bp->num_queues > 1)
115 133
116 134
117struct regp { 135/* fast path */
118 u32 lo; 136
119 u32 hi; 137struct sw_rx_bd {
138 struct sk_buff *skb;
139 DECLARE_PCI_UNMAP_ADDR(mapping)
140};
141
142struct sw_tx_bd {
143 struct sk_buff *skb;
144 u16 first_bd;
120}; 145};
121 146
122struct bmac_stats { 147struct sw_rx_page {
123 struct regp tx_gtpkt; 148 struct page *page;
124 struct regp tx_gtxpf; 149 DECLARE_PCI_UNMAP_ADDR(mapping)
125 struct regp tx_gtfcs;
126 struct regp tx_gtmca;
127 struct regp tx_gtgca;
128 struct regp tx_gtfrg;
129 struct regp tx_gtovr;
130 struct regp tx_gt64;
131 struct regp tx_gt127;
132 struct regp tx_gt255; /* 10 */
133 struct regp tx_gt511;
134 struct regp tx_gt1023;
135 struct regp tx_gt1518;
136 struct regp tx_gt2047;
137 struct regp tx_gt4095;
138 struct regp tx_gt9216;
139 struct regp tx_gt16383;
140 struct regp tx_gtmax;
141 struct regp tx_gtufl;
142 struct regp tx_gterr; /* 20 */
143 struct regp tx_gtbyt;
144
145 struct regp rx_gr64;
146 struct regp rx_gr127;
147 struct regp rx_gr255;
148 struct regp rx_gr511;
149 struct regp rx_gr1023;
150 struct regp rx_gr1518;
151 struct regp rx_gr2047;
152 struct regp rx_gr4095;
153 struct regp rx_gr9216; /* 30 */
154 struct regp rx_gr16383;
155 struct regp rx_grmax;
156 struct regp rx_grpkt;
157 struct regp rx_grfcs;
158 struct regp rx_grmca;
159 struct regp rx_grbca;
160 struct regp rx_grxcf;
161 struct regp rx_grxpf;
162 struct regp rx_grxuo;
163 struct regp rx_grjbr; /* 40 */
164 struct regp rx_grovr;
165 struct regp rx_grflr;
166 struct regp rx_grmeg;
167 struct regp rx_grmeb;
168 struct regp rx_grbyt;
169 struct regp rx_grund;
170 struct regp rx_grfrg;
171 struct regp rx_grerb;
172 struct regp rx_grfre;
173 struct regp rx_gripj; /* 50 */
174}; 150};
175 151
176struct emac_stats { 152
177 u32 rx_ifhcinoctets ; 153/* MC hsi */
178 u32 rx_ifhcinbadoctets ; 154#define BCM_PAGE_SHIFT 12
179 u32 rx_etherstatsfragments ; 155#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
180 u32 rx_ifhcinucastpkts ; 156#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
181 u32 rx_ifhcinmulticastpkts ; 157#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
182 u32 rx_ifhcinbroadcastpkts ; 158
183 u32 rx_dot3statsfcserrors ; 159#define PAGES_PER_SGE_SHIFT 0
184 u32 rx_dot3statsalignmenterrors ; 160#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
185 u32 rx_dot3statscarriersenseerrors ; 161
186 u32 rx_xonpauseframesreceived ; /* 10 */ 162/* SGE ring related macros */
187 u32 rx_xoffpauseframesreceived ; 163#define NUM_RX_SGE_PAGES 2
188 u32 rx_maccontrolframesreceived ; 164#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
189 u32 rx_xoffstateentered ; 165#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
190 u32 rx_dot3statsframestoolong ; 166/* RX_SGE_CNT is promissed to be a power of 2 */
191 u32 rx_etherstatsjabbers ; 167#define RX_SGE_MASK (RX_SGE_CNT - 1)
192 u32 rx_etherstatsundersizepkts ; 168#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
193 u32 rx_etherstatspkts64octets ; 169#define MAX_RX_SGE (NUM_RX_SGE - 1)
194 u32 rx_etherstatspkts65octetsto127octets ; 170#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
195 u32 rx_etherstatspkts128octetsto255octets ; 171 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
196 u32 rx_etherstatspkts256octetsto511octets ; /* 20 */ 172#define RX_SGE(x) ((x) & MAX_RX_SGE)
197 u32 rx_etherstatspkts512octetsto1023octets ; 173
198 u32 rx_etherstatspkts1024octetsto1522octets; 174/* SGE producer mask related macros */
199 u32 rx_etherstatspktsover1522octets ; 175/* Number of bits in one sge_mask array element */
200 176#define RX_SGE_MASK_ELEM_SZ 64
201 u32 rx_falsecarriererrors ; 177#define RX_SGE_MASK_ELEM_SHIFT 6
202 178#define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
203 u32 tx_ifhcoutoctets ; 179
204 u32 tx_ifhcoutbadoctets ; 180/* Creates a bitmask of all ones in less significant bits.
205 u32 tx_etherstatscollisions ; 181 idx - index of the most significant bit in the created mask */
206 u32 tx_outxonsent ; 182#define RX_SGE_ONES_MASK(idx) \
207 u32 tx_outxoffsent ; 183 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
208 u32 tx_flowcontroldone ; /* 30 */ 184#define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
209 u32 tx_dot3statssinglecollisionframes ; 185
210 u32 tx_dot3statsmultiplecollisionframes ; 186/* Number of u64 elements in SGE mask array */
211 u32 tx_dot3statsdeferredtransmissions ; 187#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
212 u32 tx_dot3statsexcessivecollisions ; 188 RX_SGE_MASK_ELEM_SZ)
213 u32 tx_dot3statslatecollisions ; 189#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
214 u32 tx_ifhcoutucastpkts ; 190#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
215 u32 tx_ifhcoutmulticastpkts ; 191
216 u32 tx_ifhcoutbroadcastpkts ; 192
217 u32 tx_etherstatspkts64octets ; 193struct bnx2x_fastpath {
218 u32 tx_etherstatspkts65octetsto127octets ; /* 40 */ 194
219 u32 tx_etherstatspkts128octetsto255octets ; 195 struct napi_struct napi;
220 u32 tx_etherstatspkts256octetsto511octets ; 196
221 u32 tx_etherstatspkts512octetsto1023octets ; 197 struct host_status_block *status_blk;
222 u32 tx_etherstatspkts1024octetsto1522octet ; 198 dma_addr_t status_blk_mapping;
223 u32 tx_etherstatspktsover1522octets ; 199
224 u32 tx_dot3statsinternalmactransmiterrors ; /* 46 */ 200 struct eth_tx_db_data *hw_tx_prods;
201 dma_addr_t tx_prods_mapping;
202
203 struct sw_tx_bd *tx_buf_ring;
204
205 struct eth_tx_bd *tx_desc_ring;
206 dma_addr_t tx_desc_mapping;
207
208 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
209 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
210
211 struct eth_rx_bd *rx_desc_ring;
212 dma_addr_t rx_desc_mapping;
213
214 union eth_rx_cqe *rx_comp_ring;
215 dma_addr_t rx_comp_mapping;
216
217 /* SGE ring */
218 struct eth_rx_sge *rx_sge_ring;
219 dma_addr_t rx_sge_mapping;
220
221 u64 sge_mask[RX_SGE_MASK_LEN];
222
223 int state;
224#define BNX2X_FP_STATE_CLOSED 0
225#define BNX2X_FP_STATE_IRQ 0x80000
226#define BNX2X_FP_STATE_OPENING 0x90000
227#define BNX2X_FP_STATE_OPEN 0xa0000
228#define BNX2X_FP_STATE_HALTING 0xb0000
229#define BNX2X_FP_STATE_HALTED 0xc0000
230
231 u8 index; /* number in fp array */
232 u8 cl_id; /* eth client id */
233 u8 sb_id; /* status block number in HW */
234#define FP_IDX(fp) (fp->index)
235#define FP_CL_ID(fp) (fp->cl_id)
236#define BP_CL_ID(bp) (bp->fp[0].cl_id)
237#define FP_SB_ID(fp) (fp->sb_id)
238#define CNIC_SB_ID 0
239
240 u16 tx_pkt_prod;
241 u16 tx_pkt_cons;
242 u16 tx_bd_prod;
243 u16 tx_bd_cons;
244 u16 *tx_cons_sb;
245
246 u16 fp_c_idx;
247 u16 fp_u_idx;
248
249 u16 rx_bd_prod;
250 u16 rx_bd_cons;
251 u16 rx_comp_prod;
252 u16 rx_comp_cons;
253 u16 rx_sge_prod;
254 /* The last maximal completed SGE */
255 u16 last_max_sge;
256 u16 *rx_cons_sb;
257 u16 *rx_bd_cons_sb;
258
259 unsigned long tx_pkt,
260 rx_pkt,
261 rx_calls,
262 rx_alloc_failed;
263 /* TPA related */
264 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
265 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
266#define BNX2X_TPA_START 1
267#define BNX2X_TPA_STOP 2
268 u8 disable_tpa;
269#ifdef BNX2X_STOP_ON_ERROR
270 u64 tpa_queue_used;
271#endif
272
273 struct bnx2x *bp; /* parent */
225}; 274};
226 275
227union mac_stats { 276#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
228 struct emac_stats emac; 277
229 struct bmac_stats bmac; 278
279/* MC hsi */
280#define MAX_FETCH_BD 13 /* HW max BDs per packet */
281#define RX_COPY_THRESH 92
282
283#define NUM_TX_RINGS 16
284#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
285#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
286#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
287#define MAX_TX_BD (NUM_TX_BD - 1)
288#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
289#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
290 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
291#define TX_BD(x) ((x) & MAX_TX_BD)
292#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
293
294/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
295#define NUM_RX_RINGS 8
296#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
297#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
298#define RX_DESC_MASK (RX_DESC_CNT - 1)
299#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
300#define MAX_RX_BD (NUM_RX_BD - 1)
301#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
302#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
303 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
304#define RX_BD(x) ((x) & MAX_RX_BD)
305
306/* As long as CQE is 4 times bigger than BD entry we have to allocate
307 4 times more pages for CQ ring in order to keep it balanced with
308 BD ring */
309#define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
310#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
311#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
312#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
313#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
314#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
315#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
316 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
317#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
318
319
320/* This is needed for determening of last_max */
321#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
322
323#define __SGE_MASK_SET_BIT(el, bit) \
324 do { \
325 el = ((el) | ((u64)0x1 << (bit))); \
326 } while (0)
327
328#define __SGE_MASK_CLEAR_BIT(el, bit) \
329 do { \
330 el = ((el) & (~((u64)0x1 << (bit)))); \
331 } while (0)
332
333#define SGE_MASK_SET_BIT(fp, idx) \
334 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
335 ((idx) & RX_SGE_MASK_ELEM_MASK))
336
337#define SGE_MASK_CLEAR_BIT(fp, idx) \
338 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
339 ((idx) & RX_SGE_MASK_ELEM_MASK))
340
341
342/* used on a CID received from the HW */
343#define SW_CID(x) (le32_to_cpu(x) & \
344 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
345#define CQE_CMD(x) (le32_to_cpu(x) >> \
346 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
347
348#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
349 le32_to_cpu((bd)->addr_lo))
350#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
351
352
353#define DPM_TRIGER_TYPE 0x40
354#define DOORBELL(bp, cid, val) \
355 do { \
356 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
357 DPM_TRIGER_TYPE); \
358 } while (0)
359
360
361/* TX CSUM helpers */
362#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
363 skb->csum_offset)
364#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
365 skb->csum_offset))
366
367#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
368
369#define XMIT_PLAIN 0
370#define XMIT_CSUM_V4 0x1
371#define XMIT_CSUM_V6 0x2
372#define XMIT_CSUM_TCP 0x4
373#define XMIT_GSO_V4 0x8
374#define XMIT_GSO_V6 0x10
375
376#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
377#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
378
379
380/* stuff added to make the code fit 80Col */
381
382#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
383
384#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
385#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
386#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
387 (TPA_TYPE_START | TPA_TYPE_END))
388
389#define BNX2X_RX_SUM_OK(cqe) \
390 (!(cqe->fast_path_cqe.status_flags & \
391 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
392 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
393
394#define BNX2X_RX_SUM_FIX(cqe) \
395 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
396 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
397 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
398
399#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
400 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
401 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
402
403
404#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
405#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
406
407#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
408#define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
409#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
410
411#define BNX2X_RX_SB_INDEX \
412 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
413
414#define BNX2X_RX_SB_BD_INDEX \
415 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
416
417#define BNX2X_RX_SB_INDEX_NUM \
418 (((U_SB_ETH_RX_CQ_INDEX << \
419 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
420 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
421 ((U_SB_ETH_RX_BD_INDEX << \
422 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
423 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
424
425#define BNX2X_TX_SB_INDEX \
426 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
427
428
429/* end of fast path */
430
431/* common */
432
433struct bnx2x_common {
434
435 u32 chip_id;
436/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
437#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
438
439#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
440#define CHIP_NUM_57710 0x164e
441#define CHIP_NUM_57711 0x164f
442#define CHIP_NUM_57711E 0x1650
443#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
444#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
445#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
446#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
447 CHIP_IS_57711E(bp))
448#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
449
450#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
451#define CHIP_REV_Ax 0x00000000
452/* assume maximum 5 revisions */
453#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
454/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
455#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
456 !(CHIP_REV(bp) & 0x00001000))
457/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
458#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
459 (CHIP_REV(bp) & 0x00001000))
460
461#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
462 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
463
464#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
465#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
466
467 int flash_size;
468#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
469#define NVRAM_TIMEOUT_COUNT 30000
470#define NVRAM_PAGE_SIZE 256
471
472 u32 shmem_base;
473
474 u32 hw_config;
475 u32 board;
476
477 u32 bc_ver;
478
479 char *name;
230}; 480};
231 481
482
483/* end of common */
484
485/* port */
486
232struct nig_stats { 487struct nig_stats {
233 u32 brb_discard; 488 u32 brb_discard;
234 u32 brb_packet; 489 u32 brb_packet;
@@ -244,13 +499,53 @@ struct nig_stats {
244 u32 pbf_octets; 499 u32 pbf_octets;
245 u32 pbf_packet; 500 u32 pbf_packet;
246 u32 safc_inp; 501 u32 safc_inp;
247 u32 done; 502 u32 egress_mac_pkt0_lo;
248 u32 pad; 503 u32 egress_mac_pkt0_hi;
504 u32 egress_mac_pkt1_lo;
505 u32 egress_mac_pkt1_hi;
506};
507
508struct bnx2x_port {
509 u32 pmf;
510
511 u32 link_config;
512
513 u32 supported;
514/* link settings - missing defines */
515#define SUPPORTED_2500baseX_Full (1 << 15)
516
517 u32 advertising;
518/* link settings - missing defines */
519#define ADVERTISED_2500baseX_Full (1 << 15)
520
521 u32 phy_addr;
522
523 /* used to synchronize phy accesses */
524 struct mutex phy_mutex;
525
526 u32 port_stx;
527
528 struct nig_stats old_nig_stats;
529};
530
531/* end of port */
532
533
534enum bnx2x_stats_event {
535 STATS_EVENT_PMF = 0,
536 STATS_EVENT_LINK_UP,
537 STATS_EVENT_UPDATE,
538 STATS_EVENT_STOP,
539 STATS_EVENT_MAX
540};
541
542enum bnx2x_stats_state {
543 STATS_STATE_DISABLED = 0,
544 STATS_STATE_ENABLED,
545 STATS_STATE_MAX
249}; 546};
250 547
251struct bnx2x_eth_stats { 548struct bnx2x_eth_stats {
252 u32 pad; /* to make long counters u64 aligned */
253 u32 mac_stx_start;
254 u32 total_bytes_received_hi; 549 u32 total_bytes_received_hi;
255 u32 total_bytes_received_lo; 550 u32 total_bytes_received_lo;
256 u32 total_bytes_transmitted_hi; 551 u32 total_bytes_transmitted_hi;
@@ -267,97 +562,117 @@ struct bnx2x_eth_stats {
267 u32 total_multicast_packets_transmitted_lo; 562 u32 total_multicast_packets_transmitted_lo;
268 u32 total_broadcast_packets_transmitted_hi; 563 u32 total_broadcast_packets_transmitted_hi;
269 u32 total_broadcast_packets_transmitted_lo; 564 u32 total_broadcast_packets_transmitted_lo;
270 u32 crc_receive_errors;
271 u32 alignment_errors;
272 u32 false_carrier_detections;
273 u32 runt_packets_received;
274 u32 jabber_packets_received;
275 u32 pause_xon_frames_received;
276 u32 pause_xoff_frames_received;
277 u32 pause_xon_frames_transmitted;
278 u32 pause_xoff_frames_transmitted;
279 u32 single_collision_transmit_frames;
280 u32 multiple_collision_transmit_frames;
281 u32 late_collision_frames;
282 u32 excessive_collision_frames;
283 u32 control_frames_received;
284 u32 frames_received_64_bytes;
285 u32 frames_received_65_127_bytes;
286 u32 frames_received_128_255_bytes;
287 u32 frames_received_256_511_bytes;
288 u32 frames_received_512_1023_bytes;
289 u32 frames_received_1024_1522_bytes;
290 u32 frames_received_1523_9022_bytes;
291 u32 frames_transmitted_64_bytes;
292 u32 frames_transmitted_65_127_bytes;
293 u32 frames_transmitted_128_255_bytes;
294 u32 frames_transmitted_256_511_bytes;
295 u32 frames_transmitted_512_1023_bytes;
296 u32 frames_transmitted_1024_1522_bytes;
297 u32 frames_transmitted_1523_9022_bytes;
298 u32 valid_bytes_received_hi; 565 u32 valid_bytes_received_hi;
299 u32 valid_bytes_received_lo; 566 u32 valid_bytes_received_lo;
300 u32 error_runt_packets_received; 567
301 u32 error_jabber_packets_received; 568 u32 error_bytes_received_hi;
302 u32 mac_stx_end; 569 u32 error_bytes_received_lo;
303 570
304 u32 pad2; 571 u32 rx_stat_ifhcinbadoctets_hi;
305 u32 stat_IfHCInBadOctets_hi; 572 u32 rx_stat_ifhcinbadoctets_lo;
306 u32 stat_IfHCInBadOctets_lo; 573 u32 tx_stat_ifhcoutbadoctets_hi;
307 u32 stat_IfHCOutBadOctets_hi; 574 u32 tx_stat_ifhcoutbadoctets_lo;
308 u32 stat_IfHCOutBadOctets_lo; 575 u32 rx_stat_dot3statsfcserrors_hi;
309 u32 stat_Dot3statsFramesTooLong; 576 u32 rx_stat_dot3statsfcserrors_lo;
310 u32 stat_Dot3statsInternalMacTransmitErrors; 577 u32 rx_stat_dot3statsalignmenterrors_hi;
311 u32 stat_Dot3StatsCarrierSenseErrors; 578 u32 rx_stat_dot3statsalignmenterrors_lo;
312 u32 stat_Dot3StatsDeferredTransmissions; 579 u32 rx_stat_dot3statscarriersenseerrors_hi;
313 u32 stat_FlowControlDone; 580 u32 rx_stat_dot3statscarriersenseerrors_lo;
314 u32 stat_XoffStateEntered; 581 u32 rx_stat_falsecarriererrors_hi;
315 582 u32 rx_stat_falsecarriererrors_lo;
316 u32 x_total_sent_bytes_hi; 583 u32 rx_stat_etherstatsundersizepkts_hi;
317 u32 x_total_sent_bytes_lo; 584 u32 rx_stat_etherstatsundersizepkts_lo;
318 u32 x_total_sent_pkts; 585 u32 rx_stat_dot3statsframestoolong_hi;
319 586 u32 rx_stat_dot3statsframestoolong_lo;
320 u32 t_rcv_unicast_bytes_hi; 587 u32 rx_stat_etherstatsfragments_hi;
321 u32 t_rcv_unicast_bytes_lo; 588 u32 rx_stat_etherstatsfragments_lo;
322 u32 t_rcv_broadcast_bytes_hi; 589 u32 rx_stat_etherstatsjabbers_hi;
323 u32 t_rcv_broadcast_bytes_lo; 590 u32 rx_stat_etherstatsjabbers_lo;
324 u32 t_rcv_multicast_bytes_hi; 591 u32 rx_stat_maccontrolframesreceived_hi;
325 u32 t_rcv_multicast_bytes_lo; 592 u32 rx_stat_maccontrolframesreceived_lo;
326 u32 t_total_rcv_pkt; 593 u32 rx_stat_bmac_xpf_hi;
327 594 u32 rx_stat_bmac_xpf_lo;
328 u32 checksum_discard; 595 u32 rx_stat_bmac_xcf_hi;
329 u32 packets_too_big_discard; 596 u32 rx_stat_bmac_xcf_lo;
597 u32 rx_stat_xoffstateentered_hi;
598 u32 rx_stat_xoffstateentered_lo;
599 u32 rx_stat_xonpauseframesreceived_hi;
600 u32 rx_stat_xonpauseframesreceived_lo;
601 u32 rx_stat_xoffpauseframesreceived_hi;
602 u32 rx_stat_xoffpauseframesreceived_lo;
603 u32 tx_stat_outxonsent_hi;
604 u32 tx_stat_outxonsent_lo;
605 u32 tx_stat_outxoffsent_hi;
606 u32 tx_stat_outxoffsent_lo;
607 u32 tx_stat_flowcontroldone_hi;
608 u32 tx_stat_flowcontroldone_lo;
609 u32 tx_stat_etherstatscollisions_hi;
610 u32 tx_stat_etherstatscollisions_lo;
611 u32 tx_stat_dot3statssinglecollisionframes_hi;
612 u32 tx_stat_dot3statssinglecollisionframes_lo;
613 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
614 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
615 u32 tx_stat_dot3statsdeferredtransmissions_hi;
616 u32 tx_stat_dot3statsdeferredtransmissions_lo;
617 u32 tx_stat_dot3statsexcessivecollisions_hi;
618 u32 tx_stat_dot3statsexcessivecollisions_lo;
619 u32 tx_stat_dot3statslatecollisions_hi;
620 u32 tx_stat_dot3statslatecollisions_lo;
621 u32 tx_stat_etherstatspkts64octets_hi;
622 u32 tx_stat_etherstatspkts64octets_lo;
623 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
624 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
625 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
626 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
627 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
628 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
629 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
630 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
631 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
632 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
633 u32 tx_stat_etherstatspktsover1522octets_hi;
634 u32 tx_stat_etherstatspktsover1522octets_lo;
635 u32 tx_stat_bmac_2047_hi;
636 u32 tx_stat_bmac_2047_lo;
637 u32 tx_stat_bmac_4095_hi;
638 u32 tx_stat_bmac_4095_lo;
639 u32 tx_stat_bmac_9216_hi;
640 u32 tx_stat_bmac_9216_lo;
641 u32 tx_stat_bmac_16383_hi;
642 u32 tx_stat_bmac_16383_lo;
643 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
644 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
645 u32 tx_stat_bmac_ufl_hi;
646 u32 tx_stat_bmac_ufl_lo;
647
648 u32 brb_drop_hi;
649 u32 brb_drop_lo;
650
651 u32 jabber_packets_received;
652
653 u32 etherstatspkts1024octetsto1522octets_hi;
654 u32 etherstatspkts1024octetsto1522octets_lo;
655 u32 etherstatspktsover1522octets_hi;
656 u32 etherstatspktsover1522octets_lo;
657
330 u32 no_buff_discard; 658 u32 no_buff_discard;
331 u32 ttl0_discard; 659
332 u32 mac_discard;
333 u32 mac_filter_discard; 660 u32 mac_filter_discard;
334 u32 xxoverflow_discard; 661 u32 xxoverflow_discard;
335 u32 brb_truncate_discard; 662 u32 brb_truncate_discard;
663 u32 mac_discard;
336 664
337 u32 brb_discard;
338 u32 brb_packet;
339 u32 brb_truncate;
340 u32 flow_ctrl_discard;
341 u32 flow_ctrl_octets;
342 u32 flow_ctrl_packet;
343 u32 mng_discard;
344 u32 mng_octet_inp;
345 u32 mng_octet_out;
346 u32 mng_packet_inp;
347 u32 mng_packet_out;
348 u32 pbf_octets;
349 u32 pbf_packet;
350 u32 safc_inp;
351 u32 driver_xoff; 665 u32 driver_xoff;
352 u32 number_of_bugs_found_in_stats_spec; /* just kidding */
353}; 666};
354 667
355#define MAC_STX_NA 0xffffffff 668#define STATS_OFFSET32(stat_name) \
669 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
670
356 671
357#ifdef BNX2X_MULTI 672#ifdef BNX2X_MULTI
358#define MAX_CONTEXT 16 673#define MAX_CONTEXT 16
359#else 674#else
360#define MAX_CONTEXT 1 675#define MAX_CONTEXT 1
361#endif 676#endif
362 677
363union cdu_context { 678union cdu_context {
@@ -365,345 +680,191 @@ union cdu_context {
365 char pad[1024]; 680 char pad[1024];
366}; 681};
367 682
368#define MAX_DMAE_C 5 683#define MAX_DMAE_C 8
369 684
370/* DMA memory not used in fastpath */ 685/* DMA memory not used in fastpath */
371struct bnx2x_slowpath { 686struct bnx2x_slowpath {
372 union cdu_context context[MAX_CONTEXT]; 687 union cdu_context context[MAX_CONTEXT];
373 struct eth_stats_query fw_stats; 688 struct eth_stats_query fw_stats;
374 struct mac_configuration_cmd mac_config; 689 struct mac_configuration_cmd mac_config;
375 struct mac_configuration_cmd mcast_config; 690 struct mac_configuration_cmd mcast_config;
376 691
377 /* used by dmae command executer */ 692 /* used by dmae command executer */
378 struct dmae_command dmae[MAX_DMAE_C]; 693 struct dmae_command dmae[MAX_DMAE_C];
379 694
380 union mac_stats mac_stats; 695 u32 stats_comp;
381 struct nig_stats nig; 696 union mac_stats mac_stats;
382 struct bnx2x_eth_stats eth_stats; 697 struct nig_stats nig_stats;
698 struct host_port_stats port_stats;
699 struct host_func_stats func_stats;
383 700
384 u32 wb_comp; 701 u32 wb_comp;
385#define BNX2X_WB_COMP_VAL 0xe0d0d0ae 702 u32 wb_data[4];
386 u32 wb_data[4];
387}; 703};
388 704
389#define bnx2x_sp(bp, var) (&bp->slowpath->var) 705#define bnx2x_sp(bp, var) (&bp->slowpath->var)
390#define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL)
391#define bnx2x_sp_mapping(bp, var) \ 706#define bnx2x_sp_mapping(bp, var) \
392 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 707 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
393 708
394 709
395struct sw_rx_bd {
396 struct sk_buff *skb;
397 DECLARE_PCI_UNMAP_ADDR(mapping)
398};
399
400struct sw_tx_bd {
401 struct sk_buff *skb;
402 u16 first_bd;
403};
404
405struct bnx2x_fastpath {
406
407 struct napi_struct napi;
408
409 struct host_status_block *status_blk;
410 dma_addr_t status_blk_mapping;
411
412 struct eth_tx_db_data *hw_tx_prods;
413 dma_addr_t tx_prods_mapping;
414
415 struct sw_tx_bd *tx_buf_ring;
416
417 struct eth_tx_bd *tx_desc_ring;
418 dma_addr_t tx_desc_mapping;
419
420 struct sw_rx_bd *rx_buf_ring;
421
422 struct eth_rx_bd *rx_desc_ring;
423 dma_addr_t rx_desc_mapping;
424
425 union eth_rx_cqe *rx_comp_ring;
426 dma_addr_t rx_comp_mapping;
427
428 int state;
429#define BNX2X_FP_STATE_CLOSED 0
430#define BNX2X_FP_STATE_IRQ 0x80000
431#define BNX2X_FP_STATE_OPENING 0x90000
432#define BNX2X_FP_STATE_OPEN 0xa0000
433#define BNX2X_FP_STATE_HALTING 0xb0000
434#define BNX2X_FP_STATE_HALTED 0xc0000
435
436 int index;
437
438 u16 tx_pkt_prod;
439 u16 tx_pkt_cons;
440 u16 tx_bd_prod;
441 u16 tx_bd_cons;
442 u16 *tx_cons_sb;
443
444 u16 fp_c_idx;
445 u16 fp_u_idx;
446
447 u16 rx_bd_prod;
448 u16 rx_bd_cons;
449 u16 rx_comp_prod;
450 u16 rx_comp_cons;
451 u16 *rx_cons_sb;
452
453 unsigned long tx_pkt,
454 rx_pkt,
455 rx_calls;
456
457 struct bnx2x *bp; /* parent */
458};
459
460#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
461
462
463/* attn group wiring */ 710/* attn group wiring */
464#define MAX_DYNAMIC_ATTN_GRPS 8 711#define MAX_DYNAMIC_ATTN_GRPS 8
465 712
466struct attn_route { 713struct attn_route {
467 u32 sig[4]; 714 u32 sig[4];
468}; 715};
469 716
470struct bnx2x { 717struct bnx2x {
471 /* Fields used in the tx and intr/napi performance paths 718 /* Fields used in the tx and intr/napi performance paths
472 * are grouped together in the beginning of the structure 719 * are grouped together in the beginning of the structure
473 */ 720 */
474 struct bnx2x_fastpath *fp; 721 struct bnx2x_fastpath fp[MAX_CONTEXT];
475 void __iomem *regview; 722 void __iomem *regview;
476 void __iomem *doorbells; 723 void __iomem *doorbells;
724#define BNX2X_DB_SIZE (16*2048)
477 725
478 struct net_device *dev; 726 struct net_device *dev;
479 struct pci_dev *pdev; 727 struct pci_dev *pdev;
480 728
481 atomic_t intr_sem; 729 atomic_t intr_sem;
482 struct msix_entry msix_table[MAX_CONTEXT+1]; 730 struct msix_entry msix_table[MAX_CONTEXT+1];
483 731
484 int tx_ring_size; 732 int tx_ring_size;
485 733
486#ifdef BCM_VLAN 734#ifdef BCM_VLAN
487 struct vlan_group *vlgrp; 735 struct vlan_group *vlgrp;
488#endif 736#endif
489 737
490 u32 rx_csum; 738 u32 rx_csum;
491 u32 rx_offset; 739 u32 rx_offset;
492 u32 rx_buf_use_size; /* useable size */ 740 u32 rx_buf_use_size; /* useable size */
493 u32 rx_buf_size; /* with alignment */ 741 u32 rx_buf_size; /* with alignment */
494#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ 742#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
495#define ETH_MIN_PACKET_SIZE 60 743#define ETH_MIN_PACKET_SIZE 60
496#define ETH_MAX_PACKET_SIZE 1500 744#define ETH_MAX_PACKET_SIZE 1500
497#define ETH_MAX_JUMBO_PACKET_SIZE 9600 745#define ETH_MAX_JUMBO_PACKET_SIZE 9600
498 746
499 struct host_def_status_block *def_status_blk; 747 struct host_def_status_block *def_status_blk;
500#define DEF_SB_ID 16 748#define DEF_SB_ID 16
501 u16 def_c_idx; 749 u16 def_c_idx;
502 u16 def_u_idx; 750 u16 def_u_idx;
503 u16 def_t_idx; 751 u16 def_x_idx;
504 u16 def_x_idx; 752 u16 def_t_idx;
505 u16 def_att_idx; 753 u16 def_att_idx;
506 u32 attn_state; 754 u32 attn_state;
507 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 755 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
508 u32 aeu_mask; 756 u32 aeu_mask;
509 u32 nig_mask; 757 u32 nig_mask;
510 758
511 /* slow path ring */ 759 /* slow path ring */
512 struct eth_spe *spq; 760 struct eth_spe *spq;
513 dma_addr_t spq_mapping; 761 dma_addr_t spq_mapping;
514 u16 spq_prod_idx; 762 u16 spq_prod_idx;
515 struct eth_spe *spq_prod_bd; 763 struct eth_spe *spq_prod_bd;
516 struct eth_spe *spq_last_bd; 764 struct eth_spe *spq_last_bd;
517 u16 *dsb_sp_prod; 765 u16 *dsb_sp_prod;
518 u16 spq_left; /* serialize spq */ 766 u16 spq_left; /* serialize spq */
519 spinlock_t spq_lock; 767 /* used to synchronize spq accesses */
520 768 spinlock_t spq_lock;
521 /* Flag for marking that there is either 769
522 * STAT_QUERY or CFC DELETE ramrod pending 770 /* Flags for marking that there is a STAT_QUERY or
523 */ 771 SET_MAC ramrod pending */
524 u8 stat_pending; 772 u8 stats_pending;
525 773 u8 set_mac_pending;
526 /* End of fields used in the performance code paths */ 774
527 775 /* End of fileds used in the performance code paths */
528 int panic; 776
529 int msglevel; 777 int panic;
530 778 int msglevel;
531 u32 flags; 779
532#define PCIX_FLAG 1 780 u32 flags;
533#define PCI_32BIT_FLAG 2 781#define PCIX_FLAG 1
534#define ONE_TDMA_FLAG 4 /* no longer used */ 782#define PCI_32BIT_FLAG 2
535#define NO_WOL_FLAG 8 783#define ONE_TDMA_FLAG 4 /* no longer used */
536#define USING_DAC_FLAG 0x10 784#define NO_WOL_FLAG 8
537#define USING_MSIX_FLAG 0x20 785#define USING_DAC_FLAG 0x10
538#define ASF_ENABLE_FLAG 0x40 786#define USING_MSIX_FLAG 0x20
539 787#define ASF_ENABLE_FLAG 0x40
540 int port; 788#define TPA_ENABLE_FLAG 0x80
541 789#define NO_MCP_FLAG 0x100
542 int pm_cap; 790#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
543 int pcie_cap; 791
544 792 int func;
545 /* Used to synchronize phy accesses */ 793#define BP_PORT(bp) (bp->func % PORT_MAX)
546 spinlock_t phy_lock; 794#define BP_FUNC(bp) (bp->func)
547 795#define BP_E1HVN(bp) (bp->func >> 1)
548 struct work_struct reset_task; 796#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
549 struct work_struct sp_task; 797/* assorted E1HVN */
550 798#define IS_E1HMF(bp) (bp->e1hmf != 0)
551 struct timer_list timer; 799#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
552 int timer_interval; 800
553 int current_interval; 801 int pm_cap;
554 802 int pcie_cap;
555 u32 shmem_base; 803
556 804 struct work_struct sp_task;
557 u32 chip_id; 805 struct work_struct reset_task;
558/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 806
559#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) 807 struct timer_list timer;
560 808 int timer_interval;
561#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) 809 int current_interval;
562 810
563#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) 811 u16 fw_seq;
564#define CHIP_REV_Ax 0x00000000 812 u16 fw_drv_pulse_wr_seq;
565#define CHIP_REV_Bx 0x00001000 813 u32 func_stx;
566#define CHIP_REV_Cx 0x00002000 814
567#define CHIP_REV_EMUL 0x0000e000 815 struct link_params link_params;
568#define CHIP_REV_FPGA 0x0000f000 816 struct link_vars link_vars;
569#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \ 817
570 (CHIP_REV(bp) == CHIP_REV_FPGA)) 818 struct bnx2x_common common;
571 819 struct bnx2x_port port;
572#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) 820
573#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f) 821 u32 mf_config;
574 822 u16 e1hov;
575 u16 fw_seq; 823 u8 e1hmf;
576 u16 fw_drv_pulse_wr_seq;
577 u32 fw_mb;
578
579 u32 hw_config;
580 u32 board;
581 u32 serdes_config;
582 u32 lane_config;
583 u32 ext_phy_config;
584#define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
585 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
586#define SERDES_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
587 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
588
589 u32 speed_cap_mask;
590 u32 link_config;
591#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
592#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
593#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
594#define SWITCH_CFG_ONE_TIME_DETECT \
595 PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
596
597 u8 ser_lane;
598 u8 rx_lane_swap;
599 u8 tx_lane_swap;
600
601 u8 link_up;
602 u8 phy_link_up;
603
604 u32 supported;
605/* link settings - missing defines */
606#define SUPPORTED_2500baseT_Full (1 << 15)
607
608 u32 phy_flags;
609/*#define PHY_SERDES_FLAG 0x1*/
610#define PHY_BMAC_FLAG 0x2
611#define PHY_EMAC_FLAG 0x4
612#define PHY_XGXS_FLAG 0x8
613#define PHY_SGMII_FLAG 0x10
614#define PHY_INT_MODE_MASK_FLAG 0x300
615#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
616#define PHY_INT_MODE_LINK_READY_FLAG 0x200
617
618 u32 phy_addr;
619 u32 phy_id;
620
621 u32 autoneg;
622#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
623#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
624#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
625#define AUTONEG_PARALLEL \
626 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
627#define AUTONEG_SGMII_FIBER_AUTODET \
628 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
629#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
630
631 u32 req_autoneg;
632#define AUTONEG_SPEED 0x1
633#define AUTONEG_FLOW_CTRL 0x2
634
635 u32 req_line_speed;
636/* link settings - missing defines */
637#define SPEED_12000 12000
638#define SPEED_12500 12500
639#define SPEED_13000 13000
640#define SPEED_15000 15000
641#define SPEED_16000 16000
642
643 u32 req_duplex;
644 u32 req_flow_ctrl;
645#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
646#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
647#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
648#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
649#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
650
651 u32 advertising;
652/* link settings - missing defines */
653#define ADVERTISED_2500baseT_Full (1 << 15)
654
655 u32 link_status;
656 u32 line_speed;
657 u32 duplex;
658 u32 flow_ctrl;
659
660 u32 bc_ver;
661
662 int flash_size;
663#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
664#define NVRAM_TIMEOUT_COUNT 30000
665#define NVRAM_PAGE_SIZE 256
666 824
667 u8 wol; 825 u8 wol;
668 826
669 int rx_ring_size; 827 int rx_ring_size;
670 828
671 u16 tx_quick_cons_trip_int; 829 u16 tx_quick_cons_trip_int;
672 u16 tx_quick_cons_trip; 830 u16 tx_quick_cons_trip;
673 u16 tx_ticks_int; 831 u16 tx_ticks_int;
674 u16 tx_ticks; 832 u16 tx_ticks;
675 833
676 u16 rx_quick_cons_trip_int; 834 u16 rx_quick_cons_trip_int;
677 u16 rx_quick_cons_trip; 835 u16 rx_quick_cons_trip;
678 u16 rx_ticks_int; 836 u16 rx_ticks_int;
679 u16 rx_ticks; 837 u16 rx_ticks;
680 838
681 u32 stats_ticks; 839 u32 stats_ticks;
840 u32 lin_cnt;
682 841
683 int state; 842 int state;
684#define BNX2X_STATE_CLOSED 0x0 843#define BNX2X_STATE_CLOSED 0x0
685#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 844#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
686#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 845#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
687#define BNX2X_STATE_OPEN 0x3000 846#define BNX2X_STATE_OPEN 0x3000
688#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 847#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
689#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 848#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
690#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 849#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
691#define BNX2X_STATE_ERROR 0xF000 850#define BNX2X_STATE_DISABLED 0xd000
851#define BNX2X_STATE_DIAG 0xe000
852#define BNX2X_STATE_ERROR 0xf000
692 853
693 int num_queues; 854 int num_queues;
694 855
695 u32 rx_mode; 856 u32 rx_mode;
696#define BNX2X_RX_MODE_NONE 0 857#define BNX2X_RX_MODE_NONE 0
697#define BNX2X_RX_MODE_NORMAL 1 858#define BNX2X_RX_MODE_NORMAL 1
698#define BNX2X_RX_MODE_ALLMULTI 2 859#define BNX2X_RX_MODE_ALLMULTI 2
699#define BNX2X_RX_MODE_PROMISC 3 860#define BNX2X_RX_MODE_PROMISC 3
700#define BNX2X_MAX_MULTICAST 64 861#define BNX2X_MAX_MULTICAST 64
701#define BNX2X_MAX_EMUL_MULTI 16 862#define BNX2X_MAX_EMUL_MULTI 16
702 863
703 dma_addr_t def_status_blk_mapping; 864 dma_addr_t def_status_blk_mapping;
704 865
705 struct bnx2x_slowpath *slowpath; 866 struct bnx2x_slowpath *slowpath;
706 dma_addr_t slowpath_mapping; 867 dma_addr_t slowpath_mapping;
707 868
708#ifdef BCM_ISCSI 869#ifdef BCM_ISCSI
709 void *t1; 870 void *t1;
@@ -716,264 +877,164 @@ struct bnx2x {
716 dma_addr_t qm_mapping; 877 dma_addr_t qm_mapping;
717#endif 878#endif
718 879
719 char *name; 880 int dmae_ready;
881 /* used to synchronize dmae accesses */
882 struct mutex dmae_mutex;
883 struct dmae_command init_dmae;
720 884
721 /* used to synchronize stats collecting */ 885 /* used to synchronize stats collecting */
722 int stats_state; 886 int stats_state;
723#define STATS_STATE_DISABLE 0
724#define STATS_STATE_ENABLE 1
725#define STATS_STATE_STOP 2 /* stop stats on next iteration */
726
727 /* used by dmae command loader */ 887 /* used by dmae command loader */
728 struct dmae_command dmae; 888 struct dmae_command stats_dmae;
729 int executer_idx; 889 int executer_idx;
730 890
731 u32 old_brb_discard; 891 u16 stats_counter;
732 struct bmac_stats old_bmac;
733 struct tstorm_per_client_stats old_tclient; 892 struct tstorm_per_client_stats old_tclient;
734 struct z_stream_s *strm; 893 struct xstorm_per_client_stats old_xclient;
735 void *gunzip_buf; 894 struct bnx2x_eth_stats eth_stats;
736 dma_addr_t gunzip_mapping;
737 int gunzip_outlen;
738#define FW_BUF_SIZE 0x8000
739
740};
741 895
896 struct z_stream_s *strm;
897 void *gunzip_buf;
898 dma_addr_t gunzip_mapping;
899 int gunzip_outlen;
900#define FW_BUF_SIZE 0x8000
742 901
743/* DMAE command defines */ 902};
744#define DMAE_CMD_SRC_PCI 0
745#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
746 903
747#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
748#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
749 904
750#define DMAE_CMD_C_DST_PCI 0 905void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
751#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT) 906void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
907 u32 len32);
908int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
752 909
753#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 910static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
911 int wait)
912{
913 u32 val;
754 914
755#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 915 do {
756#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 916 val = REG_RD(bp, reg);
757#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 917 if (val == expected)
758#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 918 break;
919 ms -= wait;
920 msleep(wait);
759 921
760#define DMAE_CMD_PORT_0 0 922 } while (ms > 0);
761#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
762 923
763#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 924 return val;
764#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 925}
765 926
766#define DMAE_LEN32_MAX 0x400
767 927
928/* load/unload mode */
929#define LOAD_NORMAL 0
930#define LOAD_OPEN 1
931#define LOAD_DIAG 2
932#define UNLOAD_NORMAL 0
933#define UNLOAD_CLOSE 1
768 934
769/* MC hsi */
770#define RX_COPY_THRESH 92
771#define BCM_PAGE_BITS 12
772#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
773
774#define NUM_TX_RINGS 16
775#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
776#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
777#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
778#define MAX_TX_BD (NUM_TX_BD - 1)
779#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
780#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
781 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
782#define TX_BD(x) ((x) & MAX_TX_BD)
783#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
784 935
785/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 936/* DMAE command defines */
786#define NUM_RX_RINGS 8 937#define DMAE_CMD_SRC_PCI 0
787#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 938#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
788#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
789#define RX_DESC_MASK (RX_DESC_CNT - 1)
790#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
791#define MAX_RX_BD (NUM_RX_BD - 1)
792#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
793#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
794 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
795#define RX_BD(x) ((x) & MAX_RX_BD)
796 939
797#define NUM_RCQ_RINGS (NUM_RX_RINGS * 2) 940#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
798#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 941#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
799#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
800#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
801#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
802#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
803#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
804 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
805#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
806 942
943#define DMAE_CMD_C_DST_PCI 0
944#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
807 945
808/* used on a CID received from the HW */ 946#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
809#define SW_CID(x) (le32_to_cpu(x) & \
810 (COMMON_RAMROD_ETH_RX_CQE_CID >> 1))
811#define CQE_CMD(x) (le32_to_cpu(x) >> \
812 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
813 947
814#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 948#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
815 le32_to_cpu((bd)->addr_lo)) 949#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
816#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 950#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
951#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
817 952
953#define DMAE_CMD_PORT_0 0
954#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
818 955
819#define STROM_ASSERT_ARRAY_SIZE 50 956#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
957#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
958#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
820 959
960#define DMAE_LEN32_RD_MAX 0x80
961#define DMAE_LEN32_WR_MAX 0x400
821 962
822#define MDIO_INDIRECT_REG_ADDR 0x1f 963#define DMAE_COMP_VAL 0xe0d0d0ae
823#define MDIO_SET_REG_BANK(bp, reg_bank) \
824 bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
825 964
826#define MDIO_ACCESS_TIMEOUT 1000 965#define MAX_DMAE_C_PER_PORT 8
966#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
967 BP_E1HVN(bp))
968#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
969 E1HVN_MAX)
827 970
828 971
829/* must be used on a CID before placing it on a HW ring */ 972/* PCIE link and speed */
830#define HW_CID(bp, x) (x | (bp->port << 23)) 973#define PCICFG_LINK_WIDTH 0x1f00000
974#define PCICFG_LINK_WIDTH_SHIFT 20
975#define PCICFG_LINK_SPEED 0xf0000
976#define PCICFG_LINK_SPEED_SHIFT 16
831 977
832#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
833#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
834 978
835#define ATTN_NIG_FOR_FUNC (1L << 8) 979#define BNX2X_NUM_STATS 39
836#define ATTN_SW_TIMER_4_FUNC (1L << 9) 980#define BNX2X_NUM_TESTS 8
837#define GPIO_2_FUNC (1L << 10)
838#define GPIO_3_FUNC (1L << 11)
839#define GPIO_4_FUNC (1L << 12)
840#define ATTN_GENERAL_ATTN_1 (1L << 13)
841#define ATTN_GENERAL_ATTN_2 (1L << 14)
842#define ATTN_GENERAL_ATTN_3 (1L << 15)
843#define ATTN_GENERAL_ATTN_4 (1L << 13)
844#define ATTN_GENERAL_ATTN_5 (1L << 14)
845#define ATTN_GENERAL_ATTN_6 (1L << 15)
846 981
847#define ATTN_HARD_WIRED_MASK 0xff00 982#define BNX2X_MAC_LOOPBACK 0
848#define ATTENTION_ID 4 983#define BNX2X_PHY_LOOPBACK 1
984#define BNX2X_MAC_LOOPBACK_FAILED 1
985#define BNX2X_PHY_LOOPBACK_FAILED 2
986#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
987 BNX2X_PHY_LOOPBACK_FAILED)
849 988
850 989
851#define BNX2X_BTR 3 990#define STROM_ASSERT_ARRAY_SIZE 50
852#define MAX_SPQ_PENDING 8
853 991
854 992
855#define BNX2X_NUM_STATS 34 993/* must be used on a CID before placing it on a HW ring */
856#define BNX2X_NUM_TESTS 1 994#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
857 995
996#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
997#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
858 998
859#define DPM_TRIGER_TYPE 0x40
860#define DOORBELL(bp, cid, val) \
861 do { \
862 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
863 DPM_TRIGER_TYPE); \
864 } while (0)
865 999
866/* PCIE link and speed */ 1000#define BNX2X_BTR 3
867#define PCICFG_LINK_WIDTH 0x1f00000 1001#define MAX_SPQ_PENDING 8
868#define PCICFG_LINK_WIDTH_SHIFT 20
869#define PCICFG_LINK_SPEED 0xf0000
870#define PCICFG_LINK_SPEED_SHIFT 16
871 1002
872#define BMAC_CONTROL_RX_ENABLE 2
873 1003
874#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 1004/* CMNG constants
1005 derived from lab experiments, and not from system spec calculations !!! */
1006#define DEF_MIN_RATE 100
1007/* resolution of the rate shaping timer - 100 usec */
1008#define RS_PERIODIC_TIMEOUT_USEC 100
1009/* resolution of fairness algorithm in usecs -
1010 coefficient for clauclating the actuall t fair */
1011#define T_FAIR_COEF 10000000
1012/* number of bytes in single QM arbitration cycle -
1013 coeffiecnt for calculating the fairness timer */
1014#define QM_ARB_BYTES 40000
1015#define FAIR_MEM 2
875 1016
876/* stuff added to make the code fit 80Col */
877 1017
878#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG 1018#define ATTN_NIG_FOR_FUNC (1L << 8)
879#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG 1019#define ATTN_SW_TIMER_4_FUNC (1L << 9)
880#define TPA_TYPE(cqe) (cqe->fast_path_cqe.error_type_flags & \ 1020#define GPIO_2_FUNC (1L << 10)
881 (TPA_TYPE_START | TPA_TYPE_END)) 1021#define GPIO_3_FUNC (1L << 11)
882#define BNX2X_RX_SUM_OK(cqe) \ 1022#define GPIO_4_FUNC (1L << 12)
883 (!(cqe->fast_path_cqe.status_flags & \ 1023#define ATTN_GENERAL_ATTN_1 (1L << 13)
884 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \ 1024#define ATTN_GENERAL_ATTN_2 (1L << 14)
885 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG))) 1025#define ATTN_GENERAL_ATTN_3 (1L << 15)
1026#define ATTN_GENERAL_ATTN_4 (1L << 13)
1027#define ATTN_GENERAL_ATTN_5 (1L << 14)
1028#define ATTN_GENERAL_ATTN_6 (1L << 15)
886 1029
887#define BNX2X_RX_SUM_FIX(cqe) \ 1030#define ATTN_HARD_WIRED_MASK 0xff00
888 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ 1031#define ATTENTION_ID 4
889 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
890 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
891 1032
892 1033
893#define MDIO_AN_CL73_OR_37_COMPLETE \ 1034/* stuff added to make the code fit 80Col */
894 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
895 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
896
897#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
898 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
899#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
900 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
901#define GP_STATUS_SPEED_MASK \
902 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
903#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
904#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
905#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
906#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
907#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
908#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
909#define GP_STATUS_10G_HIG \
910 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
911#define GP_STATUS_10G_CX4 \
912 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
913#define GP_STATUS_12G_HIG \
914 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
915#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
916#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
917#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
918#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
919#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
920#define GP_STATUS_10G_KX4 \
921 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
922
923#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
924#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
925#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
926#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
927#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
928#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
929#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
930#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
931#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
932#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
933#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
934#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
935#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
936#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
937#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
938#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
939#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
940#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
941#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
942#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
943#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
944#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
945#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
946
947#define NIG_STATUS_XGXS0_LINK10G \
948 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
949#define NIG_STATUS_XGXS0_LINK_STATUS \
950 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
951#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
952 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
953#define NIG_STATUS_SERDES0_LINK_STATUS \
954 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
955#define NIG_MASK_MI_INT \
956 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
957#define NIG_MASK_XGXS0_LINK10G \
958 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
959#define NIG_MASK_XGXS0_LINK_STATUS \
960 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
961#define NIG_MASK_SERDES0_LINK_STATUS \
962 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
963
964#define XGXS_RESET_BITS \
965 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
966 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
967 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
968 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
969 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
970
971#define SERDES_RESET_BITS \
972 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
973 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
974 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
975 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
976 1035
1036#define BNX2X_PMF_LINK_ASSERT \
1037 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
977 1038
978#define BNX2X_MC_ASSERT_BITS \ 1039#define BNX2X_MC_ASSERT_BITS \
979 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1040 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
@@ -987,12 +1048,20 @@ struct bnx2x {
987#define BNX2X_DOORQ_ASSERT \ 1048#define BNX2X_DOORQ_ASSERT \
988 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT 1049 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
989 1050
1051#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1052#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1053 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1054 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1055 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1056 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1057 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1058
990#define HW_INTERRUT_ASSERT_SET_0 \ 1059#define HW_INTERRUT_ASSERT_SET_0 \
991 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 1060 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
992 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 1061 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
993 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 1062 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
994 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) 1063 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
995#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 1064#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
996 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 1065 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
997 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 1066 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
998 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 1067 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
@@ -1009,7 +1078,7 @@ struct bnx2x {
1009 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 1078 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1010 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 1079 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1011 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 1080 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1012#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ 1081#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1013 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 1082 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1014 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 1083 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1015 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 1084 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
@@ -1026,7 +1095,7 @@ struct bnx2x {
1026 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 1095 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1027 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 1096 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1028 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 1097 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1029#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 1098#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1030 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 1099 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1031 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 1100 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1032 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 1101 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
@@ -1035,42 +1104,44 @@ struct bnx2x {
1035 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 1104 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1036 1105
1037 1106
1038#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
1039 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
1040 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
1041
1042
1043#define MULTI_FLAGS \ 1107#define MULTI_FLAGS \
1044 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ 1108 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1045 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ 1109 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1046 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ 1110 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1047 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ 1111 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1048 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE) 1112 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
1049
1050#define MULTI_MASK 0x7f
1051 1113
1114#define MULTI_MASK 0x7f
1052 1115
1053#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
1054#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
1055#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1056 1116
1057#define BNX2X_RX_SB_INDEX \ 1117#define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1058 &fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX] 1118#define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1119#define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1120#define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1059 1121
1060#define BNX2X_TX_SB_INDEX \ 1122#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1061 &fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]
1062 1123
1063#define BNX2X_SP_DSB_INDEX \ 1124#define BNX2X_SP_DSB_INDEX \
1064&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX] 1125(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1065 1126
1066 1127
1067#define CAM_IS_INVALID(x) \ 1128#define CAM_IS_INVALID(x) \
1068(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) 1129(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1069 1130
1070#define CAM_INVALIDATE(x) \ 1131#define CAM_INVALIDATE(x) \
1071x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE 1132 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1072 1133
1073 1134
1135/* Number of u32 elements in MC hash array */
1136#define MC_HASH_SIZE 8
1137#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1138 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1139
1140
1141#ifndef PXP2_REG_PXP2_INT_STS
1142#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1143#endif
1144
1074/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */ 1145/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1075 1146
1076#endif /* bnx2x.h */ 1147#endif /* bnx2x.h */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 06:40:06 -0500