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Diffstat (limited to 'drivers/net/bnx2x.h')
-rw-r--r--drivers/net/bnx2x.h92
1 files changed, 55 insertions, 37 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 4bf4f7b205f2..fd705d1295a7 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -40,20 +40,20 @@
40#define DP(__mask, __fmt, __args...) do { \ 40#define DP(__mask, __fmt, __args...) do { \
41 if (bp->msglevel & (__mask)) \ 41 if (bp->msglevel & (__mask)) \
42 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ 42 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
43 bp->dev?(bp->dev->name):"?", ##__args); \ 43 bp->dev ? (bp->dev->name) : "?", ##__args); \
44 } while (0) 44 } while (0)
45 45
46/* errors debug print */ 46/* errors debug print */
47#define BNX2X_DBG_ERR(__fmt, __args...) do { \ 47#define BNX2X_DBG_ERR(__fmt, __args...) do { \
48 if (bp->msglevel & NETIF_MSG_PROBE) \ 48 if (bp->msglevel & NETIF_MSG_PROBE) \
49 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ 49 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
50 bp->dev?(bp->dev->name):"?", ##__args); \ 50 bp->dev ? (bp->dev->name) : "?", ##__args); \
51 } while (0) 51 } while (0)
52 52
53/* for errors (never masked) */ 53/* for errors (never masked) */
54#define BNX2X_ERR(__fmt, __args...) do { \ 54#define BNX2X_ERR(__fmt, __args...) do { \
55 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ 55 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
56 bp->dev?(bp->dev->name):"?", ##__args); \ 56 bp->dev ? (bp->dev->name) : "?", ##__args); \
57 } while (0) 57 } while (0)
58 58
59/* before we have a dev->name use dev_info() */ 59/* before we have a dev->name use dev_info() */
@@ -120,16 +120,8 @@
120#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 120#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
122 122
123#define NIG_WR(reg, val) REG_WR(bp, reg, val) 123#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
124#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) 124#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
125#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
126
127
128#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
129
130#define for_each_nondefault_queue(bp, var) \
131 for (var = 1; var < bp->num_queues; var++)
132#define is_multi(bp) (bp->num_queues > 1)
133 125
134 126
135/* fast path */ 127/* fast path */
@@ -159,11 +151,13 @@ struct sw_rx_page {
159#define PAGES_PER_SGE_SHIFT 0 151#define PAGES_PER_SGE_SHIFT 0
160#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 152#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
161 153
154#define BCM_RX_ETH_PAYLOAD_ALIGN 64
155
162/* SGE ring related macros */ 156/* SGE ring related macros */
163#define NUM_RX_SGE_PAGES 2 157#define NUM_RX_SGE_PAGES 2
164#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 158#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
165#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) 159#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
166/* RX_SGE_CNT is promissed to be a power of 2 */ 160/* RX_SGE_CNT is promised to be a power of 2 */
167#define RX_SGE_MASK (RX_SGE_CNT - 1) 161#define RX_SGE_MASK (RX_SGE_CNT - 1)
168#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 162#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
169#define MAX_RX_SGE (NUM_RX_SGE - 1) 163#define MAX_RX_SGE (NUM_RX_SGE - 1)
@@ -258,8 +252,7 @@ struct bnx2x_fastpath {
258 252
259 unsigned long tx_pkt, 253 unsigned long tx_pkt,
260 rx_pkt, 254 rx_pkt,
261 rx_calls, 255 rx_calls;
262 rx_alloc_failed;
263 /* TPA related */ 256 /* TPA related */
264 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; 257 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
265 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; 258 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
@@ -275,6 +268,15 @@ struct bnx2x_fastpath {
275 268
276#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) 269#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
277 270
271#define BNX2X_HAS_TX_WORK(fp) \
272 ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || \
273 (fp->tx_pkt_prod != fp->tx_pkt_cons))
274
275#define BNX2X_HAS_RX_WORK(fp) \
276 (fp->rx_comp_cons != rx_cons_sb)
277
278#define BNX2X_HAS_WORK(fp) (BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp))
279
278 280
279/* MC hsi */ 281/* MC hsi */
280#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 282#define MAX_FETCH_BD 13 /* HW max BDs per packet */
@@ -317,7 +319,7 @@ struct bnx2x_fastpath {
317#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 319#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
318 320
319 321
320/* This is needed for determening of last_max */ 322/* This is needed for determining of last_max */
321#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 323#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
322 324
323#define __SGE_MASK_SET_BIT(el, bit) \ 325#define __SGE_MASK_SET_BIT(el, bit) \
@@ -386,20 +388,28 @@ struct bnx2x_fastpath {
386#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \ 388#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
387 (TPA_TYPE_START | TPA_TYPE_END)) 389 (TPA_TYPE_START | TPA_TYPE_END))
388 390
389#define BNX2X_RX_SUM_OK(cqe) \ 391#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
390 (!(cqe->fast_path_cqe.status_flags & \ 392
391 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \ 393#define BNX2X_IP_CSUM_ERR(cqe) \
392 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG))) 394 (!((cqe)->fast_path_cqe.status_flags & \
395 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
396 ((cqe)->fast_path_cqe.type_error_flags & \
397 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
398
399#define BNX2X_L4_CSUM_ERR(cqe) \
400 (!((cqe)->fast_path_cqe.status_flags & \
401 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
402 ((cqe)->fast_path_cqe.type_error_flags & \
403 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
404
405#define BNX2X_RX_CSUM_OK(cqe) \
406 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
393 407
394#define BNX2X_RX_SUM_FIX(cqe) \ 408#define BNX2X_RX_SUM_FIX(cqe) \
395 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ 409 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
396 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \ 410 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
397 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT)) 411 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
398 412
399#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
400 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
401 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
402
403 413
404#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES) 414#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
405#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES) 415#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
@@ -647,6 +657,8 @@ struct bnx2x_eth_stats {
647 657
648 u32 brb_drop_hi; 658 u32 brb_drop_hi;
649 u32 brb_drop_lo; 659 u32 brb_drop_lo;
660 u32 brb_truncate_hi;
661 u32 brb_truncate_lo;
650 662
651 u32 jabber_packets_received; 663 u32 jabber_packets_received;
652 664
@@ -663,6 +675,9 @@ struct bnx2x_eth_stats {
663 u32 mac_discard; 675 u32 mac_discard;
664 676
665 u32 driver_xoff; 677 u32 driver_xoff;
678 u32 rx_err_discard_pkt;
679 u32 rx_skb_alloc_failed;
680 u32 hw_csum_err;
666}; 681};
667 682
668#define STATS_OFFSET32(stat_name) \ 683#define STATS_OFFSET32(stat_name) \
@@ -737,8 +752,7 @@ struct bnx2x {
737 752
738 u32 rx_csum; 753 u32 rx_csum;
739 u32 rx_offset; 754 u32 rx_offset;
740 u32 rx_buf_use_size; /* useable size */ 755 u32 rx_buf_size;
741 u32 rx_buf_size; /* with alignment */
742#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ 756#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
743#define ETH_MIN_PACKET_SIZE 60 757#define ETH_MIN_PACKET_SIZE 60
744#define ETH_MAX_PACKET_SIZE 1500 758#define ETH_MAX_PACKET_SIZE 1500
@@ -753,7 +767,6 @@ struct bnx2x {
753 u16 def_att_idx; 767 u16 def_att_idx;
754 u32 attn_state; 768 u32 attn_state;
755 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 769 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
756 u32 aeu_mask;
757 u32 nig_mask; 770 u32 nig_mask;
758 771
759 /* slow path ring */ 772 /* slow path ring */
@@ -772,7 +785,7 @@ struct bnx2x {
772 u8 stats_pending; 785 u8 stats_pending;
773 u8 set_mac_pending; 786 u8 set_mac_pending;
774 787
775 /* End of fileds used in the performance code paths */ 788 /* End of fields used in the performance code paths */
776 789
777 int panic; 790 int panic;
778 int msglevel; 791 int msglevel;
@@ -794,9 +807,6 @@ struct bnx2x {
794#define BP_FUNC(bp) (bp->func) 807#define BP_FUNC(bp) (bp->func)
795#define BP_E1HVN(bp) (bp->func >> 1) 808#define BP_E1HVN(bp) (bp->func >> 1)
796#define BP_L_ID(bp) (BP_E1HVN(bp) << 2) 809#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
797/* assorted E1HVN */
798#define IS_E1HMF(bp) (bp->e1hmf != 0)
799#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
800 810
801 int pm_cap; 811 int pm_cap;
802 int pcie_cap; 812 int pcie_cap;
@@ -821,6 +831,7 @@ struct bnx2x {
821 u32 mf_config; 831 u32 mf_config;
822 u16 e1hov; 832 u16 e1hov;
823 u8 e1hmf; 833 u8 e1hmf;
834#define IS_E1HMF(bp) (bp->e1hmf != 0)
824 835
825 u8 wol; 836 u8 wol;
826 837
@@ -836,7 +847,6 @@ struct bnx2x {
836 u16 rx_ticks_int; 847 u16 rx_ticks_int;
837 u16 rx_ticks; 848 u16 rx_ticks;
838 849
839 u32 stats_ticks;
840 u32 lin_cnt; 850 u32 lin_cnt;
841 851
842 int state; 852 int state;
@@ -852,6 +862,7 @@ struct bnx2x {
852#define BNX2X_STATE_ERROR 0xf000 862#define BNX2X_STATE_ERROR 0xf000
853 863
854 int num_queues; 864 int num_queues;
865#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
855 866
856 u32 rx_mode; 867 u32 rx_mode;
857#define BNX2X_RX_MODE_NONE 0 868#define BNX2X_RX_MODE_NONE 0
@@ -902,10 +913,17 @@ struct bnx2x {
902}; 913};
903 914
904 915
916#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
917
918#define for_each_nondefault_queue(bp, var) \
919 for (var = 1; var < bp->num_queues; var++)
920#define is_multi(bp) (bp->num_queues > 1)
921
922
905void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 923void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
906void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 924void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
907 u32 len32); 925 u32 len32);
908int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); 926int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
909 927
910static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 928static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
911 int wait) 929 int wait)
@@ -976,7 +994,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
976#define PCICFG_LINK_SPEED_SHIFT 16 994#define PCICFG_LINK_SPEED_SHIFT 16
977 995
978 996
979#define BNX2X_NUM_STATS 39 997#define BNX2X_NUM_STATS 42
980#define BNX2X_NUM_TESTS 8 998#define BNX2X_NUM_TESTS 8
981 999
982#define BNX2X_MAC_LOOPBACK 0 1000#define BNX2X_MAC_LOOPBACK 0
@@ -1007,10 +1025,10 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1007/* resolution of the rate shaping timer - 100 usec */ 1025/* resolution of the rate shaping timer - 100 usec */
1008#define RS_PERIODIC_TIMEOUT_USEC 100 1026#define RS_PERIODIC_TIMEOUT_USEC 100
1009/* resolution of fairness algorithm in usecs - 1027/* resolution of fairness algorithm in usecs -
1010 coefficient for clauclating the actuall t fair */ 1028 coefficient for calculating the actual t fair */
1011#define T_FAIR_COEF 10000000 1029#define T_FAIR_COEF 10000000
1012/* number of bytes in single QM arbitration cycle - 1030/* number of bytes in single QM arbitration cycle -
1013 coeffiecnt for calculating the fairness timer */ 1031 coefficient for calculating the fairness timer */
1014#define QM_ARB_BYTES 40000 1032#define QM_ARB_BYTES 40000
1015#define FAIR_MEM 2 1033#define FAIR_MEM 2
1016 1034