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Diffstat (limited to 'drivers/net/bnx2.h')
-rw-r--r--drivers/net/bnx2.h37
1 files changed, 21 insertions, 16 deletions
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 2104c1005d02..bf371f6fe154 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -1,6 +1,6 @@
1/* bnx2.h: Broadcom NX2 network driver. 1/* bnx2.h: Broadcom NX2 network driver.
2 * 2 *
3 * Copyright (c) 2004-2009 Broadcom Corporation 3 * Copyright (c) 2004-2011 Broadcom Corporation
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
@@ -352,12 +352,7 @@ struct l2_fhdr {
352#define BNX2_L2CTX_BD_PRE_READ 0x00000000 352#define BNX2_L2CTX_BD_PRE_READ 0x00000000
353#define BNX2_L2CTX_CTX_SIZE 0x00000000 353#define BNX2_L2CTX_CTX_SIZE 0x00000000
354#define BNX2_L2CTX_CTX_TYPE 0x00000000 354#define BNX2_L2CTX_CTX_TYPE 0x00000000
355#define BNX2_L2CTX_LO_WATER_MARK_DEFAULT 4 355#define BNX2_L2CTX_FLOW_CTRL_ENABLE 0x000000ff
356#define BNX2_L2CTX_LO_WATER_MARK_SCALE 4
357#define BNX2_L2CTX_LO_WATER_MARK_DIS 0
358#define BNX2_L2CTX_HI_WATER_MARK_SHIFT 4
359#define BNX2_L2CTX_HI_WATER_MARK_SCALE 16
360#define BNX2_L2CTX_WATER_MARKS_MSK 0x000000ff
361#define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) 356#define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
362#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 357#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
363#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 358#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
@@ -466,6 +461,8 @@ struct l2_fhdr {
466#define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 461#define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
467#define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 462#define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
468 463
464#define BNX2_PCICFG_DEVICE_CONTROL 0x000000b4
465#define BNX2_PCICFG_DEVICE_STATUS_NO_PEND ((1L<<5)<<16)
469 466
470/* 467/*
471 * pci_reg definition 468 * pci_reg definition
@@ -4185,6 +4182,15 @@ struct l2_fhdr {
4185#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI (2L<<2) 4182#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI (2L<<2)
4186#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI (3L<<2) 4183#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI (3L<<2)
4187 4184
4185#define BNX2_RLUP_RSS_COMMAND 0x00002048
4186#define BNX2_RLUP_RSS_COMMAND_RSS_IND_TABLE_ADDR (0xfUL<<0)
4187#define BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK (0xffUL<<4)
4188#define BNX2_RLUP_RSS_COMMAND_WRITE (1UL<<12)
4189#define BNX2_RLUP_RSS_COMMAND_READ (1UL<<13)
4190#define BNX2_RLUP_RSS_COMMAND_HASH_MASK (0x7UL<<14)
4191
4192#define BNX2_RLUP_RSS_DATA 0x0000204c
4193
4188 4194
4189/* 4195/*
4190 * rbuf_reg definition 4196 * rbuf_reg definition
@@ -6077,6 +6083,7 @@ struct l2_fhdr {
6077 6083
6078#define BNX2_COM_SCRATCH 0x00120000 6084#define BNX2_COM_SCRATCH 0x00120000
6079 6085
6086#define BNX2_FW_RX_LOW_LATENCY 0x00120058
6080#define BNX2_FW_RX_DROP_COUNT 0x00120084 6087#define BNX2_FW_RX_DROP_COUNT 0x00120084
6081 6088
6082 6089
@@ -6200,6 +6207,8 @@ struct l2_fhdr {
6200 6207
6201#define BNX2_CP_SCRATCH 0x001a0000 6208#define BNX2_CP_SCRATCH 0x001a0000
6202 6209
6210#define BNX2_FW_MAX_ISCSI_CONN 0x001a0080
6211
6203 6212
6204/* 6213/*
6205 * mcp_reg definition 6214 * mcp_reg definition
@@ -6497,8 +6506,8 @@ struct l2_fhdr {
6497#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd)) 6506#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd))
6498#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) 6507#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
6499 6508
6500#define MAX_RX_RINGS 4 6509#define MAX_RX_RINGS 8
6501#define MAX_RX_PG_RINGS 16 6510#define MAX_RX_PG_RINGS 32
6502#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 6511#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
6503#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1) 6512#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
6504#define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS) 6513#define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS)
@@ -6734,13 +6743,10 @@ struct bnx2 {
6734#define BNX2_FLAG_JUMBO_BROKEN 0x00000800 6743#define BNX2_FLAG_JUMBO_BROKEN 0x00000800
6735#define BNX2_FLAG_CAN_KEEP_VLAN 0x00001000 6744#define BNX2_FLAG_CAN_KEEP_VLAN 0x00001000
6736#define BNX2_FLAG_BROKEN_STATS 0x00002000 6745#define BNX2_FLAG_BROKEN_STATS 0x00002000
6746#define BNX2_FLAG_AER_ENABLED 0x00004000
6737 6747
6738 struct bnx2_napi bnx2_napi[BNX2_MAX_MSIX_VEC]; 6748 struct bnx2_napi bnx2_napi[BNX2_MAX_MSIX_VEC];
6739 6749
6740#ifdef BCM_VLAN
6741 struct vlan_group *vlgrp;
6742#endif
6743
6744 u32 rx_buf_use_size; /* useable size */ 6750 u32 rx_buf_use_size; /* useable size */
6745 u32 rx_buf_size; /* with alignment */ 6751 u32 rx_buf_size; /* with alignment */
6746 u32 rx_copy_thresh; 6752 u32 rx_copy_thresh;
@@ -6748,14 +6754,12 @@ struct bnx2 {
6748 u32 rx_max_ring_idx; 6754 u32 rx_max_ring_idx;
6749 u32 rx_max_pg_ring_idx; 6755 u32 rx_max_pg_ring_idx;
6750 6756
6751 u32 rx_csum;
6752
6753 /* TX constants */ 6757 /* TX constants */
6754 int tx_ring_size; 6758 int tx_ring_size;
6755 u32 tx_wake_thresh; 6759 u32 tx_wake_thresh;
6756 6760
6757#ifdef BCM_CNIC 6761#ifdef BCM_CNIC
6758 struct cnic_ops *cnic_ops; 6762 struct cnic_ops __rcu *cnic_ops;
6759 void *cnic_data; 6763 void *cnic_data;
6760#endif 6764#endif
6761 6765
@@ -6916,6 +6920,7 @@ struct bnx2 {
6916 u8 num_tx_rings; 6920 u8 num_tx_rings;
6917 u8 num_rx_rings; 6921 u8 num_rx_rings;
6918 6922
6923 u32 leds_save;
6919 u32 idle_chk_status_idx; 6924 u32 idle_chk_status_idx;
6920 6925
6921#ifdef BCM_CNIC 6926#ifdef BCM_CNIC