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path: root/drivers/net/bnx2.c
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Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r--drivers/net/bnx2.c477
1 files changed, 173 insertions, 304 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index b787b6582e50..7d213707008a 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -14,8 +14,8 @@
14 14
15#define DRV_MODULE_NAME "bnx2" 15#define DRV_MODULE_NAME "bnx2"
16#define PFX DRV_MODULE_NAME ": " 16#define PFX DRV_MODULE_NAME ": "
17#define DRV_MODULE_VERSION "1.4.31" 17#define DRV_MODULE_VERSION "1.4.38"
18#define DRV_MODULE_RELDATE "January 19, 2006" 18#define DRV_MODULE_RELDATE "February 10, 2006"
19 19
20#define RUN_AT(x) (jiffies + (x)) 20#define RUN_AT(x) (jiffies + (x))
21 21
@@ -360,6 +360,8 @@ bnx2_netif_start(struct bnx2 *bp)
360static void 360static void
361bnx2_free_mem(struct bnx2 *bp) 361bnx2_free_mem(struct bnx2 *bp)
362{ 362{
363 int i;
364
363 if (bp->stats_blk) { 365 if (bp->stats_blk) {
364 pci_free_consistent(bp->pdev, sizeof(struct statistics_block), 366 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
365 bp->stats_blk, bp->stats_blk_mapping); 367 bp->stats_blk, bp->stats_blk_mapping);
@@ -378,19 +380,23 @@ bnx2_free_mem(struct bnx2 *bp)
378 } 380 }
379 kfree(bp->tx_buf_ring); 381 kfree(bp->tx_buf_ring);
380 bp->tx_buf_ring = NULL; 382 bp->tx_buf_ring = NULL;
381 if (bp->rx_desc_ring) { 383 for (i = 0; i < bp->rx_max_ring; i++) {
382 pci_free_consistent(bp->pdev, 384 if (bp->rx_desc_ring[i])
383 sizeof(struct rx_bd) * RX_DESC_CNT, 385 pci_free_consistent(bp->pdev,
384 bp->rx_desc_ring, bp->rx_desc_mapping); 386 sizeof(struct rx_bd) * RX_DESC_CNT,
385 bp->rx_desc_ring = NULL; 387 bp->rx_desc_ring[i],
386 } 388 bp->rx_desc_mapping[i]);
387 kfree(bp->rx_buf_ring); 389 bp->rx_desc_ring[i] = NULL;
390 }
391 vfree(bp->rx_buf_ring);
388 bp->rx_buf_ring = NULL; 392 bp->rx_buf_ring = NULL;
389} 393}
390 394
391static int 395static int
392bnx2_alloc_mem(struct bnx2 *bp) 396bnx2_alloc_mem(struct bnx2 *bp)
393{ 397{
398 int i;
399
394 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT, 400 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
395 GFP_KERNEL); 401 GFP_KERNEL);
396 if (bp->tx_buf_ring == NULL) 402 if (bp->tx_buf_ring == NULL)
@@ -404,18 +410,23 @@ bnx2_alloc_mem(struct bnx2 *bp)
404 if (bp->tx_desc_ring == NULL) 410 if (bp->tx_desc_ring == NULL)
405 goto alloc_mem_err; 411 goto alloc_mem_err;
406 412
407 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT, 413 bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
408 GFP_KERNEL); 414 bp->rx_max_ring);
409 if (bp->rx_buf_ring == NULL) 415 if (bp->rx_buf_ring == NULL)
410 goto alloc_mem_err; 416 goto alloc_mem_err;
411 417
412 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT); 418 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
413 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev, 419 bp->rx_max_ring);
414 sizeof(struct rx_bd) * 420
415 RX_DESC_CNT, 421 for (i = 0; i < bp->rx_max_ring; i++) {
416 &bp->rx_desc_mapping); 422 bp->rx_desc_ring[i] =
417 if (bp->rx_desc_ring == NULL) 423 pci_alloc_consistent(bp->pdev,
418 goto alloc_mem_err; 424 sizeof(struct rx_bd) * RX_DESC_CNT,
425 &bp->rx_desc_mapping[i]);
426 if (bp->rx_desc_ring[i] == NULL)
427 goto alloc_mem_err;
428
429 }
419 430
420 bp->status_blk = pci_alloc_consistent(bp->pdev, 431 bp->status_blk = pci_alloc_consistent(bp->pdev,
421 sizeof(struct status_block), 432 sizeof(struct status_block),
@@ -1520,7 +1531,7 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1520 struct sk_buff *skb; 1531 struct sk_buff *skb;
1521 struct sw_bd *rx_buf = &bp->rx_buf_ring[index]; 1532 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1522 dma_addr_t mapping; 1533 dma_addr_t mapping;
1523 struct rx_bd *rxbd = &bp->rx_desc_ring[index]; 1534 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
1524 unsigned long align; 1535 unsigned long align;
1525 1536
1526 skb = dev_alloc_skb(bp->rx_buf_size); 1537 skb = dev_alloc_skb(bp->rx_buf_size);
@@ -1656,23 +1667,30 @@ static inline void
1656bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb, 1667bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1657 u16 cons, u16 prod) 1668 u16 cons, u16 prod)
1658{ 1669{
1659 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons]; 1670 struct sw_bd *cons_rx_buf, *prod_rx_buf;
1660 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod]; 1671 struct rx_bd *cons_bd, *prod_bd;
1661 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons]; 1672
1662 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod]; 1673 cons_rx_buf = &bp->rx_buf_ring[cons];
1674 prod_rx_buf = &bp->rx_buf_ring[prod];
1663 1675
1664 pci_dma_sync_single_for_device(bp->pdev, 1676 pci_dma_sync_single_for_device(bp->pdev,
1665 pci_unmap_addr(cons_rx_buf, mapping), 1677 pci_unmap_addr(cons_rx_buf, mapping),
1666 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); 1678 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1667 1679
1668 prod_rx_buf->skb = cons_rx_buf->skb; 1680 bp->rx_prod_bseq += bp->rx_buf_use_size;
1669 pci_unmap_addr_set(prod_rx_buf, mapping,
1670 pci_unmap_addr(cons_rx_buf, mapping));
1671 1681
1672 memcpy(prod_bd, cons_bd, 8); 1682 prod_rx_buf->skb = skb;
1673 1683
1674 bp->rx_prod_bseq += bp->rx_buf_use_size; 1684 if (cons == prod)
1685 return;
1675 1686
1687 pci_unmap_addr_set(prod_rx_buf, mapping,
1688 pci_unmap_addr(cons_rx_buf, mapping));
1689
1690 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
1691 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1692 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
1693 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
1676} 1694}
1677 1695
1678static int 1696static int
@@ -1699,14 +1717,19 @@ bnx2_rx_int(struct bnx2 *bp, int budget)
1699 u32 status; 1717 u32 status;
1700 struct sw_bd *rx_buf; 1718 struct sw_bd *rx_buf;
1701 struct sk_buff *skb; 1719 struct sk_buff *skb;
1720 dma_addr_t dma_addr;
1702 1721
1703 sw_ring_cons = RX_RING_IDX(sw_cons); 1722 sw_ring_cons = RX_RING_IDX(sw_cons);
1704 sw_ring_prod = RX_RING_IDX(sw_prod); 1723 sw_ring_prod = RX_RING_IDX(sw_prod);
1705 1724
1706 rx_buf = &bp->rx_buf_ring[sw_ring_cons]; 1725 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1707 skb = rx_buf->skb; 1726 skb = rx_buf->skb;
1708 pci_dma_sync_single_for_cpu(bp->pdev, 1727
1709 pci_unmap_addr(rx_buf, mapping), 1728 rx_buf->skb = NULL;
1729
1730 dma_addr = pci_unmap_addr(rx_buf, mapping);
1731
1732 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
1710 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); 1733 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1711 1734
1712 rx_hdr = (struct l2_fhdr *) skb->data; 1735 rx_hdr = (struct l2_fhdr *) skb->data;
@@ -1747,8 +1770,7 @@ bnx2_rx_int(struct bnx2 *bp, int budget)
1747 skb = new_skb; 1770 skb = new_skb;
1748 } 1771 }
1749 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) { 1772 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1750 pci_unmap_single(bp->pdev, 1773 pci_unmap_single(bp->pdev, dma_addr,
1751 pci_unmap_addr(rx_buf, mapping),
1752 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); 1774 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1753 1775
1754 skb_reserve(skb, bp->rx_offset); 1776 skb_reserve(skb, bp->rx_offset);
@@ -1794,8 +1816,6 @@ reuse_rx:
1794 rx_pkt++; 1816 rx_pkt++;
1795 1817
1796next_rx: 1818next_rx:
1797 rx_buf->skb = NULL;
1798
1799 sw_cons = NEXT_RX_BD(sw_cons); 1819 sw_cons = NEXT_RX_BD(sw_cons);
1800 sw_prod = NEXT_RX_BD(sw_prod); 1820 sw_prod = NEXT_RX_BD(sw_prod);
1801 1821
@@ -3340,27 +3360,35 @@ bnx2_init_rx_ring(struct bnx2 *bp)
3340 bp->hw_rx_cons = 0; 3360 bp->hw_rx_cons = 0;
3341 bp->rx_prod_bseq = 0; 3361 bp->rx_prod_bseq = 0;
3342 3362
3343 rxbd = &bp->rx_desc_ring[0]; 3363 for (i = 0; i < bp->rx_max_ring; i++) {
3344 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) { 3364 int j;
3345 rxbd->rx_bd_len = bp->rx_buf_use_size;
3346 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3347 }
3348 3365
3349 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32; 3366 rxbd = &bp->rx_desc_ring[i][0];
3350 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff; 3367 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
3368 rxbd->rx_bd_len = bp->rx_buf_use_size;
3369 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3370 }
3371 if (i == (bp->rx_max_ring - 1))
3372 j = 0;
3373 else
3374 j = i + 1;
3375 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
3376 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
3377 0xffffffff;
3378 }
3351 3379
3352 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3380 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3353 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; 3381 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3354 val |= 0x02 << 8; 3382 val |= 0x02 << 8;
3355 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val); 3383 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3356 3384
3357 val = (u64) bp->rx_desc_mapping >> 32; 3385 val = (u64) bp->rx_desc_mapping[0] >> 32;
3358 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val); 3386 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3359 3387
3360 val = (u64) bp->rx_desc_mapping & 0xffffffff; 3388 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
3361 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val); 3389 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3362 3390
3363 for ( ;ring_prod < bp->rx_ring_size; ) { 3391 for (i = 0; i < bp->rx_ring_size; i++) {
3364 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) { 3392 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3365 break; 3393 break;
3366 } 3394 }
@@ -3375,6 +3403,29 @@ bnx2_init_rx_ring(struct bnx2 *bp)
3375} 3403}
3376 3404
3377static void 3405static void
3406bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
3407{
3408 u32 num_rings, max;
3409
3410 bp->rx_ring_size = size;
3411 num_rings = 1;
3412 while (size > MAX_RX_DESC_CNT) {
3413 size -= MAX_RX_DESC_CNT;
3414 num_rings++;
3415 }
3416 /* round to next power of 2 */
3417 max = MAX_RX_RINGS;
3418 while ((max & num_rings) == 0)
3419 max >>= 1;
3420
3421 if (num_rings != max)
3422 max <<= 1;
3423
3424 bp->rx_max_ring = max;
3425 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
3426}
3427
3428static void
3378bnx2_free_tx_skbs(struct bnx2 *bp) 3429bnx2_free_tx_skbs(struct bnx2 *bp)
3379{ 3430{
3380 int i; 3431 int i;
@@ -3419,7 +3470,7 @@ bnx2_free_rx_skbs(struct bnx2 *bp)
3419 if (bp->rx_buf_ring == NULL) 3470 if (bp->rx_buf_ring == NULL)
3420 return; 3471 return;
3421 3472
3422 for (i = 0; i < RX_DESC_CNT; i++) { 3473 for (i = 0; i < bp->rx_max_ring_idx; i++) {
3423 struct sw_bd *rx_buf = &bp->rx_buf_ring[i]; 3474 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3424 struct sk_buff *skb = rx_buf->skb; 3475 struct sk_buff *skb = rx_buf->skb;
3425 3476
@@ -3506,74 +3557,9 @@ bnx2_test_registers(struct bnx2 *bp)
3506 { 0x0c00, 0, 0x00000000, 0x00000001 }, 3557 { 0x0c00, 0, 0x00000000, 0x00000001 },
3507 { 0x0c04, 0, 0x00000000, 0x03ff0001 }, 3558 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3508 { 0x0c08, 0, 0x0f0ff073, 0x00000000 }, 3559 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3509 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3510 { 0x0c30, 0, 0x00000000, 0xffffffff },
3511 { 0x0c34, 0, 0x00000000, 0xffffffff },
3512 { 0x0c38, 0, 0x00000000, 0xffffffff },
3513 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3514 { 0x0c40, 0, 0x00000000, 0xffffffff },
3515 { 0x0c44, 0, 0x00000000, 0xffffffff },
3516 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3517 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3518 { 0x0c50, 0, 0x00000000, 0xffffffff },
3519 { 0x0c54, 0, 0x00000000, 0xffffffff },
3520 { 0x0c58, 0, 0x00000000, 0xffffffff },
3521 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3522 { 0x0c60, 0, 0x00000000, 0xffffffff },
3523 { 0x0c64, 0, 0x00000000, 0xffffffff },
3524 { 0x0c68, 0, 0x00000000, 0xffffffff },
3525 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3526 { 0x0c70, 0, 0x00000000, 0xffffffff },
3527 { 0x0c74, 0, 0x00000000, 0xffffffff },
3528 { 0x0c78, 0, 0x00000000, 0xffffffff },
3529 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3530 { 0x0c80, 0, 0x00000000, 0xffffffff },
3531 { 0x0c84, 0, 0x00000000, 0xffffffff },
3532 { 0x0c88, 0, 0x00000000, 0xffffffff },
3533 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3534 { 0x0c90, 0, 0x00000000, 0xffffffff },
3535 { 0x0c94, 0, 0x00000000, 0xffffffff },
3536 { 0x0c98, 0, 0x00000000, 0xffffffff },
3537 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3538 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3539 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3540 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3541 { 0x0cac, 0, 0x00000000, 0xffffffff },
3542 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3543 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3544 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3545 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3546 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3547 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3548 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3549 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3550 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3551 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3552 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3553 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3554 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3555 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3556 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3557 { 0x0cec, 0, 0x00000000, 0xffffffff },
3558 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3559 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3560 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3561 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3562 { 0x0d00, 0, 0x00000000, 0xffffffff },
3563 { 0x0d04, 0, 0x00000000, 0xffffffff },
3564 3560
3565 { 0x1000, 0, 0x00000000, 0x00000001 }, 3561 { 0x1000, 0, 0x00000000, 0x00000001 },
3566 { 0x1004, 0, 0x00000000, 0x000f0001 }, 3562 { 0x1004, 0, 0x00000000, 0x000f0001 },
3567 { 0x1044, 0, 0x00000000, 0xffc003ff },
3568 { 0x1080, 0, 0x00000000, 0x0001ffff },
3569 { 0x1084, 0, 0x00000000, 0xffffffff },
3570 { 0x1088, 0, 0x00000000, 0xffffffff },
3571 { 0x108c, 0, 0x00000000, 0xffffffff },
3572 { 0x1090, 0, 0x00000000, 0xffffffff },
3573 { 0x1094, 0, 0x00000000, 0xffffffff },
3574 { 0x1098, 0, 0x00000000, 0xffffffff },
3575 { 0x109c, 0, 0x00000000, 0xffffffff },
3576 { 0x10a0, 0, 0x00000000, 0xffffffff },
3577 3563
3578 { 0x1408, 0, 0x01c00800, 0x00000000 }, 3564 { 0x1408, 0, 0x01c00800, 0x00000000 },
3579 { 0x149c, 0, 0x8000ffff, 0x00000000 }, 3565 { 0x149c, 0, 0x8000ffff, 0x00000000 },
@@ -3585,111 +3571,9 @@ bnx2_test_registers(struct bnx2 *bp)
3585 { 0x14c4, 0, 0x00003fff, 0x00000000 }, 3571 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3586 { 0x14cc, 0, 0x00000000, 0x00000001 }, 3572 { 0x14cc, 0, 0x00000000, 0x00000001 },
3587 { 0x14d0, 0, 0xffffffff, 0x00000000 }, 3573 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3588 { 0x1500, 0, 0x00000000, 0xffffffff },
3589 { 0x1504, 0, 0x00000000, 0xffffffff },
3590 { 0x1508, 0, 0x00000000, 0xffffffff },
3591 { 0x150c, 0, 0x00000000, 0xffffffff },
3592 { 0x1510, 0, 0x00000000, 0xffffffff },
3593 { 0x1514, 0, 0x00000000, 0xffffffff },
3594 { 0x1518, 0, 0x00000000, 0xffffffff },
3595 { 0x151c, 0, 0x00000000, 0xffffffff },
3596 { 0x1520, 0, 0x00000000, 0xffffffff },
3597 { 0x1524, 0, 0x00000000, 0xffffffff },
3598 { 0x1528, 0, 0x00000000, 0xffffffff },
3599 { 0x152c, 0, 0x00000000, 0xffffffff },
3600 { 0x1530, 0, 0x00000000, 0xffffffff },
3601 { 0x1534, 0, 0x00000000, 0xffffffff },
3602 { 0x1538, 0, 0x00000000, 0xffffffff },
3603 { 0x153c, 0, 0x00000000, 0xffffffff },
3604 { 0x1540, 0, 0x00000000, 0xffffffff },
3605 { 0x1544, 0, 0x00000000, 0xffffffff },
3606 { 0x1548, 0, 0x00000000, 0xffffffff },
3607 { 0x154c, 0, 0x00000000, 0xffffffff },
3608 { 0x1550, 0, 0x00000000, 0xffffffff },
3609 { 0x1554, 0, 0x00000000, 0xffffffff },
3610 { 0x1558, 0, 0x00000000, 0xffffffff },
3611 { 0x1600, 0, 0x00000000, 0xffffffff },
3612 { 0x1604, 0, 0x00000000, 0xffffffff },
3613 { 0x1608, 0, 0x00000000, 0xffffffff },
3614 { 0x160c, 0, 0x00000000, 0xffffffff },
3615 { 0x1610, 0, 0x00000000, 0xffffffff },
3616 { 0x1614, 0, 0x00000000, 0xffffffff },
3617 { 0x1618, 0, 0x00000000, 0xffffffff },
3618 { 0x161c, 0, 0x00000000, 0xffffffff },
3619 { 0x1620, 0, 0x00000000, 0xffffffff },
3620 { 0x1624, 0, 0x00000000, 0xffffffff },
3621 { 0x1628, 0, 0x00000000, 0xffffffff },
3622 { 0x162c, 0, 0x00000000, 0xffffffff },
3623 { 0x1630, 0, 0x00000000, 0xffffffff },
3624 { 0x1634, 0, 0x00000000, 0xffffffff },
3625 { 0x1638, 0, 0x00000000, 0xffffffff },
3626 { 0x163c, 0, 0x00000000, 0xffffffff },
3627 { 0x1640, 0, 0x00000000, 0xffffffff },
3628 { 0x1644, 0, 0x00000000, 0xffffffff },
3629 { 0x1648, 0, 0x00000000, 0xffffffff },
3630 { 0x164c, 0, 0x00000000, 0xffffffff },
3631 { 0x1650, 0, 0x00000000, 0xffffffff },
3632 { 0x1654, 0, 0x00000000, 0xffffffff },
3633 3574
3634 { 0x1800, 0, 0x00000000, 0x00000001 }, 3575 { 0x1800, 0, 0x00000000, 0x00000001 },
3635 { 0x1804, 0, 0x00000000, 0x00000003 }, 3576 { 0x1804, 0, 0x00000000, 0x00000003 },
3636 { 0x1840, 0, 0x00000000, 0xffffffff },
3637 { 0x1844, 0, 0x00000000, 0xffffffff },
3638 { 0x1848, 0, 0x00000000, 0xffffffff },
3639 { 0x184c, 0, 0x00000000, 0xffffffff },
3640 { 0x1850, 0, 0x00000000, 0xffffffff },
3641 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3642 { 0x1904, 0, 0xffffffff, 0x00000000 },
3643 { 0x190c, 0, 0xffffffff, 0x00000000 },
3644 { 0x1914, 0, 0xffffffff, 0x00000000 },
3645 { 0x191c, 0, 0xffffffff, 0x00000000 },
3646 { 0x1924, 0, 0xffffffff, 0x00000000 },
3647 { 0x192c, 0, 0xffffffff, 0x00000000 },
3648 { 0x1934, 0, 0xffffffff, 0x00000000 },
3649 { 0x193c, 0, 0xffffffff, 0x00000000 },
3650 { 0x1944, 0, 0xffffffff, 0x00000000 },
3651 { 0x194c, 0, 0xffffffff, 0x00000000 },
3652 { 0x1954, 0, 0xffffffff, 0x00000000 },
3653 { 0x195c, 0, 0xffffffff, 0x00000000 },
3654 { 0x1964, 0, 0xffffffff, 0x00000000 },
3655 { 0x196c, 0, 0xffffffff, 0x00000000 },
3656 { 0x1974, 0, 0xffffffff, 0x00000000 },
3657 { 0x197c, 0, 0xffffffff, 0x00000000 },
3658 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3659
3660 { 0x1c00, 0, 0x00000000, 0x00000001 },
3661 { 0x1c04, 0, 0x00000000, 0x00000003 },
3662 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3663 { 0x1c40, 0, 0x00000000, 0xffffffff },
3664 { 0x1c44, 0, 0x00000000, 0xffffffff },
3665 { 0x1c48, 0, 0x00000000, 0xffffffff },
3666 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3667 { 0x1c50, 0, 0x00000000, 0xffffffff },
3668 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3669 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3670 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3671 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3672 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3673 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3674 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3675 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3676 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3677 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3678 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3679 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3680 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3681 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3682 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3683 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3684 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3685 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3686
3687 { 0x2004, 0, 0x00000000, 0x0337000f },
3688 { 0x2008, 0, 0xffffffff, 0x00000000 },
3689 { 0x200c, 0, 0xffffffff, 0x00000000 },
3690 { 0x2010, 0, 0xffffffff, 0x00000000 },
3691 { 0x2014, 0, 0x801fff80, 0x00000000 },
3692 { 0x2018, 0, 0x000003ff, 0x00000000 },
3693 3577
3694 { 0x2800, 0, 0x00000000, 0x00000001 }, 3578 { 0x2800, 0, 0x00000000, 0x00000001 },
3695 { 0x2804, 0, 0x00000000, 0x00003f01 }, 3579 { 0x2804, 0, 0x00000000, 0x00003f01 },
@@ -3707,16 +3591,6 @@ bnx2_test_registers(struct bnx2 *bp)
3707 { 0x2c00, 0, 0x00000000, 0x00000011 }, 3591 { 0x2c00, 0, 0x00000000, 0x00000011 },
3708 { 0x2c04, 0, 0x00000000, 0x00030007 }, 3592 { 0x2c04, 0, 0x00000000, 0x00030007 },
3709 3593
3710 { 0x3000, 0, 0x00000000, 0x00000001 },
3711 { 0x3004, 0, 0x00000000, 0x007007ff },
3712 { 0x3008, 0, 0x00000003, 0x00000000 },
3713 { 0x300c, 0, 0xffffffff, 0x00000000 },
3714 { 0x3010, 0, 0xffffffff, 0x00000000 },
3715 { 0x3014, 0, 0xffffffff, 0x00000000 },
3716 { 0x3034, 0, 0xffffffff, 0x00000000 },
3717 { 0x3038, 0, 0xffffffff, 0x00000000 },
3718 { 0x3050, 0, 0x00000001, 0x00000000 },
3719
3720 { 0x3c00, 0, 0x00000000, 0x00000001 }, 3594 { 0x3c00, 0, 0x00000000, 0x00000001 },
3721 { 0x3c04, 0, 0x00000000, 0x00070000 }, 3595 { 0x3c04, 0, 0x00000000, 0x00070000 },
3722 { 0x3c08, 0, 0x00007f71, 0x07f00000 }, 3596 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
@@ -3726,88 +3600,11 @@ bnx2_test_registers(struct bnx2 *bp)
3726 { 0x3c18, 0, 0x00000000, 0xffffffff }, 3600 { 0x3c18, 0, 0x00000000, 0xffffffff },
3727 { 0x3c1c, 0, 0xfffff000, 0x00000000 }, 3601 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3728 { 0x3c20, 0, 0xffffff00, 0x00000000 }, 3602 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3729 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3730 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3731 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3732 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3733 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3734 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3735 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3736 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3737 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3738 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3739 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3740 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3741 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3742 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3743 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3744 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3745 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3746 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3747 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3748 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3749 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3750 { 0x3c78, 0, 0x00000000, 0x00000000 },
3751 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3752 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3753 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3754 { 0x3c88, 0, 0x00000000, 0xffffffff },
3755 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3756
3757 { 0x4000, 0, 0x00000000, 0x00000001 },
3758 { 0x4004, 0, 0x00000000, 0x00030000 },
3759 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3760 { 0x400c, 0, 0xffffffff, 0x00000000 },
3761 { 0x4088, 0, 0x00000000, 0x00070303 },
3762
3763 { 0x4400, 0, 0x00000000, 0x00000001 },
3764 { 0x4404, 0, 0x00000000, 0x00003f01 },
3765 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3766 { 0x440c, 0, 0xffffffff, 0x00000000 },
3767 { 0x4410, 0, 0xffff, 0x0000 },
3768 { 0x4414, 0, 0xffff, 0x0000 },
3769 { 0x4418, 0, 0xffff, 0x0000 },
3770 { 0x441c, 0, 0xffff, 0x0000 },
3771 { 0x4428, 0, 0xffffffff, 0x00000000 },
3772 { 0x442c, 0, 0xffffffff, 0x00000000 },
3773 { 0x4430, 0, 0xffffffff, 0x00000000 },
3774 { 0x4434, 0, 0xffffffff, 0x00000000 },
3775 { 0x4438, 0, 0xffffffff, 0x00000000 },
3776 { 0x443c, 0, 0xffffffff, 0x00000000 },
3777 { 0x4440, 0, 0xffffffff, 0x00000000 },
3778 { 0x4444, 0, 0xffffffff, 0x00000000 },
3779
3780 { 0x4c00, 0, 0x00000000, 0x00000001 },
3781 { 0x4c04, 0, 0x00000000, 0x0000003f },
3782 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3783 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3784 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3785 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3786 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3787 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3788 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3789 { 0x4c50, 0, 0x00000000, 0xffffffff },
3790 3603
3791 { 0x5004, 0, 0x00000000, 0x0000007f }, 3604 { 0x5004, 0, 0x00000000, 0x0000007f },
3792 { 0x5008, 0, 0x0f0007ff, 0x00000000 }, 3605 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3793 { 0x500c, 0, 0xf800f800, 0x07ff07ff }, 3606 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3794 3607
3795 { 0x5400, 0, 0x00000008, 0x00000001 },
3796 { 0x5404, 0, 0x00000000, 0x0000003f },
3797 { 0x5408, 0, 0x0000001f, 0x00000000 },
3798 { 0x540c, 0, 0xffffffff, 0x00000000 },
3799 { 0x5410, 0, 0xffffffff, 0x00000000 },
3800 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3801 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3802 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3803 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3804 { 0x5428, 0, 0x000000ff, 0x00000000 },
3805 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3806 { 0x5430, 0, 0x001fff80, 0x00000000 },
3807 { 0x5438, 0, 0xffffffff, 0x00000000 },
3808 { 0x543c, 0, 0xffffffff, 0x00000000 },
3809 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3810
3811 { 0x5c00, 0, 0x00000000, 0x00000001 }, 3608 { 0x5c00, 0, 0x00000000, 0x00000001 },
3812 { 0x5c04, 0, 0x00000000, 0x0003000f }, 3609 { 0x5c04, 0, 0x00000000, 0x0003000f },
3813 { 0x5c08, 0, 0x00000003, 0x00000000 }, 3610 { 0x5c08, 0, 0x00000003, 0x00000000 },
@@ -4794,6 +4591,64 @@ bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4794 info->fw_version[5] = 0; 4591 info->fw_version[5] = 0;
4795} 4592}
4796 4593
4594#define BNX2_REGDUMP_LEN (32 * 1024)
4595
4596static int
4597bnx2_get_regs_len(struct net_device *dev)
4598{
4599 return BNX2_REGDUMP_LEN;
4600}
4601
4602static void
4603bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
4604{
4605 u32 *p = _p, i, offset;
4606 u8 *orig_p = _p;
4607 struct bnx2 *bp = netdev_priv(dev);
4608 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
4609 0x0800, 0x0880, 0x0c00, 0x0c10,
4610 0x0c30, 0x0d08, 0x1000, 0x101c,
4611 0x1040, 0x1048, 0x1080, 0x10a4,
4612 0x1400, 0x1490, 0x1498, 0x14f0,
4613 0x1500, 0x155c, 0x1580, 0x15dc,
4614 0x1600, 0x1658, 0x1680, 0x16d8,
4615 0x1800, 0x1820, 0x1840, 0x1854,
4616 0x1880, 0x1894, 0x1900, 0x1984,
4617 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
4618 0x1c80, 0x1c94, 0x1d00, 0x1d84,
4619 0x2000, 0x2030, 0x23c0, 0x2400,
4620 0x2800, 0x2820, 0x2830, 0x2850,
4621 0x2b40, 0x2c10, 0x2fc0, 0x3058,
4622 0x3c00, 0x3c94, 0x4000, 0x4010,
4623 0x4080, 0x4090, 0x43c0, 0x4458,
4624 0x4c00, 0x4c18, 0x4c40, 0x4c54,
4625 0x4fc0, 0x5010, 0x53c0, 0x5444,
4626 0x5c00, 0x5c18, 0x5c80, 0x5c90,
4627 0x5fc0, 0x6000, 0x6400, 0x6428,
4628 0x6800, 0x6848, 0x684c, 0x6860,
4629 0x6888, 0x6910, 0x8000 };
4630
4631 regs->version = 0;
4632
4633 memset(p, 0, BNX2_REGDUMP_LEN);
4634
4635 if (!netif_running(bp->dev))
4636 return;
4637
4638 i = 0;
4639 offset = reg_boundaries[0];
4640 p += offset;
4641 while (offset < BNX2_REGDUMP_LEN) {
4642 *p++ = REG_RD(bp, offset);
4643 offset += 4;
4644 if (offset == reg_boundaries[i + 1]) {
4645 offset = reg_boundaries[i + 2];
4646 p = (u32 *) (orig_p + offset);
4647 i += 2;
4648 }
4649 }
4650}
4651
4797static void 4652static void
4798bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4653bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4799{ 4654{
@@ -4979,7 +4834,7 @@ bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4979{ 4834{
4980 struct bnx2 *bp = netdev_priv(dev); 4835 struct bnx2 *bp = netdev_priv(dev);
4981 4836
4982 ering->rx_max_pending = MAX_RX_DESC_CNT; 4837 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
4983 ering->rx_mini_max_pending = 0; 4838 ering->rx_mini_max_pending = 0;
4984 ering->rx_jumbo_max_pending = 0; 4839 ering->rx_jumbo_max_pending = 0;
4985 4840
@@ -4996,17 +4851,28 @@ bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4996{ 4851{
4997 struct bnx2 *bp = netdev_priv(dev); 4852 struct bnx2 *bp = netdev_priv(dev);
4998 4853
4999 if ((ering->rx_pending > MAX_RX_DESC_CNT) || 4854 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
5000 (ering->tx_pending > MAX_TX_DESC_CNT) || 4855 (ering->tx_pending > MAX_TX_DESC_CNT) ||
5001 (ering->tx_pending <= MAX_SKB_FRAGS)) { 4856 (ering->tx_pending <= MAX_SKB_FRAGS)) {
5002 4857
5003 return -EINVAL; 4858 return -EINVAL;
5004 } 4859 }
5005 bp->rx_ring_size = ering->rx_pending; 4860 if (netif_running(bp->dev)) {
4861 bnx2_netif_stop(bp);
4862 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
4863 bnx2_free_skbs(bp);
4864 bnx2_free_mem(bp);
4865 }
4866
4867 bnx2_set_rx_ring_size(bp, ering->rx_pending);
5006 bp->tx_ring_size = ering->tx_pending; 4868 bp->tx_ring_size = ering->tx_pending;
5007 4869
5008 if (netif_running(bp->dev)) { 4870 if (netif_running(bp->dev)) {
5009 bnx2_netif_stop(bp); 4871 int rc;
4872
4873 rc = bnx2_alloc_mem(bp);
4874 if (rc)
4875 return rc;
5010 bnx2_init_nic(bp); 4876 bnx2_init_nic(bp);
5011 bnx2_netif_start(bp); 4877 bnx2_netif_start(bp);
5012 } 4878 }
@@ -5360,6 +5226,8 @@ static struct ethtool_ops bnx2_ethtool_ops = {
5360 .get_settings = bnx2_get_settings, 5226 .get_settings = bnx2_get_settings,
5361 .set_settings = bnx2_set_settings, 5227 .set_settings = bnx2_set_settings,
5362 .get_drvinfo = bnx2_get_drvinfo, 5228 .get_drvinfo = bnx2_get_drvinfo,
5229 .get_regs_len = bnx2_get_regs_len,
5230 .get_regs = bnx2_get_regs,
5363 .get_wol = bnx2_get_wol, 5231 .get_wol = bnx2_get_wol,
5364 .set_wol = bnx2_set_wol, 5232 .set_wol = bnx2_set_wol,
5365 .nway_reset = bnx2_nway_reset, 5233 .nway_reset = bnx2_nway_reset,
@@ -5678,7 +5546,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5678 bp->mac_addr[5] = (u8) reg; 5546 bp->mac_addr[5] = (u8) reg;
5679 5547
5680 bp->tx_ring_size = MAX_TX_DESC_CNT; 5548 bp->tx_ring_size = MAX_TX_DESC_CNT;
5681 bp->rx_ring_size = 100; 5549 bnx2_set_rx_ring_size(bp, 100);
5682 5550
5683 bp->rx_csum = 1; 5551 bp->rx_csum = 1;
5684 5552
@@ -5897,6 +5765,7 @@ bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5897 if (!netif_running(dev)) 5765 if (!netif_running(dev))
5898 return 0; 5766 return 0;
5899 5767
5768 flush_scheduled_work();
5900 bnx2_netif_stop(bp); 5769 bnx2_netif_stop(bp);
5901 netif_device_detach(dev); 5770 netif_device_detach(dev);
5902 del_timer_sync(&bp->timer); 5771 del_timer_sync(&bp->timer);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 11:36:56 -0500