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path: root/drivers/net/benet/be_cmds.c
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Diffstat (limited to 'drivers/net/benet/be_cmds.c')
-rw-r--r--drivers/net/benet/be_cmds.c649
1 files changed, 580 insertions, 69 deletions
diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c
index 28a0eda92680..d0ef4ac987cd 100644
--- a/drivers/net/benet/be_cmds.c
+++ b/drivers/net/benet/be_cmds.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2005 - 2009 ServerEngines 2 * Copyright (C) 2005 - 2010 ServerEngines
3 * All rights reserved. 3 * All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
@@ -71,8 +71,8 @@ static int be_mcc_compl_process(struct be_adapter *adapter,
71 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & 71 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
72 CQE_STATUS_EXTD_MASK; 72 CQE_STATUS_EXTD_MASK;
73 dev_warn(&adapter->pdev->dev, 73 dev_warn(&adapter->pdev->dev,
74 "Error in cmd completion: status(compl/extd)=%d/%d\n", 74 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
75 compl_status, extd_status); 75 compl->tag0, compl_status, extd_status);
76 } 76 }
77 return compl_status; 77 return compl_status;
78} 78}
@@ -104,10 +104,26 @@ static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
104 return NULL; 104 return NULL;
105} 105}
106 106
107int be_process_mcc(struct be_adapter *adapter) 107void be_async_mcc_enable(struct be_adapter *adapter)
108{
109 spin_lock_bh(&adapter->mcc_cq_lock);
110
111 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
112 adapter->mcc_obj.rearm_cq = true;
113
114 spin_unlock_bh(&adapter->mcc_cq_lock);
115}
116
117void be_async_mcc_disable(struct be_adapter *adapter)
118{
119 adapter->mcc_obj.rearm_cq = false;
120}
121
122int be_process_mcc(struct be_adapter *adapter, int *status)
108{ 123{
109 struct be_mcc_compl *compl; 124 struct be_mcc_compl *compl;
110 int num = 0, status = 0; 125 int num = 0;
126 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
111 127
112 spin_lock_bh(&adapter->mcc_cq_lock); 128 spin_lock_bh(&adapter->mcc_cq_lock);
113 while ((compl = be_mcc_compl_get(adapter))) { 129 while ((compl = be_mcc_compl_get(adapter))) {
@@ -119,31 +135,31 @@ int be_process_mcc(struct be_adapter *adapter)
119 be_async_link_state_process(adapter, 135 be_async_link_state_process(adapter,
120 (struct be_async_event_link_state *) compl); 136 (struct be_async_event_link_state *) compl);
121 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { 137 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
122 status = be_mcc_compl_process(adapter, compl); 138 *status = be_mcc_compl_process(adapter, compl);
123 atomic_dec(&adapter->mcc_obj.q.used); 139 atomic_dec(&mcc_obj->q.used);
124 } 140 }
125 be_mcc_compl_use(compl); 141 be_mcc_compl_use(compl);
126 num++; 142 num++;
127 } 143 }
128 144
129 if (num)
130 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, num);
131
132 spin_unlock_bh(&adapter->mcc_cq_lock); 145 spin_unlock_bh(&adapter->mcc_cq_lock);
133 return status; 146 return num;
134} 147}
135 148
136/* Wait till no more pending mcc requests are present */ 149/* Wait till no more pending mcc requests are present */
137static int be_mcc_wait_compl(struct be_adapter *adapter) 150static int be_mcc_wait_compl(struct be_adapter *adapter)
138{ 151{
139#define mcc_timeout 120000 /* 12s timeout */ 152#define mcc_timeout 120000 /* 12s timeout */
140 int i, status; 153 int i, num, status = 0;
154 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
155
141 for (i = 0; i < mcc_timeout; i++) { 156 for (i = 0; i < mcc_timeout; i++) {
142 status = be_process_mcc(adapter); 157 num = be_process_mcc(adapter, &status);
143 if (status) 158 if (num)
144 return status; 159 be_cq_notify(adapter, mcc_obj->cq.id,
160 mcc_obj->rearm_cq, num);
145 161
146 if (atomic_read(&adapter->mcc_obj.q.used) == 0) 162 if (atomic_read(&mcc_obj->q.used) == 0)
147 break; 163 break;
148 udelay(100); 164 udelay(100);
149 } 165 }
@@ -151,7 +167,7 @@ static int be_mcc_wait_compl(struct be_adapter *adapter)
151 dev_err(&adapter->pdev->dev, "mccq poll timed out\n"); 167 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
152 return -1; 168 return -1;
153 } 169 }
154 return 0; 170 return status;
155} 171}
156 172
157/* Notify MCC requests and wait for completion */ 173/* Notify MCC requests and wait for completion */
@@ -167,7 +183,14 @@ static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
167 u32 ready; 183 u32 ready;
168 184
169 do { 185 do {
170 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK; 186 ready = ioread32(db);
187 if (ready == 0xffffffff) {
188 dev_err(&adapter->pdev->dev,
189 "pci slot disconnected\n");
190 return -1;
191 }
192
193 ready &= MPU_MAILBOX_DB_RDY_MASK;
171 if (ready) 194 if (ready)
172 break; 195 break;
173 196
@@ -198,6 +221,11 @@ static int be_mbox_notify_wait(struct be_adapter *adapter)
198 struct be_mcc_mailbox *mbox = mbox_mem->va; 221 struct be_mcc_mailbox *mbox = mbox_mem->va;
199 struct be_mcc_compl *compl = &mbox->compl; 222 struct be_mcc_compl *compl = &mbox->compl;
200 223
224 /* wait for ready to be set */
225 status = be_mbox_db_ready_wait(adapter, db);
226 if (status != 0)
227 return status;
228
201 val |= MPU_MAILBOX_DB_HI_MASK; 229 val |= MPU_MAILBOX_DB_HI_MASK;
202 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ 230 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
203 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; 231 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
@@ -277,7 +305,7 @@ static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
277 305
278/* Don't touch the hdr after it's prepared */ 306/* Don't touch the hdr after it's prepared */
279static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, 307static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
280 bool embedded, u8 sge_cnt) 308 bool embedded, u8 sge_cnt, u32 opcode)
281{ 309{
282 if (embedded) 310 if (embedded)
283 wrb->embedded |= MCC_WRB_EMBEDDED_MASK; 311 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
@@ -285,7 +313,8 @@ static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
285 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << 313 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
286 MCC_WRB_SGE_CNT_SHIFT; 314 MCC_WRB_SGE_CNT_SHIFT;
287 wrb->payload_length = payload_len; 315 wrb->payload_length = payload_len;
288 be_dws_cpu_to_le(wrb, 20); 316 wrb->tag0 = opcode;
317 be_dws_cpu_to_le(wrb, 8);
289} 318}
290 319
291/* Don't touch the hdr after it's prepared */ 320/* Don't touch the hdr after it's prepared */
@@ -295,6 +324,7 @@ static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
295 req_hdr->opcode = opcode; 324 req_hdr->opcode = opcode;
296 req_hdr->subsystem = subsystem; 325 req_hdr->subsystem = subsystem;
297 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); 326 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
327 req_hdr->version = 0;
298} 328}
299 329
300static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, 330static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
@@ -349,7 +379,11 @@ static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
349 struct be_queue_info *mccq = &adapter->mcc_obj.q; 379 struct be_queue_info *mccq = &adapter->mcc_obj.q;
350 struct be_mcc_wrb *wrb; 380 struct be_mcc_wrb *wrb;
351 381
352 BUG_ON(atomic_read(&mccq->used) >= mccq->len); 382 if (atomic_read(&mccq->used) >= mccq->len) {
383 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
384 return NULL;
385 }
386
353 wrb = queue_head_node(mccq); 387 wrb = queue_head_node(mccq);
354 queue_head_inc(mccq); 388 queue_head_inc(mccq);
355 atomic_inc(&mccq->used); 389 atomic_inc(&mccq->used);
@@ -357,6 +391,60 @@ static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
357 return wrb; 391 return wrb;
358} 392}
359 393
394/* Tell fw we're about to start firing cmds by writing a
395 * special pattern across the wrb hdr; uses mbox
396 */
397int be_cmd_fw_init(struct be_adapter *adapter)
398{
399 u8 *wrb;
400 int status;
401
402 spin_lock(&adapter->mbox_lock);
403
404 wrb = (u8 *)wrb_from_mbox(adapter);
405 *wrb++ = 0xFF;
406 *wrb++ = 0x12;
407 *wrb++ = 0x34;
408 *wrb++ = 0xFF;
409 *wrb++ = 0xFF;
410 *wrb++ = 0x56;
411 *wrb++ = 0x78;
412 *wrb = 0xFF;
413
414 status = be_mbox_notify_wait(adapter);
415
416 spin_unlock(&adapter->mbox_lock);
417 return status;
418}
419
420/* Tell fw we're done with firing cmds by writing a
421 * special pattern across the wrb hdr; uses mbox
422 */
423int be_cmd_fw_clean(struct be_adapter *adapter)
424{
425 u8 *wrb;
426 int status;
427
428 if (adapter->eeh_err)
429 return -EIO;
430
431 spin_lock(&adapter->mbox_lock);
432
433 wrb = (u8 *)wrb_from_mbox(adapter);
434 *wrb++ = 0xFF;
435 *wrb++ = 0xAA;
436 *wrb++ = 0xBB;
437 *wrb++ = 0xFF;
438 *wrb++ = 0xFF;
439 *wrb++ = 0xCC;
440 *wrb++ = 0xDD;
441 *wrb = 0xFF;
442
443 status = be_mbox_notify_wait(adapter);
444
445 spin_unlock(&adapter->mbox_lock);
446 return status;
447}
360int be_cmd_eq_create(struct be_adapter *adapter, 448int be_cmd_eq_create(struct be_adapter *adapter,
361 struct be_queue_info *eq, int eq_delay) 449 struct be_queue_info *eq, int eq_delay)
362{ 450{
@@ -370,15 +458,13 @@ int be_cmd_eq_create(struct be_adapter *adapter,
370 wrb = wrb_from_mbox(adapter); 458 wrb = wrb_from_mbox(adapter);
371 req = embedded_payload(wrb); 459 req = embedded_payload(wrb);
372 460
373 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 461 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
374 462
375 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 463 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
376 OPCODE_COMMON_EQ_CREATE, sizeof(*req)); 464 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
377 465
378 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 466 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
379 467
380 AMAP_SET_BITS(struct amap_eq_context, func, req->context,
381 be_pci_func(adapter));
382 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); 468 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
383 /* 4byte eqe*/ 469 /* 4byte eqe*/
384 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); 470 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
@@ -414,7 +500,8 @@ int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
414 wrb = wrb_from_mbox(adapter); 500 wrb = wrb_from_mbox(adapter);
415 req = embedded_payload(wrb); 501 req = embedded_payload(wrb);
416 502
417 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 503 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
504 OPCODE_COMMON_NTWK_MAC_QUERY);
418 505
419 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 506 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
420 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req)); 507 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
@@ -448,9 +535,14 @@ int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
448 spin_lock_bh(&adapter->mcc_lock); 535 spin_lock_bh(&adapter->mcc_lock);
449 536
450 wrb = wrb_from_mccq(adapter); 537 wrb = wrb_from_mccq(adapter);
538 if (!wrb) {
539 status = -EBUSY;
540 goto err;
541 }
451 req = embedded_payload(wrb); 542 req = embedded_payload(wrb);
452 543
453 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 544 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
545 OPCODE_COMMON_NTWK_PMAC_ADD);
454 546
455 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 547 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
456 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req)); 548 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
@@ -464,6 +556,7 @@ int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
464 *pmac_id = le32_to_cpu(resp->pmac_id); 556 *pmac_id = le32_to_cpu(resp->pmac_id);
465 } 557 }
466 558
559err:
467 spin_unlock_bh(&adapter->mcc_lock); 560 spin_unlock_bh(&adapter->mcc_lock);
468 return status; 561 return status;
469} 562}
@@ -478,9 +571,14 @@ int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
478 spin_lock_bh(&adapter->mcc_lock); 571 spin_lock_bh(&adapter->mcc_lock);
479 572
480 wrb = wrb_from_mccq(adapter); 573 wrb = wrb_from_mccq(adapter);
574 if (!wrb) {
575 status = -EBUSY;
576 goto err;
577 }
481 req = embedded_payload(wrb); 578 req = embedded_payload(wrb);
482 579
483 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 580 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
581 OPCODE_COMMON_NTWK_PMAC_DEL);
484 582
485 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 583 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
486 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req)); 584 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
@@ -490,8 +588,8 @@ int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
490 588
491 status = be_mcc_notify_wait(adapter); 589 status = be_mcc_notify_wait(adapter);
492 590
591err:
493 spin_unlock_bh(&adapter->mcc_lock); 592 spin_unlock_bh(&adapter->mcc_lock);
494
495 return status; 593 return status;
496} 594}
497 595
@@ -512,7 +610,8 @@ int be_cmd_cq_create(struct be_adapter *adapter,
512 req = embedded_payload(wrb); 610 req = embedded_payload(wrb);
513 ctxt = &req->context; 611 ctxt = &req->context;
514 612
515 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 613 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
614 OPCODE_COMMON_CQ_CREATE);
516 615
517 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 616 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
518 OPCODE_COMMON_CQ_CREATE, sizeof(*req)); 617 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
@@ -528,7 +627,6 @@ int be_cmd_cq_create(struct be_adapter *adapter,
528 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); 627 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
529 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); 628 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
530 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); 629 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
531 AMAP_SET_BITS(struct amap_cq_context, func, ctxt, be_pci_func(adapter));
532 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 630 be_dws_cpu_to_le(ctxt, sizeof(req->context));
533 631
534 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 632 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
@@ -569,14 +667,14 @@ int be_cmd_mccq_create(struct be_adapter *adapter,
569 req = embedded_payload(wrb); 667 req = embedded_payload(wrb);
570 ctxt = &req->context; 668 ctxt = &req->context;
571 669
572 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 670 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
671 OPCODE_COMMON_MCC_CREATE);
573 672
574 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 673 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
575 OPCODE_COMMON_MCC_CREATE, sizeof(*req)); 674 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
576 675
577 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 676 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
578 677
579 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, be_pci_func(adapter));
580 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); 678 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
581 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, 679 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
582 be_encoded_q_len(mccq->len)); 680 be_encoded_q_len(mccq->len));
@@ -613,7 +711,8 @@ int be_cmd_txq_create(struct be_adapter *adapter,
613 req = embedded_payload(wrb); 711 req = embedded_payload(wrb);
614 ctxt = &req->context; 712 ctxt = &req->context;
615 713
616 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 714 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
715 OPCODE_ETH_TX_CREATE);
617 716
618 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE, 717 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
619 sizeof(*req)); 718 sizeof(*req));
@@ -624,8 +723,6 @@ int be_cmd_txq_create(struct be_adapter *adapter,
624 723
625 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, 724 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
626 be_encoded_q_len(txq->len)); 725 be_encoded_q_len(txq->len));
627 AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt,
628 be_pci_func(adapter));
629 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); 726 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
630 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); 727 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
631 728
@@ -660,7 +757,8 @@ int be_cmd_rxq_create(struct be_adapter *adapter,
660 wrb = wrb_from_mbox(adapter); 757 wrb = wrb_from_mbox(adapter);
661 req = embedded_payload(wrb); 758 req = embedded_payload(wrb);
662 759
663 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 760 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
761 OPCODE_ETH_RX_CREATE);
664 762
665 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE, 763 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
666 sizeof(*req)); 764 sizeof(*req));
@@ -696,13 +794,14 @@ int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
696 u8 subsys = 0, opcode = 0; 794 u8 subsys = 0, opcode = 0;
697 int status; 795 int status;
698 796
797 if (adapter->eeh_err)
798 return -EIO;
799
699 spin_lock(&adapter->mbox_lock); 800 spin_lock(&adapter->mbox_lock);
700 801
701 wrb = wrb_from_mbox(adapter); 802 wrb = wrb_from_mbox(adapter);
702 req = embedded_payload(wrb); 803 req = embedded_payload(wrb);
703 804
704 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
705
706 switch (queue_type) { 805 switch (queue_type) {
707 case QTYPE_EQ: 806 case QTYPE_EQ:
708 subsys = CMD_SUBSYSTEM_COMMON; 807 subsys = CMD_SUBSYSTEM_COMMON;
@@ -727,6 +826,9 @@ int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
727 default: 826 default:
728 BUG(); 827 BUG();
729 } 828 }
829
830 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
831
730 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); 832 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
731 req->id = cpu_to_le16(q->id); 833 req->id = cpu_to_le16(q->id);
732 834
@@ -752,7 +854,8 @@ int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
752 wrb = wrb_from_mbox(adapter); 854 wrb = wrb_from_mbox(adapter);
753 req = embedded_payload(wrb); 855 req = embedded_payload(wrb);
754 856
755 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 857 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
858 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
756 859
757 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 860 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
758 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req)); 861 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
@@ -782,12 +885,16 @@ int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
782 struct be_cmd_req_if_destroy *req; 885 struct be_cmd_req_if_destroy *req;
783 int status; 886 int status;
784 887
888 if (adapter->eeh_err)
889 return -EIO;
890
785 spin_lock(&adapter->mbox_lock); 891 spin_lock(&adapter->mbox_lock);
786 892
787 wrb = wrb_from_mbox(adapter); 893 wrb = wrb_from_mbox(adapter);
788 req = embedded_payload(wrb); 894 req = embedded_payload(wrb);
789 895
790 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 896 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
897 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
791 898
792 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 899 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
793 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req)); 900 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
@@ -810,15 +917,20 @@ int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
810 struct be_mcc_wrb *wrb; 917 struct be_mcc_wrb *wrb;
811 struct be_cmd_req_get_stats *req; 918 struct be_cmd_req_get_stats *req;
812 struct be_sge *sge; 919 struct be_sge *sge;
920 int status = 0;
813 921
814 spin_lock_bh(&adapter->mcc_lock); 922 spin_lock_bh(&adapter->mcc_lock);
815 923
816 wrb = wrb_from_mccq(adapter); 924 wrb = wrb_from_mccq(adapter);
925 if (!wrb) {
926 status = -EBUSY;
927 goto err;
928 }
817 req = nonemb_cmd->va; 929 req = nonemb_cmd->va;
818 sge = nonembedded_sgl(wrb); 930 sge = nonembedded_sgl(wrb);
819 931
820 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1); 932 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
821 wrb->tag0 = OPCODE_ETH_GET_STATISTICS; 933 OPCODE_ETH_GET_STATISTICS);
822 934
823 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 935 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
824 OPCODE_ETH_GET_STATISTICS, sizeof(*req)); 936 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
@@ -828,13 +940,14 @@ int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
828 940
829 be_mcc_notify(adapter); 941 be_mcc_notify(adapter);
830 942
943err:
831 spin_unlock_bh(&adapter->mcc_lock); 944 spin_unlock_bh(&adapter->mcc_lock);
832 return 0; 945 return status;
833} 946}
834 947
835/* Uses synchronous mcc */ 948/* Uses synchronous mcc */
836int be_cmd_link_status_query(struct be_adapter *adapter, 949int be_cmd_link_status_query(struct be_adapter *adapter,
837 bool *link_up) 950 bool *link_up, u8 *mac_speed, u16 *link_speed)
838{ 951{
839 struct be_mcc_wrb *wrb; 952 struct be_mcc_wrb *wrb;
840 struct be_cmd_req_link_status *req; 953 struct be_cmd_req_link_status *req;
@@ -843,11 +956,16 @@ int be_cmd_link_status_query(struct be_adapter *adapter,
843 spin_lock_bh(&adapter->mcc_lock); 956 spin_lock_bh(&adapter->mcc_lock);
844 957
845 wrb = wrb_from_mccq(adapter); 958 wrb = wrb_from_mccq(adapter);
959 if (!wrb) {
960 status = -EBUSY;
961 goto err;
962 }
846 req = embedded_payload(wrb); 963 req = embedded_payload(wrb);
847 964
848 *link_up = false; 965 *link_up = false;
849 966
850 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 967 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
968 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
851 969
852 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 970 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
853 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req)); 971 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
@@ -855,10 +973,14 @@ int be_cmd_link_status_query(struct be_adapter *adapter,
855 status = be_mcc_notify_wait(adapter); 973 status = be_mcc_notify_wait(adapter);
856 if (!status) { 974 if (!status) {
857 struct be_cmd_resp_link_status *resp = embedded_payload(wrb); 975 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
858 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) 976 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
859 *link_up = true; 977 *link_up = true;
978 *link_speed = le16_to_cpu(resp->link_speed);
979 *mac_speed = resp->mac_speed;
980 }
860 } 981 }
861 982
983err:
862 spin_unlock_bh(&adapter->mcc_lock); 984 spin_unlock_bh(&adapter->mcc_lock);
863 return status; 985 return status;
864} 986}
@@ -875,7 +997,8 @@ int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
875 wrb = wrb_from_mbox(adapter); 997 wrb = wrb_from_mbox(adapter);
876 req = embedded_payload(wrb); 998 req = embedded_payload(wrb);
877 999
878 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1000 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1001 OPCODE_COMMON_GET_FW_VERSION);
879 1002
880 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1003 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
881 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req)); 1004 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
@@ -897,13 +1020,19 @@ int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
897{ 1020{
898 struct be_mcc_wrb *wrb; 1021 struct be_mcc_wrb *wrb;
899 struct be_cmd_req_modify_eq_delay *req; 1022 struct be_cmd_req_modify_eq_delay *req;
1023 int status = 0;
900 1024
901 spin_lock_bh(&adapter->mcc_lock); 1025 spin_lock_bh(&adapter->mcc_lock);
902 1026
903 wrb = wrb_from_mccq(adapter); 1027 wrb = wrb_from_mccq(adapter);
1028 if (!wrb) {
1029 status = -EBUSY;
1030 goto err;
1031 }
904 req = embedded_payload(wrb); 1032 req = embedded_payload(wrb);
905 1033
906 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1034 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1035 OPCODE_COMMON_MODIFY_EQ_DELAY);
907 1036
908 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1037 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
909 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req)); 1038 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
@@ -915,8 +1044,9 @@ int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
915 1044
916 be_mcc_notify(adapter); 1045 be_mcc_notify(adapter);
917 1046
1047err:
918 spin_unlock_bh(&adapter->mcc_lock); 1048 spin_unlock_bh(&adapter->mcc_lock);
919 return 0; 1049 return status;
920} 1050}
921 1051
922/* Uses sycnhronous mcc */ 1052/* Uses sycnhronous mcc */
@@ -930,9 +1060,14 @@ int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
930 spin_lock_bh(&adapter->mcc_lock); 1060 spin_lock_bh(&adapter->mcc_lock);
931 1061
932 wrb = wrb_from_mccq(adapter); 1062 wrb = wrb_from_mccq(adapter);
1063 if (!wrb) {
1064 status = -EBUSY;
1065 goto err;
1066 }
933 req = embedded_payload(wrb); 1067 req = embedded_payload(wrb);
934 1068
935 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1069 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1070 OPCODE_COMMON_NTWK_VLAN_CONFIG);
936 1071
937 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1072 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
938 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req)); 1073 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
@@ -948,6 +1083,7 @@ int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
948 1083
949 status = be_mcc_notify_wait(adapter); 1084 status = be_mcc_notify_wait(adapter);
950 1085
1086err:
951 spin_unlock_bh(&adapter->mcc_lock); 1087 spin_unlock_bh(&adapter->mcc_lock);
952 return status; 1088 return status;
953} 1089}
@@ -964,9 +1100,13 @@ int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
964 spin_lock_bh(&adapter->mcc_lock); 1100 spin_lock_bh(&adapter->mcc_lock);
965 1101
966 wrb = wrb_from_mccq(adapter); 1102 wrb = wrb_from_mccq(adapter);
1103 if (!wrb) {
1104 status = -EBUSY;
1105 goto err;
1106 }
967 req = embedded_payload(wrb); 1107 req = embedded_payload(wrb);
968 1108
969 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1109 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
970 1110
971 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1111 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
972 OPCODE_ETH_PROMISCUOUS, sizeof(*req)); 1112 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
@@ -978,6 +1118,7 @@ int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
978 1118
979 status = be_mcc_notify_wait(adapter); 1119 status = be_mcc_notify_wait(adapter);
980 1120
1121err:
981 spin_unlock_bh(&adapter->mcc_lock); 1122 spin_unlock_bh(&adapter->mcc_lock);
982 return status; 1123 return status;
983} 1124}
@@ -987,40 +1128,51 @@ int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
987 * (mc == NULL) => multicast promiscous 1128 * (mc == NULL) => multicast promiscous
988 */ 1129 */
989int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id, 1130int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
990 struct dev_mc_list *mc_list, u32 mc_count) 1131 struct net_device *netdev, struct be_dma_mem *mem)
991{ 1132{
992#define BE_MAX_MC 32 /* set mcast promisc if > 32 */
993 struct be_mcc_wrb *wrb; 1133 struct be_mcc_wrb *wrb;
994 struct be_cmd_req_mcast_mac_config *req; 1134 struct be_cmd_req_mcast_mac_config *req = mem->va;
1135 struct be_sge *sge;
1136 int status;
995 1137
996 spin_lock_bh(&adapter->mcc_lock); 1138 spin_lock_bh(&adapter->mcc_lock);
997 1139
998 wrb = wrb_from_mccq(adapter); 1140 wrb = wrb_from_mccq(adapter);
999 req = embedded_payload(wrb); 1141 if (!wrb) {
1142 status = -EBUSY;
1143 goto err;
1144 }
1145 sge = nonembedded_sgl(wrb);
1146 memset(req, 0, sizeof(*req));
1000 1147
1001 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1148 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1149 OPCODE_COMMON_NTWK_MULTICAST_SET);
1150 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1151 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1152 sge->len = cpu_to_le32(mem->size);
1002 1153
1003 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1154 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1004 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req)); 1155 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1005 1156
1006 req->interface_id = if_id; 1157 req->interface_id = if_id;
1007 if (mc_list && mc_count <= BE_MAX_MC) { 1158 if (netdev) {
1008 int i; 1159 int i;
1009 struct dev_mc_list *mc; 1160 struct dev_mc_list *mc;
1010 1161
1011 req->num_mac = cpu_to_le16(mc_count); 1162 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1012 1163
1013 for (mc = mc_list, i = 0; mc; mc = mc->next, i++) 1164 i = 0;
1165 netdev_for_each_mc_addr(mc, netdev)
1014 memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN); 1166 memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN);
1015 } else { 1167 } else {
1016 req->promiscuous = 1; 1168 req->promiscuous = 1;
1017 } 1169 }
1018 1170
1019 be_mcc_notify_wait(adapter); 1171 status = be_mcc_notify_wait(adapter);
1020 1172
1173err:
1021 spin_unlock_bh(&adapter->mcc_lock); 1174 spin_unlock_bh(&adapter->mcc_lock);
1022 1175 return status;
1023 return 0;
1024} 1176}
1025 1177
1026/* Uses synchrounous mcc */ 1178/* Uses synchrounous mcc */
@@ -1033,9 +1185,14 @@ int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1033 spin_lock_bh(&adapter->mcc_lock); 1185 spin_lock_bh(&adapter->mcc_lock);
1034 1186
1035 wrb = wrb_from_mccq(adapter); 1187 wrb = wrb_from_mccq(adapter);
1188 if (!wrb) {
1189 status = -EBUSY;
1190 goto err;
1191 }
1036 req = embedded_payload(wrb); 1192 req = embedded_payload(wrb);
1037 1193
1038 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1194 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1195 OPCODE_COMMON_SET_FLOW_CONTROL);
1039 1196
1040 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1197 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1041 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req)); 1198 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
@@ -1045,6 +1202,7 @@ int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1045 1202
1046 status = be_mcc_notify_wait(adapter); 1203 status = be_mcc_notify_wait(adapter);
1047 1204
1205err:
1048 spin_unlock_bh(&adapter->mcc_lock); 1206 spin_unlock_bh(&adapter->mcc_lock);
1049 return status; 1207 return status;
1050} 1208}
@@ -1059,9 +1217,14 @@ int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1059 spin_lock_bh(&adapter->mcc_lock); 1217 spin_lock_bh(&adapter->mcc_lock);
1060 1218
1061 wrb = wrb_from_mccq(adapter); 1219 wrb = wrb_from_mccq(adapter);
1220 if (!wrb) {
1221 status = -EBUSY;
1222 goto err;
1223 }
1062 req = embedded_payload(wrb); 1224 req = embedded_payload(wrb);
1063 1225
1064 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1226 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1227 OPCODE_COMMON_GET_FLOW_CONTROL);
1065 1228
1066 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1229 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1067 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req)); 1230 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
@@ -1074,6 +1237,7 @@ int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1074 *rx_fc = le16_to_cpu(resp->rx_flow_control); 1237 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1075 } 1238 }
1076 1239
1240err:
1077 spin_unlock_bh(&adapter->mcc_lock); 1241 spin_unlock_bh(&adapter->mcc_lock);
1078 return status; 1242 return status;
1079} 1243}
@@ -1090,7 +1254,8 @@ int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap)
1090 wrb = wrb_from_mbox(adapter); 1254 wrb = wrb_from_mbox(adapter);
1091 req = embedded_payload(wrb); 1255 req = embedded_payload(wrb);
1092 1256
1093 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1257 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1258 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1094 1259
1095 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1260 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1096 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req)); 1261 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
@@ -1118,7 +1283,8 @@ int be_cmd_reset_function(struct be_adapter *adapter)
1118 wrb = wrb_from_mbox(adapter); 1283 wrb = wrb_from_mbox(adapter);
1119 req = embedded_payload(wrb); 1284 req = embedded_payload(wrb);
1120 1285
1121 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1286 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1287 OPCODE_COMMON_FUNCTION_RESET);
1122 1288
1123 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, 1289 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1124 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req)); 1290 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
@@ -1129,20 +1295,133 @@ int be_cmd_reset_function(struct be_adapter *adapter)
1129 return status; 1295 return status;
1130} 1296}
1131 1297
1298/* Uses sync mcc */
1299int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1300 u8 bcn, u8 sts, u8 state)
1301{
1302 struct be_mcc_wrb *wrb;
1303 struct be_cmd_req_enable_disable_beacon *req;
1304 int status;
1305
1306 spin_lock_bh(&adapter->mcc_lock);
1307
1308 wrb = wrb_from_mccq(adapter);
1309 if (!wrb) {
1310 status = -EBUSY;
1311 goto err;
1312 }
1313 req = embedded_payload(wrb);
1314
1315 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1316 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1317
1318 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1319 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1320
1321 req->port_num = port_num;
1322 req->beacon_state = state;
1323 req->beacon_duration = bcn;
1324 req->status_duration = sts;
1325
1326 status = be_mcc_notify_wait(adapter);
1327
1328err:
1329 spin_unlock_bh(&adapter->mcc_lock);
1330 return status;
1331}
1332
1333/* Uses sync mcc */
1334int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1335{
1336 struct be_mcc_wrb *wrb;
1337 struct be_cmd_req_get_beacon_state *req;
1338 int status;
1339
1340 spin_lock_bh(&adapter->mcc_lock);
1341
1342 wrb = wrb_from_mccq(adapter);
1343 if (!wrb) {
1344 status = -EBUSY;
1345 goto err;
1346 }
1347 req = embedded_payload(wrb);
1348
1349 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1350 OPCODE_COMMON_GET_BEACON_STATE);
1351
1352 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1353 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1354
1355 req->port_num = port_num;
1356
1357 status = be_mcc_notify_wait(adapter);
1358 if (!status) {
1359 struct be_cmd_resp_get_beacon_state *resp =
1360 embedded_payload(wrb);
1361 *state = resp->beacon_state;
1362 }
1363
1364err:
1365 spin_unlock_bh(&adapter->mcc_lock);
1366 return status;
1367}
1368
1369/* Uses sync mcc */
1370int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1371 u8 *connector)
1372{
1373 struct be_mcc_wrb *wrb;
1374 struct be_cmd_req_port_type *req;
1375 int status;
1376
1377 spin_lock_bh(&adapter->mcc_lock);
1378
1379 wrb = wrb_from_mccq(adapter);
1380 if (!wrb) {
1381 status = -EBUSY;
1382 goto err;
1383 }
1384 req = embedded_payload(wrb);
1385
1386 be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1387 OPCODE_COMMON_READ_TRANSRECV_DATA);
1388
1389 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1390 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1391
1392 req->port = cpu_to_le32(port);
1393 req->page_num = cpu_to_le32(TR_PAGE_A0);
1394 status = be_mcc_notify_wait(adapter);
1395 if (!status) {
1396 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1397 *connector = resp->data.connector;
1398 }
1399
1400err:
1401 spin_unlock_bh(&adapter->mcc_lock);
1402 return status;
1403}
1404
1132int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, 1405int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1133 u32 flash_type, u32 flash_opcode, u32 buf_size) 1406 u32 flash_type, u32 flash_opcode, u32 buf_size)
1134{ 1407{
1135 struct be_mcc_wrb *wrb; 1408 struct be_mcc_wrb *wrb;
1136 struct be_cmd_write_flashrom *req = cmd->va; 1409 struct be_cmd_write_flashrom *req;
1137 struct be_sge *sge; 1410 struct be_sge *sge;
1138 int status; 1411 int status;
1139 1412
1140 spin_lock_bh(&adapter->mcc_lock); 1413 spin_lock_bh(&adapter->mcc_lock);
1141 1414
1142 wrb = wrb_from_mccq(adapter); 1415 wrb = wrb_from_mccq(adapter);
1416 if (!wrb) {
1417 status = -EBUSY;
1418 goto err;
1419 }
1420 req = cmd->va;
1143 sge = nonembedded_sgl(wrb); 1421 sge = nonembedded_sgl(wrb);
1144 1422
1145 be_wrb_hdr_prepare(wrb, cmd->size, false, 1); 1423 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1424 OPCODE_COMMON_WRITE_FLASHROM);
1146 1425
1147 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1426 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1148 OPCODE_COMMON_WRITE_FLASHROM, cmd->size); 1427 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
@@ -1156,6 +1435,238 @@ int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1156 1435
1157 status = be_mcc_notify_wait(adapter); 1436 status = be_mcc_notify_wait(adapter);
1158 1437
1438err:
1439 spin_unlock_bh(&adapter->mcc_lock);
1440 return status;
1441}
1442
1443int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1444 int offset)
1445{
1446 struct be_mcc_wrb *wrb;
1447 struct be_cmd_write_flashrom *req;
1448 int status;
1449
1450 spin_lock_bh(&adapter->mcc_lock);
1451
1452 wrb = wrb_from_mccq(adapter);
1453 if (!wrb) {
1454 status = -EBUSY;
1455 goto err;
1456 }
1457 req = embedded_payload(wrb);
1458
1459 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1460 OPCODE_COMMON_READ_FLASHROM);
1461
1462 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1463 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1464
1465 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1466 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1467 req->params.offset = cpu_to_le32(offset);
1468 req->params.data_buf_size = cpu_to_le32(0x4);
1469
1470 status = be_mcc_notify_wait(adapter);
1471 if (!status)
1472 memcpy(flashed_crc, req->params.data_buf, 4);
1473
1474err:
1475 spin_unlock_bh(&adapter->mcc_lock);
1476 return status;
1477}
1478
1479extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1480 struct be_dma_mem *nonemb_cmd)
1481{
1482 struct be_mcc_wrb *wrb;
1483 struct be_cmd_req_acpi_wol_magic_config *req;
1484 struct be_sge *sge;
1485 int status;
1486
1487 spin_lock_bh(&adapter->mcc_lock);
1488
1489 wrb = wrb_from_mccq(adapter);
1490 if (!wrb) {
1491 status = -EBUSY;
1492 goto err;
1493 }
1494 req = nonemb_cmd->va;
1495 sge = nonembedded_sgl(wrb);
1496
1497 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1498 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1499
1500 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1501 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1502 memcpy(req->magic_mac, mac, ETH_ALEN);
1503
1504 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1505 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1506 sge->len = cpu_to_le32(nonemb_cmd->size);
1507
1508 status = be_mcc_notify_wait(adapter);
1509
1510err:
1511 spin_unlock_bh(&adapter->mcc_lock);
1512 return status;
1513}
1514
1515int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1516 u8 loopback_type, u8 enable)
1517{
1518 struct be_mcc_wrb *wrb;
1519 struct be_cmd_req_set_lmode *req;
1520 int status;
1521
1522 spin_lock_bh(&adapter->mcc_lock);
1523
1524 wrb = wrb_from_mccq(adapter);
1525 if (!wrb) {
1526 status = -EBUSY;
1527 goto err;
1528 }
1529
1530 req = embedded_payload(wrb);
1531
1532 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1533 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1534
1535 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1536 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1537 sizeof(*req));
1538
1539 req->src_port = port_num;
1540 req->dest_port = port_num;
1541 req->loopback_type = loopback_type;
1542 req->loopback_state = enable;
1543
1544 status = be_mcc_notify_wait(adapter);
1545err:
1546 spin_unlock_bh(&adapter->mcc_lock);
1547 return status;
1548}
1549
1550int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1551 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1552{
1553 struct be_mcc_wrb *wrb;
1554 struct be_cmd_req_loopback_test *req;
1555 int status;
1556
1557 spin_lock_bh(&adapter->mcc_lock);
1558
1559 wrb = wrb_from_mccq(adapter);
1560 if (!wrb) {
1561 status = -EBUSY;
1562 goto err;
1563 }
1564
1565 req = embedded_payload(wrb);
1566
1567 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1568 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1569
1570 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1571 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1572 req->hdr.timeout = 4;
1573
1574 req->pattern = cpu_to_le64(pattern);
1575 req->src_port = cpu_to_le32(port_num);
1576 req->dest_port = cpu_to_le32(port_num);
1577 req->pkt_size = cpu_to_le32(pkt_size);
1578 req->num_pkts = cpu_to_le32(num_pkts);
1579 req->loopback_type = cpu_to_le32(loopback_type);
1580
1581 status = be_mcc_notify_wait(adapter);
1582 if (!status) {
1583 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1584 status = le32_to_cpu(resp->status);
1585 }
1586
1587err:
1588 spin_unlock_bh(&adapter->mcc_lock);
1589 return status;
1590}
1591
1592int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1593 u32 byte_cnt, struct be_dma_mem *cmd)
1594{
1595 struct be_mcc_wrb *wrb;
1596 struct be_cmd_req_ddrdma_test *req;
1597 struct be_sge *sge;
1598 int status;
1599 int i, j = 0;
1600
1601 spin_lock_bh(&adapter->mcc_lock);
1602
1603 wrb = wrb_from_mccq(adapter);
1604 if (!wrb) {
1605 status = -EBUSY;
1606 goto err;
1607 }
1608 req = cmd->va;
1609 sge = nonembedded_sgl(wrb);
1610 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1611 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1612 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1613 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1614
1615 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1616 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1617 sge->len = cpu_to_le32(cmd->size);
1618
1619 req->pattern = cpu_to_le64(pattern);
1620 req->byte_count = cpu_to_le32(byte_cnt);
1621 for (i = 0; i < byte_cnt; i++) {
1622 req->snd_buff[i] = (u8)(pattern >> (j*8));
1623 j++;
1624 if (j > 7)
1625 j = 0;
1626 }
1627
1628 status = be_mcc_notify_wait(adapter);
1629
1630 if (!status) {
1631 struct be_cmd_resp_ddrdma_test *resp;
1632 resp = cmd->va;
1633 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1634 resp->snd_err) {
1635 status = -1;
1636 }
1637 }
1638
1639err:
1640 spin_unlock_bh(&adapter->mcc_lock);
1641 return status;
1642}
1643
1644extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1645 struct be_dma_mem *nonemb_cmd)
1646{
1647 struct be_mcc_wrb *wrb;
1648 struct be_cmd_req_seeprom_read *req;
1649 struct be_sge *sge;
1650 int status;
1651
1652 spin_lock_bh(&adapter->mcc_lock);
1653
1654 wrb = wrb_from_mccq(adapter);
1655 req = nonemb_cmd->va;
1656 sge = nonembedded_sgl(wrb);
1657
1658 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1659 OPCODE_COMMON_SEEPROM_READ);
1660
1661 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1662 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1663
1664 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1665 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1666 sge->len = cpu_to_le32(nonemb_cmd->size);
1667
1668 status = be_mcc_notify_wait(adapter);
1669
1159 spin_unlock_bh(&adapter->mcc_lock); 1670 spin_unlock_bh(&adapter->mcc_lock);
1160 return status; 1671 return status;
1161} 1672}