1 files changed, 94 insertions, 254 deletions

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 4d01cda68844..17f8518cc5eb 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -117,7 +117,7 @@ struct pxa3xx_nand_info {
         struct nand_chip        nand_chip;
 
         struct platform_device   *pdev;
-        const struct pxa3xx_nand_flash *flash_info;
+        struct pxa3xx_nand_cmdset *cmdset;
 
         struct clk              *clk;
         void __iomem            *mmio_base;
@@ -131,6 +131,7 @@ struct pxa3xx_nand_info {
         int                     drcmr_cmd;
 
         unsigned char           *data_buff;
+        unsigned char           *oob_buff;
         dma_addr_t              data_buff_phys;
         size_t                  data_buff_size;
         int                     data_dma_ch;
@@ -149,7 +150,8 @@ struct pxa3xx_nand_info {
         int                     use_ecc;        /* use HW ECC ? */
         int                     use_dma;        /* use DMA ? */
 
-        size_t                  data_size;      /* data size in FIFO */
+        unsigned int            page_size;      /* page size of attached chip */
+        unsigned int            data_size;      /* data size in FIFO */
         int                     retcode;
         struct completion       cmd_complete;
 
@@ -158,6 +160,10 @@ struct pxa3xx_nand_info {
         uint32_t                ndcb1;
         uint32_t                ndcb2;
 
+        /* timing calcuted from setting */
+        uint32_t                ndtr0cs0;
+        uint32_t                ndtr1cs0;
+
         /* calculated from pxa3xx_nand_flash data */
         size_t          oob_size;
         size_t          read_id_bytes;
@@ -174,23 +180,7 @@ MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
  * Default NAND flash controller configuration setup by the
  * bootloader. This configuration is used only when pdata->keep_config is set
  */
-static struct pxa3xx_nand_timing default_timing;
-static struct pxa3xx_nand_flash default_flash;
-
-static struct pxa3xx_nand_cmdset smallpage_cmdset = {
-        .read1          = 0x0000,
-        .read2          = 0x0050,
-        .program        = 0x1080,
-        .read_status    = 0x0070,
-        .read_id        = 0x0090,
-        .erase          = 0xD060,
-        .reset          = 0x00FF,
-        .lock           = 0x002A,
-        .unlock         = 0x2423,
-        .lock_status    = 0x007A,
-};
-
-static struct pxa3xx_nand_cmdset largepage_cmdset = {
+static struct pxa3xx_nand_cmdset default_cmdset = {
         .read1          = 0x3000,
         .read2          = 0x0050,
         .program        = 0x1080,
@@ -203,142 +193,27 @@ static struct pxa3xx_nand_cmdset largepage_cmdset = {
         .lock_status    = 0x007A,
 };
 
-#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
-static struct pxa3xx_nand_timing samsung512MbX16_timing = {
-        .tCH    = 10,
-        .tCS    = 0,
-        .tWH    = 20,
-        .tWP    = 40,
-        .tRH    = 30,
-        .tRP    = 40,
-        .tR     = 11123,
-        .tWHR   = 110,
-        .tAR    = 10,
-};
-
-static struct pxa3xx_nand_flash samsung512MbX16 = {
-        .timing         = &samsung512MbX16_timing,
-        .cmdset         = &smallpage_cmdset,
-        .page_per_block = 32,
-        .page_size      = 512,
-        .flash_width    = 16,
-        .dfc_width      = 16,
-        .num_blocks     = 4096,
-        .chip_id        = 0x46ec,
-};
-
-static struct pxa3xx_nand_flash samsung2GbX8 = {
-        .timing         = &samsung512MbX16_timing,
-        .cmdset         = &smallpage_cmdset,
-        .page_per_block = 64,
-        .page_size      = 2048,
-        .flash_width    = 8,
-        .dfc_width      = 8,
-        .num_blocks     = 2048,
-        .chip_id        = 0xdaec,
+static struct pxa3xx_nand_timing timing[] = {
+        { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
+        { 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
+        { 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
+        { 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
 };
 
-static struct pxa3xx_nand_flash samsung32GbX8 = {
-        .timing         = &samsung512MbX16_timing,
-        .cmdset         = &smallpage_cmdset,
-        .page_per_block = 128,
-        .page_size      = 4096,
-        .flash_width    = 8,
-        .dfc_width      = 8,
-        .num_blocks     = 8192,
-        .chip_id        = 0xd7ec,
+static struct pxa3xx_nand_flash builtin_flash_types[] = {
+        {      0,   0, 2048,  8,  8,    0, &default_cmdset, &timing[0] },
+        { 0x46ec,  32,  512, 16, 16, 4096, &default_cmdset, &timing[1] },
+        { 0xdaec,  64, 2048,  8,  8, 2048, &default_cmdset, &timing[1] },
+        { 0xd7ec, 128, 4096,  8,  8, 8192, &default_cmdset, &timing[1] },
+        { 0xa12c,  64, 2048,  8,  8, 1024, &default_cmdset, &timing[2] },
+        { 0xb12c,  64, 2048, 16, 16, 1024, &default_cmdset, &timing[2] },
+        { 0xdc2c,  64, 2048,  8,  8, 4096, &default_cmdset, &timing[2] },
+        { 0xcc2c,  64, 2048, 16, 16, 4096, &default_cmdset, &timing[2] },
+        { 0xba20,  64, 2048, 16, 16, 2048, &default_cmdset, &timing[3] },
 };
 
-static struct pxa3xx_nand_timing micron_timing = {
-        .tCH    = 10,
-        .tCS    = 25,
-        .tWH    = 15,
-        .tWP    = 25,
-        .tRH    = 15,
-        .tRP    = 30,
-        .tR     = 25000,
-        .tWHR   = 60,
-        .tAR    = 10,
-};
-
-static struct pxa3xx_nand_flash micron1GbX8 = {
-        .timing         = &micron_timing,
-        .cmdset         = &largepage_cmdset,
-        .page_per_block = 64,
-        .page_size      = 2048,
-        .flash_width    = 8,
-        .dfc_width      = 8,
-        .num_blocks     = 1024,
-        .chip_id        = 0xa12c,
-};
-
-static struct pxa3xx_nand_flash micron1GbX16 = {
-        .timing         = &micron_timing,
-        .cmdset         = &largepage_cmdset,
-        .page_per_block = 64,
-        .page_size      = 2048,
-        .flash_width    = 16,
-        .dfc_width      = 16,
-        .num_blocks     = 1024,
-        .chip_id        = 0xb12c,
-};
-
-static struct pxa3xx_nand_flash micron4GbX8 = {
-        .timing         = &micron_timing,
-        .cmdset         = &largepage_cmdset,
-        .page_per_block = 64,
-        .page_size      = 2048,
-        .flash_width    = 8,
-        .dfc_width      = 8,
-        .num_blocks     = 4096,
-        .chip_id        = 0xdc2c,
-};
-
-static struct pxa3xx_nand_flash micron4GbX16 = {
-        .timing         = &micron_timing,
-        .cmdset         = &largepage_cmdset,
-        .page_per_block = 64,
-        .page_size      = 2048,
-        .flash_width    = 16,
-        .dfc_width      = 16,
-        .num_blocks     = 4096,
-        .chip_id        = 0xcc2c,
-};
-
-static struct pxa3xx_nand_timing stm2GbX16_timing = {
-        .tCH = 10,
-        .tCS = 35,
-        .tWH = 15,
-        .tWP = 25,
-        .tRH = 15,
-        .tRP = 25,
-        .tR = 25000,
-        .tWHR = 60,
-        .tAR = 10,
-};
-
-static struct pxa3xx_nand_flash stm2GbX16 = {
-        .timing = &stm2GbX16_timing,
-        .cmdset = &largepage_cmdset,
-        .page_per_block = 64,
-        .page_size = 2048,
-        .flash_width = 16,
-        .dfc_width = 16,
-        .num_blocks = 2048,
-        .chip_id = 0xba20,
-};
-
-static struct pxa3xx_nand_flash *builtin_flash_types[] = {
-        &samsung512MbX16,
-        &samsung2GbX8,
-        &samsung32GbX8,
-        &micron1GbX8,
-        &micron1GbX16,
-        &micron4GbX8,
-        &micron4GbX16,
-        &stm2GbX16,
-};
-#endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
+/* Define a default flash type setting serve as flash detecting only */
+#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
 
 #define NDTR0_tCH(c)    (min((c), 7) << 19)
 #define NDTR0_tCS(c)    (min((c), 7) << 16)
@@ -351,23 +226,9 @@ static struct pxa3xx_nand_flash *builtin_flash_types[] = {
 #define NDTR1_tWHR(c)   (min((c), 15) << 4)
 #define NDTR1_tAR(c)    (min((c), 15) << 0)
 
-#define tCH_NDTR0(r)    (((r) >> 19) & 0x7)
-#define tCS_NDTR0(r)    (((r) >> 16) & 0x7)
-#define tWH_NDTR0(r)    (((r) >> 11) & 0x7)
-#define tWP_NDTR0(r)    (((r) >> 8) & 0x7)
-#define tRH_NDTR0(r)    (((r) >> 3) & 0x7)
-#define tRP_NDTR0(r)    (((r) >> 0) & 0x7)
-
-#define tR_NDTR1(r)     (((r) >> 16) & 0xffff)
-#define tWHR_NDTR1(r)   (((r) >> 4) & 0xf)
-#define tAR_NDTR1(r)    (((r) >> 0) & 0xf)
-
 /* convert nano-seconds to nand flash controller clock cycles */
 #define ns2cycle(ns, clk)       (int)((ns) * (clk / 1000000) / 1000)
 
-/* convert nand flash controller clock cycles to nano-seconds */
-#define cycle2ns(c, clk)        ((((c) + 1) * 1000000 + clk / 500) / (clk / 1000))
-
 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
                                    const struct pxa3xx_nand_timing *t)
 {
@@ -385,6 +246,8 @@ static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
 
+        info->ndtr0cs0 = ndtr0;
+        info->ndtr1cs0 = ndtr1;
         nand_writel(info, NDTR0CS0, ndtr0);
         nand_writel(info, NDTR1CS0, ndtr1);
 }
@@ -408,23 +271,31 @@ static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
         return -ETIMEDOUT;
 }
 
-static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
-                        uint16_t cmd, int column, int page_addr)
+static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 {
-        const struct pxa3xx_nand_flash *f = info->flash_info;
-        const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
+        int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
 
-        /* calculate data size */
-        switch (f->page_size) {
+        info->data_size = info->page_size;
+        if (!oob_enable) {
+                info->oob_size = 0;
+                return;
+        }
+
+        switch (info->page_size) {
         case 2048:
-                info->data_size = (info->use_ecc) ? 2088 : 2112;
+                info->oob_size = (info->use_ecc) ? 40 : 64;
                 break;
         case 512:
-                info->data_size = (info->use_ecc) ? 520 : 528;
+                info->oob_size = (info->use_ecc) ? 8 : 16;
                 break;
-        default:
-                return -EINVAL;
         }
+}
+
+static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
+                uint16_t cmd, int column, int page_addr)
+{
+        const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
+        pxa3xx_set_datasize(info);
 
         /* generate values for NDCBx registers */
         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
@@ -463,12 +334,13 @@ static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
 
 static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
 {
-        const struct pxa3xx_nand_cmdset *cmdset = info->flash_info->cmdset;
+        const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
 
         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
         info->ndcb1 = 0;
         info->ndcb2 = 0;
 
+        info->oob_size = 0;
         if (cmd == cmdset->read_id) {
                 info->ndcb0 |= NDCB0_CMD_TYPE(3);
                 info->data_size = 8;
@@ -537,6 +409,9 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
         case STATE_PIO_WRITING:
                 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
                                 DIV_ROUND_UP(info->data_size, 4));
+                if (info->oob_size > 0)
+                        __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
+                                        DIV_ROUND_UP(info->oob_size, 4));
 
                 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
 
@@ -549,6 +424,9 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
         case STATE_PIO_READING:
                 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
                                 DIV_ROUND_UP(info->data_size, 4));
+                if (info->oob_size > 0)
+                        __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
+                                        DIV_ROUND_UP(info->oob_size, 4));
                 break;
         default:
                 printk(KERN_ERR "%s: invalid state %d\n", __func__,
@@ -563,7 +441,7 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
 static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
 {
         struct pxa_dma_desc *desc = info->data_desc;
-        int dma_len = ALIGN(info->data_size, 32);
+        int dma_len = ALIGN(info->data_size + info->oob_size, 32);
 
         desc->ddadr = DDADR_STOP;
         desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
@@ -700,8 +578,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
                                 int column, int page_addr)
 {
         struct pxa3xx_nand_info *info = mtd->priv;
-        const struct pxa3xx_nand_flash *flash_info = info->flash_info;
-        const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset;
+        const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
         int ret;
 
         info->use_dma = (use_dma) ? 1 : 0;
@@ -925,8 +802,7 @@ static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
 
 static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
 {
-        const struct pxa3xx_nand_flash *f = info->flash_info;
-        const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
+        const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
         uint32_t ndcr;
         uint8_t  id_buff[8];
 
@@ -968,7 +844,9 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
                 return -EINVAL;
 
         /* calculate flash information */
-        info->oob_size = (f->page_size == 2048) ? 64 : 16;
+        info->cmdset = f->cmdset;
+        info->page_size = f->page_size;
+        info->oob_buff = info->data_buff + f->page_size;
         info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
 
         /* calculate addressing information */
@@ -992,49 +870,20 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
         info->reg_ndcr = ndcr;
 
         pxa3xx_nand_set_timing(info, f->timing);
-        info->flash_info = f;
         return 0;
 }
 
-static void pxa3xx_nand_detect_timing(struct pxa3xx_nand_info *info,
-                                      struct pxa3xx_nand_timing *t)
-{
-        unsigned long nand_clk = clk_get_rate(info->clk);
-        uint32_t ndtr0 = nand_readl(info, NDTR0CS0);
-        uint32_t ndtr1 = nand_readl(info, NDTR1CS0);
-
-        t->tCH = cycle2ns(tCH_NDTR0(ndtr0), nand_clk);
-        t->tCS = cycle2ns(tCS_NDTR0(ndtr0), nand_clk);
-        t->tWH = cycle2ns(tWH_NDTR0(ndtr0), nand_clk);
-        t->tWP = cycle2ns(tWP_NDTR0(ndtr0), nand_clk);
-        t->tRH = cycle2ns(tRH_NDTR0(ndtr0), nand_clk);
-        t->tRP = cycle2ns(tRP_NDTR0(ndtr0), nand_clk);
-
-        t->tR = cycle2ns(tR_NDTR1(ndtr1), nand_clk);
-        t->tWHR = cycle2ns(tWHR_NDTR1(ndtr1), nand_clk);
-        t->tAR = cycle2ns(tAR_NDTR1(ndtr1), nand_clk);
-}
-
 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 {
         uint32_t ndcr = nand_readl(info, NDCR);
         struct nand_flash_dev *type = NULL;
-        uint32_t id = -1;
+        uint32_t id = -1, page_per_block, num_blocks;
         int i;
 
-        default_flash.page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
-        default_flash.page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
-        default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;
-        default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;
-
-        if (default_flash.page_size == 2048)
-                default_flash.cmdset = &largepage_cmdset;
-        else
-                default_flash.cmdset = &smallpage_cmdset;
-
+        page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
+        info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
         /* set info fields needed to __readid */
-        info->flash_info = &default_flash;
-        info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
+        info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
         info->reg_ndcr = ndcr;
 
         if (__readid(info, &id))
@@ -1053,21 +902,20 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
                 return -ENODEV;
 
         /* fill the missing flash information */
-        i = __ffs(default_flash.page_per_block * default_flash.page_size);
-        default_flash.num_blocks = type->chipsize << (20 - i);
-
-        info->oob_size = (default_flash.page_size == 2048) ? 64 : 16;
+        i = __ffs(page_per_block * info->page_size);
+        num_blocks = type->chipsize << (20 - i);
 
         /* calculate addressing information */
-        info->col_addr_cycles = (default_flash.page_size == 2048) ? 2 : 1;
+        info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;
 
-        if (default_flash.num_blocks * default_flash.page_per_block > 65536)
+        if (num_blocks * page_per_block > 65536)
                 info->row_addr_cycles = 3;
         else
                 info->row_addr_cycles = 2;
 
-        pxa3xx_nand_detect_timing(info, &default_timing);
-        default_flash.timing = &default_timing;
+        info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
+        info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
+        info->cmdset = &default_cmdset;
 
         return 0;
 }
@@ -1083,38 +931,29 @@ static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
                 if (pxa3xx_nand_detect_config(info) == 0)
                         return 0;
 
-        for (i = 0; i<pdata->num_flash; ++i) {
-                f = pdata->flash + i;
-
-                if (pxa3xx_nand_config_flash(info, f))
-                        continue;
-
-                if (__readid(info, &id))
-                        continue;
-
-                if (id == f->chip_id)
-                        return 0;
-        }
-
-#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
-        for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
-
-                f = builtin_flash_types[i];
-
-                if (pxa3xx_nand_config_flash(info, f))
-                        continue;
-
-                if (__readid(info, &id))
-                        continue;
-
-                if (id == f->chip_id)
+        /* we use default timing to detect id */
+        f = DEFAULT_FLASH_TYPE;
+        pxa3xx_nand_config_flash(info, f);
+        if (__readid(info, &id))
+                goto fail_detect;
+
+        for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
+                /* we first choose the flash definition from platfrom */
+                if (i < pdata->num_flash)
+                        f = pdata->flash + i;
+                else
+                        f = &builtin_flash_types[i - pdata->num_flash + 1];
+                if (f->chip_id == id) {
+                        dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
+                        pxa3xx_nand_config_flash(info, f);
                         return 0;
+                }
         }
-#endif
 
         dev_warn(&info->pdev->dev,
                  "failed to detect configured nand flash; found %04x instead of\n",
                  id);
+fail_detect:
         return -ENODEV;
 }
 
@@ -1177,10 +1016,9 @@ static struct nand_ecclayout hw_largepage_ecclayout = {
 static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
                                  struct pxa3xx_nand_info *info)
 {
-        const struct pxa3xx_nand_flash *f = info->flash_info;
         struct nand_chip *this = &info->nand_chip;
 
-        this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
+        this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
 
         this->waitfunc          = pxa3xx_nand_waitfunc;
         this->select_chip       = pxa3xx_nand_select_chip;
@@ -1196,9 +1034,9 @@ static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
         this->ecc.hwctl         = pxa3xx_nand_ecc_hwctl;
         this->ecc.calculate     = pxa3xx_nand_ecc_calculate;
         this->ecc.correct       = pxa3xx_nand_ecc_correct;
-        this->ecc.size          = f->page_size;
+        this->ecc.size          = info->page_size;
 
-        if (f->page_size == 2048)
+        if (info->page_size == 2048)
                 this->ecc.layout = &hw_largepage_ecclayout;
         else
                 this->ecc.layout = &hw_smallpage_ecclayout;
@@ -1411,9 +1249,11 @@ static int pxa3xx_nand_resume(struct platform_device *pdev)
         struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
         struct pxa3xx_nand_info *info = mtd->priv;
 
+        nand_writel(info, NDTR0CS0, info->ndtr0cs0);
+        nand_writel(info, NDTR1CS0, info->ndtr1cs0);
         clk_enable(info->clk);
 
-        return pxa3xx_nand_config_flash(info, info->flash_info);
+        return 0;
 }
 #else
 #define pxa3xx_nand_suspend     NULL