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path: root/drivers/mtd/nand/fsl_elbc_nand.c
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Diffstat (limited to 'drivers/mtd/nand/fsl_elbc_nand.c')
-rw-r--r--drivers/mtd/nand/fsl_elbc_nand.c219
1 files changed, 12 insertions, 207 deletions
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index b025dfe0b274..378b7aa63812 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -36,207 +36,12 @@
36#include <linux/mtd/partitions.h> 36#include <linux/mtd/partitions.h>
37 37
38#include <asm/io.h> 38#include <asm/io.h>
39 39#include <asm/fsl_lbc.h>
40 40
41#define MAX_BANKS 8 41#define MAX_BANKS 8
42#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ 42#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
43#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */ 43#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
44 44
45struct elbc_bank {
46 __be32 br; /**< Base Register */
47#define BR_BA 0xFFFF8000
48#define BR_BA_SHIFT 15
49#define BR_PS 0x00001800
50#define BR_PS_SHIFT 11
51#define BR_PS_8 0x00000800 /* Port Size 8 bit */
52#define BR_PS_16 0x00001000 /* Port Size 16 bit */
53#define BR_PS_32 0x00001800 /* Port Size 32 bit */
54#define BR_DECC 0x00000600
55#define BR_DECC_SHIFT 9
56#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
57#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
58#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
59#define BR_WP 0x00000100
60#define BR_WP_SHIFT 8
61#define BR_MSEL 0x000000E0
62#define BR_MSEL_SHIFT 5
63#define BR_MS_GPCM 0x00000000 /* GPCM */
64#define BR_MS_FCM 0x00000020 /* FCM */
65#define BR_MS_SDRAM 0x00000060 /* SDRAM */
66#define BR_MS_UPMA 0x00000080 /* UPMA */
67#define BR_MS_UPMB 0x000000A0 /* UPMB */
68#define BR_MS_UPMC 0x000000C0 /* UPMC */
69#define BR_V 0x00000001
70#define BR_V_SHIFT 0
71#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
72
73 __be32 or; /**< Base Register */
74#define OR0 0x5004
75#define OR1 0x500C
76#define OR2 0x5014
77#define OR3 0x501C
78#define OR4 0x5024
79#define OR5 0x502C
80#define OR6 0x5034
81#define OR7 0x503C
82
83#define OR_FCM_AM 0xFFFF8000
84#define OR_FCM_AM_SHIFT 15
85#define OR_FCM_BCTLD 0x00001000
86#define OR_FCM_BCTLD_SHIFT 12
87#define OR_FCM_PGS 0x00000400
88#define OR_FCM_PGS_SHIFT 10
89#define OR_FCM_CSCT 0x00000200
90#define OR_FCM_CSCT_SHIFT 9
91#define OR_FCM_CST 0x00000100
92#define OR_FCM_CST_SHIFT 8
93#define OR_FCM_CHT 0x00000080
94#define OR_FCM_CHT_SHIFT 7
95#define OR_FCM_SCY 0x00000070
96#define OR_FCM_SCY_SHIFT 4
97#define OR_FCM_SCY_1 0x00000010
98#define OR_FCM_SCY_2 0x00000020
99#define OR_FCM_SCY_3 0x00000030
100#define OR_FCM_SCY_4 0x00000040
101#define OR_FCM_SCY_5 0x00000050
102#define OR_FCM_SCY_6 0x00000060
103#define OR_FCM_SCY_7 0x00000070
104#define OR_FCM_RST 0x00000008
105#define OR_FCM_RST_SHIFT 3
106#define OR_FCM_TRLX 0x00000004
107#define OR_FCM_TRLX_SHIFT 2
108#define OR_FCM_EHTR 0x00000002
109#define OR_FCM_EHTR_SHIFT 1
110};
111
112struct elbc_regs {
113 struct elbc_bank bank[8];
114 u8 res0[0x28];
115 __be32 mar; /**< UPM Address Register */
116 u8 res1[0x4];
117 __be32 mamr; /**< UPMA Mode Register */
118 __be32 mbmr; /**< UPMB Mode Register */
119 __be32 mcmr; /**< UPMC Mode Register */
120 u8 res2[0x8];
121 __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
122 __be32 mdr; /**< UPM Data Register */
123 u8 res3[0x4];
124 __be32 lsor; /**< Special Operation Initiation Register */
125 __be32 lsdmr; /**< SDRAM Mode Register */
126 u8 res4[0x8];
127 __be32 lurt; /**< UPM Refresh Timer */
128 __be32 lsrt; /**< SDRAM Refresh Timer */
129 u8 res5[0x8];
130 __be32 ltesr; /**< Transfer Error Status Register */
131#define LTESR_BM 0x80000000
132#define LTESR_FCT 0x40000000
133#define LTESR_PAR 0x20000000
134#define LTESR_WP 0x04000000
135#define LTESR_ATMW 0x00800000
136#define LTESR_ATMR 0x00400000
137#define LTESR_CS 0x00080000
138#define LTESR_CC 0x00000001
139#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
140 __be32 ltedr; /**< Transfer Error Disable Register */
141 __be32 lteir; /**< Transfer Error Interrupt Register */
142 __be32 lteatr; /**< Transfer Error Attributes Register */
143 __be32 ltear; /**< Transfer Error Address Register */
144 u8 res6[0xC];
145 __be32 lbcr; /**< Configuration Register */
146#define LBCR_LDIS 0x80000000
147#define LBCR_LDIS_SHIFT 31
148#define LBCR_BCTLC 0x00C00000
149#define LBCR_BCTLC_SHIFT 22
150#define LBCR_AHD 0x00200000
151#define LBCR_LPBSE 0x00020000
152#define LBCR_LPBSE_SHIFT 17
153#define LBCR_EPAR 0x00010000
154#define LBCR_EPAR_SHIFT 16
155#define LBCR_BMT 0x0000FF00
156#define LBCR_BMT_SHIFT 8
157#define LBCR_INIT 0x00040000
158 __be32 lcrr; /**< Clock Ratio Register */
159#define LCRR_DBYP 0x80000000
160#define LCRR_DBYP_SHIFT 31
161#define LCRR_BUFCMDC 0x30000000
162#define LCRR_BUFCMDC_SHIFT 28
163#define LCRR_ECL 0x03000000
164#define LCRR_ECL_SHIFT 24
165#define LCRR_EADC 0x00030000
166#define LCRR_EADC_SHIFT 16
167#define LCRR_CLKDIV 0x0000000F
168#define LCRR_CLKDIV_SHIFT 0
169 u8 res7[0x8];
170 __be32 fmr; /**< Flash Mode Register */
171#define FMR_CWTO 0x0000F000
172#define FMR_CWTO_SHIFT 12
173#define FMR_BOOT 0x00000800
174#define FMR_ECCM 0x00000100
175#define FMR_AL 0x00000030
176#define FMR_AL_SHIFT 4
177#define FMR_OP 0x00000003
178#define FMR_OP_SHIFT 0
179 __be32 fir; /**< Flash Instruction Register */
180#define FIR_OP0 0xF0000000
181#define FIR_OP0_SHIFT 28
182#define FIR_OP1 0x0F000000
183#define FIR_OP1_SHIFT 24
184#define FIR_OP2 0x00F00000
185#define FIR_OP2_SHIFT 20
186#define FIR_OP3 0x000F0000
187#define FIR_OP3_SHIFT 16
188#define FIR_OP4 0x0000F000
189#define FIR_OP4_SHIFT 12
190#define FIR_OP5 0x00000F00
191#define FIR_OP5_SHIFT 8
192#define FIR_OP6 0x000000F0
193#define FIR_OP6_SHIFT 4
194#define FIR_OP7 0x0000000F
195#define FIR_OP7_SHIFT 0
196#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
197#define FIR_OP_CA 0x1 /* Issue current column address */
198#define FIR_OP_PA 0x2 /* Issue current block+page address */
199#define FIR_OP_UA 0x3 /* Issue user defined address */
200#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
201#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
202#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
203#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
204#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
205#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
206#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
207#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
208#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
209#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
210#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
211#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
212 __be32 fcr; /**< Flash Command Register */
213#define FCR_CMD0 0xFF000000
214#define FCR_CMD0_SHIFT 24
215#define FCR_CMD1 0x00FF0000
216#define FCR_CMD1_SHIFT 16
217#define FCR_CMD2 0x0000FF00
218#define FCR_CMD2_SHIFT 8
219#define FCR_CMD3 0x000000FF
220#define FCR_CMD3_SHIFT 0
221 __be32 fbar; /**< Flash Block Address Register */
222#define FBAR_BLK 0x00FFFFFF
223 __be32 fpar; /**< Flash Page Address Register */
224#define FPAR_SP_PI 0x00007C00
225#define FPAR_SP_PI_SHIFT 10
226#define FPAR_SP_MS 0x00000200
227#define FPAR_SP_CI 0x000001FF
228#define FPAR_SP_CI_SHIFT 0
229#define FPAR_LP_PI 0x0003F000
230#define FPAR_LP_PI_SHIFT 12
231#define FPAR_LP_MS 0x00000800
232#define FPAR_LP_CI 0x000007FF
233#define FPAR_LP_CI_SHIFT 0
234 __be32 fbcr; /**< Flash Byte Count Register */
235#define FBCR_BC 0x00000FFF
236 u8 res11[0x8];
237 u8 res8[0xF00];
238};
239
240struct fsl_elbc_ctrl; 45struct fsl_elbc_ctrl;
241 46
242/* mtd information per set */ 47/* mtd information per set */
@@ -261,7 +66,7 @@ struct fsl_elbc_ctrl {
261 66
262 /* device info */ 67 /* device info */
263 struct device *dev; 68 struct device *dev;
264 struct elbc_regs __iomem *regs; 69 struct fsl_lbc_regs __iomem *regs;
265 int irq; 70 int irq;
266 wait_queue_head_t irq_wait; 71 wait_queue_head_t irq_wait;
267 unsigned int irq_status; /* status read from LTESR by irq handler */ 72 unsigned int irq_status; /* status read from LTESR by irq handler */
@@ -322,7 +127,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
322 struct nand_chip *chip = mtd->priv; 127 struct nand_chip *chip = mtd->priv;
323 struct fsl_elbc_mtd *priv = chip->priv; 128 struct fsl_elbc_mtd *priv = chip->priv;
324 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 129 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
325 struct elbc_regs __iomem *lbc = ctrl->regs; 130 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
326 int buf_num; 131 int buf_num;
327 132
328 ctrl->page = page_addr; 133 ctrl->page = page_addr;
@@ -363,7 +168,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
363 struct nand_chip *chip = mtd->priv; 168 struct nand_chip *chip = mtd->priv;
364 struct fsl_elbc_mtd *priv = chip->priv; 169 struct fsl_elbc_mtd *priv = chip->priv;
365 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 170 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
366 struct elbc_regs __iomem *lbc = ctrl->regs; 171 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
367 172
368 /* Setup the FMR[OP] to execute without write protection */ 173 /* Setup the FMR[OP] to execute without write protection */
369 out_be32(&lbc->fmr, priv->fmr | 3); 174 out_be32(&lbc->fmr, priv->fmr | 3);
@@ -406,7 +211,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
406{ 211{
407 struct fsl_elbc_mtd *priv = chip->priv; 212 struct fsl_elbc_mtd *priv = chip->priv;
408 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 213 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
409 struct elbc_regs __iomem *lbc = ctrl->regs; 214 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
410 215
411 if (priv->page_size) { 216 if (priv->page_size) {
412 out_be32(&lbc->fir, 217 out_be32(&lbc->fir,
@@ -439,7 +244,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
439 struct nand_chip *chip = mtd->priv; 244 struct nand_chip *chip = mtd->priv;
440 struct fsl_elbc_mtd *priv = chip->priv; 245 struct fsl_elbc_mtd *priv = chip->priv;
441 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 246 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
442 struct elbc_regs __iomem *lbc = ctrl->regs; 247 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
443 248
444 ctrl->use_mdr = 0; 249 ctrl->use_mdr = 0;
445 250
@@ -775,7 +580,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
775{ 580{
776 struct fsl_elbc_mtd *priv = chip->priv; 581 struct fsl_elbc_mtd *priv = chip->priv;
777 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 582 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
778 struct elbc_regs __iomem *lbc = ctrl->regs; 583 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
779 584
780 if (ctrl->status != LTESR_CC) 585 if (ctrl->status != LTESR_CC)
781 return NAND_STATUS_FAIL; 586 return NAND_STATUS_FAIL;
@@ -807,7 +612,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
807 struct nand_chip *chip = mtd->priv; 612 struct nand_chip *chip = mtd->priv;
808 struct fsl_elbc_mtd *priv = chip->priv; 613 struct fsl_elbc_mtd *priv = chip->priv;
809 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 614 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
810 struct elbc_regs __iomem *lbc = ctrl->regs; 615 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
811 unsigned int al; 616 unsigned int al;
812 617
813 /* calculate FMR Address Length field */ 618 /* calculate FMR Address Length field */
@@ -922,7 +727,7 @@ static void fsl_elbc_write_page(struct mtd_info *mtd,
922static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) 727static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
923{ 728{
924 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 729 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
925 struct elbc_regs __iomem *lbc = ctrl->regs; 730 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
926 struct nand_chip *chip = &priv->chip; 731 struct nand_chip *chip = &priv->chip;
927 732
928 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); 733 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
@@ -986,7 +791,7 @@ static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
986static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl, 791static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
987 struct device_node *node) 792 struct device_node *node)
988{ 793{
989 struct elbc_regs __iomem *lbc = ctrl->regs; 794 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
990 struct fsl_elbc_mtd *priv; 795 struct fsl_elbc_mtd *priv;
991 struct resource res; 796 struct resource res;
992#ifdef CONFIG_MTD_PARTITIONS 797#ifdef CONFIG_MTD_PARTITIONS
@@ -1083,7 +888,7 @@ err:
1083 888
1084static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl) 889static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
1085{ 890{
1086 struct elbc_regs __iomem *lbc = ctrl->regs; 891 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
1087 892
1088 /* clear event registers */ 893 /* clear event registers */
1089 setbits32(&lbc->ltesr, LTESR_NAND_MASK); 894 setbits32(&lbc->ltesr, LTESR_NAND_MASK);
@@ -1128,7 +933,7 @@ static int __devexit fsl_elbc_ctrl_remove(struct of_device *ofdev)
1128static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data) 933static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
1129{ 934{
1130 struct fsl_elbc_ctrl *ctrl = data; 935 struct fsl_elbc_ctrl *ctrl = data;
1131 struct elbc_regs __iomem *lbc = ctrl->regs; 936 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
1132 __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK; 937 __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
1133 938
1134 if (status) { 939 if (status) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 12:47:46 -0500