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path: root/drivers/mtd/nand/ams-delta.c
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Diffstat (limited to 'drivers/mtd/nand/ams-delta.c')
-rw-r--r--drivers/mtd/nand/ams-delta.c74
1 files changed, 52 insertions, 22 deletions
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
index 3197e9764fcd..73416951f4c1 100644
--- a/drivers/mtd/nand/ams-delta.c
+++ b/drivers/mtd/nand/ams-delta.c
@@ -26,7 +26,7 @@
26#include <asm/io.h> 26#include <asm/io.h>
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <asm/sizes.h> 28#include <asm/sizes.h>
29#include <asm/gpio.h> 29#include <linux/gpio.h>
30#include <plat/board-ams-delta.h> 30#include <plat/board-ams-delta.h>
31 31
32/* 32/*
@@ -34,8 +34,6 @@
34 */ 34 */
35static struct mtd_info *ams_delta_mtd = NULL; 35static struct mtd_info *ams_delta_mtd = NULL;
36 36
37#define NAND_MASK (AMS_DELTA_LATCH2_NAND_NRE | AMS_DELTA_LATCH2_NAND_NWE | AMS_DELTA_LATCH2_NAND_CLE | AMS_DELTA_LATCH2_NAND_ALE | AMS_DELTA_LATCH2_NAND_NCE | AMS_DELTA_LATCH2_NAND_NWP)
38
39/* 37/*
40 * Define partitions for flash devices 38 * Define partitions for flash devices
41 */ 39 */
@@ -68,10 +66,9 @@ static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
68 66
69 writew(0, io_base + OMAP_MPUIO_IO_CNTL); 67 writew(0, io_base + OMAP_MPUIO_IO_CNTL);
70 writew(byte, this->IO_ADDR_W); 68 writew(byte, this->IO_ADDR_W);
71 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE, 0); 69 gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0);
72 ndelay(40); 70 ndelay(40);
73 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE, 71 gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1);
74 AMS_DELTA_LATCH2_NAND_NWE);
75} 72}
76 73
77static u_char ams_delta_read_byte(struct mtd_info *mtd) 74static u_char ams_delta_read_byte(struct mtd_info *mtd)
@@ -80,12 +77,11 @@ static u_char ams_delta_read_byte(struct mtd_info *mtd)
80 struct nand_chip *this = mtd->priv; 77 struct nand_chip *this = mtd->priv;
81 void __iomem *io_base = this->priv; 78 void __iomem *io_base = this->priv;
82 79
83 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NRE, 0); 80 gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 0);
84 ndelay(40); 81 ndelay(40);
85 writew(~0, io_base + OMAP_MPUIO_IO_CNTL); 82 writew(~0, io_base + OMAP_MPUIO_IO_CNTL);
86 res = readw(this->IO_ADDR_R); 83 res = readw(this->IO_ADDR_R);
87 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NRE, 84 gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 1);
88 AMS_DELTA_LATCH2_NAND_NRE);
89 85
90 return res; 86 return res;
91} 87}
@@ -132,15 +128,12 @@ static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd,
132{ 128{
133 129
134 if (ctrl & NAND_CTRL_CHANGE) { 130 if (ctrl & NAND_CTRL_CHANGE) {
135 unsigned long bits; 131 gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NCE,
136 132 (ctrl & NAND_NCE) == 0);
137 bits = (~ctrl & NAND_NCE) ? AMS_DELTA_LATCH2_NAND_NCE : 0; 133 gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_CLE,
138 bits |= (ctrl & NAND_CLE) ? AMS_DELTA_LATCH2_NAND_CLE : 0; 134 (ctrl & NAND_CLE) != 0);
139 bits |= (ctrl & NAND_ALE) ? AMS_DELTA_LATCH2_NAND_ALE : 0; 135 gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_ALE,
140 136 (ctrl & NAND_ALE) != 0);
141 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_CLE |
142 AMS_DELTA_LATCH2_NAND_ALE |
143 AMS_DELTA_LATCH2_NAND_NCE, bits);
144 } 137 }
145 138
146 if (cmd != NAND_CMD_NONE) 139 if (cmd != NAND_CMD_NONE)
@@ -152,6 +145,39 @@ static int ams_delta_nand_ready(struct mtd_info *mtd)
152 return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB); 145 return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB);
153} 146}
154 147
148static const struct gpio _mandatory_gpio[] = {
149 {
150 .gpio = AMS_DELTA_GPIO_PIN_NAND_NCE,
151 .flags = GPIOF_OUT_INIT_HIGH,
152 .label = "nand_nce",
153 },
154 {
155 .gpio = AMS_DELTA_GPIO_PIN_NAND_NRE,
156 .flags = GPIOF_OUT_INIT_HIGH,
157 .label = "nand_nre",
158 },
159 {
160 .gpio = AMS_DELTA_GPIO_PIN_NAND_NWP,
161 .flags = GPIOF_OUT_INIT_HIGH,
162 .label = "nand_nwp",
163 },
164 {
165 .gpio = AMS_DELTA_GPIO_PIN_NAND_NWE,
166 .flags = GPIOF_OUT_INIT_HIGH,
167 .label = "nand_nwe",
168 },
169 {
170 .gpio = AMS_DELTA_GPIO_PIN_NAND_ALE,
171 .flags = GPIOF_OUT_INIT_LOW,
172 .label = "nand_ale",
173 },
174 {
175 .gpio = AMS_DELTA_GPIO_PIN_NAND_CLE,
176 .flags = GPIOF_OUT_INIT_LOW,
177 .label = "nand_cle",
178 },
179};
180
155/* 181/*
156 * Main initialization routine 182 * Main initialization routine
157 */ 183 */
@@ -223,10 +249,9 @@ static int __devinit ams_delta_init(struct platform_device *pdev)
223 platform_set_drvdata(pdev, io_base); 249 platform_set_drvdata(pdev, io_base);
224 250
225 /* Set chip enabled, but */ 251 /* Set chip enabled, but */
226 ams_delta_latch2_write(NAND_MASK, AMS_DELTA_LATCH2_NAND_NRE | 252 err = gpio_request_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
227 AMS_DELTA_LATCH2_NAND_NWE | 253 if (err)
228 AMS_DELTA_LATCH2_NAND_NCE | 254 goto out_gpio;
229 AMS_DELTA_LATCH2_NAND_NWP);
230 255
231 /* Scan to find existence of the device */ 256 /* Scan to find existence of the device */
232 if (nand_scan(ams_delta_mtd, 1)) { 257 if (nand_scan(ams_delta_mtd, 1)) {
@@ -241,7 +266,10 @@ static int __devinit ams_delta_init(struct platform_device *pdev)
241 goto out; 266 goto out;
242 267
243 out_mtd: 268 out_mtd:
269 gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
270out_gpio:
244 platform_set_drvdata(pdev, NULL); 271 platform_set_drvdata(pdev, NULL);
272 gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
245 iounmap(io_base); 273 iounmap(io_base);
246out_release_io: 274out_release_io:
247 release_mem_region(res->start, resource_size(res)); 275 release_mem_region(res->start, resource_size(res));
@@ -262,6 +290,8 @@ static int __devexit ams_delta_cleanup(struct platform_device *pdev)
262 /* Release resources, unregister device */ 290 /* Release resources, unregister device */
263 nand_release(ams_delta_mtd); 291 nand_release(ams_delta_mtd);
264 292
293 gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
294 gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
265 iounmap(io_base); 295 iounmap(io_base);
266 release_mem_region(res->start, resource_size(res)); 296 release_mem_region(res->start, resource_size(res));
267 297