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Diffstat (limited to 'drivers/mtd/chips/cfi_cmdset_0002.c')
-rw-r--r--drivers/mtd/chips/cfi_cmdset_0002.c497
1 files changed, 377 insertions, 120 deletions
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
index fca8ff6f7e14..8505f118f2db 100644
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -4,16 +4,20 @@
4 * 4 *
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp> 5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com> 6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
7 * 8 *
8 * 2_by_8 routines added by Simon Munton 9 * 2_by_8 routines added by Simon Munton
9 * 10 *
10 * 4_by_16 work by Carolyn J. Smith 11 * 4_by_16 work by Carolyn J. Smith
11 * 12 *
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
14 * by Nicolas Pitre)
15 *
12 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com 16 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
13 * 17 *
14 * This code is GPL 18 * This code is GPL
15 * 19 *
16 * $Id: cfi_cmdset_0002.c,v 1.114 2004/12/11 15:43:53 dedekind Exp $ 20 * $Id: cfi_cmdset_0002.c,v 1.118 2005/07/04 22:34:29 gleixner Exp $
17 * 21 *
18 */ 22 */
19 23
@@ -34,6 +38,7 @@
34#include <linux/mtd/map.h> 38#include <linux/mtd/map.h>
35#include <linux/mtd/mtd.h> 39#include <linux/mtd/mtd.h>
36#include <linux/mtd/cfi.h> 40#include <linux/mtd/cfi.h>
41#include <linux/mtd/xip.h>
37 42
38#define AMD_BOOTLOC_BUG 43#define AMD_BOOTLOC_BUG
39#define FORCE_WORD_WRITE 0 44#define FORCE_WORD_WRITE 0
@@ -43,6 +48,7 @@
43#define MANUFACTURER_AMD 0x0001 48#define MANUFACTURER_AMD 0x0001
44#define MANUFACTURER_SST 0x00BF 49#define MANUFACTURER_SST 0x00BF
45#define SST49LF004B 0x0060 50#define SST49LF004B 0x0060
51#define SST49LF008A 0x005a
46 52
47static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); 53static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
48static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); 54static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
@@ -191,6 +197,7 @@ static struct cfi_fixup cfi_fixup_table[] = {
191}; 197};
192static struct cfi_fixup jedec_fixup_table[] = { 198static struct cfi_fixup jedec_fixup_table[] = {
193 { MANUFACTURER_SST, SST49LF004B, fixup_use_fwh_lock, NULL, }, 199 { MANUFACTURER_SST, SST49LF004B, fixup_use_fwh_lock, NULL, },
200 { MANUFACTURER_SST, SST49LF008A, fixup_use_fwh_lock, NULL, },
194 { 0, 0, NULL, NULL } 201 { 0, 0, NULL, NULL }
195}; 202};
196 203
@@ -391,7 +398,7 @@ static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
391 * correctly and is therefore not done (particulary with interleaved chips 398 * correctly and is therefore not done (particulary with interleaved chips
392 * as each chip must be checked independantly of the others). 399 * as each chip must be checked independantly of the others).
393 */ 400 */
394static int chip_ready(struct map_info *map, unsigned long addr) 401static int __xipram chip_ready(struct map_info *map, unsigned long addr)
395{ 402{
396 map_word d, t; 403 map_word d, t;
397 404
@@ -401,6 +408,32 @@ static int chip_ready(struct map_info *map, unsigned long addr)
401 return map_word_equal(map, d, t); 408 return map_word_equal(map, d, t);
402} 409}
403 410
411/*
412 * Return true if the chip is ready and has the correct value.
413 *
414 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
415 * non-suspended sector) and it is indicated by no bits toggling.
416 *
417 * Error are indicated by toggling bits or bits held with the wrong value,
418 * or with bits toggling.
419 *
420 * Note that anything more complicated than checking if no bits are toggling
421 * (including checking DQ5 for an error status) is tricky to get working
422 * correctly and is therefore not done (particulary with interleaved chips
423 * as each chip must be checked independantly of the others).
424 *
425 */
426static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
427{
428 map_word oldd, curd;
429
430 oldd = map_read(map, addr);
431 curd = map_read(map, addr);
432
433 return map_word_equal(map, oldd, curd) &&
434 map_word_equal(map, curd, expected);
435}
436
404static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode) 437static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
405{ 438{
406 DECLARE_WAITQUEUE(wait, current); 439 DECLARE_WAITQUEUE(wait, current);
@@ -420,12 +453,12 @@ static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr
420 453
421 if (time_after(jiffies, timeo)) { 454 if (time_after(jiffies, timeo)) {
422 printk(KERN_ERR "Waiting for chip to be ready timed out.\n"); 455 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
423 cfi_spin_unlock(chip->mutex); 456 spin_unlock(chip->mutex);
424 return -EIO; 457 return -EIO;
425 } 458 }
426 cfi_spin_unlock(chip->mutex); 459 spin_unlock(chip->mutex);
427 cfi_udelay(1); 460 cfi_udelay(1);
428 cfi_spin_lock(chip->mutex); 461 spin_lock(chip->mutex);
429 /* Someone else might have been playing with it. */ 462 /* Someone else might have been playing with it. */
430 goto retry; 463 goto retry;
431 } 464 }
@@ -473,15 +506,23 @@ static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr
473 return -EIO; 506 return -EIO;
474 } 507 }
475 508
476 cfi_spin_unlock(chip->mutex); 509 spin_unlock(chip->mutex);
477 cfi_udelay(1); 510 cfi_udelay(1);
478 cfi_spin_lock(chip->mutex); 511 spin_lock(chip->mutex);
479 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING. 512 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
480 So we can just loop here. */ 513 So we can just loop here. */
481 } 514 }
482 chip->state = FL_READY; 515 chip->state = FL_READY;
483 return 0; 516 return 0;
484 517
518 case FL_XIP_WHILE_ERASING:
519 if (mode != FL_READY && mode != FL_POINT &&
520 (!cfip || !(cfip->EraseSuspend&2)))
521 goto sleep;
522 chip->oldstate = chip->state;
523 chip->state = FL_READY;
524 return 0;
525
485 case FL_POINT: 526 case FL_POINT:
486 /* Only if there's no operation suspended... */ 527 /* Only if there's no operation suspended... */
487 if (mode == FL_READY && chip->oldstate == FL_READY) 528 if (mode == FL_READY && chip->oldstate == FL_READY)
@@ -491,10 +532,10 @@ static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr
491 sleep: 532 sleep:
492 set_current_state(TASK_UNINTERRUPTIBLE); 533 set_current_state(TASK_UNINTERRUPTIBLE);
493 add_wait_queue(&chip->wq, &wait); 534 add_wait_queue(&chip->wq, &wait);
494 cfi_spin_unlock(chip->mutex); 535 spin_unlock(chip->mutex);
495 schedule(); 536 schedule();
496 remove_wait_queue(&chip->wq, &wait); 537 remove_wait_queue(&chip->wq, &wait);
497 cfi_spin_lock(chip->mutex); 538 spin_lock(chip->mutex);
498 goto resettime; 539 goto resettime;
499 } 540 }
500} 541}
@@ -512,6 +553,11 @@ static void put_chip(struct map_info *map, struct flchip *chip, unsigned long ad
512 chip->state = FL_ERASING; 553 chip->state = FL_ERASING;
513 break; 554 break;
514 555
556 case FL_XIP_WHILE_ERASING:
557 chip->state = chip->oldstate;
558 chip->oldstate = FL_READY;
559 break;
560
515 case FL_READY: 561 case FL_READY:
516 case FL_STATUS: 562 case FL_STATUS:
517 /* We should really make set_vpp() count, rather than doing this */ 563 /* We should really make set_vpp() count, rather than doing this */
@@ -523,6 +569,198 @@ static void put_chip(struct map_info *map, struct flchip *chip, unsigned long ad
523 wake_up(&chip->wq); 569 wake_up(&chip->wq);
524} 570}
525 571
572#ifdef CONFIG_MTD_XIP
573
574/*
575 * No interrupt what so ever can be serviced while the flash isn't in array
576 * mode. This is ensured by the xip_disable() and xip_enable() functions
577 * enclosing any code path where the flash is known not to be in array mode.
578 * And within a XIP disabled code path, only functions marked with __xipram
579 * may be called and nothing else (it's a good thing to inspect generated
580 * assembly to make sure inline functions were actually inlined and that gcc
581 * didn't emit calls to its own support functions). Also configuring MTD CFI
582 * support to a single buswidth and a single interleave is also recommended.
583 */
584
585static void xip_disable(struct map_info *map, struct flchip *chip,
586 unsigned long adr)
587{
588 /* TODO: chips with no XIP use should ignore and return */
589 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
590 local_irq_disable();
591}
592
593static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
594 unsigned long adr)
595{
596 struct cfi_private *cfi = map->fldrv_priv;
597
598 if (chip->state != FL_POINT && chip->state != FL_READY) {
599 map_write(map, CMD(0xf0), adr);
600 chip->state = FL_READY;
601 }
602 (void) map_read(map, adr);
603 xip_iprefetch();
604 local_irq_enable();
605}
606
607/*
608 * When a delay is required for the flash operation to complete, the
609 * xip_udelay() function is polling for both the given timeout and pending
610 * (but still masked) hardware interrupts. Whenever there is an interrupt
611 * pending then the flash erase operation is suspended, array mode restored
612 * and interrupts unmasked. Task scheduling might also happen at that
613 * point. The CPU eventually returns from the interrupt or the call to
614 * schedule() and the suspended flash operation is resumed for the remaining
615 * of the delay period.
616 *
617 * Warning: this function _will_ fool interrupt latency tracing tools.
618 */
619
620static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
621 unsigned long adr, int usec)
622{
623 struct cfi_private *cfi = map->fldrv_priv;
624 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
625 map_word status, OK = CMD(0x80);
626 unsigned long suspended, start = xip_currtime();
627 flstate_t oldstate;
628
629 do {
630 cpu_relax();
631 if (xip_irqpending() && extp &&
632 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
633 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
634 /*
635 * Let's suspend the erase operation when supported.
636 * Note that we currently don't try to suspend
637 * interleaved chips if there is already another
638 * operation suspended (imagine what happens
639 * when one chip was already done with the current
640 * operation while another chip suspended it, then
641 * we resume the whole thing at once). Yes, it
642 * can happen!
643 */
644 map_write(map, CMD(0xb0), adr);
645 usec -= xip_elapsed_since(start);
646 suspended = xip_currtime();
647 do {
648 if (xip_elapsed_since(suspended) > 100000) {
649 /*
650 * The chip doesn't want to suspend
651 * after waiting for 100 msecs.
652 * This is a critical error but there
653 * is not much we can do here.
654 */
655 return;
656 }
657 status = map_read(map, adr);
658 } while (!map_word_andequal(map, status, OK, OK));
659
660 /* Suspend succeeded */
661 oldstate = chip->state;
662 if (!map_word_bitsset(map, status, CMD(0x40)))
663 break;
664 chip->state = FL_XIP_WHILE_ERASING;
665 chip->erase_suspended = 1;
666 map_write(map, CMD(0xf0), adr);
667 (void) map_read(map, adr);
668 asm volatile (".rep 8; nop; .endr");
669 local_irq_enable();
670 spin_unlock(chip->mutex);
671 asm volatile (".rep 8; nop; .endr");
672 cond_resched();
673
674 /*
675 * We're back. However someone else might have
676 * decided to go write to the chip if we are in
677 * a suspended erase state. If so let's wait
678 * until it's done.
679 */
680 spin_lock(chip->mutex);
681 while (chip->state != FL_XIP_WHILE_ERASING) {
682 DECLARE_WAITQUEUE(wait, current);
683 set_current_state(TASK_UNINTERRUPTIBLE);
684 add_wait_queue(&chip->wq, &wait);
685 spin_unlock(chip->mutex);
686 schedule();
687 remove_wait_queue(&chip->wq, &wait);
688 spin_lock(chip->mutex);
689 }
690 /* Disallow XIP again */
691 local_irq_disable();
692
693 /* Resume the write or erase operation */
694 map_write(map, CMD(0x30), adr);
695 chip->state = oldstate;
696 start = xip_currtime();
697 } else if (usec >= 1000000/HZ) {
698 /*
699 * Try to save on CPU power when waiting delay
700 * is at least a system timer tick period.
701 * No need to be extremely accurate here.
702 */
703 xip_cpu_idle();
704 }
705 status = map_read(map, adr);
706 } while (!map_word_andequal(map, status, OK, OK)
707 && xip_elapsed_since(start) < usec);
708}
709
710#define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
711
712/*
713 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
714 * the flash is actively programming or erasing since we have to poll for
715 * the operation to complete anyway. We can't do that in a generic way with
716 * a XIP setup so do it before the actual flash operation in this case
717 * and stub it out from INVALIDATE_CACHE_UDELAY.
718 */
719#define XIP_INVAL_CACHED_RANGE(map, from, size) \
720 INVALIDATE_CACHED_RANGE(map, from, size)
721
722#define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
723 UDELAY(map, chip, adr, usec)
724
725/*
726 * Extra notes:
727 *
728 * Activating this XIP support changes the way the code works a bit. For
729 * example the code to suspend the current process when concurrent access
730 * happens is never executed because xip_udelay() will always return with the
731 * same chip state as it was entered with. This is why there is no care for
732 * the presence of add_wait_queue() or schedule() calls from within a couple
733 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
734 * The queueing and scheduling are always happening within xip_udelay().
735 *
736 * Similarly, get_chip() and put_chip() just happen to always be executed
737 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
738 * is in array mode, therefore never executing many cases therein and not
739 * causing any problem with XIP.
740 */
741
742#else
743
744#define xip_disable(map, chip, adr)
745#define xip_enable(map, chip, adr)
746#define XIP_INVAL_CACHED_RANGE(x...)
747
748#define UDELAY(map, chip, adr, usec) \
749do { \
750 spin_unlock(chip->mutex); \
751 cfi_udelay(usec); \
752 spin_lock(chip->mutex); \
753} while (0)
754
755#define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
756do { \
757 spin_unlock(chip->mutex); \
758 INVALIDATE_CACHED_RANGE(map, adr, len); \
759 cfi_udelay(usec); \
760 spin_lock(chip->mutex); \
761} while (0)
762
763#endif
526 764
527static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf) 765static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
528{ 766{
@@ -535,10 +773,10 @@ static inline int do_read_onechip(struct map_info *map, struct flchip *chip, lof
535 /* Ensure cmd read/writes are aligned. */ 773 /* Ensure cmd read/writes are aligned. */
536 cmd_addr = adr & ~(map_bankwidth(map)-1); 774 cmd_addr = adr & ~(map_bankwidth(map)-1);
537 775
538 cfi_spin_lock(chip->mutex); 776 spin_lock(chip->mutex);
539 ret = get_chip(map, chip, cmd_addr, FL_READY); 777 ret = get_chip(map, chip, cmd_addr, FL_READY);
540 if (ret) { 778 if (ret) {
541 cfi_spin_unlock(chip->mutex); 779 spin_unlock(chip->mutex);
542 return ret; 780 return ret;
543 } 781 }
544 782
@@ -551,7 +789,7 @@ static inline int do_read_onechip(struct map_info *map, struct flchip *chip, lof
551 789
552 put_chip(map, chip, cmd_addr); 790 put_chip(map, chip, cmd_addr);
553 791
554 cfi_spin_unlock(chip->mutex); 792 spin_unlock(chip->mutex);
555 return 0; 793 return 0;
556} 794}
557 795
@@ -605,7 +843,7 @@ static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chi
605 struct cfi_private *cfi = map->fldrv_priv; 843 struct cfi_private *cfi = map->fldrv_priv;
606 844
607 retry: 845 retry:
608 cfi_spin_lock(chip->mutex); 846 spin_lock(chip->mutex);
609 847
610 if (chip->state != FL_READY){ 848 if (chip->state != FL_READY){
611#if 0 849#if 0
@@ -614,7 +852,7 @@ static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chi
614 set_current_state(TASK_UNINTERRUPTIBLE); 852 set_current_state(TASK_UNINTERRUPTIBLE);
615 add_wait_queue(&chip->wq, &wait); 853 add_wait_queue(&chip->wq, &wait);
616 854
617 cfi_spin_unlock(chip->mutex); 855 spin_unlock(chip->mutex);
618 856
619 schedule(); 857 schedule();
620 remove_wait_queue(&chip->wq, &wait); 858 remove_wait_queue(&chip->wq, &wait);
@@ -643,7 +881,7 @@ static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chi
643 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 881 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
644 882
645 wake_up(&chip->wq); 883 wake_up(&chip->wq);
646 cfi_spin_unlock(chip->mutex); 884 spin_unlock(chip->mutex);
647 885
648 return 0; 886 return 0;
649} 887}
@@ -692,7 +930,7 @@ static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len,
692} 930}
693 931
694 932
695static int do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum) 933static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
696{ 934{
697 struct cfi_private *cfi = map->fldrv_priv; 935 struct cfi_private *cfi = map->fldrv_priv;
698 unsigned long timeo = jiffies + HZ; 936 unsigned long timeo = jiffies + HZ;
@@ -712,10 +950,10 @@ static int do_write_oneword(struct map_info *map, struct flchip *chip, unsigned
712 950
713 adr += chip->start; 951 adr += chip->start;
714 952
715 cfi_spin_lock(chip->mutex); 953 spin_lock(chip->mutex);
716 ret = get_chip(map, chip, adr, FL_WRITING); 954 ret = get_chip(map, chip, adr, FL_WRITING);
717 if (ret) { 955 if (ret) {
718 cfi_spin_unlock(chip->mutex); 956 spin_unlock(chip->mutex);
719 return ret; 957 return ret;
720 } 958 }
721 959
@@ -735,7 +973,9 @@ static int do_write_oneword(struct map_info *map, struct flchip *chip, unsigned
735 goto op_done; 973 goto op_done;
736 } 974 }
737 975
976 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
738 ENABLE_VPP(map); 977 ENABLE_VPP(map);
978 xip_disable(map, chip, adr);
739 retry: 979 retry:
740 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 980 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
741 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 981 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
@@ -743,9 +983,9 @@ static int do_write_oneword(struct map_info *map, struct flchip *chip, unsigned
743 map_write(map, datum, adr); 983 map_write(map, datum, adr);
744 chip->state = FL_WRITING; 984 chip->state = FL_WRITING;
745 985
746 cfi_spin_unlock(chip->mutex); 986 INVALIDATE_CACHE_UDELAY(map, chip,
747 cfi_udelay(chip->word_write_time); 987 adr, map_bankwidth(map),
748 cfi_spin_lock(chip->mutex); 988 chip->word_write_time);
749 989
750 /* See comment above for timeout value. */ 990 /* See comment above for timeout value. */
751 timeo = jiffies + uWriteTimeout; 991 timeo = jiffies + uWriteTimeout;
@@ -756,39 +996,43 @@ static int do_write_oneword(struct map_info *map, struct flchip *chip, unsigned
756 996
757 set_current_state(TASK_UNINTERRUPTIBLE); 997 set_current_state(TASK_UNINTERRUPTIBLE);
758 add_wait_queue(&chip->wq, &wait); 998 add_wait_queue(&chip->wq, &wait);
759 cfi_spin_unlock(chip->mutex); 999 spin_unlock(chip->mutex);
760 schedule(); 1000 schedule();
761 remove_wait_queue(&chip->wq, &wait); 1001 remove_wait_queue(&chip->wq, &wait);
762 timeo = jiffies + (HZ / 2); /* FIXME */ 1002 timeo = jiffies + (HZ / 2); /* FIXME */
763 cfi_spin_lock(chip->mutex); 1003 spin_lock(chip->mutex);
764 continue; 1004 continue;
765 } 1005 }
766 1006
767 if (chip_ready(map, adr)) 1007 if (chip_ready(map, adr))
768 goto op_done; 1008 break;
769 1009
770 if (time_after(jiffies, timeo)) 1010 if (time_after(jiffies, timeo)) {
1011 xip_enable(map, chip, adr);
1012 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1013 xip_disable(map, chip, adr);
771 break; 1014 break;
1015 }
772 1016
773 /* Latency issues. Drop the lock, wait a while and retry */ 1017 /* Latency issues. Drop the lock, wait a while and retry */
774 cfi_spin_unlock(chip->mutex); 1018 UDELAY(map, chip, adr, 1);
775 cfi_udelay(1);
776 cfi_spin_lock(chip->mutex);
777 } 1019 }
1020 /* Did we succeed? */
1021 if (!chip_good(map, adr, datum)) {
1022 /* reset on all failures. */
1023 map_write( map, CMD(0xF0), chip->start );
1024 /* FIXME - should have reset delay before continuing */
778 1025
779 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__); 1026 if (++retry_cnt <= MAX_WORD_RETRIES)
780 1027 goto retry;
781 /* reset on all failures. */
782 map_write( map, CMD(0xF0), chip->start );
783 /* FIXME - should have reset delay before continuing */
784 if (++retry_cnt <= MAX_WORD_RETRIES)
785 goto retry;
786 1028
787 ret = -EIO; 1029 ret = -EIO;
1030 }
1031 xip_enable(map, chip, adr);
788 op_done: 1032 op_done:
789 chip->state = FL_READY; 1033 chip->state = FL_READY;
790 put_chip(map, chip, adr); 1034 put_chip(map, chip, adr);
791 cfi_spin_unlock(chip->mutex); 1035 spin_unlock(chip->mutex);
792 1036
793 return ret; 1037 return ret;
794} 1038}
@@ -820,7 +1064,7 @@ static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
820 map_word tmp_buf; 1064 map_word tmp_buf;
821 1065
822 retry: 1066 retry:
823 cfi_spin_lock(cfi->chips[chipnum].mutex); 1067 spin_lock(cfi->chips[chipnum].mutex);
824 1068
825 if (cfi->chips[chipnum].state != FL_READY) { 1069 if (cfi->chips[chipnum].state != FL_READY) {
826#if 0 1070#if 0
@@ -829,7 +1073,7 @@ static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
829 set_current_state(TASK_UNINTERRUPTIBLE); 1073 set_current_state(TASK_UNINTERRUPTIBLE);
830 add_wait_queue(&cfi->chips[chipnum].wq, &wait); 1074 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
831 1075
832 cfi_spin_unlock(cfi->chips[chipnum].mutex); 1076 spin_unlock(cfi->chips[chipnum].mutex);
833 1077
834 schedule(); 1078 schedule();
835 remove_wait_queue(&cfi->chips[chipnum].wq, &wait); 1079 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
@@ -843,7 +1087,7 @@ static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
843 /* Load 'tmp_buf' with old contents of flash */ 1087 /* Load 'tmp_buf' with old contents of flash */
844 tmp_buf = map_read(map, bus_ofs+chipstart); 1088 tmp_buf = map_read(map, bus_ofs+chipstart);
845 1089
846 cfi_spin_unlock(cfi->chips[chipnum].mutex); 1090 spin_unlock(cfi->chips[chipnum].mutex);
847 1091
848 /* Number of bytes to copy from buffer */ 1092 /* Number of bytes to copy from buffer */
849 n = min_t(int, len, map_bankwidth(map)-i); 1093 n = min_t(int, len, map_bankwidth(map)-i);
@@ -898,7 +1142,7 @@ static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
898 map_word tmp_buf; 1142 map_word tmp_buf;
899 1143
900 retry1: 1144 retry1:
901 cfi_spin_lock(cfi->chips[chipnum].mutex); 1145 spin_lock(cfi->chips[chipnum].mutex);
902 1146
903 if (cfi->chips[chipnum].state != FL_READY) { 1147 if (cfi->chips[chipnum].state != FL_READY) {
904#if 0 1148#if 0
@@ -907,7 +1151,7 @@ static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
907 set_current_state(TASK_UNINTERRUPTIBLE); 1151 set_current_state(TASK_UNINTERRUPTIBLE);
908 add_wait_queue(&cfi->chips[chipnum].wq, &wait); 1152 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
909 1153
910 cfi_spin_unlock(cfi->chips[chipnum].mutex); 1154 spin_unlock(cfi->chips[chipnum].mutex);
911 1155
912 schedule(); 1156 schedule();
913 remove_wait_queue(&cfi->chips[chipnum].wq, &wait); 1157 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
@@ -920,7 +1164,7 @@ static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
920 1164
921 tmp_buf = map_read(map, ofs + chipstart); 1165 tmp_buf = map_read(map, ofs + chipstart);
922 1166
923 cfi_spin_unlock(cfi->chips[chipnum].mutex); 1167 spin_unlock(cfi->chips[chipnum].mutex);
924 1168
925 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len); 1169 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
926 1170
@@ -939,8 +1183,9 @@ static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
939/* 1183/*
940 * FIXME: interleaved mode not tested, and probably not supported! 1184 * FIXME: interleaved mode not tested, and probably not supported!
941 */ 1185 */
942static inline int do_write_buffer(struct map_info *map, struct flchip *chip, 1186static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
943 unsigned long adr, const u_char *buf, int len) 1187 unsigned long adr, const u_char *buf,
1188 int len)
944{ 1189{
945 struct cfi_private *cfi = map->fldrv_priv; 1190 struct cfi_private *cfi = map->fldrv_priv;
946 unsigned long timeo = jiffies + HZ; 1191 unsigned long timeo = jiffies + HZ;
@@ -954,10 +1199,10 @@ static inline int do_write_buffer(struct map_info *map, struct flchip *chip,
954 adr += chip->start; 1199 adr += chip->start;
955 cmd_adr = adr; 1200 cmd_adr = adr;
956 1201
957 cfi_spin_lock(chip->mutex); 1202 spin_lock(chip->mutex);
958 ret = get_chip(map, chip, adr, FL_WRITING); 1203 ret = get_chip(map, chip, adr, FL_WRITING);
959 if (ret) { 1204 if (ret) {
960 cfi_spin_unlock(chip->mutex); 1205 spin_unlock(chip->mutex);
961 return ret; 1206 return ret;
962 } 1207 }
963 1208
@@ -966,7 +1211,10 @@ static inline int do_write_buffer(struct map_info *map, struct flchip *chip,
966 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", 1211 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
967 __func__, adr, datum.x[0] ); 1212 __func__, adr, datum.x[0] );
968 1213
1214 XIP_INVAL_CACHED_RANGE(map, adr, len);
969 ENABLE_VPP(map); 1215 ENABLE_VPP(map);
1216 xip_disable(map, chip, cmd_adr);
1217
970 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1218 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
971 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 1219 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
972 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1220 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
@@ -996,9 +1244,9 @@ static inline int do_write_buffer(struct map_info *map, struct flchip *chip,
996 map_write(map, CMD(0x29), cmd_adr); 1244 map_write(map, CMD(0x29), cmd_adr);
997 chip->state = FL_WRITING; 1245 chip->state = FL_WRITING;
998 1246
999 cfi_spin_unlock(chip->mutex); 1247 INVALIDATE_CACHE_UDELAY(map, chip,
1000 cfi_udelay(chip->buffer_write_time); 1248 adr, map_bankwidth(map),
1001 cfi_spin_lock(chip->mutex); 1249 chip->word_write_time);
1002 1250
1003 timeo = jiffies + uWriteTimeout; 1251 timeo = jiffies + uWriteTimeout;
1004 1252
@@ -1009,38 +1257,39 @@ static inline int do_write_buffer(struct map_info *map, struct flchip *chip,
1009 1257
1010 set_current_state(TASK_UNINTERRUPTIBLE); 1258 set_current_state(TASK_UNINTERRUPTIBLE);
1011 add_wait_queue(&chip->wq, &wait); 1259 add_wait_queue(&chip->wq, &wait);
1012 cfi_spin_unlock(chip->mutex); 1260 spin_unlock(chip->mutex);
1013 schedule(); 1261 schedule();
1014 remove_wait_queue(&chip->wq, &wait); 1262 remove_wait_queue(&chip->wq, &wait);
1015 timeo = jiffies + (HZ / 2); /* FIXME */ 1263 timeo = jiffies + (HZ / 2); /* FIXME */
1016 cfi_spin_lock(chip->mutex); 1264 spin_lock(chip->mutex);
1017 continue; 1265 continue;
1018 } 1266 }
1019 1267
1020 if (chip_ready(map, adr)) 1268 if (chip_ready(map, adr)) {
1269 xip_enable(map, chip, adr);
1021 goto op_done; 1270 goto op_done;
1271 }
1022 1272
1023 if( time_after(jiffies, timeo)) 1273 if( time_after(jiffies, timeo))
1024 break; 1274 break;
1025 1275
1026 /* Latency issues. Drop the lock, wait a while and retry */ 1276 /* Latency issues. Drop the lock, wait a while and retry */
1027 cfi_spin_unlock(chip->mutex); 1277 UDELAY(map, chip, adr, 1);
1028 cfi_udelay(1);
1029 cfi_spin_lock(chip->mutex);
1030 } 1278 }
1031 1279
1032 printk(KERN_WARNING "MTD %s(): software timeout\n",
1033 __func__ );
1034
1035 /* reset on all failures. */ 1280 /* reset on all failures. */
1036 map_write( map, CMD(0xF0), chip->start ); 1281 map_write( map, CMD(0xF0), chip->start );
1282 xip_enable(map, chip, adr);
1037 /* FIXME - should have reset delay before continuing */ 1283 /* FIXME - should have reset delay before continuing */
1038 1284
1285 printk(KERN_WARNING "MTD %s(): software timeout\n",
1286 __func__ );
1287
1039 ret = -EIO; 1288 ret = -EIO;
1040 op_done: 1289 op_done:
1041 chip->state = FL_READY; 1290 chip->state = FL_READY;
1042 put_chip(map, chip, adr); 1291 put_chip(map, chip, adr);
1043 cfi_spin_unlock(chip->mutex); 1292 spin_unlock(chip->mutex);
1044 1293
1045 return ret; 1294 return ret;
1046} 1295}
@@ -1130,7 +1379,7 @@ static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1130 * Handle devices with one erase region, that only implement 1379 * Handle devices with one erase region, that only implement
1131 * the chip erase command. 1380 * the chip erase command.
1132 */ 1381 */
1133static inline int do_erase_chip(struct map_info *map, struct flchip *chip) 1382static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1134{ 1383{
1135 struct cfi_private *cfi = map->fldrv_priv; 1384 struct cfi_private *cfi = map->fldrv_priv;
1136 unsigned long timeo = jiffies + HZ; 1385 unsigned long timeo = jiffies + HZ;
@@ -1140,17 +1389,20 @@ static inline int do_erase_chip(struct map_info *map, struct flchip *chip)
1140 1389
1141 adr = cfi->addr_unlock1; 1390 adr = cfi->addr_unlock1;
1142 1391
1143 cfi_spin_lock(chip->mutex); 1392 spin_lock(chip->mutex);
1144 ret = get_chip(map, chip, adr, FL_WRITING); 1393 ret = get_chip(map, chip, adr, FL_WRITING);
1145 if (ret) { 1394 if (ret) {
1146 cfi_spin_unlock(chip->mutex); 1395 spin_unlock(chip->mutex);
1147 return ret; 1396 return ret;
1148 } 1397 }
1149 1398
1150 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n", 1399 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1151 __func__, chip->start ); 1400 __func__, chip->start );
1152 1401
1402 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1153 ENABLE_VPP(map); 1403 ENABLE_VPP(map);
1404 xip_disable(map, chip, adr);
1405
1154 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1406 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1155 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 1407 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1156 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1408 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
@@ -1162,9 +1414,9 @@ static inline int do_erase_chip(struct map_info *map, struct flchip *chip)
1162 chip->erase_suspended = 0; 1414 chip->erase_suspended = 0;
1163 chip->in_progress_block_addr = adr; 1415 chip->in_progress_block_addr = adr;
1164 1416
1165 cfi_spin_unlock(chip->mutex); 1417 INVALIDATE_CACHE_UDELAY(map, chip,
1166 msleep(chip->erase_time/2); 1418 adr, map->size,
1167 cfi_spin_lock(chip->mutex); 1419 chip->erase_time*500);
1168 1420
1169 timeo = jiffies + (HZ*20); 1421 timeo = jiffies + (HZ*20);
1170 1422
@@ -1173,10 +1425,10 @@ static inline int do_erase_chip(struct map_info *map, struct flchip *chip)
1173 /* Someone's suspended the erase. Sleep */ 1425 /* Someone's suspended the erase. Sleep */
1174 set_current_state(TASK_UNINTERRUPTIBLE); 1426 set_current_state(TASK_UNINTERRUPTIBLE);
1175 add_wait_queue(&chip->wq, &wait); 1427 add_wait_queue(&chip->wq, &wait);
1176 cfi_spin_unlock(chip->mutex); 1428 spin_unlock(chip->mutex);
1177 schedule(); 1429 schedule();
1178 remove_wait_queue(&chip->wq, &wait); 1430 remove_wait_queue(&chip->wq, &wait);
1179 cfi_spin_lock(chip->mutex); 1431 spin_lock(chip->mutex);
1180 continue; 1432 continue;
1181 } 1433 }
1182 if (chip->erase_suspended) { 1434 if (chip->erase_suspended) {
@@ -1187,36 +1439,36 @@ static inline int do_erase_chip(struct map_info *map, struct flchip *chip)
1187 } 1439 }
1188 1440
1189 if (chip_ready(map, adr)) 1441 if (chip_ready(map, adr))
1190 goto op_done; 1442 break;
1191 1443
1192 if (time_after(jiffies, timeo)) 1444 if (time_after(jiffies, timeo)) {
1445 printk(KERN_WARNING "MTD %s(): software timeout\n",
1446 __func__ );
1193 break; 1447 break;
1448 }
1194 1449
1195 /* Latency issues. Drop the lock, wait a while and retry */ 1450 /* Latency issues. Drop the lock, wait a while and retry */
1196 cfi_spin_unlock(chip->mutex); 1451 UDELAY(map, chip, adr, 1000000/HZ);
1197 set_current_state(TASK_UNINTERRUPTIBLE);
1198 schedule_timeout(1);
1199 cfi_spin_lock(chip->mutex);
1200 } 1452 }
1453 /* Did we succeed? */
1454 if (!chip_good(map, adr, map_word_ff(map))) {
1455 /* reset on all failures. */
1456 map_write( map, CMD(0xF0), chip->start );
1457 /* FIXME - should have reset delay before continuing */
1201 1458
1202 printk(KERN_WARNING "MTD %s(): software timeout\n", 1459 ret = -EIO;
1203 __func__ ); 1460 }
1204
1205 /* reset on all failures. */
1206 map_write( map, CMD(0xF0), chip->start );
1207 /* FIXME - should have reset delay before continuing */
1208 1461
1209 ret = -EIO;
1210 op_done:
1211 chip->state = FL_READY; 1462 chip->state = FL_READY;
1463 xip_enable(map, chip, adr);
1212 put_chip(map, chip, adr); 1464 put_chip(map, chip, adr);
1213 cfi_spin_unlock(chip->mutex); 1465 spin_unlock(chip->mutex);
1214 1466
1215 return ret; 1467 return ret;
1216} 1468}
1217 1469
1218 1470
1219static inline int do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk) 1471static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1220{ 1472{
1221 struct cfi_private *cfi = map->fldrv_priv; 1473 struct cfi_private *cfi = map->fldrv_priv;
1222 unsigned long timeo = jiffies + HZ; 1474 unsigned long timeo = jiffies + HZ;
@@ -1225,17 +1477,20 @@ static inline int do_erase_oneblock(struct map_info *map, struct flchip *chip, u
1225 1477
1226 adr += chip->start; 1478 adr += chip->start;
1227 1479
1228 cfi_spin_lock(chip->mutex); 1480 spin_lock(chip->mutex);
1229 ret = get_chip(map, chip, adr, FL_ERASING); 1481 ret = get_chip(map, chip, adr, FL_ERASING);
1230 if (ret) { 1482 if (ret) {
1231 cfi_spin_unlock(chip->mutex); 1483 spin_unlock(chip->mutex);
1232 return ret; 1484 return ret;
1233 } 1485 }
1234 1486
1235 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n", 1487 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1236 __func__, adr ); 1488 __func__, adr );
1237 1489
1490 XIP_INVAL_CACHED_RANGE(map, adr, len);
1238 ENABLE_VPP(map); 1491 ENABLE_VPP(map);
1492 xip_disable(map, chip, adr);
1493
1239 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1494 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1240 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 1495 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1241 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1496 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
@@ -1246,10 +1501,10 @@ static inline int do_erase_oneblock(struct map_info *map, struct flchip *chip, u
1246 chip->state = FL_ERASING; 1501 chip->state = FL_ERASING;
1247 chip->erase_suspended = 0; 1502 chip->erase_suspended = 0;
1248 chip->in_progress_block_addr = adr; 1503 chip->in_progress_block_addr = adr;
1249 1504
1250 cfi_spin_unlock(chip->mutex); 1505 INVALIDATE_CACHE_UDELAY(map, chip,
1251 msleep(chip->erase_time/2); 1506 adr, len,
1252 cfi_spin_lock(chip->mutex); 1507 chip->erase_time*500);
1253 1508
1254 timeo = jiffies + (HZ*20); 1509 timeo = jiffies + (HZ*20);
1255 1510
@@ -1258,10 +1513,10 @@ static inline int do_erase_oneblock(struct map_info *map, struct flchip *chip, u
1258 /* Someone's suspended the erase. Sleep */ 1513 /* Someone's suspended the erase. Sleep */
1259 set_current_state(TASK_UNINTERRUPTIBLE); 1514 set_current_state(TASK_UNINTERRUPTIBLE);
1260 add_wait_queue(&chip->wq, &wait); 1515 add_wait_queue(&chip->wq, &wait);
1261 cfi_spin_unlock(chip->mutex); 1516 spin_unlock(chip->mutex);
1262 schedule(); 1517 schedule();
1263 remove_wait_queue(&chip->wq, &wait); 1518 remove_wait_queue(&chip->wq, &wait);
1264 cfi_spin_lock(chip->mutex); 1519 spin_lock(chip->mutex);
1265 continue; 1520 continue;
1266 } 1521 }
1267 if (chip->erase_suspended) { 1522 if (chip->erase_suspended) {
@@ -1271,31 +1526,33 @@ static inline int do_erase_oneblock(struct map_info *map, struct flchip *chip, u
1271 chip->erase_suspended = 0; 1526 chip->erase_suspended = 0;
1272 } 1527 }
1273 1528
1274 if (chip_ready(map, adr)) 1529 if (chip_ready(map, adr)) {
1275 goto op_done; 1530 xip_enable(map, chip, adr);
1531 break;
1532 }
1276 1533
1277 if (time_after(jiffies, timeo)) 1534 if (time_after(jiffies, timeo)) {
1535 xip_enable(map, chip, adr);
1536 printk(KERN_WARNING "MTD %s(): software timeout\n",
1537 __func__ );
1278 break; 1538 break;
1539 }
1279 1540
1280 /* Latency issues. Drop the lock, wait a while and retry */ 1541 /* Latency issues. Drop the lock, wait a while and retry */
1281 cfi_spin_unlock(chip->mutex); 1542 UDELAY(map, chip, adr, 1000000/HZ);
1282 set_current_state(TASK_UNINTERRUPTIBLE); 1543 }
1283 schedule_timeout(1); 1544 /* Did we succeed? */
1284 cfi_spin_lock(chip->mutex); 1545 if (!chip_good(map, adr, map_word_ff(map))) {
1546 /* reset on all failures. */
1547 map_write( map, CMD(0xF0), chip->start );
1548 /* FIXME - should have reset delay before continuing */
1549
1550 ret = -EIO;
1285 } 1551 }
1286
1287 printk(KERN_WARNING "MTD %s(): software timeout\n",
1288 __func__ );
1289
1290 /* reset on all failures. */
1291 map_write( map, CMD(0xF0), chip->start );
1292 /* FIXME - should have reset delay before continuing */
1293 1552
1294 ret = -EIO;
1295 op_done:
1296 chip->state = FL_READY; 1553 chip->state = FL_READY;
1297 put_chip(map, chip, adr); 1554 put_chip(map, chip, adr);
1298 cfi_spin_unlock(chip->mutex); 1555 spin_unlock(chip->mutex);
1299 return ret; 1556 return ret;
1300} 1557}
1301 1558
@@ -1355,7 +1612,7 @@ static void cfi_amdstd_sync (struct mtd_info *mtd)
1355 chip = &cfi->chips[i]; 1612 chip = &cfi->chips[i];
1356 1613
1357 retry: 1614 retry:
1358 cfi_spin_lock(chip->mutex); 1615 spin_lock(chip->mutex);
1359 1616
1360 switch(chip->state) { 1617 switch(chip->state) {
1361 case FL_READY: 1618 case FL_READY:
@@ -1369,14 +1626,14 @@ static void cfi_amdstd_sync (struct mtd_info *mtd)
1369 * with the chip now anyway. 1626 * with the chip now anyway.
1370 */ 1627 */
1371 case FL_SYNCING: 1628 case FL_SYNCING:
1372 cfi_spin_unlock(chip->mutex); 1629 spin_unlock(chip->mutex);
1373 break; 1630 break;
1374 1631
1375 default: 1632 default:
1376 /* Not an idle state */ 1633 /* Not an idle state */
1377 add_wait_queue(&chip->wq, &wait); 1634 add_wait_queue(&chip->wq, &wait);
1378 1635
1379 cfi_spin_unlock(chip->mutex); 1636 spin_unlock(chip->mutex);
1380 1637
1381 schedule(); 1638 schedule();
1382 1639
@@ -1391,13 +1648,13 @@ static void cfi_amdstd_sync (struct mtd_info *mtd)
1391 for (i--; i >=0; i--) { 1648 for (i--; i >=0; i--) {
1392 chip = &cfi->chips[i]; 1649 chip = &cfi->chips[i];
1393 1650
1394 cfi_spin_lock(chip->mutex); 1651 spin_lock(chip->mutex);
1395 1652
1396 if (chip->state == FL_SYNCING) { 1653 if (chip->state == FL_SYNCING) {
1397 chip->state = chip->oldstate; 1654 chip->state = chip->oldstate;
1398 wake_up(&chip->wq); 1655 wake_up(&chip->wq);
1399 } 1656 }
1400 cfi_spin_unlock(chip->mutex); 1657 spin_unlock(chip->mutex);
1401 } 1658 }
1402} 1659}
1403 1660
@@ -1413,7 +1670,7 @@ static int cfi_amdstd_suspend(struct mtd_info *mtd)
1413 for (i=0; !ret && i<cfi->numchips; i++) { 1670 for (i=0; !ret && i<cfi->numchips; i++) {
1414 chip = &cfi->chips[i]; 1671 chip = &cfi->chips[i];
1415 1672
1416 cfi_spin_lock(chip->mutex); 1673 spin_lock(chip->mutex);
1417 1674
1418 switch(chip->state) { 1675 switch(chip->state) {
1419 case FL_READY: 1676 case FL_READY:
@@ -1433,7 +1690,7 @@ static int cfi_amdstd_suspend(struct mtd_info *mtd)
1433 ret = -EAGAIN; 1690 ret = -EAGAIN;
1434 break; 1691 break;
1435 } 1692 }
1436 cfi_spin_unlock(chip->mutex); 1693 spin_unlock(chip->mutex);
1437 } 1694 }
1438 1695
1439 /* Unlock the chips again */ 1696 /* Unlock the chips again */
@@ -1442,13 +1699,13 @@ static int cfi_amdstd_suspend(struct mtd_info *mtd)
1442 for (i--; i >=0; i--) { 1699 for (i--; i >=0; i--) {
1443 chip = &cfi->chips[i]; 1700 chip = &cfi->chips[i];
1444 1701
1445 cfi_spin_lock(chip->mutex); 1702 spin_lock(chip->mutex);
1446 1703
1447 if (chip->state == FL_PM_SUSPENDED) { 1704 if (chip->state == FL_PM_SUSPENDED) {
1448 chip->state = chip->oldstate; 1705 chip->state = chip->oldstate;
1449 wake_up(&chip->wq); 1706 wake_up(&chip->wq);
1450 } 1707 }
1451 cfi_spin_unlock(chip->mutex); 1708 spin_unlock(chip->mutex);
1452 } 1709 }
1453 } 1710 }
1454 1711
@@ -1467,7 +1724,7 @@ static void cfi_amdstd_resume(struct mtd_info *mtd)
1467 1724
1468 chip = &cfi->chips[i]; 1725 chip = &cfi->chips[i];
1469 1726
1470 cfi_spin_lock(chip->mutex); 1727 spin_lock(chip->mutex);
1471 1728
1472 if (chip->state == FL_PM_SUSPENDED) { 1729 if (chip->state == FL_PM_SUSPENDED) {
1473 chip->state = FL_READY; 1730 chip->state = FL_READY;
@@ -1477,7 +1734,7 @@ static void cfi_amdstd_resume(struct mtd_info *mtd)
1477 else 1734 else
1478 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n"); 1735 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1479 1736
1480 cfi_spin_unlock(chip->mutex); 1737 spin_unlock(chip->mutex);
1481 } 1738 }
1482} 1739}
1483 1740