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path: root/drivers/mmc/host/sdhci.c
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Diffstat (limited to 'drivers/mmc/host/sdhci.c')
-rw-r--r--drivers/mmc/host/sdhci.c34
1 files changed, 32 insertions, 2 deletions
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 07c2048b230b..b413aa6c246b 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -55,6 +55,10 @@ static unsigned int debug_quirks = 0;
55#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7) 55#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7)
56/* Controller needs to be reset after each request to stay stable */ 56/* Controller needs to be reset after each request to stay stable */
57#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8) 57#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8)
58/* Controller needs voltage and power writes to happen separately */
59#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<9)
60/* Controller has an off-by-one issue with timeout value */
61#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<10)
58 62
59static const struct pci_device_id pci_ids[] __devinitdata = { 63static const struct pci_device_id pci_ids[] __devinitdata = {
60 { 64 {
@@ -115,7 +119,8 @@ static const struct pci_device_id pci_ids[] __devinitdata = {
115 .subvendor = PCI_ANY_ID, 119 .subvendor = PCI_ANY_ID,
116 .subdevice = PCI_ANY_ID, 120 .subdevice = PCI_ANY_ID,
117 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE | 121 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
118 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS, 122 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
123 SDHCI_QUIRK_BROKEN_DMA,
119 }, 124 },
120 125
121 { 126 {
@@ -124,7 +129,17 @@ static const struct pci_device_id pci_ids[] __devinitdata = {
124 .subvendor = PCI_ANY_ID, 129 .subvendor = PCI_ANY_ID,
125 .subdevice = PCI_ANY_ID, 130 .subdevice = PCI_ANY_ID,
126 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE | 131 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
127 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS, 132 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
133 SDHCI_QUIRK_BROKEN_DMA,
134 },
135
136 {
137 .vendor = PCI_VENDOR_ID_MARVELL,
138 .device = PCI_DEVICE_ID_MARVELL_CAFE_SD,
139 .subvendor = PCI_ANY_ID,
140 .subdevice = PCI_ANY_ID,
141 .driver_data = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
142 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL,
128 }, 143 },
129 144
130 { 145 {
@@ -469,6 +484,13 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
469 break; 484 break;
470 } 485 }
471 486
487 /*
488 * Compensate for an off-by-one error in the CaFe hardware; otherwise,
489 * a too-small count gives us interrupt timeouts.
490 */
491 if ((host->chip->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL))
492 count++;
493
472 if (count >= 0xF) { 494 if (count >= 0xF) {
473 printk(KERN_WARNING "%s: Too large timeout requested!\n", 495 printk(KERN_WARNING "%s: Too large timeout requested!\n",
474 mmc_hostname(host->mmc)); 496 mmc_hostname(host->mmc));
@@ -774,6 +796,14 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
774 BUG(); 796 BUG();
775 } 797 }
776 798
799 /*
800 * At least the CaFe chip gets confused if we set the voltage
801 * and set turn on power at the same time, so set the voltage first.
802 */
803 if ((host->chip->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
804 writeb(pwr & ~SDHCI_POWER_ON,
805 host->ioaddr + SDHCI_POWER_CONTROL);
806
777 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); 807 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
778 808
779out: 809out: