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path: root/drivers/mfd/db8500-prcmu.c
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Diffstat (limited to 'drivers/mfd/db8500-prcmu.c')
-rw-r--r--drivers/mfd/db8500-prcmu.c17
1 files changed, 6 insertions, 11 deletions
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index dc8826d8d69d..67d8b25d183e 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -36,7 +36,6 @@
36#include <mach/hardware.h> 36#include <mach/hardware.h>
37#include <mach/irqs.h> 37#include <mach/irqs.h>
38#include <mach/db8500-regs.h> 38#include <mach/db8500-regs.h>
39#include <mach/id.h>
40#include "dbx500-prcmu-regs.h" 39#include "dbx500-prcmu-regs.h"
41 40
42/* Offset for the firmware version within the TCPM */ 41/* Offset for the firmware version within the TCPM */
@@ -216,10 +215,8 @@
216#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) 215#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
217#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) 216#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
218#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) 217#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
219#define PRCMU_I2C_WRITE(slave) \ 218#define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
220 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) 219#define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
221#define PRCMU_I2C_READ(slave) \
222 (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
223#define PRCMU_I2C_STOP_EN BIT(3) 220#define PRCMU_I2C_STOP_EN BIT(3)
224 221
225/* Mailbox 5 ACKs */ 222/* Mailbox 5 ACKs */
@@ -1049,12 +1046,13 @@ int db8500_prcmu_get_ddr_opp(void)
1049 * 1046 *
1050 * This function sets the operating point of the DDR. 1047 * This function sets the operating point of the DDR.
1051 */ 1048 */
1049static bool enable_set_ddr_opp;
1052int db8500_prcmu_set_ddr_opp(u8 opp) 1050int db8500_prcmu_set_ddr_opp(u8 opp)
1053{ 1051{
1054 if (opp < DDR_100_OPP || opp > DDR_25_OPP) 1052 if (opp < DDR_100_OPP || opp > DDR_25_OPP)
1055 return -EINVAL; 1053 return -EINVAL;
1056 /* Changing the DDR OPP can hang the hardware pre-v21 */ 1054 /* Changing the DDR OPP can hang the hardware pre-v21 */
1057 if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) 1055 if (enable_set_ddr_opp)
1058 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); 1056 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
1059 1057
1060 return 0; 1058 return 0;
@@ -2790,6 +2788,7 @@ void __init db8500_prcmu_early_init(void)
2790 pr_err("prcmu: Unsupported chip version\n"); 2788 pr_err("prcmu: Unsupported chip version\n");
2791 BUG(); 2789 BUG();
2792 } 2790 }
2791 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
2793 2792
2794 spin_lock_init(&mb0_transfer.lock); 2793 spin_lock_init(&mb0_transfer.lock);
2795 spin_lock_init(&mb0_transfer.dbb_irqs_lock); 2794 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
@@ -3104,9 +3103,6 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
3104 struct device_node *np = pdev->dev.of_node; 3103 struct device_node *np = pdev->dev.of_node;
3105 int irq = 0, err = 0, i; 3104 int irq = 0, err = 0, i;
3106 3105
3107 if (ux500_is_svp())
3108 return -ENODEV;
3109
3110 init_prcm_registers(); 3106 init_prcm_registers();
3111 3107
3112 /* Clean up the mailbox interrupts after pre-kernel code. */ 3108 /* Clean up the mailbox interrupts after pre-kernel code. */
@@ -3135,8 +3131,7 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
3135 } 3131 }
3136 } 3132 }
3137 3133
3138 if (cpu_is_u8500v20_or_later()) 3134 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3139 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3140 3135
3141 db8500_prcmu_update_cpufreq(); 3136 db8500_prcmu_update_cpufreq();
3142 3137