2 files changed, 152 insertions, 170 deletions
diff --git a/drivers/media/dvb/frontends/s5h1432.c b/drivers/media/dvb/frontends/s5h1432.c
index cff164c812e0..5fc3bf5f1c0b 100644
--- a/drivers/media/dvb/frontends/s5h1432.c
+++ b/drivers/media/dvb/frontends/s5h1432.c
@@ -53,14 +53,13 @@ static int debug;
                printk(arg);    \
        } while (0)
 static int s5h1432_writereg(struct s5h1432_state *state,
-        u8 addr, u8 reg, u8 data)
+                            u8 addr, u8 reg, u8 data)
 {
        int ret;
        u8 buf[] = { reg, data };
-        struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 2 };
+        struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 };
        ret = i2c_transfer(state->i2c, &msg, 1);
@@ -78,14 +77,15 @@ static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
        u8 b1[] = { 0 };
        struct i2c_msg msg[] = {
-                { .addr = addr, .flags = 0, .buf = b0, .len = 1 },
+                {.addr = addr, .flags = 0, .buf = b0, .len = 1},
-                { .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
+                {.addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1}
+        };
        ret = i2c_transfer(state->i2c, msg, 2);
        if (ret != 2)
                printk(KERN_ERR "%s: readreg error (ret == %i)\n",
-                        __func__, ret);
+                       __func__, ret);
        return b1[0];
 }
@@ -94,15 +94,14 @@ static int s5h1432_sleep(struct dvb_frontend *fe)
        return 0;
 }
-static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
+static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe,
+                                         u32 bandwidth)
 {
        struct s5h1432_state *state = fe->demodulator_priv;
        u8 reg = 0;
+        /* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */
-    /* Register        [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2*/
        reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
        reg &= ~(0x0C);
        switch (bandwidth) {
@@ -116,141 +115,129 @@ static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
                reg |= 0x00;
                break;
        default:
-        return 0;
+                return 0;
        }
        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
-    return 1;
+        return 1;
 }
 static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
 {
        struct s5h1432_state *state = fe->demodulator_priv;
        switch (ifFreqHz) {
        case TAIWAN_HI_IF_FREQ_44_MHZ:
-                {
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x15);
+                break;
-                    break;
-                }
        case EUROPE_HI_IF_FREQ_36_MHZ:
-                {
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x40);
+                break;
-                    break;
-                }
        case IF_FREQ_6_MHZ:
-                {
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xe0);
+                break;
-                    break;
-                }
        case IF_FREQ_3point3_MHZ:
-                {
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
+                break;
-                    break;
-                }
        case IF_FREQ_3point5_MHZ:
-                {
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xED);
+                break;
-                    break;
-                }
        case IF_FREQ_4_MHZ:
-                {
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0xAA);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0xAA);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEA);
+                break;
-                    break;
-                }
        default:
                {
-                u32 value = 0;
+                        u32 value = 0;
-                value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
+                        value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
-                                 (u32) 32768) / (48 * 1000));
+                                        (u32) 32768) / (48 * 1000));
-                printk(KERN_INFO "Default IFFreq %d :reg value = 0x%x \n",
+                        printk(KERN_INFO
-                                 ifFreqHz, value);
+                               "Default IFFreq %d :reg value = 0x%x \n",
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 ,
+                               ifFreqHz, value);
-                                 (u8) value & 0xFF);
+                        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 ,
+                                         (u8) value & 0xFF);
-                                 (u8)(value>>8) & 0xFF);
+                        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,
-                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 ,
+                                         (u8) (value >> 8) & 0xFF);
-                                 (u8)(value>>16) & 0xFF);
+                        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,
-                    break;
+                                         (u8) (value >> 16) & 0xFF);
-        }
+                        break;
+                }
        }
-    return 1;
+        return 1;
 }
 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
 static int s5h1432_set_frontend(struct dvb_frontend *fe,
-        struct dvb_frontend_parameters *p)
+                                struct dvb_frontend_parameters *p)
 {
        u32 dvb_bandwidth = 8;
        struct s5h1432_state *state = fe->demodulator_priv;
        if (p->frequency == state->current_frequency) {
-                /*current_frequency = p->frequency;*/
+                /*current_frequency = p->frequency; */
-                /*state->current_frequency = p->frequency;*/
+                /*state->current_frequency = p->frequency; */
        } else {
-                fe->ops.tuner_ops.set_params(fe, p); msleep(300);
+                fe->ops.tuner_ops.set_params(fe, p);
+                msleep(300);
                s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
                switch (p->u.ofdm.bandwidth) {
                case BANDWIDTH_6_MHZ:
-                                dvb_bandwidth = 6;
+                        dvb_bandwidth = 6;
-                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                        s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
-                                break;
+                        break;
                case BANDWIDTH_7_MHZ:
-                                dvb_bandwidth = 7;
+                        dvb_bandwidth = 7;
-                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                        s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
-                                break;
+                        break;
                case BANDWIDTH_8_MHZ:
-                                dvb_bandwidth = 8;
+                        dvb_bandwidth = 8;
-                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                        s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
-                                break;
+                        break;
                default:
-                                return 0;
+                        return 0;
-                        }
+                }
-                /*fe->ops.tuner_ops.set_params(fe, p);*/
+                /*fe->ops.tuner_ops.set_params(fe, p); */
 /*Soft Reset chip*/
-        msleep(30);
+                msleep(30);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1a);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
-        msleep(30);
+                msleep(30);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1b);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
                s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
                switch (p->u.ofdm.bandwidth) {
                case BANDWIDTH_6_MHZ:
-                                dvb_bandwidth = 6;
+                        dvb_bandwidth = 6;
-                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                        s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
-                                break;
+                        break;
                case BANDWIDTH_7_MHZ:
-                                dvb_bandwidth = 7;
+                        dvb_bandwidth = 7;
-                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                        s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
-                                break;
+                        break;
                case BANDWIDTH_8_MHZ:
-                                dvb_bandwidth = 8;
+                        dvb_bandwidth = 8;
-                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                        s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
-                                break;
+                        break;
                default:
-                                return 0;
+                        return 0;
-                        }
+                }
-                /*fe->ops.tuner_ops.set_params(fe,p);*/
+                /*fe->ops.tuner_ops.set_params(fe,p); */
-/*Soft Reset chip*/
+                /*Soft Reset chip*/
-        msleep(30);
+                msleep(30);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1a);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
-        msleep(30);
+                msleep(30);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1b);
+                s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
        }
@@ -259,7 +246,6 @@ static int s5h1432_set_frontend(struct dvb_frontend *fe,
        return 0;
 }
 static int s5h1432_init(struct dvb_frontend *fe)
 {
        struct s5h1432_state *state = fe->demodulator_priv;
@@ -268,66 +254,62 @@ static int s5h1432_init(struct dvb_frontend *fe)
        state->current_frequency = 0;
        printk(KERN_INFO " s5h1432_init().\n");
+        /*Set VSB mode as default, this also does a soft reset */
-    /*Set VSB mode as default, this also does a soft reset*/
+        /*Initialize registers */
-    /*Initialize registers*/
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04,     0xa8);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05,     0x01);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07,     0x70);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19,     0x80);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b,     0x9D);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c,     0x30);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d,     0x20);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e,     0x1B);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e,     0x40);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42,     0x84);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50,     0x5a);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a,     0xd3);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68,     0x50);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8,     0x3c);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4,     0x10);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc,     0x9c);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA,     0x00);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1,     0x94);
+        /* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */
-/*      s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4,     0xa1);*/
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9,     0x00);
+        /*For NXP tuner*/
-/*For NXP tuner*/
+        /*Set 3.3MHz as default IF frequency */
-    /*Set 3.3MHz as default IF frequency*/
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
+        /* Set reg 0x1E to get the full dynamic range */
-    /* Set reg 0x1E to get the full dynamic range */
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e,     0x31);
+        /* Mode setting in demod */
-/*Mode setting in demod*/
        reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
        reg |= 0x80;
        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
-        /*Serial mode*/
+        /* Serial mode */
-/*Soft Reset chip*/
+        /* Soft Reset chip */
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1a);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
        msleep(30);
-        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1b);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
        return 0;
 }
 static int s5h1432_read_status(struct dvb_frontend *fe, fe_status_t *status)
 {
        return 0;
 }
 static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
-        u16 *signal_strength)
+                                        u16 *signal_strength)
 {
        return 0;
 }
@@ -397,34 +379,34 @@ error:
        kfree(state);
        return NULL;
 }
 EXPORT_SYMBOL(s5h1432_attach);
 static struct dvb_frontend_ops s5h1432_ops = {
        .info = {
-                .name                   = "Samsung s5h1432 DVB-T Frontend",
+                 .name = "Samsung s5h1432 DVB-T Frontend",
-                .type                   = FE_OFDM,
+                 .type = FE_OFDM,
-                .frequency_min          = 177000000,
+                 .frequency_min = 177000000,
-                .frequency_max          = 858000000,
+                 .frequency_max = 858000000,
-                .frequency_stepsize     = 166666,
+                 .frequency_stepsize = 166666,
-                .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
-                FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
-                FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
+                 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
-                FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
+                 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
-                FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
+                 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER},
-        },
+        .init = s5h1432_init,
-        .init                 = s5h1432_init,
+        .sleep = s5h1432_sleep,
-        .sleep                = s5h1432_sleep,
+        .set_frontend = s5h1432_set_frontend,
-        .set_frontend         = s5h1432_set_frontend,
+        .get_frontend = s5h1432_get_frontend,
-        .get_frontend         = s5h1432_get_frontend,
+        .get_tune_settings = s5h1432_get_tune_settings,
-        .get_tune_settings    = s5h1432_get_tune_settings,
+        .read_status = s5h1432_read_status,
-        .read_status          = s5h1432_read_status,
+        .read_ber = s5h1432_read_ber,
-        .read_ber             = s5h1432_read_ber,
        .read_signal_strength = s5h1432_read_signal_strength,
-        .read_snr             = s5h1432_read_snr,
+        .read_snr = s5h1432_read_snr,
-        .read_ucblocks        = s5h1432_read_ucblocks,
+        .read_ucblocks = s5h1432_read_ucblocks,
-        .release              = s5h1432_release,
+        .release = s5h1432_release,
 };
 module_param(debug, int, 0644);
diff --git a/drivers/media/dvb/frontends/s5h1432.h b/drivers/media/dvb/frontends/s5h1432.h
index 241a9044d863..6ed654fb9b16 100644
--- a/drivers/media/dvb/frontends/s5h1432.h
+++ b/drivers/media/dvb/frontends/s5h1432.h
@@ -79,9 +79,9 @@ struct s5h1432_config {
 extern struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
                                           struct i2c_adapter *i2c);
 #else
-static inline struct dvb_frontend *s5h1432_attach(
+static inline struct dvb_frontend *s5h1432_attach(const struct s5h1432_config
-        const struct s5h1432_config *config,
+                                                  *config,
-        struct i2c_adapter *i2c)
+                                                  struct i2c_adapter *i2c)
 {
        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
        return NULL;

diff --git a/drivers/media/dvb/frontends/s5h1432.c b/drivers/media/dvb/frontends/s5h1432.c index cff164c812e0..5fc3bf5f1c0b 100644 --- a/drivers/media/dvb/frontends/s5h1432.c +++ b/drivers/media/dvb/frontends/s5h1432.c
@@ -53,14 +53,13 @@ static int debug;
53	printk(arg); \	53	printk(arg); \
54	} while (0)	54	} while (0)
55		55
56
57	static int s5h1432_writereg(struct s5h1432_state *state,	56	static int s5h1432_writereg(struct s5h1432_state *state,
58	u8 addr, u8 reg, u8 data)	57	u8 addr, u8 reg, u8 data)
59	{	58	{
60	int ret;	59	int ret;
61	u8 buf[] = { reg, data };	60	u8 buf[] = { reg, data };
62		61
63	struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 2 };	62	struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 };
64		63
65	ret = i2c_transfer(state->i2c, &msg, 1);	64	ret = i2c_transfer(state->i2c, &msg, 1);
66		65
@@ -78,14 +77,15 @@ static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
78	u8 b1[] = { 0 };	77	u8 b1[] = { 0 };
79		78
80	struct i2c_msg msg[] = {	79	struct i2c_msg msg[] = {
81	{ .addr = addr, .flags = 0, .buf = b0, .len = 1 },	80	{.addr = addr, .flags = 0, .buf = b0, .len = 1},
82	{ .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } };	81	{.addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1}
		82	};
83		83
84	ret = i2c_transfer(state->i2c, msg, 2);	84	ret = i2c_transfer(state->i2c, msg, 2);
85		85
86	if (ret != 2)	86	if (ret != 2)
87	printk(KERN_ERR "%s: readreg error (ret == %i)\n",	87	printk(KERN_ERR "%s: readreg error (ret == %i)\n",
88	__func__, ret);	88	__func__, ret);
89	return b1[0];	89	return b1[0];
90	}	90	}
91		91
@@ -94,15 +94,14 @@ static int s5h1432_sleep(struct dvb_frontend *fe)
94	return 0;	94	return 0;
95	}	95	}
96		96
97	static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, u32 bandwidth)	97	static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe,
		98	u32 bandwidth)
98	{	99	{
99
100	struct s5h1432_state *state = fe->demodulator_priv;	100	struct s5h1432_state *state = fe->demodulator_priv;
101		101
102	u8 reg = 0;	102	u8 reg = 0;
103		103
104		104	/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */
105	/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2*/
106	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);	105	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
107	reg &= ~(0x0C);	106	reg &= ~(0x0C);
108	switch (bandwidth) {	107	switch (bandwidth) {
@@ -116,141 +115,129 @@ static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
116	reg \|= 0x00;	115	reg \|= 0x00;
117	break;	116	break;
118	default:	117	default:
119	return 0;	118	return 0;
120	}	119	}
121	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);	120	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
122	return 1;	121	return 1;
123	}	122	}
124		123
125	static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)	124	static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
126	{	125	{
127
128	struct s5h1432_state *state = fe->demodulator_priv;	126	struct s5h1432_state *state = fe->demodulator_priv;
129		127
130	switch (ifFreqHz) {	128	switch (ifFreqHz) {
131	case TAIWAN_HI_IF_FREQ_44_MHZ:	129	case TAIWAN_HI_IF_FREQ_44_MHZ:
132	{	130	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
133	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);	131	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
134	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);	132	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);
135	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x15);	133	break;
136	break;
137	}
138	case EUROPE_HI_IF_FREQ_36_MHZ:	134	case EUROPE_HI_IF_FREQ_36_MHZ:
139	{	135	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
140	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);	136	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
141	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);	137	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);
142	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x40);	138	break;
143	break;
144	}
145	case IF_FREQ_6_MHZ:	139	case IF_FREQ_6_MHZ:
146	{	140	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
147	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);	141	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
148	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);	142	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);
149	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xe0);	143	break;
150	break;
151	}
152	case IF_FREQ_3point3_MHZ:	144	case IF_FREQ_3point3_MHZ:
153	{	145	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
154	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);	146	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
155	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);	147	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
156	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);	148	break;
157	break;
158	}
159	case IF_FREQ_3point5_MHZ:	149	case IF_FREQ_3point5_MHZ:
160	{	150	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
161	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);	151	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
162	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);	152	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);
163	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xED);	153	break;
164	break;
165	}
166	case IF_FREQ_4_MHZ:	154	case IF_FREQ_4_MHZ:
167	{	155	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);
168	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0xAA);	156	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);
169	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0xAA);	157	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);
170	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEA);	158	break;
171	break;
172	}
173	default:	159	default:
174	{	160	{
175	u32 value = 0;	161	u32 value = 0;
176	value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *	162	value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
177	(u32) 32768) / (48 * 1000));	163	(u32) 32768) / (48 * 1000));
178	printk(KERN_INFO "Default IFFreq %d :reg value = 0x%x \n",	164	printk(KERN_INFO
179	ifFreqHz, value);	165	"Default IFFreq %d :reg value = 0x%x \n",
180	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 ,	166	ifFreqHz, value);
181	(u8) value & 0xFF);	167	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
182	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 ,	168	(u8) value & 0xFF);
183	(u8)(value>>8) & 0xFF);	169	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,
184	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 ,	170	(u8) (value >> 8) & 0xFF);
185	(u8)(value>>16) & 0xFF);	171	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,
186	break;	172	(u8) (value >> 16) & 0xFF);
187	}	173	break;
		174	}
188		175
189	}	176	}
190		177
191	return 1;	178	return 1;
192	}	179	}
193		180
194	/* Talk to the demod, set the FEC, GUARD, QAM settings etc */	181	/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
195	static int s5h1432_set_frontend(struct dvb_frontend *fe,	182	static int s5h1432_set_frontend(struct dvb_frontend *fe,
196	struct dvb_frontend_parameters *p)	183	struct dvb_frontend_parameters *p)
197	{	184	{
198	u32 dvb_bandwidth = 8;	185	u32 dvb_bandwidth = 8;
199	struct s5h1432_state *state = fe->demodulator_priv;	186	struct s5h1432_state *state = fe->demodulator_priv;
200		187
201	if (p->frequency == state->current_frequency) {	188	if (p->frequency == state->current_frequency) {
202	/current_frequency = p->frequency;/	189	/current_frequency = p->frequency; /
203	/state->current_frequency = p->frequency;/	190	/state->current_frequency = p->frequency; /
204	} else {	191	} else {
205	fe->ops.tuner_ops.set_params(fe, p); msleep(300);	192	fe->ops.tuner_ops.set_params(fe, p);
		193	msleep(300);
206	s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);	194	s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
207	switch (p->u.ofdm.bandwidth) {	195	switch (p->u.ofdm.bandwidth) {
208	case BANDWIDTH_6_MHZ:	196	case BANDWIDTH_6_MHZ:
209	dvb_bandwidth = 6;	197	dvb_bandwidth = 6;
210	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);	198	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
211	break;	199	break;
212	case BANDWIDTH_7_MHZ:	200	case BANDWIDTH_7_MHZ:
213	dvb_bandwidth = 7;	201	dvb_bandwidth = 7;
214	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);	202	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
215	break;	203	break;
216	case BANDWIDTH_8_MHZ:	204	case BANDWIDTH_8_MHZ:
217	dvb_bandwidth = 8;	205	dvb_bandwidth = 8;
218	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);	206	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
219	break;	207	break;
220	default:	208	default:
221	return 0;	209	return 0;
222	}	210	}
223	/fe->ops.tuner_ops.set_params(fe, p);/	211	/fe->ops.tuner_ops.set_params(fe, p); /
224	/Soft Reset chip/	212	/Soft Reset chip/
225	msleep(30);	213	msleep(30);
226	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);	214	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
227	msleep(30);	215	msleep(30);
228	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);	216	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
229
230		217
231	s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);	218	s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
232	switch (p->u.ofdm.bandwidth) {	219	switch (p->u.ofdm.bandwidth) {
233	case BANDWIDTH_6_MHZ:	220	case BANDWIDTH_6_MHZ:
234	dvb_bandwidth = 6;	221	dvb_bandwidth = 6;
235	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);	222	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
236	break;	223	break;
237	case BANDWIDTH_7_MHZ:	224	case BANDWIDTH_7_MHZ:
238	dvb_bandwidth = 7;	225	dvb_bandwidth = 7;
239	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);	226	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
240	break;	227	break;
241	case BANDWIDTH_8_MHZ:	228	case BANDWIDTH_8_MHZ:
242	dvb_bandwidth = 8;	229	dvb_bandwidth = 8;
243	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);	230	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
244	break;	231	break;
245	default:	232	default:
246	return 0;	233	return 0;
247	}	234	}
248	/fe->ops.tuner_ops.set_params(fe,p);/	235	/fe->ops.tuner_ops.set_params(fe,p); /
249	/Soft Reset chip/	236	/Soft Reset chip/
250	msleep(30);	237	msleep(30);
251	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);	238	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
252	msleep(30);	239	msleep(30);
253	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);	240	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
254		241
255	}	242	}
256		243
@@ -259,7 +246,6 @@ static int s5h1432_set_frontend(struct dvb_frontend *fe,
259	return 0;	246	return 0;
260	}	247	}
261		248
262
263	static int s5h1432_init(struct dvb_frontend *fe)	249	static int s5h1432_init(struct dvb_frontend *fe)
264	{	250	{
265	struct s5h1432_state *state = fe->demodulator_priv;	251	struct s5h1432_state *state = fe->demodulator_priv;
@@ -268,66 +254,62 @@ static int s5h1432_init(struct dvb_frontend *fe)
268	state->current_frequency = 0;	254	state->current_frequency = 0;
269	printk(KERN_INFO " s5h1432_init().\n");	255	printk(KERN_INFO " s5h1432_init().\n");
270		256
271		257	/Set VSB mode as default, this also does a soft reset /
272	/Set VSB mode as default, this also does a soft reset/	258	/Initialize registers /
273	/Initialize registers/	259
274		260	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
275	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);	261	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
276	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);	262	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
277	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);	263	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
278	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);	264	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
279	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);	265	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
280	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);	266	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
281	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);	267	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
282	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);	268	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
283	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);	269	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
284	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);	270	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
285	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);	271	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
286	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);	272	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
287	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);	273	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
288	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);	274	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
289	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);	275	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
290	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);	276	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
291	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);	277	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
292	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);	278	/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */
293	/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1);*/	279	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
294	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);	280
295		281	/For NXP tuner/
296	/For NXP tuner/	282
297		283	/Set 3.3MHz as default IF frequency /
298	/Set 3.3MHz as default IF frequency/	284	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
299	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);	285	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
300	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);	286	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
301	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);	287	/* Set reg 0x1E to get the full dynamic range */
302	/* Set reg 0x1E to get the full dynamic range */	288	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
303	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);	289
304		290	/* Mode setting in demod */
305	/Mode setting in demod/
306	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);	291	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
307	reg \|= 0x80;	292	reg \|= 0x80;
308	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);	293	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
309	/Serial mode/	294	/* Serial mode */
310		295
311	/Soft Reset chip/	296	/* Soft Reset chip */
312		297
313	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);	298	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
314	msleep(30);	299	msleep(30);
315	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);	300	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
316		301
317		302
318	return 0;	303	return 0;
319	}	304	}
320		305
321
322	static int s5h1432_read_status(struct dvb_frontend fe, fe_status_t status)	306	static int s5h1432_read_status(struct dvb_frontend fe, fe_status_t status)
323	{	307	{
324	return 0;	308	return 0;
325	}	309	}
326		310
327
328
329	static int s5h1432_read_signal_strength(struct dvb_frontend *fe,	311	static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
330	u16 *signal_strength)	312	u16 *signal_strength)
331	{	313	{
332	return 0;	314	return 0;
333	}	315	}
@@ -397,34 +379,34 @@ error:
397	kfree(state);	379	kfree(state);
398	return NULL;	380	return NULL;
399	}	381	}
		382
400	EXPORT_SYMBOL(s5h1432_attach);	383	EXPORT_SYMBOL(s5h1432_attach);
401		384
402	static struct dvb_frontend_ops s5h1432_ops = {	385	static struct dvb_frontend_ops s5h1432_ops = {
403		386
404	.info = {	387	.info = {
405	.name = "Samsung s5h1432 DVB-T Frontend",	388	.name = "Samsung s5h1432 DVB-T Frontend",
406	.type = FE_OFDM,	389	.type = FE_OFDM,
407	.frequency_min = 177000000,	390	.frequency_min = 177000000,
408	.frequency_max = 858000000,	391	.frequency_max = 858000000,
409	.frequency_stepsize = 166666,	392	.frequency_stepsize = 166666,
410	.caps = FE_CAN_FEC_1_2 \| FE_CAN_FEC_2_3 \| FE_CAN_FEC_3_4 \|	393	.caps = FE_CAN_FEC_1_2 \| FE_CAN_FEC_2_3 \| FE_CAN_FEC_3_4 \|
411	FE_CAN_FEC_5_6 \| FE_CAN_FEC_7_8 \| FE_CAN_FEC_AUTO \|	394	FE_CAN_FEC_5_6 \| FE_CAN_FEC_7_8 \| FE_CAN_FEC_AUTO \|
412	FE_CAN_QPSK \| FE_CAN_QAM_16 \| FE_CAN_QAM_64 \| FE_CAN_QAM_AUTO \|	395	FE_CAN_QPSK \| FE_CAN_QAM_16 \| FE_CAN_QAM_64 \| FE_CAN_QAM_AUTO \|
413	FE_CAN_HIERARCHY_AUTO \| FE_CAN_GUARD_INTERVAL_AUTO \|	396	FE_CAN_HIERARCHY_AUTO \| FE_CAN_GUARD_INTERVAL_AUTO \|
414	FE_CAN_TRANSMISSION_MODE_AUTO \| FE_CAN_RECOVER	397	FE_CAN_TRANSMISSION_MODE_AUTO \| FE_CAN_RECOVER},
415	},	398
416		399	.init = s5h1432_init,
417	.init = s5h1432_init,	400	.sleep = s5h1432_sleep,
418	.sleep = s5h1432_sleep,	401	.set_frontend = s5h1432_set_frontend,
419	.set_frontend = s5h1432_set_frontend,	402	.get_frontend = s5h1432_get_frontend,
420	.get_frontend = s5h1432_get_frontend,	403	.get_tune_settings = s5h1432_get_tune_settings,
421	.get_tune_settings = s5h1432_get_tune_settings,	404	.read_status = s5h1432_read_status,
422	.read_status = s5h1432_read_status,	405	.read_ber = s5h1432_read_ber,
423	.read_ber = s5h1432_read_ber,
424	.read_signal_strength = s5h1432_read_signal_strength,	406	.read_signal_strength = s5h1432_read_signal_strength,
425	.read_snr = s5h1432_read_snr,	407	.read_snr = s5h1432_read_snr,
426	.read_ucblocks = s5h1432_read_ucblocks,	408	.read_ucblocks = s5h1432_read_ucblocks,
427	.release = s5h1432_release,	409	.release = s5h1432_release,
428	};	410	};
429		411
430	module_param(debug, int, 0644);	412	module_param(debug, int, 0644);


diff --git a/drivers/media/dvb/frontends/s5h1432.h b/drivers/media/dvb/frontends/s5h1432.h index 241a9044d863..6ed654fb9b16 100644 --- a/drivers/media/dvb/frontends/s5h1432.h +++ b/drivers/media/dvb/frontends/s5h1432.h
@@ -79,9 +79,9 @@ struct s5h1432_config {
79	extern struct dvb_frontend s5h1432_attach(const struct s5h1432_config config,	79	extern struct dvb_frontend s5h1432_attach(const struct s5h1432_config config,
80	struct i2c_adapter *i2c);	80	struct i2c_adapter *i2c);
81	#else	81	#else
82	static inline struct dvb_frontend *s5h1432_attach(	82	static inline struct dvb_frontend *s5h1432_attach(const struct s5h1432_config
83	const struct s5h1432_config *config,	83	*config,
84	struct i2c_adapter *i2c)	84	struct i2c_adapter *i2c)
85	{	85	{
86	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);	86	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
87	return NULL;	87	return NULL;