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-rw-r--r--drivers/media/video/s5p-fimc/fimc-reg.h326
1 files changed, 0 insertions, 326 deletions
diff --git a/drivers/media/video/s5p-fimc/fimc-reg.h b/drivers/media/video/s5p-fimc/fimc-reg.h
deleted file mode 100644
index 579ac8ac03de..000000000000
--- a/drivers/media/video/s5p-fimc/fimc-reg.h
+++ /dev/null
@@ -1,326 +0,0 @@
1/*
2 * Samsung camera host interface (FIMC) registers definition
3 *
4 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef FIMC_REG_H_
12#define FIMC_REG_H_
13
14#include "fimc-core.h"
15
16/* Input source format */
17#define FIMC_REG_CISRCFMT 0x00
18#define FIMC_REG_CISRCFMT_ITU601_8BIT (1 << 31)
19#define FIMC_REG_CISRCFMT_ITU601_16BIT (1 << 29)
20#define FIMC_REG_CISRCFMT_ORDER422_YCBYCR (0 << 14)
21#define FIMC_REG_CISRCFMT_ORDER422_YCRYCB (1 << 14)
22#define FIMC_REG_CISRCFMT_ORDER422_CBYCRY (2 << 14)
23#define FIMC_REG_CISRCFMT_ORDER422_CRYCBY (3 << 14)
24
25/* Window offset */
26#define FIMC_REG_CIWDOFST 0x04
27#define FIMC_REG_CIWDOFST_OFF_EN (1 << 31)
28#define FIMC_REG_CIWDOFST_CLROVFIY (1 << 30)
29#define FIMC_REG_CIWDOFST_CLROVRLB (1 << 29)
30#define FIMC_REG_CIWDOFST_HOROFF_MASK (0x7ff << 16)
31#define FIMC_REG_CIWDOFST_CLROVFICB (1 << 15)
32#define FIMC_REG_CIWDOFST_CLROVFICR (1 << 14)
33#define FIMC_REG_CIWDOFST_VEROFF_MASK (0xfff << 0)
34
35/* Global control */
36#define FIMC_REG_CIGCTRL 0x08
37#define FIMC_REG_CIGCTRL_SWRST (1 << 31)
38#define FIMC_REG_CIGCTRL_CAMRST_A (1 << 30)
39#define FIMC_REG_CIGCTRL_SELCAM_ITU_A (1 << 29)
40#define FIMC_REG_CIGCTRL_TESTPAT_NORMAL (0 << 27)
41#define FIMC_REG_CIGCTRL_TESTPAT_COLOR_BAR (1 << 27)
42#define FIMC_REG_CIGCTRL_TESTPAT_HOR_INC (2 << 27)
43#define FIMC_REG_CIGCTRL_TESTPAT_VER_INC (3 << 27)
44#define FIMC_REG_CIGCTRL_TESTPAT_MASK (3 << 27)
45#define FIMC_REG_CIGCTRL_TESTPAT_SHIFT 27
46#define FIMC_REG_CIGCTRL_INVPOLPCLK (1 << 26)
47#define FIMC_REG_CIGCTRL_INVPOLVSYNC (1 << 25)
48#define FIMC_REG_CIGCTRL_INVPOLHREF (1 << 24)
49#define FIMC_REG_CIGCTRL_IRQ_OVFEN (1 << 22)
50#define FIMC_REG_CIGCTRL_HREF_MASK (1 << 21)
51#define FIMC_REG_CIGCTRL_IRQ_LEVEL (1 << 20)
52#define FIMC_REG_CIGCTRL_IRQ_CLR (1 << 19)
53#define FIMC_REG_CIGCTRL_IRQ_ENABLE (1 << 16)
54#define FIMC_REG_CIGCTRL_SHDW_DISABLE (1 << 12)
55#define FIMC_REG_CIGCTRL_CAM_JPEG (1 << 8)
56#define FIMC_REG_CIGCTRL_SELCAM_MIPI_A (1 << 7)
57#define FIMC_REG_CIGCTRL_CAMIF_SELWB (1 << 6)
58/* 0 - ITU601; 1 - ITU709 */
59#define FIMC_REG_CIGCTRL_CSC_ITU601_709 (1 << 5)
60#define FIMC_REG_CIGCTRL_INVPOLHSYNC (1 << 4)
61#define FIMC_REG_CIGCTRL_SELCAM_MIPI (1 << 3)
62#define FIMC_REG_CIGCTRL_INVPOLFIELD (1 << 1)
63#define FIMC_REG_CIGCTRL_INTERLACE (1 << 0)
64
65/* Window offset 2 */
66#define FIMC_REG_CIWDOFST2 0x14
67#define FIMC_REG_CIWDOFST2_HOROFF_MASK (0xfff << 16)
68#define FIMC_REG_CIWDOFST2_VEROFF_MASK (0xfff << 0)
69
70/* Output DMA Y/Cb/Cr plane start addresses */
71#define FIMC_REG_CIOYSA(n) (0x18 + (n) * 4)
72#define FIMC_REG_CIOCBSA(n) (0x28 + (n) * 4)
73#define FIMC_REG_CIOCRSA(n) (0x38 + (n) * 4)
74
75/* Target image format */
76#define FIMC_REG_CITRGFMT 0x48
77#define FIMC_REG_CITRGFMT_INROT90 (1 << 31)
78#define FIMC_REG_CITRGFMT_YCBCR420 (0 << 29)
79#define FIMC_REG_CITRGFMT_YCBCR422 (1 << 29)
80#define FIMC_REG_CITRGFMT_YCBCR422_1P (2 << 29)
81#define FIMC_REG_CITRGFMT_RGB (3 << 29)
82#define FIMC_REG_CITRGFMT_FMT_MASK (3 << 29)
83#define FIMC_REG_CITRGFMT_HSIZE_MASK (0xfff << 16)
84#define FIMC_REG_CITRGFMT_FLIP_SHIFT 14
85#define FIMC_REG_CITRGFMT_FLIP_NORMAL (0 << 14)
86#define FIMC_REG_CITRGFMT_FLIP_X_MIRROR (1 << 14)
87#define FIMC_REG_CITRGFMT_FLIP_Y_MIRROR (2 << 14)
88#define FIMC_REG_CITRGFMT_FLIP_180 (3 << 14)
89#define FIMC_REG_CITRGFMT_FLIP_MASK (3 << 14)
90#define FIMC_REG_CITRGFMT_OUTROT90 (1 << 13)
91#define FIMC_REG_CITRGFMT_VSIZE_MASK (0xfff << 0)
92
93/* Output DMA control */
94#define FIMC_REG_CIOCTRL 0x4c
95#define FIMC_REG_CIOCTRL_ORDER422_MASK (3 << 0)
96#define FIMC_REG_CIOCTRL_ORDER422_CRYCBY (0 << 0)
97#define FIMC_REG_CIOCTRL_ORDER422_CBYCRY (1 << 0)
98#define FIMC_REG_CIOCTRL_ORDER422_YCRYCB (2 << 0)
99#define FIMC_REG_CIOCTRL_ORDER422_YCBYCR (3 << 0)
100#define FIMC_REG_CIOCTRL_LASTIRQ_ENABLE (1 << 2)
101#define FIMC_REG_CIOCTRL_YCBCR_3PLANE (0 << 3)
102#define FIMC_REG_CIOCTRL_YCBCR_2PLANE (1 << 3)
103#define FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK (1 << 3)
104#define FIMC_REG_CIOCTRL_ALPHA_OUT_MASK (0xff << 4)
105#define FIMC_REG_CIOCTRL_RGB16FMT_MASK (3 << 16)
106#define FIMC_REG_CIOCTRL_RGB565 (0 << 16)
107#define FIMC_REG_CIOCTRL_ARGB1555 (1 << 16)
108#define FIMC_REG_CIOCTRL_ARGB4444 (2 << 16)
109#define FIMC_REG_CIOCTRL_ORDER2P_SHIFT 24
110#define FIMC_REG_CIOCTRL_ORDER2P_MASK (3 << 24)
111#define FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB (0 << 24)
112
113/* Pre-scaler control 1 */
114#define FIMC_REG_CISCPRERATIO 0x50
115
116#define FIMC_REG_CISCPREDST 0x54
117
118/* Main scaler control */
119#define FIMC_REG_CISCCTRL 0x58
120#define FIMC_REG_CISCCTRL_SCALERBYPASS (1 << 31)
121#define FIMC_REG_CISCCTRL_SCALEUP_H (1 << 30)
122#define FIMC_REG_CISCCTRL_SCALEUP_V (1 << 29)
123#define FIMC_REG_CISCCTRL_CSCR2Y_WIDE (1 << 28)
124#define FIMC_REG_CISCCTRL_CSCY2R_WIDE (1 << 27)
125#define FIMC_REG_CISCCTRL_LCDPATHEN_FIFO (1 << 26)
126#define FIMC_REG_CISCCTRL_INTERLACE (1 << 25)
127#define FIMC_REG_CISCCTRL_SCALERSTART (1 << 15)
128#define FIMC_REG_CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
129#define FIMC_REG_CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
130#define FIMC_REG_CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
131#define FIMC_REG_CISCCTRL_INRGB_FMT_MASK (3 << 13)
132#define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
133#define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
134#define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
135#define FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
136#define FIMC_REG_CISCCTRL_RGB_EXT (1 << 10)
137#define FIMC_REG_CISCCTRL_ONE2ONE (1 << 9)
138#define FIMC_REG_CISCCTRL_MHRATIO(x) ((x) << 16)
139#define FIMC_REG_CISCCTRL_MVRATIO(x) ((x) << 0)
140#define FIMC_REG_CISCCTRL_MHRATIO_MASK (0x1ff << 16)
141#define FIMC_REG_CISCCTRL_MVRATIO_MASK (0x1ff << 0)
142#define FIMC_REG_CISCCTRL_MHRATIO_EXT(x) (((x) >> 6) << 16)
143#define FIMC_REG_CISCCTRL_MVRATIO_EXT(x) (((x) >> 6) << 0)
144
145/* Target area */
146#define FIMC_REG_CITAREA 0x5c
147#define FIMC_REG_CITAREA_MASK 0x0fffffff
148
149/* General status */
150#define FIMC_REG_CISTATUS 0x64
151#define FIMC_REG_CISTATUS_OVFIY (1 << 31)
152#define FIMC_REG_CISTATUS_OVFICB (1 << 30)
153#define FIMC_REG_CISTATUS_OVFICR (1 << 29)
154#define FIMC_REG_CISTATUS_VSYNC (1 << 28)
155#define FIMC_REG_CISTATUS_FRAMECNT_MASK (3 << 26)
156#define FIMC_REG_CISTATUS_FRAMECNT_SHIFT 26
157#define FIMC_REG_CISTATUS_WINOFF_EN (1 << 25)
158#define FIMC_REG_CISTATUS_IMGCPT_EN (1 << 22)
159#define FIMC_REG_CISTATUS_IMGCPT_SCEN (1 << 21)
160#define FIMC_REG_CISTATUS_VSYNC_A (1 << 20)
161#define FIMC_REG_CISTATUS_VSYNC_B (1 << 19)
162#define FIMC_REG_CISTATUS_OVRLB (1 << 18)
163#define FIMC_REG_CISTATUS_FRAME_END (1 << 17)
164#define FIMC_REG_CISTATUS_LASTCAPT_END (1 << 16)
165#define FIMC_REG_CISTATUS_VVALID_A (1 << 15)
166#define FIMC_REG_CISTATUS_VVALID_B (1 << 14)
167
168/* Indexes to the last and the currently processed buffer. */
169#define FIMC_REG_CISTATUS2 0x68
170
171/* Image capture control */
172#define FIMC_REG_CIIMGCPT 0xc0
173#define FIMC_REG_CIIMGCPT_IMGCPTEN (1 << 31)
174#define FIMC_REG_CIIMGCPT_IMGCPTEN_SC (1 << 30)
175#define FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE (1 << 25)
176#define FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT (1 << 18)
177
178/* Frame capture sequence */
179#define FIMC_REG_CICPTSEQ 0xc4
180
181/* Image effect */
182#define FIMC_REG_CIIMGEFF 0xd0
183#define FIMC_REG_CIIMGEFF_IE_ENABLE (1 << 30)
184#define FIMC_REG_CIIMGEFF_IE_SC_BEFORE (0 << 29)
185#define FIMC_REG_CIIMGEFF_IE_SC_AFTER (1 << 29)
186#define FIMC_REG_CIIMGEFF_FIN_BYPASS (0 << 26)
187#define FIMC_REG_CIIMGEFF_FIN_ARBITRARY (1 << 26)
188#define FIMC_REG_CIIMGEFF_FIN_NEGATIVE (2 << 26)
189#define FIMC_REG_CIIMGEFF_FIN_ARTFREEZE (3 << 26)
190#define FIMC_REG_CIIMGEFF_FIN_EMBOSSING (4 << 26)
191#define FIMC_REG_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
192#define FIMC_REG_CIIMGEFF_FIN_MASK (7 << 26)
193#define FIMC_REG_CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | 0xff)
194
195/* Input DMA Y/Cb/Cr plane start address 0/1 */
196#define FIMC_REG_CIIYSA(n) (0xd4 + (n) * 0x70)
197#define FIMC_REG_CIICBSA(n) (0xd8 + (n) * 0x70)
198#define FIMC_REG_CIICRSA(n) (0xdc + (n) * 0x70)
199
200/* Real input DMA image size */
201#define FIMC_REG_CIREAL_ISIZE 0xf8
202#define FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN (1 << 31)
203#define FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS (1 << 30)
204
205/* Input DMA control */
206#define FIMC_REG_MSCTRL 0xfc
207#define FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK (0xf << 24)
208#define FIMC_REG_MSCTRL_2P_IN_ORDER_MASK (3 << 16)
209#define FIMC_REG_MSCTRL_2P_IN_ORDER_SHIFT 16
210#define FIMC_REG_MSCTRL_C_INT_IN_3PLANE (0 << 15)
211#define FIMC_REG_MSCTRL_C_INT_IN_2PLANE (1 << 15)
212#define FIMC_REG_MSCTRL_C_INT_IN_MASK (1 << 15)
213#define FIMC_REG_MSCTRL_FLIP_SHIFT 13
214#define FIMC_REG_MSCTRL_FLIP_MASK (3 << 13)
215#define FIMC_REG_MSCTRL_FLIP_NORMAL (0 << 13)
216#define FIMC_REG_MSCTRL_FLIP_X_MIRROR (1 << 13)
217#define FIMC_REG_MSCTRL_FLIP_Y_MIRROR (2 << 13)
218#define FIMC_REG_MSCTRL_FLIP_180 (3 << 13)
219#define FIMC_REG_MSCTRL_FIFO_CTRL_FULL (1 << 12)
220#define FIMC_REG_MSCTRL_ORDER422_SHIFT 4
221#define FIMC_REG_MSCTRL_ORDER422_YCBYCR (0 << 4)
222#define FIMC_REG_MSCTRL_ORDER422_CBYCRY (1 << 4)
223#define FIMC_REG_MSCTRL_ORDER422_YCRYCB (2 << 4)
224#define FIMC_REG_MSCTRL_ORDER422_CRYCBY (3 << 4)
225#define FIMC_REG_MSCTRL_ORDER422_MASK (3 << 4)
226#define FIMC_REG_MSCTRL_INPUT_EXTCAM (0 << 3)
227#define FIMC_REG_MSCTRL_INPUT_MEMORY (1 << 3)
228#define FIMC_REG_MSCTRL_INPUT_MASK (1 << 3)
229#define FIMC_REG_MSCTRL_INFORMAT_YCBCR420 (0 << 1)
230#define FIMC_REG_MSCTRL_INFORMAT_YCBCR422 (1 << 1)
231#define FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P (2 << 1)
232#define FIMC_REG_MSCTRL_INFORMAT_RGB (3 << 1)
233#define FIMC_REG_MSCTRL_INFORMAT_MASK (3 << 1)
234#define FIMC_REG_MSCTRL_ENVID (1 << 0)
235#define FIMC_REG_MSCTRL_IN_BURST_COUNT(x) ((x) << 24)
236
237/* Output DMA Y/Cb/Cr offset */
238#define FIMC_REG_CIOYOFF 0x168
239#define FIMC_REG_CIOCBOFF 0x16c
240#define FIMC_REG_CIOCROFF 0x170
241
242/* Input DMA Y/Cb/Cr offset */
243#define FIMC_REG_CIIYOFF 0x174
244#define FIMC_REG_CIICBOFF 0x178
245#define FIMC_REG_CIICROFF 0x17c
246
247/* Input DMA original image size */
248#define FIMC_REG_ORGISIZE 0x180
249
250/* Output DMA original image size */
251#define FIMC_REG_ORGOSIZE 0x184
252
253/* Real output DMA image size (extension register) */
254#define FIMC_REG_CIEXTEN 0x188
255#define FIMC_REG_CIEXTEN_MHRATIO_EXT(x) (((x) & 0x3f) << 10)
256#define FIMC_REG_CIEXTEN_MVRATIO_EXT(x) ((x) & 0x3f)
257#define FIMC_REG_CIEXTEN_MHRATIO_EXT_MASK (0x3f << 10)
258#define FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK 0x3f
259
260#define FIMC_REG_CIDMAPARAM 0x18c
261#define FIMC_REG_CIDMAPARAM_R_LINEAR (0 << 29)
262#define FIMC_REG_CIDMAPARAM_R_64X32 (3 << 29)
263#define FIMC_REG_CIDMAPARAM_W_LINEAR (0 << 13)
264#define FIMC_REG_CIDMAPARAM_W_64X32 (3 << 13)
265#define FIMC_REG_CIDMAPARAM_TILE_MASK ((3 << 29) | (3 << 13))
266
267/* MIPI CSI image format */
268#define FIMC_REG_CSIIMGFMT 0x194
269#define FIMC_REG_CSIIMGFMT_YCBCR422_8BIT 0x1e
270#define FIMC_REG_CSIIMGFMT_RAW8 0x2a
271#define FIMC_REG_CSIIMGFMT_RAW10 0x2b
272#define FIMC_REG_CSIIMGFMT_RAW12 0x2c
273/* User defined formats. x = 0...16. */
274#define FIMC_REG_CSIIMGFMT_USER(x) (0x30 + x - 1)
275
276/* Output frame buffer sequence mask */
277#define FIMC_REG_CIFCNTSEQ 0x1fc
278
279/*
280 * Function declarations
281 */
282void fimc_hw_reset(struct fimc_dev *fimc);
283void fimc_hw_set_rotation(struct fimc_ctx *ctx);
284void fimc_hw_set_target_format(struct fimc_ctx *ctx);
285void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
286void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
287void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
288void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
289void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
290void fimc_hw_en_capture(struct fimc_ctx *ctx);
291void fimc_hw_set_effect(struct fimc_ctx *ctx);
292void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx);
293void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
294void fimc_hw_set_input_path(struct fimc_ctx *ctx);
295void fimc_hw_set_output_path(struct fimc_ctx *ctx);
296void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
297void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
298 int index);
299int fimc_hw_set_camera_source(struct fimc_dev *fimc,
300 struct s5p_fimc_isp_info *cam);
301void fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
302int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
303 struct s5p_fimc_isp_info *cam);
304int fimc_hw_set_camera_type(struct fimc_dev *fimc,
305 struct s5p_fimc_isp_info *cam);
306void fimc_hw_clear_irq(struct fimc_dev *dev);
307void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on);
308void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on);
309void fimc_hw_dis_capture(struct fimc_dev *dev);
310u32 fimc_hw_get_frame_index(struct fimc_dev *dev);
311void fimc_activate_capture(struct fimc_ctx *ctx);
312void fimc_deactivate_capture(struct fimc_dev *fimc);
313
314/**
315 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
316 * @mask: bitmask for the DMA output buffer registers, set to 0 to skip buffer
317 * This function masks output DMA ring buffers, it allows to select which of
318 * the 32 available output buffer address registers will be used by the DMA
319 * engine.
320 */
321static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
322{
323 writel(mask, dev->regs + FIMC_REG_CIFCNTSEQ);
324}
325
326#endif /* FIMC_REG_H_ */
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