diff options
Diffstat (limited to 'drivers/media/video/pxa_camera.c')
-rw-r--r-- | drivers/media/video/pxa_camera.c | 1852 |
1 files changed, 0 insertions, 1852 deletions
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c deleted file mode 100644 index 9c21e01f2c24..000000000000 --- a/drivers/media/video/pxa_camera.c +++ /dev/null | |||
@@ -1,1852 +0,0 @@ | |||
1 | /* | ||
2 | * V4L2 Driver for PXA camera host | ||
3 | * | ||
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | ||
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #include <linux/init.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/delay.h> | ||
17 | #include <linux/dma-mapping.h> | ||
18 | #include <linux/errno.h> | ||
19 | #include <linux/fs.h> | ||
20 | #include <linux/interrupt.h> | ||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/mm.h> | ||
23 | #include <linux/moduleparam.h> | ||
24 | #include <linux/time.h> | ||
25 | #include <linux/device.h> | ||
26 | #include <linux/platform_device.h> | ||
27 | #include <linux/clk.h> | ||
28 | #include <linux/sched.h> | ||
29 | #include <linux/slab.h> | ||
30 | |||
31 | #include <media/v4l2-common.h> | ||
32 | #include <media/v4l2-dev.h> | ||
33 | #include <media/videobuf-dma-sg.h> | ||
34 | #include <media/soc_camera.h> | ||
35 | #include <media/soc_mediabus.h> | ||
36 | |||
37 | #include <linux/videodev2.h> | ||
38 | |||
39 | #include <mach/dma.h> | ||
40 | #include <mach/camera.h> | ||
41 | |||
42 | #define PXA_CAM_VERSION "0.0.6" | ||
43 | #define PXA_CAM_DRV_NAME "pxa27x-camera" | ||
44 | |||
45 | /* Camera Interface */ | ||
46 | #define CICR0 0x0000 | ||
47 | #define CICR1 0x0004 | ||
48 | #define CICR2 0x0008 | ||
49 | #define CICR3 0x000C | ||
50 | #define CICR4 0x0010 | ||
51 | #define CISR 0x0014 | ||
52 | #define CIFR 0x0018 | ||
53 | #define CITOR 0x001C | ||
54 | #define CIBR0 0x0028 | ||
55 | #define CIBR1 0x0030 | ||
56 | #define CIBR2 0x0038 | ||
57 | |||
58 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | ||
59 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | ||
60 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | ||
61 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | ||
62 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | ||
63 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | ||
64 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | ||
65 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | ||
66 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | ||
67 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | ||
68 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | ||
69 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | ||
70 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | ||
71 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | ||
72 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | ||
73 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | ||
74 | |||
75 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | ||
76 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | ||
77 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | ||
78 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | ||
79 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | ||
80 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | ||
81 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | ||
82 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | ||
83 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | ||
84 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | ||
85 | |||
86 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | ||
87 | wait count mask */ | ||
88 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | ||
89 | wait count mask */ | ||
90 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | ||
91 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | ||
92 | wait count mask */ | ||
93 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | ||
94 | wait count mask */ | ||
95 | |||
96 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | ||
97 | wait count mask */ | ||
98 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | ||
99 | wait count mask */ | ||
100 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | ||
101 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | ||
102 | wait count mask */ | ||
103 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | ||
104 | |||
105 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | ||
106 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | ||
107 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | ||
108 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | ||
109 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | ||
110 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | ||
111 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | ||
112 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | ||
113 | |||
114 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | ||
115 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | ||
116 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | ||
117 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | ||
118 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | ||
119 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | ||
120 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | ||
121 | #define CISR_EOL (1 << 8) /* End of line */ | ||
122 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | ||
123 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | ||
124 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | ||
125 | #define CISR_SOF (1 << 4) /* Start of frame */ | ||
126 | #define CISR_EOF (1 << 3) /* End of frame */ | ||
127 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | ||
128 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | ||
129 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | ||
130 | |||
131 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | ||
132 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | ||
133 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | ||
134 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | ||
135 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | ||
136 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | ||
137 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | ||
138 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | ||
139 | |||
140 | #define CICR0_SIM_MP (0 << 24) | ||
141 | #define CICR0_SIM_SP (1 << 24) | ||
142 | #define CICR0_SIM_MS (2 << 24) | ||
143 | #define CICR0_SIM_EP (3 << 24) | ||
144 | #define CICR0_SIM_ES (4 << 24) | ||
145 | |||
146 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | ||
147 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | ||
148 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ | ||
149 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | ||
150 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | ||
151 | |||
152 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | ||
153 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | ||
154 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | ||
155 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | ||
156 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | ||
157 | |||
158 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | ||
159 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | ||
160 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | ||
161 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | ||
162 | |||
163 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ | ||
164 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | ||
165 | CICR0_EOFM | CICR0_FOM) | ||
166 | |||
167 | /* | ||
168 | * Structures | ||
169 | */ | ||
170 | enum pxa_camera_active_dma { | ||
171 | DMA_Y = 0x1, | ||
172 | DMA_U = 0x2, | ||
173 | DMA_V = 0x4, | ||
174 | }; | ||
175 | |||
176 | /* descriptor needed for the PXA DMA engine */ | ||
177 | struct pxa_cam_dma { | ||
178 | dma_addr_t sg_dma; | ||
179 | struct pxa_dma_desc *sg_cpu; | ||
180 | size_t sg_size; | ||
181 | int sglen; | ||
182 | }; | ||
183 | |||
184 | /* buffer for one video frame */ | ||
185 | struct pxa_buffer { | ||
186 | /* common v4l buffer stuff -- must be first */ | ||
187 | struct videobuf_buffer vb; | ||
188 | enum v4l2_mbus_pixelcode code; | ||
189 | /* our descriptor lists for Y, U and V channels */ | ||
190 | struct pxa_cam_dma dmas[3]; | ||
191 | int inwork; | ||
192 | enum pxa_camera_active_dma active_dma; | ||
193 | }; | ||
194 | |||
195 | struct pxa_camera_dev { | ||
196 | struct soc_camera_host soc_host; | ||
197 | /* | ||
198 | * PXA27x is only supposed to handle one camera on its Quick Capture | ||
199 | * interface. If anyone ever builds hardware to enable more than | ||
200 | * one camera, they will have to modify this driver too | ||
201 | */ | ||
202 | struct soc_camera_device *icd; | ||
203 | struct clk *clk; | ||
204 | |||
205 | unsigned int irq; | ||
206 | void __iomem *base; | ||
207 | |||
208 | int channels; | ||
209 | unsigned int dma_chans[3]; | ||
210 | |||
211 | struct pxacamera_platform_data *pdata; | ||
212 | struct resource *res; | ||
213 | unsigned long platform_flags; | ||
214 | unsigned long ciclk; | ||
215 | unsigned long mclk; | ||
216 | u32 mclk_divisor; | ||
217 | u16 width_flags; /* max 10 bits */ | ||
218 | |||
219 | struct list_head capture; | ||
220 | |||
221 | spinlock_t lock; | ||
222 | |||
223 | struct pxa_buffer *active; | ||
224 | struct pxa_dma_desc *sg_tail[3]; | ||
225 | |||
226 | u32 save_cicr[5]; | ||
227 | }; | ||
228 | |||
229 | struct pxa_cam { | ||
230 | unsigned long flags; | ||
231 | }; | ||
232 | |||
233 | static const char *pxa_cam_driver_description = "PXA_Camera"; | ||
234 | |||
235 | static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ | ||
236 | |||
237 | /* | ||
238 | * Videobuf operations | ||
239 | */ | ||
240 | static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, | ||
241 | unsigned int *size) | ||
242 | { | ||
243 | struct soc_camera_device *icd = vq->priv_data; | ||
244 | |||
245 | dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size); | ||
246 | |||
247 | *size = icd->sizeimage; | ||
248 | |||
249 | if (0 == *count) | ||
250 | *count = 32; | ||
251 | if (*size * *count > vid_limit * 1024 * 1024) | ||
252 | *count = (vid_limit * 1024 * 1024) / *size; | ||
253 | |||
254 | return 0; | ||
255 | } | ||
256 | |||
257 | static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) | ||
258 | { | ||
259 | struct soc_camera_device *icd = vq->priv_data; | ||
260 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | ||
261 | struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); | ||
262 | int i; | ||
263 | |||
264 | BUG_ON(in_interrupt()); | ||
265 | |||
266 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, | ||
267 | &buf->vb, buf->vb.baddr, buf->vb.bsize); | ||
268 | |||
269 | /* | ||
270 | * This waits until this buffer is out of danger, i.e., until it is no | ||
271 | * longer in STATE_QUEUED or STATE_ACTIVE | ||
272 | */ | ||
273 | videobuf_waiton(vq, &buf->vb, 0, 0); | ||
274 | videobuf_dma_unmap(vq->dev, dma); | ||
275 | videobuf_dma_free(dma); | ||
276 | |||
277 | for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) { | ||
278 | if (buf->dmas[i].sg_cpu) | ||
279 | dma_free_coherent(ici->v4l2_dev.dev, | ||
280 | buf->dmas[i].sg_size, | ||
281 | buf->dmas[i].sg_cpu, | ||
282 | buf->dmas[i].sg_dma); | ||
283 | buf->dmas[i].sg_cpu = NULL; | ||
284 | } | ||
285 | |||
286 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | ||
287 | } | ||
288 | |||
289 | static int calculate_dma_sglen(struct scatterlist *sglist, int sglen, | ||
290 | int sg_first_ofs, int size) | ||
291 | { | ||
292 | int i, offset, dma_len, xfer_len; | ||
293 | struct scatterlist *sg; | ||
294 | |||
295 | offset = sg_first_ofs; | ||
296 | for_each_sg(sglist, sg, sglen, i) { | ||
297 | dma_len = sg_dma_len(sg); | ||
298 | |||
299 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | ||
300 | xfer_len = roundup(min(dma_len - offset, size), 8); | ||
301 | |||
302 | size = max(0, size - xfer_len); | ||
303 | offset = 0; | ||
304 | if (size == 0) | ||
305 | break; | ||
306 | } | ||
307 | |||
308 | BUG_ON(size != 0); | ||
309 | return i + 1; | ||
310 | } | ||
311 | |||
312 | /** | ||
313 | * pxa_init_dma_channel - init dma descriptors | ||
314 | * @pcdev: pxa camera device | ||
315 | * @buf: pxa buffer to find pxa dma channel | ||
316 | * @dma: dma video buffer | ||
317 | * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') | ||
318 | * @cibr: camera Receive Buffer Register | ||
319 | * @size: bytes to transfer | ||
320 | * @sg_first: first element of sg_list | ||
321 | * @sg_first_ofs: offset in first element of sg_list | ||
322 | * | ||
323 | * Prepares the pxa dma descriptors to transfer one camera channel. | ||
324 | * Beware sg_first and sg_first_ofs are both input and output parameters. | ||
325 | * | ||
326 | * Returns 0 or -ENOMEM if no coherent memory is available | ||
327 | */ | ||
328 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, | ||
329 | struct pxa_buffer *buf, | ||
330 | struct videobuf_dmabuf *dma, int channel, | ||
331 | int cibr, int size, | ||
332 | struct scatterlist **sg_first, int *sg_first_ofs) | ||
333 | { | ||
334 | struct pxa_cam_dma *pxa_dma = &buf->dmas[channel]; | ||
335 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; | ||
336 | struct scatterlist *sg; | ||
337 | int i, offset, sglen; | ||
338 | int dma_len = 0, xfer_len = 0; | ||
339 | |||
340 | if (pxa_dma->sg_cpu) | ||
341 | dma_free_coherent(dev, pxa_dma->sg_size, | ||
342 | pxa_dma->sg_cpu, pxa_dma->sg_dma); | ||
343 | |||
344 | sglen = calculate_dma_sglen(*sg_first, dma->sglen, | ||
345 | *sg_first_ofs, size); | ||
346 | |||
347 | pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc); | ||
348 | pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size, | ||
349 | &pxa_dma->sg_dma, GFP_KERNEL); | ||
350 | if (!pxa_dma->sg_cpu) | ||
351 | return -ENOMEM; | ||
352 | |||
353 | pxa_dma->sglen = sglen; | ||
354 | offset = *sg_first_ofs; | ||
355 | |||
356 | dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n", | ||
357 | *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma); | ||
358 | |||
359 | |||
360 | for_each_sg(*sg_first, sg, sglen, i) { | ||
361 | dma_len = sg_dma_len(sg); | ||
362 | |||
363 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | ||
364 | xfer_len = roundup(min(dma_len - offset, size), 8); | ||
365 | |||
366 | size = max(0, size - xfer_len); | ||
367 | |||
368 | pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr; | ||
369 | pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset; | ||
370 | pxa_dma->sg_cpu[i].dcmd = | ||
371 | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len; | ||
372 | #ifdef DEBUG | ||
373 | if (!i) | ||
374 | pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN; | ||
375 | #endif | ||
376 | pxa_dma->sg_cpu[i].ddadr = | ||
377 | pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc); | ||
378 | |||
379 | dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n", | ||
380 | pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc), | ||
381 | sg_dma_address(sg) + offset, xfer_len); | ||
382 | offset = 0; | ||
383 | |||
384 | if (size == 0) | ||
385 | break; | ||
386 | } | ||
387 | |||
388 | pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP; | ||
389 | pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN; | ||
390 | |||
391 | /* | ||
392 | * Handle 1 special case : | ||
393 | * - in 3 planes (YUV422P format), we might finish with xfer_len equal | ||
394 | * to dma_len (end on PAGE boundary). In this case, the sg element | ||
395 | * for next plane should be the next after the last used to store the | ||
396 | * last scatter gather RAM page | ||
397 | */ | ||
398 | if (xfer_len >= dma_len) { | ||
399 | *sg_first_ofs = xfer_len - dma_len; | ||
400 | *sg_first = sg_next(sg); | ||
401 | } else { | ||
402 | *sg_first_ofs = xfer_len; | ||
403 | *sg_first = sg; | ||
404 | } | ||
405 | |||
406 | return 0; | ||
407 | } | ||
408 | |||
409 | static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev, | ||
410 | struct pxa_buffer *buf) | ||
411 | { | ||
412 | buf->active_dma = DMA_Y; | ||
413 | if (pcdev->channels == 3) | ||
414 | buf->active_dma |= DMA_U | DMA_V; | ||
415 | } | ||
416 | |||
417 | /* | ||
418 | * Please check the DMA prepared buffer structure in : | ||
419 | * Documentation/video4linux/pxa_camera.txt | ||
420 | * Please check also in pxa_camera_check_link_miss() to understand why DMA chain | ||
421 | * modification while DMA chain is running will work anyway. | ||
422 | */ | ||
423 | static int pxa_videobuf_prepare(struct videobuf_queue *vq, | ||
424 | struct videobuf_buffer *vb, enum v4l2_field field) | ||
425 | { | ||
426 | struct soc_camera_device *icd = vq->priv_data; | ||
427 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | ||
428 | struct pxa_camera_dev *pcdev = ici->priv; | ||
429 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; | ||
430 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | ||
431 | int ret; | ||
432 | int size_y, size_u = 0, size_v = 0; | ||
433 | |||
434 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, | ||
435 | vb, vb->baddr, vb->bsize); | ||
436 | |||
437 | /* Added list head initialization on alloc */ | ||
438 | WARN_ON(!list_empty(&vb->queue)); | ||
439 | |||
440 | #ifdef DEBUG | ||
441 | /* | ||
442 | * This can be useful if you want to see if we actually fill | ||
443 | * the buffer with something | ||
444 | */ | ||
445 | memset((void *)vb->baddr, 0xaa, vb->bsize); | ||
446 | #endif | ||
447 | |||
448 | BUG_ON(NULL == icd->current_fmt); | ||
449 | |||
450 | /* | ||
451 | * I think, in buf_prepare you only have to protect global data, | ||
452 | * the actual buffer is yours | ||
453 | */ | ||
454 | buf->inwork = 1; | ||
455 | |||
456 | if (buf->code != icd->current_fmt->code || | ||
457 | vb->width != icd->user_width || | ||
458 | vb->height != icd->user_height || | ||
459 | vb->field != field) { | ||
460 | buf->code = icd->current_fmt->code; | ||
461 | vb->width = icd->user_width; | ||
462 | vb->height = icd->user_height; | ||
463 | vb->field = field; | ||
464 | vb->state = VIDEOBUF_NEEDS_INIT; | ||
465 | } | ||
466 | |||
467 | vb->size = icd->sizeimage; | ||
468 | if (0 != vb->baddr && vb->bsize < vb->size) { | ||
469 | ret = -EINVAL; | ||
470 | goto out; | ||
471 | } | ||
472 | |||
473 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | ||
474 | int size = vb->size; | ||
475 | int next_ofs = 0; | ||
476 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); | ||
477 | struct scatterlist *sg; | ||
478 | |||
479 | ret = videobuf_iolock(vq, vb, NULL); | ||
480 | if (ret) | ||
481 | goto fail; | ||
482 | |||
483 | if (pcdev->channels == 3) { | ||
484 | size_y = size / 2; | ||
485 | size_u = size_v = size / 4; | ||
486 | } else { | ||
487 | size_y = size; | ||
488 | } | ||
489 | |||
490 | sg = dma->sglist; | ||
491 | |||
492 | /* init DMA for Y channel */ | ||
493 | ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y, | ||
494 | &sg, &next_ofs); | ||
495 | if (ret) { | ||
496 | dev_err(dev, "DMA initialization for Y/RGB failed\n"); | ||
497 | goto fail; | ||
498 | } | ||
499 | |||
500 | /* init DMA for U channel */ | ||
501 | if (size_u) | ||
502 | ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1, | ||
503 | size_u, &sg, &next_ofs); | ||
504 | if (ret) { | ||
505 | dev_err(dev, "DMA initialization for U failed\n"); | ||
506 | goto fail_u; | ||
507 | } | ||
508 | |||
509 | /* init DMA for V channel */ | ||
510 | if (size_v) | ||
511 | ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2, | ||
512 | size_v, &sg, &next_ofs); | ||
513 | if (ret) { | ||
514 | dev_err(dev, "DMA initialization for V failed\n"); | ||
515 | goto fail_v; | ||
516 | } | ||
517 | |||
518 | vb->state = VIDEOBUF_PREPARED; | ||
519 | } | ||
520 | |||
521 | buf->inwork = 0; | ||
522 | pxa_videobuf_set_actdma(pcdev, buf); | ||
523 | |||
524 | return 0; | ||
525 | |||
526 | fail_v: | ||
527 | dma_free_coherent(dev, buf->dmas[1].sg_size, | ||
528 | buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma); | ||
529 | fail_u: | ||
530 | dma_free_coherent(dev, buf->dmas[0].sg_size, | ||
531 | buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma); | ||
532 | fail: | ||
533 | free_buffer(vq, buf); | ||
534 | out: | ||
535 | buf->inwork = 0; | ||
536 | return ret; | ||
537 | } | ||
538 | |||
539 | /** | ||
540 | * pxa_dma_start_channels - start DMA channel for active buffer | ||
541 | * @pcdev: pxa camera device | ||
542 | * | ||
543 | * Initialize DMA channels to the beginning of the active video buffer, and | ||
544 | * start these channels. | ||
545 | */ | ||
546 | static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) | ||
547 | { | ||
548 | int i; | ||
549 | struct pxa_buffer *active; | ||
550 | |||
551 | active = pcdev->active; | ||
552 | |||
553 | for (i = 0; i < pcdev->channels; i++) { | ||
554 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, | ||
555 | "%s (channel=%d) ddadr=%08x\n", __func__, | ||
556 | i, active->dmas[i].sg_dma); | ||
557 | DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma; | ||
558 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | ||
559 | } | ||
560 | } | ||
561 | |||
562 | static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) | ||
563 | { | ||
564 | int i; | ||
565 | |||
566 | for (i = 0; i < pcdev->channels; i++) { | ||
567 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, | ||
568 | "%s (channel=%d)\n", __func__, i); | ||
569 | DCSR(pcdev->dma_chans[i]) = 0; | ||
570 | } | ||
571 | } | ||
572 | |||
573 | static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, | ||
574 | struct pxa_buffer *buf) | ||
575 | { | ||
576 | int i; | ||
577 | struct pxa_dma_desc *buf_last_desc; | ||
578 | |||
579 | for (i = 0; i < pcdev->channels; i++) { | ||
580 | buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen; | ||
581 | buf_last_desc->ddadr = DDADR_STOP; | ||
582 | |||
583 | if (pcdev->sg_tail[i]) | ||
584 | /* Link the new buffer to the old tail */ | ||
585 | pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma; | ||
586 | |||
587 | /* Update the channel tail */ | ||
588 | pcdev->sg_tail[i] = buf_last_desc; | ||
589 | } | ||
590 | } | ||
591 | |||
592 | /** | ||
593 | * pxa_camera_start_capture - start video capturing | ||
594 | * @pcdev: camera device | ||
595 | * | ||
596 | * Launch capturing. DMA channels should not be active yet. They should get | ||
597 | * activated at the end of frame interrupt, to capture only whole frames, and | ||
598 | * never begin the capture of a partial frame. | ||
599 | */ | ||
600 | static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) | ||
601 | { | ||
602 | unsigned long cicr0; | ||
603 | |||
604 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); | ||
605 | /* Enable End-Of-Frame Interrupt */ | ||
606 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | ||
607 | cicr0 &= ~CICR0_EOFM; | ||
608 | __raw_writel(cicr0, pcdev->base + CICR0); | ||
609 | } | ||
610 | |||
611 | static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) | ||
612 | { | ||
613 | unsigned long cicr0; | ||
614 | |||
615 | pxa_dma_stop_channels(pcdev); | ||
616 | |||
617 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | ||
618 | __raw_writel(cicr0, pcdev->base + CICR0); | ||
619 | |||
620 | pcdev->active = NULL; | ||
621 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); | ||
622 | } | ||
623 | |||
624 | /* Called under spinlock_irqsave(&pcdev->lock, ...) */ | ||
625 | static void pxa_videobuf_queue(struct videobuf_queue *vq, | ||
626 | struct videobuf_buffer *vb) | ||
627 | { | ||
628 | struct soc_camera_device *icd = vq->priv_data; | ||
629 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | ||
630 | struct pxa_camera_dev *pcdev = ici->priv; | ||
631 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | ||
632 | |||
633 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n", | ||
634 | __func__, vb, vb->baddr, vb->bsize, pcdev->active); | ||
635 | |||
636 | list_add_tail(&vb->queue, &pcdev->capture); | ||
637 | |||
638 | vb->state = VIDEOBUF_ACTIVE; | ||
639 | pxa_dma_add_tail_buf(pcdev, buf); | ||
640 | |||
641 | if (!pcdev->active) | ||
642 | pxa_camera_start_capture(pcdev); | ||
643 | } | ||
644 | |||
645 | static void pxa_videobuf_release(struct videobuf_queue *vq, | ||
646 | struct videobuf_buffer *vb) | ||
647 | { | ||
648 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | ||
649 | #ifdef DEBUG | ||
650 | struct soc_camera_device *icd = vq->priv_data; | ||
651 | struct device *dev = icd->parent; | ||
652 | |||
653 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, | ||
654 | vb, vb->baddr, vb->bsize); | ||
655 | |||
656 | switch (vb->state) { | ||
657 | case VIDEOBUF_ACTIVE: | ||
658 | dev_dbg(dev, "%s (active)\n", __func__); | ||
659 | break; | ||
660 | case VIDEOBUF_QUEUED: | ||
661 | dev_dbg(dev, "%s (queued)\n", __func__); | ||
662 | break; | ||
663 | case VIDEOBUF_PREPARED: | ||
664 | dev_dbg(dev, "%s (prepared)\n", __func__); | ||
665 | break; | ||
666 | default: | ||
667 | dev_dbg(dev, "%s (unknown)\n", __func__); | ||
668 | break; | ||
669 | } | ||
670 | #endif | ||
671 | |||
672 | free_buffer(vq, buf); | ||
673 | } | ||
674 | |||
675 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, | ||
676 | struct videobuf_buffer *vb, | ||
677 | struct pxa_buffer *buf) | ||
678 | { | ||
679 | int i; | ||
680 | |||
681 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ | ||
682 | list_del_init(&vb->queue); | ||
683 | vb->state = VIDEOBUF_DONE; | ||
684 | do_gettimeofday(&vb->ts); | ||
685 | vb->field_count++; | ||
686 | wake_up(&vb->done); | ||
687 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n", | ||
688 | __func__, vb); | ||
689 | |||
690 | if (list_empty(&pcdev->capture)) { | ||
691 | pxa_camera_stop_capture(pcdev); | ||
692 | for (i = 0; i < pcdev->channels; i++) | ||
693 | pcdev->sg_tail[i] = NULL; | ||
694 | return; | ||
695 | } | ||
696 | |||
697 | pcdev->active = list_entry(pcdev->capture.next, | ||
698 | struct pxa_buffer, vb.queue); | ||
699 | } | ||
700 | |||
701 | /** | ||
702 | * pxa_camera_check_link_miss - check missed DMA linking | ||
703 | * @pcdev: camera device | ||
704 | * | ||
705 | * The DMA chaining is done with DMA running. This means a tiny temporal window | ||
706 | * remains, where a buffer is queued on the chain, while the chain is already | ||
707 | * stopped. This means the tailed buffer would never be transferred by DMA. | ||
708 | * This function restarts the capture for this corner case, where : | ||
709 | * - DADR() == DADDR_STOP | ||
710 | * - a videobuffer is queued on the pcdev->capture list | ||
711 | * | ||
712 | * Please check the "DMA hot chaining timeslice issue" in | ||
713 | * Documentation/video4linux/pxa_camera.txt | ||
714 | * | ||
715 | * Context: should only be called within the dma irq handler | ||
716 | */ | ||
717 | static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev) | ||
718 | { | ||
719 | int i, is_dma_stopped = 1; | ||
720 | |||
721 | for (i = 0; i < pcdev->channels; i++) | ||
722 | if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP) | ||
723 | is_dma_stopped = 0; | ||
724 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, | ||
725 | "%s : top queued buffer=%p, dma_stopped=%d\n", | ||
726 | __func__, pcdev->active, is_dma_stopped); | ||
727 | if (pcdev->active && is_dma_stopped) | ||
728 | pxa_camera_start_capture(pcdev); | ||
729 | } | ||
730 | |||
731 | static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, | ||
732 | enum pxa_camera_active_dma act_dma) | ||
733 | { | ||
734 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; | ||
735 | struct pxa_buffer *buf; | ||
736 | unsigned long flags; | ||
737 | u32 status, camera_status, overrun; | ||
738 | struct videobuf_buffer *vb; | ||
739 | |||
740 | spin_lock_irqsave(&pcdev->lock, flags); | ||
741 | |||
742 | status = DCSR(channel); | ||
743 | DCSR(channel) = status; | ||
744 | |||
745 | camera_status = __raw_readl(pcdev->base + CISR); | ||
746 | overrun = CISR_IFO_0; | ||
747 | if (pcdev->channels == 3) | ||
748 | overrun |= CISR_IFO_1 | CISR_IFO_2; | ||
749 | |||
750 | if (status & DCSR_BUSERR) { | ||
751 | dev_err(dev, "DMA Bus Error IRQ!\n"); | ||
752 | goto out; | ||
753 | } | ||
754 | |||
755 | if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) { | ||
756 | dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n", | ||
757 | status); | ||
758 | goto out; | ||
759 | } | ||
760 | |||
761 | /* | ||
762 | * pcdev->active should not be NULL in DMA irq handler. | ||
763 | * | ||
764 | * But there is one corner case : if capture was stopped due to an | ||
765 | * overrun of channel 1, and at that same channel 2 was completed. | ||
766 | * | ||
767 | * When handling the overrun in DMA irq for channel 1, we'll stop the | ||
768 | * capture and restart it (and thus set pcdev->active to NULL). But the | ||
769 | * DMA irq handler will already be pending for channel 2. So on entering | ||
770 | * the DMA irq handler for channel 2 there will be no active buffer, yet | ||
771 | * that is normal. | ||
772 | */ | ||
773 | if (!pcdev->active) | ||
774 | goto out; | ||
775 | |||
776 | vb = &pcdev->active->vb; | ||
777 | buf = container_of(vb, struct pxa_buffer, vb); | ||
778 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | ||
779 | |||
780 | dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n", | ||
781 | __func__, channel, status & DCSR_STARTINTR ? "SOF " : "", | ||
782 | status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel)); | ||
783 | |||
784 | if (status & DCSR_ENDINTR) { | ||
785 | /* | ||
786 | * It's normal if the last frame creates an overrun, as there | ||
787 | * are no more DMA descriptors to fetch from QCI fifos | ||
788 | */ | ||
789 | if (camera_status & overrun && | ||
790 | !list_is_last(pcdev->capture.next, &pcdev->capture)) { | ||
791 | dev_dbg(dev, "FIFO overrun! CISR: %x\n", | ||
792 | camera_status); | ||
793 | pxa_camera_stop_capture(pcdev); | ||
794 | pxa_camera_start_capture(pcdev); | ||
795 | goto out; | ||
796 | } | ||
797 | buf->active_dma &= ~act_dma; | ||
798 | if (!buf->active_dma) { | ||
799 | pxa_camera_wakeup(pcdev, vb, buf); | ||
800 | pxa_camera_check_link_miss(pcdev); | ||
801 | } | ||
802 | } | ||
803 | |||
804 | out: | ||
805 | spin_unlock_irqrestore(&pcdev->lock, flags); | ||
806 | } | ||
807 | |||
808 | static void pxa_camera_dma_irq_y(int channel, void *data) | ||
809 | { | ||
810 | struct pxa_camera_dev *pcdev = data; | ||
811 | pxa_camera_dma_irq(channel, pcdev, DMA_Y); | ||
812 | } | ||
813 | |||
814 | static void pxa_camera_dma_irq_u(int channel, void *data) | ||
815 | { | ||
816 | struct pxa_camera_dev *pcdev = data; | ||
817 | pxa_camera_dma_irq(channel, pcdev, DMA_U); | ||
818 | } | ||
819 | |||
820 | static void pxa_camera_dma_irq_v(int channel, void *data) | ||
821 | { | ||
822 | struct pxa_camera_dev *pcdev = data; | ||
823 | pxa_camera_dma_irq(channel, pcdev, DMA_V); | ||
824 | } | ||
825 | |||
826 | static struct videobuf_queue_ops pxa_videobuf_ops = { | ||
827 | .buf_setup = pxa_videobuf_setup, | ||
828 | .buf_prepare = pxa_videobuf_prepare, | ||
829 | .buf_queue = pxa_videobuf_queue, | ||
830 | .buf_release = pxa_videobuf_release, | ||
831 | }; | ||
832 | |||
833 | static void pxa_camera_init_videobuf(struct videobuf_queue *q, | ||
834 | struct soc_camera_device *icd) | ||
835 | { | ||
836 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | ||
837 | struct pxa_camera_dev *pcdev = ici->priv; | ||
838 | |||
839 | /* | ||
840 | * We must pass NULL as dev pointer, then all pci_* dma operations | ||
841 | * transform to normal dma_* ones. | ||
842 | */ | ||
843 | videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock, | ||
844 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, | ||
845 | sizeof(struct pxa_buffer), icd, &icd->video_lock); | ||
846 | } | ||
847 | |||
848 | static u32 mclk_get_divisor(struct platform_device *pdev, | ||
849 | struct pxa_camera_dev *pcdev) | ||
850 | { | ||
851 | unsigned long mclk = pcdev->mclk; | ||
852 | struct device *dev = &pdev->dev; | ||
853 | u32 div; | ||
854 | unsigned long lcdclk; | ||
855 | |||
856 | lcdclk = clk_get_rate(pcdev->clk); | ||
857 | pcdev->ciclk = lcdclk; | ||
858 | |||
859 | /* mclk <= ciclk / 4 (27.4.2) */ | ||
860 | if (mclk > lcdclk / 4) { | ||
861 | mclk = lcdclk / 4; | ||
862 | dev_warn(dev, "Limiting master clock to %lu\n", mclk); | ||
863 | } | ||
864 | |||
865 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | ||
866 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | ||
867 | |||
868 | /* If we're not supplying MCLK, leave it at 0 */ | ||
869 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | ||
870 | pcdev->mclk = lcdclk / (2 * (div + 1)); | ||
871 | |||
872 | dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n", | ||
873 | lcdclk, mclk, div); | ||
874 | |||
875 | return div; | ||
876 | } | ||
877 | |||
878 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, | ||
879 | unsigned long pclk) | ||
880 | { | ||
881 | /* We want a timeout > 1 pixel time, not ">=" */ | ||
882 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | ||
883 | |||
884 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | ||
885 | } | ||
886 | |||
887 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) | ||
888 | { | ||
889 | u32 cicr4 = 0; | ||
890 | |||
891 | /* disable all interrupts */ | ||
892 | __raw_writel(0x3ff, pcdev->base + CICR0); | ||
893 | |||
894 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | ||
895 | cicr4 |= CICR4_PCLK_EN; | ||
896 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | ||
897 | cicr4 |= CICR4_MCLK_EN; | ||
898 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | ||
899 | cicr4 |= CICR4_PCP; | ||
900 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | ||
901 | cicr4 |= CICR4_HSP; | ||
902 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | ||
903 | cicr4 |= CICR4_VSP; | ||
904 | |||
905 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); | ||
906 | |||
907 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | ||
908 | /* Initialise the timeout under the assumption pclk = mclk */ | ||
909 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | ||
910 | else | ||
911 | /* "Safe default" - 13MHz */ | ||
912 | recalculate_fifo_timeout(pcdev, 13000000); | ||
913 | |||
914 | clk_prepare_enable(pcdev->clk); | ||
915 | } | ||
916 | |||
917 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) | ||
918 | { | ||
919 | clk_disable_unprepare(pcdev->clk); | ||
920 | } | ||
921 | |||
922 | static irqreturn_t pxa_camera_irq(int irq, void *data) | ||
923 | { | ||
924 | struct pxa_camera_dev *pcdev = data; | ||
925 | unsigned long status, cifr, cicr0; | ||
926 | struct pxa_buffer *buf; | ||
927 | struct videobuf_buffer *vb; | ||
928 | |||
929 | status = __raw_readl(pcdev->base + CISR); | ||
930 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, | ||
931 | "Camera interrupt status 0x%lx\n", status); | ||
932 | |||
933 | if (!status) | ||
934 | return IRQ_NONE; | ||
935 | |||
936 | __raw_writel(status, pcdev->base + CISR); | ||
937 | |||
938 | if (status & CISR_EOF) { | ||
939 | /* Reset the FIFOs */ | ||
940 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | ||
941 | __raw_writel(cifr, pcdev->base + CIFR); | ||
942 | |||
943 | pcdev->active = list_first_entry(&pcdev->capture, | ||
944 | struct pxa_buffer, vb.queue); | ||
945 | vb = &pcdev->active->vb; | ||
946 | buf = container_of(vb, struct pxa_buffer, vb); | ||
947 | pxa_videobuf_set_actdma(pcdev, buf); | ||
948 | |||
949 | pxa_dma_start_channels(pcdev); | ||
950 | |||
951 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; | ||
952 | __raw_writel(cicr0, pcdev->base + CICR0); | ||
953 | } | ||
954 | |||
955 | return IRQ_HANDLED; | ||
956 | } | ||
957 | |||
958 | /* | ||
959 | * The following two functions absolutely depend on the fact, that | ||
960 | * there can be only one camera on PXA quick capture interface | ||
961 | * Called with .video_lock held | ||
962 | */ | ||
963 | static int pxa_camera_add_device(struct soc_camera_device *icd) | ||
964 | { | ||
965 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | ||
966 | struct pxa_camera_dev *pcdev = ici->priv; | ||
967 | |||
968 | if (pcdev->icd) | ||
969 | return -EBUSY; | ||
970 | |||
971 | pxa_camera_activate(pcdev); | ||
972 | |||
973 | pcdev->icd = icd; | ||
974 | |||
975 | dev_info(icd->parent, "PXA Camera driver attached to camera %d\n", | ||
976 | icd->devnum); | ||
977 | |||
978 | return 0; | ||
979 | } | ||
980 | |||
981 | /* Called with .video_lock held */ | ||
982 | static void pxa_camera_remove_device(struct soc_camera_device *icd) | ||
983 | { | ||
984 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | ||
985 | struct pxa_camera_dev *pcdev = ici->priv; | ||
986 | |||
987 | BUG_ON(icd != pcdev->icd); | ||
988 | |||
989 | dev_info(icd->parent, "PXA Camera driver detached from camera %d\n", | ||
990 | icd->devnum); | ||
991 | |||
992 | /* disable capture, disable interrupts */ | ||
993 | __raw_writel(0x3ff, pcdev->base + CICR0); | ||
994 | |||
995 | /* Stop DMA engine */ | ||
996 | DCSR(pcdev->dma_chans[0]) = 0; | ||
997 | DCSR(pcdev->dma_chans[1]) = 0; | ||
998 | DCSR(pcdev->dma_chans[2]) = 0; | ||
999 | |||
1000 | pxa_camera_deactivate(pcdev); | ||
1001 | |||
1002 | pcdev->icd = NULL; | ||
1003 | } | ||
1004 | |||
1005 | static int test_platform_param(struct pxa_camera_dev *pcdev, | ||
1006 | unsigned char buswidth, unsigned long *flags) | ||
1007 | { | ||
1008 | /* | ||
1009 | * Platform specified synchronization and pixel clock polarities are | ||
1010 | * only a recommendation and are only used during probing. The PXA270 | ||
1011 | * quick capture interface supports both. | ||
1012 | */ | ||
1013 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | ||
1014 | V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) | | ||
1015 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | | ||
1016 | V4L2_MBUS_HSYNC_ACTIVE_LOW | | ||
1017 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | ||
1018 | V4L2_MBUS_VSYNC_ACTIVE_LOW | | ||
1019 | V4L2_MBUS_DATA_ACTIVE_HIGH | | ||
1020 | V4L2_MBUS_PCLK_SAMPLE_RISING | | ||
1021 | V4L2_MBUS_PCLK_SAMPLE_FALLING; | ||
1022 | |||
1023 | /* If requested data width is supported by the platform, use it */ | ||
1024 | if ((1 << (buswidth - 1)) & pcdev->width_flags) | ||
1025 | return 0; | ||
1026 | |||
1027 | return -EINVAL; | ||
1028 | } | ||
1029 | |||
1030 | static void pxa_camera_setup_cicr(struct soc_camera_device *icd, | ||
1031 | unsigned long flags, __u32 pixfmt) | ||
1032 | { | ||
1033 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | ||
1034 | struct pxa_camera_dev *pcdev = ici->priv; | ||
1035 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); | ||
1036 | unsigned long dw, bpp; | ||
1037 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top; | ||
1038 | int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top); | ||
1039 | |||
1040 | if (ret < 0) | ||
1041 | y_skip_top = 0; | ||
1042 | |||
1043 | /* | ||
1044 | * Datawidth is now guaranteed to be equal to one of the three values. | ||
1045 | * We fix bit-per-pixel equal to data-width... | ||
1046 | */ | ||
1047 | switch (icd->current_fmt->host_fmt->bits_per_sample) { | ||
1048 | case 10: | ||
1049 | dw = 4; | ||
1050 | bpp = 0x40; | ||
1051 | break; | ||
1052 | case 9: | ||
1053 | dw = 3; | ||
1054 | bpp = 0x20; | ||
1055 | break; | ||
1056 | default: | ||
1057 | /* | ||
1058 | * Actually it can only be 8 now, | ||
1059 | * default is just to silence compiler warnings | ||
1060 | */ | ||
1061 | case 8: | ||
1062 | dw = 2; | ||
1063 | bpp = 0; | ||
1064 | } | ||
1065 | |||
1066 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | ||
1067 | cicr4 |= CICR4_PCLK_EN; | ||
1068 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | ||
1069 | cicr4 |= CICR4_MCLK_EN; | ||
1070 | if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) | ||
1071 | cicr4 |= CICR4_PCP; | ||
1072 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) | ||
1073 | cicr4 |= CICR4_HSP; | ||
1074 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) | ||
1075 | cicr4 |= CICR4_VSP; | ||
1076 | |||
1077 | cicr0 = __raw_readl(pcdev->base + CICR0); | ||
1078 | if (cicr0 & CICR0_ENB) | ||
1079 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); | ||
1080 | |||
1081 | cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw; | ||
1082 | |||
1083 | switch (pixfmt) { | ||
1084 | case V4L2_PIX_FMT_YUV422P: | ||
1085 | pcdev->channels = 3; | ||
1086 | cicr1 |= CICR1_YCBCR_F; | ||
1087 | /* | ||
1088 | * Normally, pxa bus wants as input UYVY format. We allow all | ||
1089 | * reorderings of the YUV422 format, as no processing is done, | ||
1090 | * and the YUV stream is just passed through without any | ||
1091 | * transformation. Note that UYVY is the only format that | ||
1092 | * should be used if pxa framebuffer Overlay2 is used. | ||
1093 | */ | ||
1094 | case V4L2_PIX_FMT_UYVY: | ||
1095 | case V4L2_PIX_FMT_VYUY: | ||
1096 | case V4L2_PIX_FMT_YUYV: | ||
1097 | case V4L2_PIX_FMT_YVYU: | ||
1098 | cicr1 |= CICR1_COLOR_SP_VAL(2); | ||
1099 | break; | ||
1100 | case V4L2_PIX_FMT_RGB555: | ||
1101 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | ||
1102 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | ||
1103 | break; | ||
1104 | case V4L2_PIX_FMT_RGB565: | ||
1105 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | ||
1106 | break; | ||
1107 | } | ||
1108 | |||
1109 | cicr2 = 0; | ||
1110 | cicr3 = CICR3_LPF_VAL(icd->user_height - 1) | | ||
1111 | CICR3_BFW_VAL(min((u32)255, y_skip_top)); | ||
1112 | cicr4 |= pcdev->mclk_divisor; | ||
1113 | |||
1114 | __raw_writel(cicr1, pcdev->base + CICR1); | ||
1115 | __raw_writel(cicr2, pcdev->base + CICR2); | ||
1116 | __raw_writel(cicr3, pcdev->base + CICR3); | ||
1117 | __raw_writel(cicr4, pcdev->base + CICR4); | ||
1118 | |||
1119 | /* CIF interrupts are not used, only DMA */ | ||
1120 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? | ||
1121 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | ||
1122 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | ||
1123 | __raw_writel(cicr0, pcdev->base + CICR0); | ||
1124 | } | ||
1125 | |||
1126 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd) | ||
1127 | { | ||
1128 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); | ||
1129 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | ||
1130 | struct pxa_camera_dev *pcdev = ici->priv; | ||
1131 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; | ||
1132 | u32 pixfmt = icd->current_fmt->host_fmt->fourcc; | ||
1133 | unsigned long bus_flags, common_flags; | ||
1134 | int ret; | ||
1135 | struct pxa_cam *cam = icd->host_priv; | ||
1136 | |||
1137 | ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample, | ||
1138 | &bus_flags); | ||
1139 | if (ret < 0) | ||
1140 | return ret; | ||
1141 | |||
1142 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); | ||
1143 | if (!ret) { | ||
1144 | common_flags = soc_mbus_config_compatible(&cfg, | ||
1145 | bus_flags); | ||
1146 | if (!common_flags) { | ||
1147 | dev_warn(icd->parent, | ||
1148 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | ||
1149 | cfg.flags, bus_flags); | ||
1150 | return -EINVAL; | ||
1151 | } | ||
1152 | } else if (ret != -ENOIOCTLCMD) { | ||
1153 | return ret; | ||
1154 | } else { | ||
1155 | common_flags = bus_flags; | ||
1156 | } | ||
1157 | |||
1158 | pcdev->channels = 1; | ||
1159 | |||
1160 | /* Make choises, based on platform preferences */ | ||
1161 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && | ||
1162 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | ||
1163 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | ||
1164 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; | ||
1165 | else | ||
1166 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; | ||
1167 | } | ||
1168 | |||
1169 | if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && | ||
1170 | (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { | ||
1171 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | ||
1172 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; | ||
1173 | else | ||
1174 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; | ||
1175 | } | ||
1176 | |||
1177 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && | ||
1178 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | ||
1179 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | ||
1180 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; | ||
1181 | else | ||
1182 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; | ||
1183 | } | ||
1184 | |||
1185 | cfg.flags = common_flags; | ||
1186 | ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); | ||
1187 | if (ret < 0 && ret != -ENOIOCTLCMD) { | ||
1188 | dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n", | ||
1189 | common_flags, ret); | ||
1190 | return ret; | ||
1191 | } | ||
1192 | |||
1193 | cam->flags = common_flags; | ||
1194 | |||
1195 | pxa_camera_setup_cicr(icd, common_flags, pixfmt); | ||
1196 | |||
1197 | return 0; | ||
1198 | } | ||
1199 | |||
1200 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, | ||
1201 | unsigned char buswidth) | ||
1202 | { | ||
1203 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); | ||
1204 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | ||
1205 | struct pxa_camera_dev *pcdev = ici->priv; | ||
1206 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; | ||
1207 | unsigned long bus_flags, common_flags; | ||
1208 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); | ||
1209 | |||
1210 | if (ret < 0) | ||
1211 | return ret; | ||
1212 | |||
1213 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); | ||
1214 | if (!ret) { | ||
1215 | common_flags = soc_mbus_config_compatible(&cfg, | ||
1216 | bus_flags); | ||
1217 | if (!common_flags) { | ||
1218 | dev_warn(icd->parent, | ||
1219 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | ||
1220 | cfg.flags, bus_flags); | ||
1221 | return -EINVAL; | ||
1222 | } | ||
1223 | } else if (ret == -ENOIOCTLCMD) { | ||
1224 | ret = 0; | ||
1225 | } | ||
1226 | |||
1227 | return ret; | ||
1228 | } | ||
1229 | |||
1230 | static const struct soc_mbus_pixelfmt pxa_camera_formats[] = { | ||
1231 | { | ||
1232 | .fourcc = V4L2_PIX_FMT_YUV422P, | ||
1233 | .name = "Planar YUV422 16 bit", | ||
1234 | .bits_per_sample = 8, | ||
1235 | .packing = SOC_MBUS_PACKING_2X8_PADHI, | ||
1236 | .order = SOC_MBUS_ORDER_LE, | ||
1237 | .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V, | ||
1238 | }, | ||
1239 | }; | ||
1240 | |||
1241 | /* This will be corrected as we get more formats */ | ||
1242 | static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | ||
1243 | { | ||
1244 | return fmt->packing == SOC_MBUS_PACKING_NONE || | ||
1245 | (fmt->bits_per_sample == 8 && | ||
1246 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | ||
1247 | (fmt->bits_per_sample > 8 && | ||
1248 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | ||
1249 | } | ||
1250 | |||
1251 | static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, | ||
1252 | struct soc_camera_format_xlate *xlate) | ||
1253 | { | ||
1254 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); | ||
1255 | struct device *dev = icd->parent; | ||
1256 | int formats = 0, ret; | ||
1257 | struct pxa_cam *cam; | ||
1258 | enum v4l2_mbus_pixelcode code; | ||
1259 | const struct soc_mbus_pixelfmt *fmt; | ||
1260 | |||
1261 | ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); | ||
1262 | if (ret < 0) | ||
1263 | /* No more formats */ | ||
1264 | return 0; | ||
1265 | |||
1266 | fmt = soc_mbus_get_fmtdesc(code); | ||
1267 | if (!fmt) { | ||
1268 | dev_err(dev, "Invalid format code #%u: %d\n", idx, code); | ||
1269 | return 0; | ||
1270 | } | ||
1271 | |||
1272 | /* This also checks support for the requested bits-per-sample */ | ||
1273 | ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample); | ||
1274 | if (ret < 0) | ||
1275 | return 0; | ||
1276 | |||
1277 | if (!icd->host_priv) { | ||
1278 | cam = kzalloc(sizeof(*cam), GFP_KERNEL); | ||
1279 | if (!cam) | ||
1280 | return -ENOMEM; | ||
1281 | |||
1282 | icd->host_priv = cam; | ||
1283 | } else { | ||
1284 | cam = icd->host_priv; | ||
1285 | } | ||
1286 | |||
1287 | switch (code) { | ||
1288 | case V4L2_MBUS_FMT_UYVY8_2X8: | ||
1289 | formats++; | ||
1290 | if (xlate) { | ||
1291 | xlate->host_fmt = &pxa_camera_formats[0]; | ||
1292 | xlate->code = code; | ||
1293 | xlate++; | ||
1294 | dev_dbg(dev, "Providing format %s using code %d\n", | ||
1295 | pxa_camera_formats[0].name, code); | ||
1296 | } | ||
1297 | case V4L2_MBUS_FMT_VYUY8_2X8: | ||
1298 | case V4L2_MBUS_FMT_YUYV8_2X8: | ||
1299 | case V4L2_MBUS_FMT_YVYU8_2X8: | ||
1300 | case V4L2_MBUS_FMT_RGB565_2X8_LE: | ||
1301 | case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE: | ||
1302 | if (xlate) | ||
1303 | dev_dbg(dev, "Providing format %s packed\n", | ||
1304 | fmt->name); | ||
1305 | break; | ||
1306 | default: | ||
1307 | if (!pxa_camera_packing_supported(fmt)) | ||
1308 | return 0; | ||
1309 | if (xlate) | ||
1310 | dev_dbg(dev, | ||
1311 | "Providing format %s in pass-through mode\n", | ||
1312 | fmt->name); | ||
1313 | } | ||
1314 | |||
1315 | /* Generic pass-through */ | ||
1316 | formats++; | ||
1317 | if (xlate) { | ||
1318 | xlate->host_fmt = fmt; | ||
1319 | xlate->code = code; | ||
1320 | xlate++; | ||
1321 | } | ||
1322 | |||
1323 | return formats; | ||
1324 | } | ||
1325 | |||
1326 | static void pxa_camera_put_formats(struct soc_camera_device *icd) | ||
1327 | { | ||
1328 | kfree(icd->host_priv); | ||
1329 | icd->host_priv = NULL; | ||
1330 | } | ||
1331 | |||
1332 | static int pxa_camera_check_frame(u32 width, u32 height) | ||
1333 | { | ||
1334 | /* limit to pxa hardware capabilities */ | ||
1335 | return height < 32 || height > 2048 || width < 48 || width > 2048 || | ||
1336 | (width & 0x01); | ||
1337 | } | ||
1338 | |||
1339 | static int pxa_camera_set_crop(struct soc_camera_device *icd, | ||
1340 | struct v4l2_crop *a) | ||
1341 | { | ||
1342 | struct v4l2_rect *rect = &a->c; | ||
1343 | struct device *dev = icd->parent; | ||
1344 | struct soc_camera_host *ici = to_soc_camera_host(dev); | ||
1345 | struct pxa_camera_dev *pcdev = ici->priv; | ||
1346 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); | ||
1347 | struct soc_camera_sense sense = { | ||
1348 | .master_clock = pcdev->mclk, | ||
1349 | .pixel_clock_max = pcdev->ciclk / 4, | ||
1350 | }; | ||
1351 | struct v4l2_mbus_framefmt mf; | ||
1352 | struct pxa_cam *cam = icd->host_priv; | ||
1353 | u32 fourcc = icd->current_fmt->host_fmt->fourcc; | ||
1354 | int ret; | ||
1355 | |||
1356 | /* If PCLK is used to latch data from the sensor, check sense */ | ||
1357 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | ||
1358 | icd->sense = &sense; | ||
1359 | |||
1360 | ret = v4l2_subdev_call(sd, video, s_crop, a); | ||
1361 | |||
1362 | icd->sense = NULL; | ||
1363 | |||
1364 | if (ret < 0) { | ||
1365 | dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n", | ||
1366 | rect->width, rect->height, rect->left, rect->top); | ||
1367 | return ret; | ||
1368 | } | ||
1369 | |||
1370 | ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); | ||
1371 | if (ret < 0) | ||
1372 | return ret; | ||
1373 | |||
1374 | if (pxa_camera_check_frame(mf.width, mf.height)) { | ||
1375 | /* | ||
1376 | * Camera cropping produced a frame beyond our capabilities. | ||
1377 | * FIXME: just extract a subframe, that we can process. | ||
1378 | */ | ||
1379 | v4l_bound_align_image(&mf.width, 48, 2048, 1, | ||
1380 | &mf.height, 32, 2048, 0, | ||
1381 | fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0); | ||
1382 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | ||
1383 | if (ret < 0) | ||
1384 | return ret; | ||
1385 | |||
1386 | if (pxa_camera_check_frame(mf.width, mf.height)) { | ||
1387 | dev_warn(icd->parent, | ||
1388 | "Inconsistent state. Use S_FMT to repair\n"); | ||
1389 | return -EINVAL; | ||
1390 | } | ||
1391 | } | ||
1392 | |||
1393 | if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { | ||
1394 | if (sense.pixel_clock > sense.pixel_clock_max) { | ||
1395 | dev_err(dev, | ||
1396 | "pixel clock %lu set by the camera too high!", | ||
1397 | sense.pixel_clock); | ||
1398 | return -EIO; | ||
1399 | } | ||
1400 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | ||
1401 | } | ||
1402 | |||
1403 | icd->user_width = mf.width; | ||
1404 | icd->user_height = mf.height; | ||
1405 | |||
1406 | pxa_camera_setup_cicr(icd, cam->flags, fourcc); | ||
1407 | |||
1408 | return ret; | ||
1409 | } | ||
1410 | |||
1411 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, | ||
1412 | struct v4l2_format *f) | ||
1413 | { | ||
1414 | struct device *dev = icd->parent; | ||
1415 | struct soc_camera_host *ici = to_soc_camera_host(dev); | ||
1416 | struct pxa_camera_dev *pcdev = ici->priv; | ||
1417 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); | ||
1418 | const struct soc_camera_format_xlate *xlate = NULL; | ||
1419 | struct soc_camera_sense sense = { | ||
1420 | .master_clock = pcdev->mclk, | ||
1421 | .pixel_clock_max = pcdev->ciclk / 4, | ||
1422 | }; | ||
1423 | struct v4l2_pix_format *pix = &f->fmt.pix; | ||
1424 | struct v4l2_mbus_framefmt mf; | ||
1425 | int ret; | ||
1426 | |||
1427 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); | ||
1428 | if (!xlate) { | ||
1429 | dev_warn(dev, "Format %x not found\n", pix->pixelformat); | ||
1430 | return -EINVAL; | ||
1431 | } | ||
1432 | |||
1433 | /* If PCLK is used to latch data from the sensor, check sense */ | ||
1434 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | ||
1435 | /* The caller holds a mutex. */ | ||
1436 | icd->sense = &sense; | ||
1437 | |||
1438 | mf.width = pix->width; | ||
1439 | mf.height = pix->height; | ||
1440 | mf.field = pix->field; | ||
1441 | mf.colorspace = pix->colorspace; | ||
1442 | mf.code = xlate->code; | ||
1443 | |||
1444 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | ||
1445 | |||
1446 | if (mf.code != xlate->code) | ||
1447 | return -EINVAL; | ||
1448 | |||
1449 | icd->sense = NULL; | ||
1450 | |||
1451 | if (ret < 0) { | ||
1452 | dev_warn(dev, "Failed to configure for format %x\n", | ||
1453 | pix->pixelformat); | ||
1454 | } else if (pxa_camera_check_frame(mf.width, mf.height)) { | ||
1455 | dev_warn(dev, | ||
1456 | "Camera driver produced an unsupported frame %dx%d\n", | ||
1457 | mf.width, mf.height); | ||
1458 | ret = -EINVAL; | ||
1459 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { | ||
1460 | if (sense.pixel_clock > sense.pixel_clock_max) { | ||
1461 | dev_err(dev, | ||
1462 | "pixel clock %lu set by the camera too high!", | ||
1463 | sense.pixel_clock); | ||
1464 | return -EIO; | ||
1465 | } | ||
1466 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | ||
1467 | } | ||
1468 | |||
1469 | if (ret < 0) | ||
1470 | return ret; | ||
1471 | |||
1472 | pix->width = mf.width; | ||
1473 | pix->height = mf.height; | ||
1474 | pix->field = mf.field; | ||
1475 | pix->colorspace = mf.colorspace; | ||
1476 | icd->current_fmt = xlate; | ||
1477 | |||
1478 | return ret; | ||
1479 | } | ||
1480 | |||
1481 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, | ||
1482 | struct v4l2_format *f) | ||
1483 | { | ||
1484 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); | ||
1485 | const struct soc_camera_format_xlate *xlate; | ||
1486 | struct v4l2_pix_format *pix = &f->fmt.pix; | ||
1487 | struct v4l2_mbus_framefmt mf; | ||
1488 | __u32 pixfmt = pix->pixelformat; | ||
1489 | int ret; | ||
1490 | |||
1491 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); | ||
1492 | if (!xlate) { | ||
1493 | dev_warn(icd->parent, "Format %x not found\n", pixfmt); | ||
1494 | return -EINVAL; | ||
1495 | } | ||
1496 | |||
1497 | /* | ||
1498 | * Limit to pxa hardware capabilities. YUV422P planar format requires | ||
1499 | * images size to be a multiple of 16 bytes. If not, zeros will be | ||
1500 | * inserted between Y and U planes, and U and V planes, which violates | ||
1501 | * the YUV422P standard. | ||
1502 | */ | ||
1503 | v4l_bound_align_image(&pix->width, 48, 2048, 1, | ||
1504 | &pix->height, 32, 2048, 0, | ||
1505 | pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); | ||
1506 | |||
1507 | /* limit to sensor capabilities */ | ||
1508 | mf.width = pix->width; | ||
1509 | mf.height = pix->height; | ||
1510 | /* Only progressive video supported so far */ | ||
1511 | mf.field = V4L2_FIELD_NONE; | ||
1512 | mf.colorspace = pix->colorspace; | ||
1513 | mf.code = xlate->code; | ||
1514 | |||
1515 | ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); | ||
1516 | if (ret < 0) | ||
1517 | return ret; | ||
1518 | |||
1519 | pix->width = mf.width; | ||
1520 | pix->height = mf.height; | ||
1521 | pix->colorspace = mf.colorspace; | ||
1522 | |||
1523 | switch (mf.field) { | ||
1524 | case V4L2_FIELD_ANY: | ||
1525 | case V4L2_FIELD_NONE: | ||
1526 | pix->field = V4L2_FIELD_NONE; | ||
1527 | break; | ||
1528 | default: | ||
1529 | /* TODO: support interlaced at least in pass-through mode */ | ||
1530 | dev_err(icd->parent, "Field type %d unsupported.\n", | ||
1531 | mf.field); | ||
1532 | return -EINVAL; | ||
1533 | } | ||
1534 | |||
1535 | return ret; | ||
1536 | } | ||
1537 | |||
1538 | static int pxa_camera_reqbufs(struct soc_camera_device *icd, | ||
1539 | struct v4l2_requestbuffers *p) | ||
1540 | { | ||
1541 | int i; | ||
1542 | |||
1543 | /* | ||
1544 | * This is for locking debugging only. I removed spinlocks and now I | ||
1545 | * check whether .prepare is ever called on a linked buffer, or whether | ||
1546 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | ||
1547 | * it hadn't triggered | ||
1548 | */ | ||
1549 | for (i = 0; i < p->count; i++) { | ||
1550 | struct pxa_buffer *buf = container_of(icd->vb_vidq.bufs[i], | ||
1551 | struct pxa_buffer, vb); | ||
1552 | buf->inwork = 0; | ||
1553 | INIT_LIST_HEAD(&buf->vb.queue); | ||
1554 | } | ||
1555 | |||
1556 | return 0; | ||
1557 | } | ||
1558 | |||
1559 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) | ||
1560 | { | ||
1561 | struct soc_camera_device *icd = file->private_data; | ||
1562 | struct pxa_buffer *buf; | ||
1563 | |||
1564 | buf = list_entry(icd->vb_vidq.stream.next, struct pxa_buffer, | ||
1565 | vb.stream); | ||
1566 | |||
1567 | poll_wait(file, &buf->vb.done, pt); | ||
1568 | |||
1569 | if (buf->vb.state == VIDEOBUF_DONE || | ||
1570 | buf->vb.state == VIDEOBUF_ERROR) | ||
1571 | return POLLIN|POLLRDNORM; | ||
1572 | |||
1573 | return 0; | ||
1574 | } | ||
1575 | |||
1576 | static int pxa_camera_querycap(struct soc_camera_host *ici, | ||
1577 | struct v4l2_capability *cap) | ||
1578 | { | ||
1579 | /* cap->name is set by the firendly caller:-> */ | ||
1580 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | ||
1581 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; | ||
1582 | |||
1583 | return 0; | ||
1584 | } | ||
1585 | |||
1586 | static int pxa_camera_suspend(struct device *dev) | ||
1587 | { | ||
1588 | struct soc_camera_host *ici = to_soc_camera_host(dev); | ||
1589 | struct pxa_camera_dev *pcdev = ici->priv; | ||
1590 | int i = 0, ret = 0; | ||
1591 | |||
1592 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); | ||
1593 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | ||
1594 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | ||
1595 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | ||
1596 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | ||
1597 | |||
1598 | if (pcdev->icd) { | ||
1599 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->icd); | ||
1600 | ret = v4l2_subdev_call(sd, core, s_power, 0); | ||
1601 | if (ret == -ENOIOCTLCMD) | ||
1602 | ret = 0; | ||
1603 | } | ||
1604 | |||
1605 | return ret; | ||
1606 | } | ||
1607 | |||
1608 | static int pxa_camera_resume(struct device *dev) | ||
1609 | { | ||
1610 | struct soc_camera_host *ici = to_soc_camera_host(dev); | ||
1611 | struct pxa_camera_dev *pcdev = ici->priv; | ||
1612 | int i = 0, ret = 0; | ||
1613 | |||
1614 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; | ||
1615 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | ||
1616 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | ||
1617 | |||
1618 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); | ||
1619 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | ||
1620 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | ||
1621 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | ||
1622 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | ||
1623 | |||
1624 | if (pcdev->icd) { | ||
1625 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->icd); | ||
1626 | ret = v4l2_subdev_call(sd, core, s_power, 1); | ||
1627 | if (ret == -ENOIOCTLCMD) | ||
1628 | ret = 0; | ||
1629 | } | ||
1630 | |||
1631 | /* Restart frame capture if active buffer exists */ | ||
1632 | if (!ret && pcdev->active) | ||
1633 | pxa_camera_start_capture(pcdev); | ||
1634 | |||
1635 | return ret; | ||
1636 | } | ||
1637 | |||
1638 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { | ||
1639 | .owner = THIS_MODULE, | ||
1640 | .add = pxa_camera_add_device, | ||
1641 | .remove = pxa_camera_remove_device, | ||
1642 | .set_crop = pxa_camera_set_crop, | ||
1643 | .get_formats = pxa_camera_get_formats, | ||
1644 | .put_formats = pxa_camera_put_formats, | ||
1645 | .set_fmt = pxa_camera_set_fmt, | ||
1646 | .try_fmt = pxa_camera_try_fmt, | ||
1647 | .init_videobuf = pxa_camera_init_videobuf, | ||
1648 | .reqbufs = pxa_camera_reqbufs, | ||
1649 | .poll = pxa_camera_poll, | ||
1650 | .querycap = pxa_camera_querycap, | ||
1651 | .set_bus_param = pxa_camera_set_bus_param, | ||
1652 | }; | ||
1653 | |||
1654 | static int __devinit pxa_camera_probe(struct platform_device *pdev) | ||
1655 | { | ||
1656 | struct pxa_camera_dev *pcdev; | ||
1657 | struct resource *res; | ||
1658 | void __iomem *base; | ||
1659 | int irq; | ||
1660 | int err = 0; | ||
1661 | |||
1662 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1663 | irq = platform_get_irq(pdev, 0); | ||
1664 | if (!res || irq < 0) { | ||
1665 | err = -ENODEV; | ||
1666 | goto exit; | ||
1667 | } | ||
1668 | |||
1669 | pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); | ||
1670 | if (!pcdev) { | ||
1671 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); | ||
1672 | err = -ENOMEM; | ||
1673 | goto exit; | ||
1674 | } | ||
1675 | |||
1676 | pcdev->clk = clk_get(&pdev->dev, NULL); | ||
1677 | if (IS_ERR(pcdev->clk)) { | ||
1678 | err = PTR_ERR(pcdev->clk); | ||
1679 | goto exit_kfree; | ||
1680 | } | ||
1681 | |||
1682 | pcdev->res = res; | ||
1683 | |||
1684 | pcdev->pdata = pdev->dev.platform_data; | ||
1685 | pcdev->platform_flags = pcdev->pdata->flags; | ||
1686 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | | ||
1687 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | ||
1688 | /* | ||
1689 | * Platform hasn't set available data widths. This is bad. | ||
1690 | * Warn and use a default. | ||
1691 | */ | ||
1692 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " | ||
1693 | "data widths, using default 10 bit\n"); | ||
1694 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | ||
1695 | } | ||
1696 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8) | ||
1697 | pcdev->width_flags = 1 << 7; | ||
1698 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9) | ||
1699 | pcdev->width_flags |= 1 << 8; | ||
1700 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10) | ||
1701 | pcdev->width_flags |= 1 << 9; | ||
1702 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; | ||
1703 | if (!pcdev->mclk) { | ||
1704 | dev_warn(&pdev->dev, | ||
1705 | "mclk == 0! Please, fix your platform data. " | ||
1706 | "Using default 20MHz\n"); | ||
1707 | pcdev->mclk = 20000000; | ||
1708 | } | ||
1709 | |||
1710 | pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); | ||
1711 | |||
1712 | INIT_LIST_HEAD(&pcdev->capture); | ||
1713 | spin_lock_init(&pcdev->lock); | ||
1714 | |||
1715 | /* | ||
1716 | * Request the regions. | ||
1717 | */ | ||
1718 | if (!request_mem_region(res->start, resource_size(res), | ||
1719 | PXA_CAM_DRV_NAME)) { | ||
1720 | err = -EBUSY; | ||
1721 | goto exit_clk; | ||
1722 | } | ||
1723 | |||
1724 | base = ioremap(res->start, resource_size(res)); | ||
1725 | if (!base) { | ||
1726 | err = -ENOMEM; | ||
1727 | goto exit_release; | ||
1728 | } | ||
1729 | pcdev->irq = irq; | ||
1730 | pcdev->base = base; | ||
1731 | |||
1732 | /* request dma */ | ||
1733 | err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, | ||
1734 | pxa_camera_dma_irq_y, pcdev); | ||
1735 | if (err < 0) { | ||
1736 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); | ||
1737 | goto exit_iounmap; | ||
1738 | } | ||
1739 | pcdev->dma_chans[0] = err; | ||
1740 | dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]); | ||
1741 | |||
1742 | err = pxa_request_dma("CI_U", DMA_PRIO_HIGH, | ||
1743 | pxa_camera_dma_irq_u, pcdev); | ||
1744 | if (err < 0) { | ||
1745 | dev_err(&pdev->dev, "Can't request DMA for U\n"); | ||
1746 | goto exit_free_dma_y; | ||
1747 | } | ||
1748 | pcdev->dma_chans[1] = err; | ||
1749 | dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]); | ||
1750 | |||
1751 | err = pxa_request_dma("CI_V", DMA_PRIO_HIGH, | ||
1752 | pxa_camera_dma_irq_v, pcdev); | ||
1753 | if (err < 0) { | ||
1754 | dev_err(&pdev->dev, "Can't request DMA for V\n"); | ||
1755 | goto exit_free_dma_u; | ||
1756 | } | ||
1757 | pcdev->dma_chans[2] = err; | ||
1758 | dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]); | ||
1759 | |||
1760 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; | ||
1761 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | ||
1762 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | ||
1763 | |||
1764 | /* request irq */ | ||
1765 | err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME, | ||
1766 | pcdev); | ||
1767 | if (err) { | ||
1768 | dev_err(&pdev->dev, "Camera interrupt register failed \n"); | ||
1769 | goto exit_free_dma; | ||
1770 | } | ||
1771 | |||
1772 | pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME; | ||
1773 | pcdev->soc_host.ops = &pxa_soc_camera_host_ops; | ||
1774 | pcdev->soc_host.priv = pcdev; | ||
1775 | pcdev->soc_host.v4l2_dev.dev = &pdev->dev; | ||
1776 | pcdev->soc_host.nr = pdev->id; | ||
1777 | |||
1778 | err = soc_camera_host_register(&pcdev->soc_host); | ||
1779 | if (err) | ||
1780 | goto exit_free_irq; | ||
1781 | |||
1782 | return 0; | ||
1783 | |||
1784 | exit_free_irq: | ||
1785 | free_irq(pcdev->irq, pcdev); | ||
1786 | exit_free_dma: | ||
1787 | pxa_free_dma(pcdev->dma_chans[2]); | ||
1788 | exit_free_dma_u: | ||
1789 | pxa_free_dma(pcdev->dma_chans[1]); | ||
1790 | exit_free_dma_y: | ||
1791 | pxa_free_dma(pcdev->dma_chans[0]); | ||
1792 | exit_iounmap: | ||
1793 | iounmap(base); | ||
1794 | exit_release: | ||
1795 | release_mem_region(res->start, resource_size(res)); | ||
1796 | exit_clk: | ||
1797 | clk_put(pcdev->clk); | ||
1798 | exit_kfree: | ||
1799 | kfree(pcdev); | ||
1800 | exit: | ||
1801 | return err; | ||
1802 | } | ||
1803 | |||
1804 | static int __devexit pxa_camera_remove(struct platform_device *pdev) | ||
1805 | { | ||
1806 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); | ||
1807 | struct pxa_camera_dev *pcdev = container_of(soc_host, | ||
1808 | struct pxa_camera_dev, soc_host); | ||
1809 | struct resource *res; | ||
1810 | |||
1811 | clk_put(pcdev->clk); | ||
1812 | |||
1813 | pxa_free_dma(pcdev->dma_chans[0]); | ||
1814 | pxa_free_dma(pcdev->dma_chans[1]); | ||
1815 | pxa_free_dma(pcdev->dma_chans[2]); | ||
1816 | free_irq(pcdev->irq, pcdev); | ||
1817 | |||
1818 | soc_camera_host_unregister(soc_host); | ||
1819 | |||
1820 | iounmap(pcdev->base); | ||
1821 | |||
1822 | res = pcdev->res; | ||
1823 | release_mem_region(res->start, resource_size(res)); | ||
1824 | |||
1825 | kfree(pcdev); | ||
1826 | |||
1827 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); | ||
1828 | |||
1829 | return 0; | ||
1830 | } | ||
1831 | |||
1832 | static struct dev_pm_ops pxa_camera_pm = { | ||
1833 | .suspend = pxa_camera_suspend, | ||
1834 | .resume = pxa_camera_resume, | ||
1835 | }; | ||
1836 | |||
1837 | static struct platform_driver pxa_camera_driver = { | ||
1838 | .driver = { | ||
1839 | .name = PXA_CAM_DRV_NAME, | ||
1840 | .pm = &pxa_camera_pm, | ||
1841 | }, | ||
1842 | .probe = pxa_camera_probe, | ||
1843 | .remove = __devexit_p(pxa_camera_remove), | ||
1844 | }; | ||
1845 | |||
1846 | module_platform_driver(pxa_camera_driver); | ||
1847 | |||
1848 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | ||
1849 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | ||
1850 | MODULE_LICENSE("GPL"); | ||
1851 | MODULE_VERSION(PXA_CAM_VERSION); | ||
1852 | MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); | ||