diff options
Diffstat (limited to 'drivers/media/video/davinci/vpif.h')
-rw-r--r-- | drivers/media/video/davinci/vpif.h | 688 |
1 files changed, 0 insertions, 688 deletions
diff --git a/drivers/media/video/davinci/vpif.h b/drivers/media/video/davinci/vpif.h deleted file mode 100644 index c2ce4d97c279..000000000000 --- a/drivers/media/video/davinci/vpif.h +++ /dev/null | |||
@@ -1,688 +0,0 @@ | |||
1 | /* | ||
2 | * VPIF header file | ||
3 | * | ||
4 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License as | ||
8 | * published by the Free Software Foundation version 2. | ||
9 | * | ||
10 | * This program is distributed .as is. WITHOUT ANY WARRANTY of any | ||
11 | * kind, whether express or implied; without even the implied warranty | ||
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef VPIF_H | ||
17 | #define VPIF_H | ||
18 | |||
19 | #include <linux/io.h> | ||
20 | #include <linux/videodev2.h> | ||
21 | #include <media/davinci/vpif_types.h> | ||
22 | |||
23 | /* Maximum channel allowed */ | ||
24 | #define VPIF_NUM_CHANNELS (4) | ||
25 | #define VPIF_CAPTURE_NUM_CHANNELS (2) | ||
26 | #define VPIF_DISPLAY_NUM_CHANNELS (2) | ||
27 | |||
28 | /* Macros to read/write registers */ | ||
29 | extern void __iomem *vpif_base; | ||
30 | extern spinlock_t vpif_lock; | ||
31 | |||
32 | #define regr(reg) readl((reg) + vpif_base) | ||
33 | #define regw(value, reg) writel(value, (reg + vpif_base)) | ||
34 | |||
35 | /* Register Address Offsets */ | ||
36 | #define VPIF_PID (0x0000) | ||
37 | #define VPIF_CH0_CTRL (0x0004) | ||
38 | #define VPIF_CH1_CTRL (0x0008) | ||
39 | #define VPIF_CH2_CTRL (0x000C) | ||
40 | #define VPIF_CH3_CTRL (0x0010) | ||
41 | |||
42 | #define VPIF_INTEN (0x0020) | ||
43 | #define VPIF_INTEN_SET (0x0024) | ||
44 | #define VPIF_INTEN_CLR (0x0028) | ||
45 | #define VPIF_STATUS (0x002C) | ||
46 | #define VPIF_STATUS_CLR (0x0030) | ||
47 | #define VPIF_EMULATION_CTRL (0x0034) | ||
48 | #define VPIF_REQ_SIZE (0x0038) | ||
49 | |||
50 | #define VPIF_CH0_TOP_STRT_ADD_LUMA (0x0040) | ||
51 | #define VPIF_CH0_BTM_STRT_ADD_LUMA (0x0044) | ||
52 | #define VPIF_CH0_TOP_STRT_ADD_CHROMA (0x0048) | ||
53 | #define VPIF_CH0_BTM_STRT_ADD_CHROMA (0x004c) | ||
54 | #define VPIF_CH0_TOP_STRT_ADD_HANC (0x0050) | ||
55 | #define VPIF_CH0_BTM_STRT_ADD_HANC (0x0054) | ||
56 | #define VPIF_CH0_TOP_STRT_ADD_VANC (0x0058) | ||
57 | #define VPIF_CH0_BTM_STRT_ADD_VANC (0x005c) | ||
58 | #define VPIF_CH0_SP_CFG (0x0060) | ||
59 | #define VPIF_CH0_IMG_ADD_OFST (0x0064) | ||
60 | #define VPIF_CH0_HANC_ADD_OFST (0x0068) | ||
61 | #define VPIF_CH0_H_CFG (0x006c) | ||
62 | #define VPIF_CH0_V_CFG_00 (0x0070) | ||
63 | #define VPIF_CH0_V_CFG_01 (0x0074) | ||
64 | #define VPIF_CH0_V_CFG_02 (0x0078) | ||
65 | #define VPIF_CH0_V_CFG_03 (0x007c) | ||
66 | |||
67 | #define VPIF_CH1_TOP_STRT_ADD_LUMA (0x0080) | ||
68 | #define VPIF_CH1_BTM_STRT_ADD_LUMA (0x0084) | ||
69 | #define VPIF_CH1_TOP_STRT_ADD_CHROMA (0x0088) | ||
70 | #define VPIF_CH1_BTM_STRT_ADD_CHROMA (0x008c) | ||
71 | #define VPIF_CH1_TOP_STRT_ADD_HANC (0x0090) | ||
72 | #define VPIF_CH1_BTM_STRT_ADD_HANC (0x0094) | ||
73 | #define VPIF_CH1_TOP_STRT_ADD_VANC (0x0098) | ||
74 | #define VPIF_CH1_BTM_STRT_ADD_VANC (0x009c) | ||
75 | #define VPIF_CH1_SP_CFG (0x00a0) | ||
76 | #define VPIF_CH1_IMG_ADD_OFST (0x00a4) | ||
77 | #define VPIF_CH1_HANC_ADD_OFST (0x00a8) | ||
78 | #define VPIF_CH1_H_CFG (0x00ac) | ||
79 | #define VPIF_CH1_V_CFG_00 (0x00b0) | ||
80 | #define VPIF_CH1_V_CFG_01 (0x00b4) | ||
81 | #define VPIF_CH1_V_CFG_02 (0x00b8) | ||
82 | #define VPIF_CH1_V_CFG_03 (0x00bc) | ||
83 | |||
84 | #define VPIF_CH2_TOP_STRT_ADD_LUMA (0x00c0) | ||
85 | #define VPIF_CH2_BTM_STRT_ADD_LUMA (0x00c4) | ||
86 | #define VPIF_CH2_TOP_STRT_ADD_CHROMA (0x00c8) | ||
87 | #define VPIF_CH2_BTM_STRT_ADD_CHROMA (0x00cc) | ||
88 | #define VPIF_CH2_TOP_STRT_ADD_HANC (0x00d0) | ||
89 | #define VPIF_CH2_BTM_STRT_ADD_HANC (0x00d4) | ||
90 | #define VPIF_CH2_TOP_STRT_ADD_VANC (0x00d8) | ||
91 | #define VPIF_CH2_BTM_STRT_ADD_VANC (0x00dc) | ||
92 | #define VPIF_CH2_SP_CFG (0x00e0) | ||
93 | #define VPIF_CH2_IMG_ADD_OFST (0x00e4) | ||
94 | #define VPIF_CH2_HANC_ADD_OFST (0x00e8) | ||
95 | #define VPIF_CH2_H_CFG (0x00ec) | ||
96 | #define VPIF_CH2_V_CFG_00 (0x00f0) | ||
97 | #define VPIF_CH2_V_CFG_01 (0x00f4) | ||
98 | #define VPIF_CH2_V_CFG_02 (0x00f8) | ||
99 | #define VPIF_CH2_V_CFG_03 (0x00fc) | ||
100 | #define VPIF_CH2_HANC0_STRT (0x0100) | ||
101 | #define VPIF_CH2_HANC0_SIZE (0x0104) | ||
102 | #define VPIF_CH2_HANC1_STRT (0x0108) | ||
103 | #define VPIF_CH2_HANC1_SIZE (0x010c) | ||
104 | #define VPIF_CH2_VANC0_STRT (0x0110) | ||
105 | #define VPIF_CH2_VANC0_SIZE (0x0114) | ||
106 | #define VPIF_CH2_VANC1_STRT (0x0118) | ||
107 | #define VPIF_CH2_VANC1_SIZE (0x011c) | ||
108 | |||
109 | #define VPIF_CH3_TOP_STRT_ADD_LUMA (0x0140) | ||
110 | #define VPIF_CH3_BTM_STRT_ADD_LUMA (0x0144) | ||
111 | #define VPIF_CH3_TOP_STRT_ADD_CHROMA (0x0148) | ||
112 | #define VPIF_CH3_BTM_STRT_ADD_CHROMA (0x014c) | ||
113 | #define VPIF_CH3_TOP_STRT_ADD_HANC (0x0150) | ||
114 | #define VPIF_CH3_BTM_STRT_ADD_HANC (0x0154) | ||
115 | #define VPIF_CH3_TOP_STRT_ADD_VANC (0x0158) | ||
116 | #define VPIF_CH3_BTM_STRT_ADD_VANC (0x015c) | ||
117 | #define VPIF_CH3_SP_CFG (0x0160) | ||
118 | #define VPIF_CH3_IMG_ADD_OFST (0x0164) | ||
119 | #define VPIF_CH3_HANC_ADD_OFST (0x0168) | ||
120 | #define VPIF_CH3_H_CFG (0x016c) | ||
121 | #define VPIF_CH3_V_CFG_00 (0x0170) | ||
122 | #define VPIF_CH3_V_CFG_01 (0x0174) | ||
123 | #define VPIF_CH3_V_CFG_02 (0x0178) | ||
124 | #define VPIF_CH3_V_CFG_03 (0x017c) | ||
125 | #define VPIF_CH3_HANC0_STRT (0x0180) | ||
126 | #define VPIF_CH3_HANC0_SIZE (0x0184) | ||
127 | #define VPIF_CH3_HANC1_STRT (0x0188) | ||
128 | #define VPIF_CH3_HANC1_SIZE (0x018c) | ||
129 | #define VPIF_CH3_VANC0_STRT (0x0190) | ||
130 | #define VPIF_CH3_VANC0_SIZE (0x0194) | ||
131 | #define VPIF_CH3_VANC1_STRT (0x0198) | ||
132 | #define VPIF_CH3_VANC1_SIZE (0x019c) | ||
133 | |||
134 | #define VPIF_IODFT_CTRL (0x01c0) | ||
135 | |||
136 | /* Functions for bit Manipulation */ | ||
137 | static inline void vpif_set_bit(u32 reg, u32 bit) | ||
138 | { | ||
139 | regw((regr(reg)) | (0x01 << bit), reg); | ||
140 | } | ||
141 | |||
142 | static inline void vpif_clr_bit(u32 reg, u32 bit) | ||
143 | { | ||
144 | regw(((regr(reg)) & ~(0x01 << bit)), reg); | ||
145 | } | ||
146 | |||
147 | /* Macro for Generating mask */ | ||
148 | #ifdef GENERATE_MASK | ||
149 | #undef GENERATE_MASK | ||
150 | #endif | ||
151 | |||
152 | #define GENERATE_MASK(bits, pos) \ | ||
153 | ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos) | ||
154 | |||
155 | /* Bit positions in the channel control registers */ | ||
156 | #define VPIF_CH_DATA_MODE_BIT (2) | ||
157 | #define VPIF_CH_YC_MUX_BIT (3) | ||
158 | #define VPIF_CH_SDR_FMT_BIT (4) | ||
159 | #define VPIF_CH_HANC_EN_BIT (8) | ||
160 | #define VPIF_CH_VANC_EN_BIT (9) | ||
161 | |||
162 | #define VPIF_CAPTURE_CH_NIP (10) | ||
163 | #define VPIF_DISPLAY_CH_NIP (11) | ||
164 | |||
165 | #define VPIF_DISPLAY_PIX_EN_BIT (10) | ||
166 | |||
167 | #define VPIF_CH_INPUT_FIELD_FRAME_BIT (12) | ||
168 | |||
169 | #define VPIF_CH_FID_POLARITY_BIT (15) | ||
170 | #define VPIF_CH_V_VALID_POLARITY_BIT (14) | ||
171 | #define VPIF_CH_H_VALID_POLARITY_BIT (13) | ||
172 | #define VPIF_CH_DATA_WIDTH_BIT (28) | ||
173 | |||
174 | #define VPIF_CH_CLK_EDGE_CTRL_BIT (31) | ||
175 | |||
176 | /* Mask various length */ | ||
177 | #define VPIF_CH_EAVSAV_MASK GENERATE_MASK(13, 0) | ||
178 | #define VPIF_CH_LEN_MASK GENERATE_MASK(12, 0) | ||
179 | #define VPIF_CH_WIDTH_MASK GENERATE_MASK(13, 0) | ||
180 | #define VPIF_CH_LEN_SHIFT (16) | ||
181 | |||
182 | /* VPIF masks for registers */ | ||
183 | #define VPIF_REQ_SIZE_MASK (0x1ff) | ||
184 | |||
185 | /* bit posotion of interrupt vpif_ch_intr register */ | ||
186 | #define VPIF_INTEN_FRAME_CH0 (0x00000001) | ||
187 | #define VPIF_INTEN_FRAME_CH1 (0x00000002) | ||
188 | #define VPIF_INTEN_FRAME_CH2 (0x00000004) | ||
189 | #define VPIF_INTEN_FRAME_CH3 (0x00000008) | ||
190 | |||
191 | /* bit position of clock and channel enable in vpif_chn_ctrl register */ | ||
192 | |||
193 | #define VPIF_CH0_CLK_EN (0x00000002) | ||
194 | #define VPIF_CH0_EN (0x00000001) | ||
195 | #define VPIF_CH1_CLK_EN (0x00000002) | ||
196 | #define VPIF_CH1_EN (0x00000001) | ||
197 | #define VPIF_CH2_CLK_EN (0x00000002) | ||
198 | #define VPIF_CH2_EN (0x00000001) | ||
199 | #define VPIF_CH3_CLK_EN (0x00000002) | ||
200 | #define VPIF_CH3_EN (0x00000001) | ||
201 | #define VPIF_CH_CLK_EN (0x00000002) | ||
202 | #define VPIF_CH_EN (0x00000001) | ||
203 | |||
204 | #define VPIF_INT_TOP (0x00) | ||
205 | #define VPIF_INT_BOTTOM (0x01) | ||
206 | #define VPIF_INT_BOTH (0x02) | ||
207 | |||
208 | #define VPIF_CH0_INT_CTRL_SHIFT (6) | ||
209 | #define VPIF_CH1_INT_CTRL_SHIFT (6) | ||
210 | #define VPIF_CH2_INT_CTRL_SHIFT (6) | ||
211 | #define VPIF_CH3_INT_CTRL_SHIFT (6) | ||
212 | #define VPIF_CH_INT_CTRL_SHIFT (6) | ||
213 | |||
214 | #define VPIF_CH2_CLIP_ANC_EN 14 | ||
215 | #define VPIF_CH2_CLIP_ACTIVE_EN 13 | ||
216 | |||
217 | #define VPIF_CH3_CLIP_ANC_EN 14 | ||
218 | #define VPIF_CH3_CLIP_ACTIVE_EN 13 | ||
219 | |||
220 | /* enabled interrupt on both the fields on vpid_ch0_ctrl register */ | ||
221 | #define channel0_intr_assert() (regw((regr(VPIF_CH0_CTRL)|\ | ||
222 | (VPIF_INT_BOTH << VPIF_CH0_INT_CTRL_SHIFT)), VPIF_CH0_CTRL)) | ||
223 | |||
224 | /* enabled interrupt on both the fields on vpid_ch1_ctrl register */ | ||
225 | #define channel1_intr_assert() (regw((regr(VPIF_CH1_CTRL)|\ | ||
226 | (VPIF_INT_BOTH << VPIF_CH1_INT_CTRL_SHIFT)), VPIF_CH1_CTRL)) | ||
227 | |||
228 | /* enabled interrupt on both the fields on vpid_ch0_ctrl register */ | ||
229 | #define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\ | ||
230 | (VPIF_INT_BOTH << VPIF_CH2_INT_CTRL_SHIFT)), VPIF_CH2_CTRL)) | ||
231 | |||
232 | /* enabled interrupt on both the fields on vpid_ch1_ctrl register */ | ||
233 | #define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\ | ||
234 | (VPIF_INT_BOTH << VPIF_CH3_INT_CTRL_SHIFT)), VPIF_CH3_CTRL)) | ||
235 | |||
236 | #define VPIF_CH_FID_MASK (0x20) | ||
237 | #define VPIF_CH_FID_SHIFT (5) | ||
238 | |||
239 | #define VPIF_NTSC_VBI_START_FIELD0 (1) | ||
240 | #define VPIF_NTSC_VBI_START_FIELD1 (263) | ||
241 | #define VPIF_PAL_VBI_START_FIELD0 (624) | ||
242 | #define VPIF_PAL_VBI_START_FIELD1 (311) | ||
243 | |||
244 | #define VPIF_NTSC_HBI_START_FIELD0 (1) | ||
245 | #define VPIF_NTSC_HBI_START_FIELD1 (263) | ||
246 | #define VPIF_PAL_HBI_START_FIELD0 (624) | ||
247 | #define VPIF_PAL_HBI_START_FIELD1 (311) | ||
248 | |||
249 | #define VPIF_NTSC_VBI_COUNT_FIELD0 (20) | ||
250 | #define VPIF_NTSC_VBI_COUNT_FIELD1 (19) | ||
251 | #define VPIF_PAL_VBI_COUNT_FIELD0 (24) | ||
252 | #define VPIF_PAL_VBI_COUNT_FIELD1 (25) | ||
253 | |||
254 | #define VPIF_NTSC_HBI_COUNT_FIELD0 (263) | ||
255 | #define VPIF_NTSC_HBI_COUNT_FIELD1 (262) | ||
256 | #define VPIF_PAL_HBI_COUNT_FIELD0 (312) | ||
257 | #define VPIF_PAL_HBI_COUNT_FIELD1 (313) | ||
258 | |||
259 | #define VPIF_NTSC_VBI_SAMPLES_PER_LINE (720) | ||
260 | #define VPIF_PAL_VBI_SAMPLES_PER_LINE (720) | ||
261 | #define VPIF_NTSC_HBI_SAMPLES_PER_LINE (268) | ||
262 | #define VPIF_PAL_HBI_SAMPLES_PER_LINE (280) | ||
263 | |||
264 | #define VPIF_CH_VANC_EN (0x20) | ||
265 | #define VPIF_DMA_REQ_SIZE (0x080) | ||
266 | #define VPIF_EMULATION_DISABLE (0x01) | ||
267 | |||
268 | extern u8 irq_vpif_capture_channel[VPIF_NUM_CHANNELS]; | ||
269 | |||
270 | /* inline function to enable/disable channel0 */ | ||
271 | static inline void enable_channel0(int enable) | ||
272 | { | ||
273 | if (enable) | ||
274 | regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL); | ||
275 | else | ||
276 | regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL); | ||
277 | } | ||
278 | |||
279 | /* inline function to enable/disable channel1 */ | ||
280 | static inline void enable_channel1(int enable) | ||
281 | { | ||
282 | if (enable) | ||
283 | regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL); | ||
284 | else | ||
285 | regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL); | ||
286 | } | ||
287 | |||
288 | /* inline function to enable interrupt for channel0 */ | ||
289 | static inline void channel0_intr_enable(int enable) | ||
290 | { | ||
291 | unsigned long flags; | ||
292 | |||
293 | spin_lock_irqsave(&vpif_lock, flags); | ||
294 | |||
295 | if (enable) { | ||
296 | regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); | ||
297 | regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); | ||
298 | |||
299 | regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN); | ||
300 | regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), | ||
301 | VPIF_INTEN_SET); | ||
302 | } else { | ||
303 | regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN); | ||
304 | regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), | ||
305 | VPIF_INTEN_SET); | ||
306 | } | ||
307 | spin_unlock_irqrestore(&vpif_lock, flags); | ||
308 | } | ||
309 | |||
310 | /* inline function to enable interrupt for channel1 */ | ||
311 | static inline void channel1_intr_enable(int enable) | ||
312 | { | ||
313 | unsigned long flags; | ||
314 | |||
315 | spin_lock_irqsave(&vpif_lock, flags); | ||
316 | |||
317 | if (enable) { | ||
318 | regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); | ||
319 | regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); | ||
320 | |||
321 | regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN); | ||
322 | regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), | ||
323 | VPIF_INTEN_SET); | ||
324 | } else { | ||
325 | regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN); | ||
326 | regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), | ||
327 | VPIF_INTEN_SET); | ||
328 | } | ||
329 | spin_unlock_irqrestore(&vpif_lock, flags); | ||
330 | } | ||
331 | |||
332 | /* inline function to set buffer addresses in case of Y/C non mux mode */ | ||
333 | static inline void ch0_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma, | ||
334 | unsigned long btm_strt_luma, | ||
335 | unsigned long top_strt_chroma, | ||
336 | unsigned long btm_strt_chroma) | ||
337 | { | ||
338 | regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA); | ||
339 | regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA); | ||
340 | regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA); | ||
341 | regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA); | ||
342 | } | ||
343 | |||
344 | /* inline function to set buffer addresses in VPIF registers for video data */ | ||
345 | static inline void ch0_set_videobuf_addr(unsigned long top_strt_luma, | ||
346 | unsigned long btm_strt_luma, | ||
347 | unsigned long top_strt_chroma, | ||
348 | unsigned long btm_strt_chroma) | ||
349 | { | ||
350 | regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA); | ||
351 | regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA); | ||
352 | regw(top_strt_chroma, VPIF_CH0_TOP_STRT_ADD_CHROMA); | ||
353 | regw(btm_strt_chroma, VPIF_CH0_BTM_STRT_ADD_CHROMA); | ||
354 | } | ||
355 | |||
356 | static inline void ch1_set_videobuf_addr(unsigned long top_strt_luma, | ||
357 | unsigned long btm_strt_luma, | ||
358 | unsigned long top_strt_chroma, | ||
359 | unsigned long btm_strt_chroma) | ||
360 | { | ||
361 | |||
362 | regw(top_strt_luma, VPIF_CH1_TOP_STRT_ADD_LUMA); | ||
363 | regw(btm_strt_luma, VPIF_CH1_BTM_STRT_ADD_LUMA); | ||
364 | regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA); | ||
365 | regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA); | ||
366 | } | ||
367 | |||
368 | static inline void ch0_set_vbi_addr(unsigned long top_vbi, | ||
369 | unsigned long btm_vbi, unsigned long a, unsigned long b) | ||
370 | { | ||
371 | regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_VANC); | ||
372 | regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_VANC); | ||
373 | } | ||
374 | |||
375 | static inline void ch0_set_hbi_addr(unsigned long top_vbi, | ||
376 | unsigned long btm_vbi, unsigned long a, unsigned long b) | ||
377 | { | ||
378 | regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_HANC); | ||
379 | regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_HANC); | ||
380 | } | ||
381 | |||
382 | static inline void ch1_set_vbi_addr(unsigned long top_vbi, | ||
383 | unsigned long btm_vbi, unsigned long a, unsigned long b) | ||
384 | { | ||
385 | regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_VANC); | ||
386 | regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_VANC); | ||
387 | } | ||
388 | |||
389 | static inline void ch1_set_hbi_addr(unsigned long top_vbi, | ||
390 | unsigned long btm_vbi, unsigned long a, unsigned long b) | ||
391 | { | ||
392 | regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_HANC); | ||
393 | regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_HANC); | ||
394 | } | ||
395 | |||
396 | /* Inline function to enable raw vbi in the given channel */ | ||
397 | static inline void disable_raw_feature(u8 channel_id, u8 index) | ||
398 | { | ||
399 | u32 ctrl_reg; | ||
400 | if (0 == channel_id) | ||
401 | ctrl_reg = VPIF_CH0_CTRL; | ||
402 | else | ||
403 | ctrl_reg = VPIF_CH1_CTRL; | ||
404 | |||
405 | if (1 == index) | ||
406 | vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); | ||
407 | else | ||
408 | vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); | ||
409 | } | ||
410 | |||
411 | static inline void enable_raw_feature(u8 channel_id, u8 index) | ||
412 | { | ||
413 | u32 ctrl_reg; | ||
414 | if (0 == channel_id) | ||
415 | ctrl_reg = VPIF_CH0_CTRL; | ||
416 | else | ||
417 | ctrl_reg = VPIF_CH1_CTRL; | ||
418 | |||
419 | if (1 == index) | ||
420 | vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); | ||
421 | else | ||
422 | vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); | ||
423 | } | ||
424 | |||
425 | /* inline function to enable/disable channel2 */ | ||
426 | static inline void enable_channel2(int enable) | ||
427 | { | ||
428 | if (enable) { | ||
429 | regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL); | ||
430 | regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL); | ||
431 | } else { | ||
432 | regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL); | ||
433 | regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL); | ||
434 | } | ||
435 | } | ||
436 | |||
437 | /* inline function to enable/disable channel3 */ | ||
438 | static inline void enable_channel3(int enable) | ||
439 | { | ||
440 | if (enable) { | ||
441 | regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL); | ||
442 | regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL); | ||
443 | } else { | ||
444 | regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL); | ||
445 | regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL); | ||
446 | } | ||
447 | } | ||
448 | |||
449 | /* inline function to enable interrupt for channel2 */ | ||
450 | static inline void channel2_intr_enable(int enable) | ||
451 | { | ||
452 | unsigned long flags; | ||
453 | |||
454 | spin_lock_irqsave(&vpif_lock, flags); | ||
455 | |||
456 | if (enable) { | ||
457 | regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); | ||
458 | regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); | ||
459 | regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN); | ||
460 | regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), | ||
461 | VPIF_INTEN_SET); | ||
462 | } else { | ||
463 | regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN); | ||
464 | regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), | ||
465 | VPIF_INTEN_SET); | ||
466 | } | ||
467 | spin_unlock_irqrestore(&vpif_lock, flags); | ||
468 | } | ||
469 | |||
470 | /* inline function to enable interrupt for channel3 */ | ||
471 | static inline void channel3_intr_enable(int enable) | ||
472 | { | ||
473 | unsigned long flags; | ||
474 | |||
475 | spin_lock_irqsave(&vpif_lock, flags); | ||
476 | |||
477 | if (enable) { | ||
478 | regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); | ||
479 | regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); | ||
480 | |||
481 | regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN); | ||
482 | regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), | ||
483 | VPIF_INTEN_SET); | ||
484 | } else { | ||
485 | regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN); | ||
486 | regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), | ||
487 | VPIF_INTEN_SET); | ||
488 | } | ||
489 | spin_unlock_irqrestore(&vpif_lock, flags); | ||
490 | } | ||
491 | |||
492 | /* inline function to enable raw vbi data for channel2 */ | ||
493 | static inline void channel2_raw_enable(int enable, u8 index) | ||
494 | { | ||
495 | u32 mask; | ||
496 | |||
497 | if (1 == index) | ||
498 | mask = VPIF_CH_VANC_EN_BIT; | ||
499 | else | ||
500 | mask = VPIF_CH_HANC_EN_BIT; | ||
501 | |||
502 | if (enable) | ||
503 | vpif_set_bit(VPIF_CH2_CTRL, mask); | ||
504 | else | ||
505 | vpif_clr_bit(VPIF_CH2_CTRL, mask); | ||
506 | } | ||
507 | |||
508 | /* inline function to enable raw vbi data for channel3*/ | ||
509 | static inline void channel3_raw_enable(int enable, u8 index) | ||
510 | { | ||
511 | u32 mask; | ||
512 | |||
513 | if (1 == index) | ||
514 | mask = VPIF_CH_VANC_EN_BIT; | ||
515 | else | ||
516 | mask = VPIF_CH_HANC_EN_BIT; | ||
517 | |||
518 | if (enable) | ||
519 | vpif_set_bit(VPIF_CH3_CTRL, mask); | ||
520 | else | ||
521 | vpif_clr_bit(VPIF_CH3_CTRL, mask); | ||
522 | } | ||
523 | |||
524 | /* function to enable clipping (for both active and blanking regions) on ch 2 */ | ||
525 | static inline void channel2_clipping_enable(int enable) | ||
526 | { | ||
527 | if (enable) { | ||
528 | vpif_set_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ANC_EN); | ||
529 | vpif_set_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ACTIVE_EN); | ||
530 | } else { | ||
531 | vpif_clr_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ANC_EN); | ||
532 | vpif_clr_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ACTIVE_EN); | ||
533 | } | ||
534 | } | ||
535 | |||
536 | /* function to enable clipping (for both active and blanking regions) on ch 2 */ | ||
537 | static inline void channel3_clipping_enable(int enable) | ||
538 | { | ||
539 | if (enable) { | ||
540 | vpif_set_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ANC_EN); | ||
541 | vpif_set_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ACTIVE_EN); | ||
542 | } else { | ||
543 | vpif_clr_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ANC_EN); | ||
544 | vpif_clr_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ACTIVE_EN); | ||
545 | } | ||
546 | } | ||
547 | |||
548 | /* inline function to set buffer addresses in case of Y/C non mux mode */ | ||
549 | static inline void ch2_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma, | ||
550 | unsigned long btm_strt_luma, | ||
551 | unsigned long top_strt_chroma, | ||
552 | unsigned long btm_strt_chroma) | ||
553 | { | ||
554 | regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA); | ||
555 | regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA); | ||
556 | regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA); | ||
557 | regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA); | ||
558 | } | ||
559 | |||
560 | /* inline function to set buffer addresses in VPIF registers for video data */ | ||
561 | static inline void ch2_set_videobuf_addr(unsigned long top_strt_luma, | ||
562 | unsigned long btm_strt_luma, | ||
563 | unsigned long top_strt_chroma, | ||
564 | unsigned long btm_strt_chroma) | ||
565 | { | ||
566 | regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA); | ||
567 | regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA); | ||
568 | regw(top_strt_chroma, VPIF_CH2_TOP_STRT_ADD_CHROMA); | ||
569 | regw(btm_strt_chroma, VPIF_CH2_BTM_STRT_ADD_CHROMA); | ||
570 | } | ||
571 | |||
572 | static inline void ch3_set_videobuf_addr(unsigned long top_strt_luma, | ||
573 | unsigned long btm_strt_luma, | ||
574 | unsigned long top_strt_chroma, | ||
575 | unsigned long btm_strt_chroma) | ||
576 | { | ||
577 | regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_LUMA); | ||
578 | regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_LUMA); | ||
579 | regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA); | ||
580 | regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA); | ||
581 | } | ||
582 | |||
583 | /* inline function to set buffer addresses in VPIF registers for vbi data */ | ||
584 | static inline void ch2_set_vbi_addr(unsigned long top_strt_luma, | ||
585 | unsigned long btm_strt_luma, | ||
586 | unsigned long top_strt_chroma, | ||
587 | unsigned long btm_strt_chroma) | ||
588 | { | ||
589 | regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_VANC); | ||
590 | regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_VANC); | ||
591 | } | ||
592 | |||
593 | static inline void ch3_set_vbi_addr(unsigned long top_strt_luma, | ||
594 | unsigned long btm_strt_luma, | ||
595 | unsigned long top_strt_chroma, | ||
596 | unsigned long btm_strt_chroma) | ||
597 | { | ||
598 | regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_VANC); | ||
599 | regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_VANC); | ||
600 | } | ||
601 | |||
602 | static inline int vpif_intr_status(int channel) | ||
603 | { | ||
604 | int status = 0; | ||
605 | int mask; | ||
606 | |||
607 | if (channel < 0 || channel > 3) | ||
608 | return 0; | ||
609 | |||
610 | mask = 1 << channel; | ||
611 | status = regr(VPIF_STATUS) & mask; | ||
612 | regw(status, VPIF_STATUS_CLR); | ||
613 | |||
614 | return status; | ||
615 | } | ||
616 | |||
617 | #define VPIF_MAX_NAME (30) | ||
618 | |||
619 | /* This structure will store size parameters as per the mode selected by user */ | ||
620 | struct vpif_channel_config_params { | ||
621 | char name[VPIF_MAX_NAME]; /* Name of the mode */ | ||
622 | u16 width; /* Indicates width of the image */ | ||
623 | u16 height; /* Indicates height of the image */ | ||
624 | u8 frm_fmt; /* Interlaced (0) or progressive (1) */ | ||
625 | u8 ycmux_mode; /* This mode requires one (0) or two (1) | ||
626 | channels */ | ||
627 | u16 eav2sav; /* length of eav 2 sav */ | ||
628 | u16 sav2eav; /* length of sav 2 eav */ | ||
629 | u16 l1, l3, l5, l7, l9, l11; /* Other parameter configurations */ | ||
630 | u16 vsize; /* Vertical size of the image */ | ||
631 | u8 capture_format; /* Indicates whether capture format | ||
632 | * is in BT or in CCD/CMOS */ | ||
633 | u8 vbi_supported; /* Indicates whether this mode | ||
634 | * supports capturing vbi or not */ | ||
635 | u8 hd_sd; /* HDTV (1) or SDTV (0) format */ | ||
636 | v4l2_std_id stdid; /* SDTV format */ | ||
637 | u32 dv_preset; /* HDTV format */ | ||
638 | }; | ||
639 | |||
640 | extern const unsigned int vpif_ch_params_count; | ||
641 | extern const struct vpif_channel_config_params ch_params[]; | ||
642 | |||
643 | struct vpif_video_params; | ||
644 | struct vpif_params; | ||
645 | struct vpif_vbi_params; | ||
646 | |||
647 | int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id); | ||
648 | void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams, | ||
649 | u8 channel_id); | ||
650 | int vpif_channel_getfid(u8 channel_id); | ||
651 | |||
652 | enum data_size { | ||
653 | _8BITS = 0, | ||
654 | _10BITS, | ||
655 | _12BITS, | ||
656 | }; | ||
657 | |||
658 | /* Structure for vpif parameters for raw vbi data */ | ||
659 | struct vpif_vbi_params { | ||
660 | __u32 hstart0; /* Horizontal start of raw vbi data for first field */ | ||
661 | __u32 vstart0; /* Vertical start of raw vbi data for first field */ | ||
662 | __u32 hsize0; /* Horizontal size of raw vbi data for first field */ | ||
663 | __u32 vsize0; /* Vertical size of raw vbi data for first field */ | ||
664 | __u32 hstart1; /* Horizontal start of raw vbi data for second field */ | ||
665 | __u32 vstart1; /* Vertical start of raw vbi data for second field */ | ||
666 | __u32 hsize1; /* Horizontal size of raw vbi data for second field */ | ||
667 | __u32 vsize1; /* Vertical size of raw vbi data for second field */ | ||
668 | }; | ||
669 | |||
670 | /* structure for vpif parameters */ | ||
671 | struct vpif_video_params { | ||
672 | __u8 storage_mode; /* Indicates field or frame mode */ | ||
673 | unsigned long hpitch; | ||
674 | v4l2_std_id stdid; | ||
675 | }; | ||
676 | |||
677 | struct vpif_params { | ||
678 | struct vpif_interface iface; | ||
679 | struct vpif_video_params video_params; | ||
680 | struct vpif_channel_config_params std_info; | ||
681 | union param { | ||
682 | struct vpif_vbi_params vbi_params; | ||
683 | enum data_size data_sz; | ||
684 | } params; | ||
685 | }; | ||
686 | |||
687 | #endif /* End of #ifndef VPIF_H */ | ||
688 | |||