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path: root/drivers/media/video/davinci/vpif.c
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Diffstat (limited to 'drivers/media/video/davinci/vpif.c')
-rw-r--r--drivers/media/video/davinci/vpif.c514
1 files changed, 0 insertions, 514 deletions
diff --git a/drivers/media/video/davinci/vpif.c b/drivers/media/video/davinci/vpif.c
deleted file mode 100644
index 9bd3caa34a3e..000000000000
--- a/drivers/media/video/davinci/vpif.c
+++ /dev/null
@@ -1,514 +0,0 @@
1/*
2 * vpif - Video Port Interface driver
3 * VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
4 * that receiveing video byte stream and two channels(2, 3) for video output.
5 * The hardware supports SDTV, HDTV formats, raw data capture.
6 * Currently, the driver supports NTSC and PAL standards.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation version 2.
13 *
14 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
15 * kind, whether express or implied; without even the implied warranty
16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/spinlock.h>
24#include <linux/kernel.h>
25#include <linux/io.h>
26#include <linux/clk.h>
27#include <linux/err.h>
28#include <mach/hardware.h>
29
30#include "vpif.h"
31
32MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
33MODULE_LICENSE("GPL");
34
35#define VPIF_CH0_MAX_MODES (22)
36#define VPIF_CH1_MAX_MODES (02)
37#define VPIF_CH2_MAX_MODES (15)
38#define VPIF_CH3_MAX_MODES (02)
39
40static resource_size_t res_len;
41static struct resource *res;
42spinlock_t vpif_lock;
43
44void __iomem *vpif_base;
45struct clk *vpif_clk;
46
47/**
48 * ch_params: video standard configuration parameters for vpif
49 * The table must include all presets from supported subdevices.
50 */
51const struct vpif_channel_config_params ch_params[] = {
52 /* HDTV formats */
53 {
54 .name = "480p59_94",
55 .width = 720,
56 .height = 480,
57 .frm_fmt = 1,
58 .ycmux_mode = 0,
59 .eav2sav = 138-8,
60 .sav2eav = 720,
61 .l1 = 1,
62 .l3 = 43,
63 .l5 = 523,
64 .vsize = 525,
65 .capture_format = 0,
66 .vbi_supported = 0,
67 .hd_sd = 1,
68 .dv_preset = V4L2_DV_480P59_94,
69 },
70 {
71 .name = "576p50",
72 .width = 720,
73 .height = 576,
74 .frm_fmt = 1,
75 .ycmux_mode = 0,
76 .eav2sav = 144-8,
77 .sav2eav = 720,
78 .l1 = 1,
79 .l3 = 45,
80 .l5 = 621,
81 .vsize = 625,
82 .capture_format = 0,
83 .vbi_supported = 0,
84 .hd_sd = 1,
85 .dv_preset = V4L2_DV_576P50,
86 },
87 {
88 .name = "720p50",
89 .width = 1280,
90 .height = 720,
91 .frm_fmt = 1,
92 .ycmux_mode = 0,
93 .eav2sav = 700-8,
94 .sav2eav = 1280,
95 .l1 = 1,
96 .l3 = 26,
97 .l5 = 746,
98 .vsize = 750,
99 .capture_format = 0,
100 .vbi_supported = 0,
101 .hd_sd = 1,
102 .dv_preset = V4L2_DV_720P50,
103 },
104 {
105 .name = "720p60",
106 .width = 1280,
107 .height = 720,
108 .frm_fmt = 1,
109 .ycmux_mode = 0,
110 .eav2sav = 370 - 8,
111 .sav2eav = 1280,
112 .l1 = 1,
113 .l3 = 26,
114 .l5 = 746,
115 .vsize = 750,
116 .capture_format = 0,
117 .vbi_supported = 0,
118 .hd_sd = 1,
119 .dv_preset = V4L2_DV_720P60,
120 },
121 {
122 .name = "1080I50",
123 .width = 1920,
124 .height = 1080,
125 .frm_fmt = 0,
126 .ycmux_mode = 0,
127 .eav2sav = 720 - 8,
128 .sav2eav = 1920,
129 .l1 = 1,
130 .l3 = 21,
131 .l5 = 561,
132 .l7 = 563,
133 .l9 = 584,
134 .l11 = 1124,
135 .vsize = 1125,
136 .capture_format = 0,
137 .vbi_supported = 0,
138 .hd_sd = 1,
139 .dv_preset = V4L2_DV_1080I50,
140 },
141 {
142 .name = "1080I60",
143 .width = 1920,
144 .height = 1080,
145 .frm_fmt = 0,
146 .ycmux_mode = 0,
147 .eav2sav = 280 - 8,
148 .sav2eav = 1920,
149 .l1 = 1,
150 .l3 = 21,
151 .l5 = 561,
152 .l7 = 563,
153 .l9 = 584,
154 .l11 = 1124,
155 .vsize = 1125,
156 .capture_format = 0,
157 .vbi_supported = 0,
158 .hd_sd = 1,
159 .dv_preset = V4L2_DV_1080I60,
160 },
161 {
162 .name = "1080p60",
163 .width = 1920,
164 .height = 1080,
165 .frm_fmt = 1,
166 .ycmux_mode = 0,
167 .eav2sav = 280 - 8,
168 .sav2eav = 1920,
169 .l1 = 1,
170 .l3 = 42,
171 .l5 = 1122,
172 .vsize = 1125,
173 .capture_format = 0,
174 .vbi_supported = 0,
175 .hd_sd = 1,
176 .dv_preset = V4L2_DV_1080P60,
177 },
178
179 /* SDTV formats */
180 {
181 .name = "NTSC_M",
182 .width = 720,
183 .height = 480,
184 .frm_fmt = 0,
185 .ycmux_mode = 1,
186 .eav2sav = 268,
187 .sav2eav = 1440,
188 .l1 = 1,
189 .l3 = 23,
190 .l5 = 263,
191 .l7 = 266,
192 .l9 = 286,
193 .l11 = 525,
194 .vsize = 525,
195 .capture_format = 0,
196 .vbi_supported = 1,
197 .hd_sd = 0,
198 .stdid = V4L2_STD_525_60,
199 },
200 {
201 .name = "PAL_BDGHIK",
202 .width = 720,
203 .height = 576,
204 .frm_fmt = 0,
205 .ycmux_mode = 1,
206 .eav2sav = 280,
207 .sav2eav = 1440,
208 .l1 = 1,
209 .l3 = 23,
210 .l5 = 311,
211 .l7 = 313,
212 .l9 = 336,
213 .l11 = 624,
214 .vsize = 625,
215 .capture_format = 0,
216 .vbi_supported = 1,
217 .hd_sd = 0,
218 .stdid = V4L2_STD_625_50,
219 },
220};
221
222const unsigned int vpif_ch_params_count = ARRAY_SIZE(ch_params);
223
224static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
225{
226 if (val)
227 vpif_set_bit(reg, bit);
228 else
229 vpif_clr_bit(reg, bit);
230}
231
232/* This structure is used to keep track of VPIF size register's offsets */
233struct vpif_registers {
234 u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
235 u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
236 u32 vanc1_size, width_mask, len_mask;
237 u8 max_modes;
238};
239
240static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
241 /* Channel0 */
242 {
243 VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
244 VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
245 VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
246 VPIF_CH0_MAX_MODES,
247 },
248 /* Channel1 */
249 {
250 VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
251 VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
252 VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
253 VPIF_CH1_MAX_MODES,
254 },
255 /* Channel2 */
256 {
257 VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
258 VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
259 VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
260 VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
261 VPIF_CH2_MAX_MODES
262 },
263 /* Channel3 */
264 {
265 VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
266 VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
267 VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
268 VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
269 VPIF_CH3_MAX_MODES
270 },
271};
272
273/* vpif_set_mode_info:
274 * This function is used to set horizontal and vertical config parameters
275 * As per the standard in the channel, configure the values of L1, L3,
276 * L5, L7 L9, L11 in VPIF Register , also write width and height
277 */
278static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
279 u8 channel_id, u8 config_channel_id)
280{
281 u32 value;
282
283 value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
284 value <<= VPIF_CH_LEN_SHIFT;
285 value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
286 regw(value, vpifregs[channel_id].h_cfg);
287
288 value = (config->l1 & vpifregs[config_channel_id].len_mask);
289 value <<= VPIF_CH_LEN_SHIFT;
290 value |= (config->l3 & vpifregs[config_channel_id].len_mask);
291 regw(value, vpifregs[channel_id].v_cfg_00);
292
293 value = (config->l5 & vpifregs[config_channel_id].len_mask);
294 value <<= VPIF_CH_LEN_SHIFT;
295 value |= (config->l7 & vpifregs[config_channel_id].len_mask);
296 regw(value, vpifregs[channel_id].v_cfg_01);
297
298 value = (config->l9 & vpifregs[config_channel_id].len_mask);
299 value <<= VPIF_CH_LEN_SHIFT;
300 value |= (config->l11 & vpifregs[config_channel_id].len_mask);
301 regw(value, vpifregs[channel_id].v_cfg_02);
302
303 value = (config->vsize & vpifregs[config_channel_id].len_mask);
304 regw(value, vpifregs[channel_id].v_cfg);
305}
306
307/* config_vpif_params
308 * Function to set the parameters of a channel
309 * Mainly modifies the channel ciontrol register
310 * It sets frame format, yc mux mode
311 */
312static void config_vpif_params(struct vpif_params *vpifparams,
313 u8 channel_id, u8 found)
314{
315 const struct vpif_channel_config_params *config = &vpifparams->std_info;
316 u32 value, ch_nip, reg;
317 u8 start, end;
318 int i;
319
320 start = channel_id;
321 end = channel_id + found;
322
323 for (i = start; i < end; i++) {
324 reg = vpifregs[i].ch_ctrl;
325 if (channel_id < 2)
326 ch_nip = VPIF_CAPTURE_CH_NIP;
327 else
328 ch_nip = VPIF_DISPLAY_CH_NIP;
329
330 vpif_wr_bit(reg, ch_nip, config->frm_fmt);
331 vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
332 vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
333 vpifparams->video_params.storage_mode);
334
335 /* Set raster scanning SDR Format */
336 vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
337 vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
338
339 if (channel_id > 1) /* Set the Pixel enable bit */
340 vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
341 else if (config->capture_format) {
342 /* Set the polarity of various pins */
343 vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
344 vpifparams->iface.fid_pol);
345 vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
346 vpifparams->iface.vd_pol);
347 vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
348 vpifparams->iface.hd_pol);
349
350 value = regr(reg);
351 /* Set data width */
352 value &= ~(0x3u <<
353 VPIF_CH_DATA_WIDTH_BIT);
354 value |= ((vpifparams->params.data_sz) <<
355 VPIF_CH_DATA_WIDTH_BIT);
356 regw(value, reg);
357 }
358
359 /* Write the pitch in the driver */
360 regw((vpifparams->video_params.hpitch),
361 vpifregs[i].line_offset);
362 }
363}
364
365/* vpif_set_video_params
366 * This function is used to set video parameters in VPIF register
367 */
368int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
369{
370 const struct vpif_channel_config_params *config = &vpifparams->std_info;
371 int found = 1;
372
373 vpif_set_mode_info(config, channel_id, channel_id);
374 if (!config->ycmux_mode) {
375 /* YC are on separate channels (HDTV formats) */
376 vpif_set_mode_info(config, channel_id + 1, channel_id);
377 found = 2;
378 }
379
380 config_vpif_params(vpifparams, channel_id, found);
381
382 regw(0x80, VPIF_REQ_SIZE);
383 regw(0x01, VPIF_EMULATION_CTRL);
384
385 return found;
386}
387EXPORT_SYMBOL(vpif_set_video_params);
388
389void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
390 u8 channel_id)
391{
392 u32 value;
393
394 value = 0x3F8 & (vbiparams->hstart0);
395 value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
396 regw(value, vpifregs[channel_id].vanc0_strt);
397
398 value = 0x3F8 & (vbiparams->hstart1);
399 value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
400 regw(value, vpifregs[channel_id].vanc1_strt);
401
402 value = 0x3F8 & (vbiparams->hsize0);
403 value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
404 regw(value, vpifregs[channel_id].vanc0_size);
405
406 value = 0x3F8 & (vbiparams->hsize1);
407 value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
408 regw(value, vpifregs[channel_id].vanc1_size);
409
410}
411EXPORT_SYMBOL(vpif_set_vbi_display_params);
412
413int vpif_channel_getfid(u8 channel_id)
414{
415 return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
416 >> VPIF_CH_FID_SHIFT;
417}
418EXPORT_SYMBOL(vpif_channel_getfid);
419
420static int __devinit vpif_probe(struct platform_device *pdev)
421{
422 int status = 0;
423
424 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
425 if (!res)
426 return -ENOENT;
427
428 res_len = resource_size(res);
429
430 res = request_mem_region(res->start, res_len, res->name);
431 if (!res)
432 return -EBUSY;
433
434 vpif_base = ioremap(res->start, res_len);
435 if (!vpif_base) {
436 status = -EBUSY;
437 goto fail;
438 }
439
440 vpif_clk = clk_get(&pdev->dev, "vpif");
441 if (IS_ERR(vpif_clk)) {
442 status = PTR_ERR(vpif_clk);
443 goto clk_fail;
444 }
445 clk_enable(vpif_clk);
446
447 spin_lock_init(&vpif_lock);
448 dev_info(&pdev->dev, "vpif probe success\n");
449 return 0;
450
451clk_fail:
452 iounmap(vpif_base);
453fail:
454 release_mem_region(res->start, res_len);
455 return status;
456}
457
458static int __devexit vpif_remove(struct platform_device *pdev)
459{
460 if (vpif_clk) {
461 clk_disable(vpif_clk);
462 clk_put(vpif_clk);
463 }
464
465 iounmap(vpif_base);
466 release_mem_region(res->start, res_len);
467 return 0;
468}
469
470#ifdef CONFIG_PM
471static int vpif_suspend(struct device *dev)
472{
473 clk_disable(vpif_clk);
474 return 0;
475}
476
477static int vpif_resume(struct device *dev)
478{
479 clk_enable(vpif_clk);
480 return 0;
481}
482
483static const struct dev_pm_ops vpif_pm = {
484 .suspend = vpif_suspend,
485 .resume = vpif_resume,
486};
487
488#define vpif_pm_ops (&vpif_pm)
489#else
490#define vpif_pm_ops NULL
491#endif
492
493static struct platform_driver vpif_driver = {
494 .driver = {
495 .name = "vpif",
496 .owner = THIS_MODULE,
497 .pm = vpif_pm_ops,
498 },
499 .remove = __devexit_p(vpif_remove),
500 .probe = vpif_probe,
501};
502
503static void vpif_exit(void)
504{
505 platform_driver_unregister(&vpif_driver);
506}
507
508static int __init vpif_init(void)
509{
510 return platform_driver_register(&vpif_driver);
511}
512subsys_initcall(vpif_init);
513module_exit(vpif_exit);
514
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