diff options
Diffstat (limited to 'drivers/media/video/cx88/cx88-core.c')
-rw-r--r-- | drivers/media/video/cx88/cx88-core.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/drivers/media/video/cx88/cx88-core.c b/drivers/media/video/cx88/cx88-core.c index d4d39c1751af..f01a631d0c00 100644 --- a/drivers/media/video/cx88/cx88-core.c +++ b/drivers/media/video/cx88/cx88-core.c | |||
@@ -153,26 +153,26 @@ static u32* cx88_risc_field(u32 *rp, struct scatterlist *sglist, | |||
153 | } | 153 | } |
154 | if (bpl <= sg_dma_len(sg)-offset) { | 154 | if (bpl <= sg_dma_len(sg)-offset) { |
155 | /* fits into current chunk */ | 155 | /* fits into current chunk */ |
156 | *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl); | 156 | *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl); |
157 | *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); | 157 | *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); |
158 | offset+=bpl; | 158 | offset+=bpl; |
159 | } else { | 159 | } else { |
160 | /* scanline needs to be splitted */ | 160 | /* scanline needs to be splitted */ |
161 | todo = bpl; | 161 | todo = bpl; |
162 | *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL| | 162 | *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL| |
163 | (sg_dma_len(sg)-offset)); | 163 | (sg_dma_len(sg)-offset)); |
164 | *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); | 164 | *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); |
165 | todo -= (sg_dma_len(sg)-offset); | 165 | todo -= (sg_dma_len(sg)-offset); |
166 | offset = 0; | 166 | offset = 0; |
167 | sg++; | 167 | sg++; |
168 | while (todo > sg_dma_len(sg)) { | 168 | while (todo > sg_dma_len(sg)) { |
169 | *(rp++)=cpu_to_le32(RISC_WRITE| | 169 | *(rp++)=cpu_to_le32(RISC_WRITE| |
170 | sg_dma_len(sg)); | 170 | sg_dma_len(sg)); |
171 | *(rp++)=cpu_to_le32(sg_dma_address(sg)); | 171 | *(rp++)=cpu_to_le32(sg_dma_address(sg)); |
172 | todo -= sg_dma_len(sg); | 172 | todo -= sg_dma_len(sg); |
173 | sg++; | 173 | sg++; |
174 | } | 174 | } |
175 | *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo); | 175 | *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo); |
176 | *(rp++)=cpu_to_le32(sg_dma_address(sg)); | 176 | *(rp++)=cpu_to_le32(sg_dma_address(sg)); |
177 | offset += todo; | 177 | offset += todo; |
178 | } | 178 | } |
@@ -309,7 +309,7 @@ struct sram_channel cx88_sram_channels[] = { | |||
309 | .name = "video y / packed", | 309 | .name = "video y / packed", |
310 | .cmds_start = 0x180040, | 310 | .cmds_start = 0x180040, |
311 | .ctrl_start = 0x180400, | 311 | .ctrl_start = 0x180400, |
312 | .cdt = 0x180400 + 64, | 312 | .cdt = 0x180400 + 64, |
313 | .fifo_start = 0x180c00, | 313 | .fifo_start = 0x180c00, |
314 | .fifo_size = 0x002800, | 314 | .fifo_size = 0x002800, |
315 | .ptr1_reg = MO_DMA21_PTR1, | 315 | .ptr1_reg = MO_DMA21_PTR1, |
@@ -321,7 +321,7 @@ struct sram_channel cx88_sram_channels[] = { | |||
321 | .name = "video u", | 321 | .name = "video u", |
322 | .cmds_start = 0x180080, | 322 | .cmds_start = 0x180080, |
323 | .ctrl_start = 0x1804a0, | 323 | .ctrl_start = 0x1804a0, |
324 | .cdt = 0x1804a0 + 64, | 324 | .cdt = 0x1804a0 + 64, |
325 | .fifo_start = 0x183400, | 325 | .fifo_start = 0x183400, |
326 | .fifo_size = 0x000800, | 326 | .fifo_size = 0x000800, |
327 | .ptr1_reg = MO_DMA22_PTR1, | 327 | .ptr1_reg = MO_DMA22_PTR1, |
@@ -333,7 +333,7 @@ struct sram_channel cx88_sram_channels[] = { | |||
333 | .name = "video v", | 333 | .name = "video v", |
334 | .cmds_start = 0x1800c0, | 334 | .cmds_start = 0x1800c0, |
335 | .ctrl_start = 0x180540, | 335 | .ctrl_start = 0x180540, |
336 | .cdt = 0x180540 + 64, | 336 | .cdt = 0x180540 + 64, |
337 | .fifo_start = 0x183c00, | 337 | .fifo_start = 0x183c00, |
338 | .fifo_size = 0x000800, | 338 | .fifo_size = 0x000800, |
339 | .ptr1_reg = MO_DMA23_PTR1, | 339 | .ptr1_reg = MO_DMA23_PTR1, |
@@ -345,7 +345,7 @@ struct sram_channel cx88_sram_channels[] = { | |||
345 | .name = "vbi", | 345 | .name = "vbi", |
346 | .cmds_start = 0x180100, | 346 | .cmds_start = 0x180100, |
347 | .ctrl_start = 0x1805e0, | 347 | .ctrl_start = 0x1805e0, |
348 | .cdt = 0x1805e0 + 64, | 348 | .cdt = 0x1805e0 + 64, |
349 | .fifo_start = 0x184400, | 349 | .fifo_start = 0x184400, |
350 | .fifo_size = 0x001000, | 350 | .fifo_size = 0x001000, |
351 | .ptr1_reg = MO_DMA24_PTR1, | 351 | .ptr1_reg = MO_DMA24_PTR1, |
@@ -357,7 +357,7 @@ struct sram_channel cx88_sram_channels[] = { | |||
357 | .name = "audio from", | 357 | .name = "audio from", |
358 | .cmds_start = 0x180140, | 358 | .cmds_start = 0x180140, |
359 | .ctrl_start = 0x180680, | 359 | .ctrl_start = 0x180680, |
360 | .cdt = 0x180680 + 64, | 360 | .cdt = 0x180680 + 64, |
361 | .fifo_start = 0x185400, | 361 | .fifo_start = 0x185400, |
362 | .fifo_size = 0x000200, | 362 | .fifo_size = 0x000200, |
363 | .ptr1_reg = MO_DMA25_PTR1, | 363 | .ptr1_reg = MO_DMA25_PTR1, |
@@ -369,7 +369,7 @@ struct sram_channel cx88_sram_channels[] = { | |||
369 | .name = "audio to", | 369 | .name = "audio to", |
370 | .cmds_start = 0x180180, | 370 | .cmds_start = 0x180180, |
371 | .ctrl_start = 0x180720, | 371 | .ctrl_start = 0x180720, |
372 | .cdt = 0x180680 + 64, /* same as audio IN */ | 372 | .cdt = 0x180680 + 64, /* same as audio IN */ |
373 | .fifo_start = 0x185400, /* same as audio IN */ | 373 | .fifo_start = 0x185400, /* same as audio IN */ |
374 | .fifo_size = 0x000200, /* same as audio IN */ | 374 | .fifo_size = 0x000200, /* same as audio IN */ |
375 | .ptr1_reg = MO_DMA26_PTR1, | 375 | .ptr1_reg = MO_DMA26_PTR1, |
@@ -1137,7 +1137,7 @@ struct cx88_core* cx88_core_get(struct pci_dev *pci) | |||
1137 | if (!core->radio_addr) | 1137 | if (!core->radio_addr) |
1138 | core->radio_addr = cx88_boards[core->board].radio_addr; | 1138 | core->radio_addr = cx88_boards[core->board].radio_addr; |
1139 | 1139 | ||
1140 | printk(KERN_INFO "TV tuner %d at 0x%02x, Radio tuner %d at 0x%02x\n", | 1140 | printk(KERN_INFO "TV tuner %d at 0x%02x, Radio tuner %d at 0x%02x\n", |
1141 | core->tuner_type, core->tuner_addr<<1, | 1141 | core->tuner_type, core->tuner_addr<<1, |
1142 | core->radio_type, core->radio_addr<<1); | 1142 | core->radio_type, core->radio_addr<<1); |
1143 | 1143 | ||