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path: root/drivers/media/video/cx23885/cx23885-core.c
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Diffstat (limited to 'drivers/media/video/cx23885/cx23885-core.c')
-rw-r--r--drivers/media/video/cx23885/cx23885-core.c147
1 files changed, 139 insertions, 8 deletions
diff --git a/drivers/media/video/cx23885/cx23885-core.c b/drivers/media/video/cx23885/cx23885-core.c
index d17343ea0d33..6286a9cf957e 100644
--- a/drivers/media/video/cx23885/cx23885-core.c
+++ b/drivers/media/video/cx23885/cx23885-core.c
@@ -76,6 +76,117 @@ LIST_HEAD(cx23885_devlist);
76 * 0x00010ea0 0x00010xxx Free 76 * 0x00010ea0 0x00010xxx Free
77 */ 77 */
78 78
79static struct sram_channel cx23885_sram_channels[] = {
80 [SRAM_CH01] = {
81 .name = "VID A",
82 .cmds_start = 0x10000,
83 .ctrl_start = 0x10380,
84 .cdt = 0x104c0,
85 .fifo_start = 0x40,
86 .fifo_size = 0x2800,
87 .ptr1_reg = DMA1_PTR1,
88 .ptr2_reg = DMA1_PTR2,
89 .cnt1_reg = DMA1_CNT1,
90 .cnt2_reg = DMA1_CNT2,
91 },
92 [SRAM_CH02] = {
93 .name = "ch2",
94 .cmds_start = 0x0,
95 .ctrl_start = 0x0,
96 .cdt = 0x0,
97 .fifo_start = 0x0,
98 .fifo_size = 0x0,
99 .ptr1_reg = DMA2_PTR1,
100 .ptr2_reg = DMA2_PTR2,
101 .cnt1_reg = DMA2_CNT1,
102 .cnt2_reg = DMA2_CNT2,
103 },
104 [SRAM_CH03] = {
105 .name = "TS1 B",
106 .cmds_start = 0x100A0,
107 .ctrl_start = 0x10400,
108 .cdt = 0x10580,
109 .fifo_start = 0x5000,
110 .fifo_size = 0x1000,
111 .ptr1_reg = DMA3_PTR1,
112 .ptr2_reg = DMA3_PTR2,
113 .cnt1_reg = DMA3_CNT1,
114 .cnt2_reg = DMA3_CNT2,
115 },
116 [SRAM_CH04] = {
117 .name = "ch4",
118 .cmds_start = 0x0,
119 .ctrl_start = 0x0,
120 .cdt = 0x0,
121 .fifo_start = 0x0,
122 .fifo_size = 0x0,
123 .ptr1_reg = DMA4_PTR1,
124 .ptr2_reg = DMA4_PTR2,
125 .cnt1_reg = DMA4_CNT1,
126 .cnt2_reg = DMA4_CNT2,
127 },
128 [SRAM_CH05] = {
129 .name = "ch5",
130 .cmds_start = 0x0,
131 .ctrl_start = 0x0,
132 .cdt = 0x0,
133 .fifo_start = 0x0,
134 .fifo_size = 0x0,
135 .ptr1_reg = DMA5_PTR1,
136 .ptr2_reg = DMA5_PTR2,
137 .cnt1_reg = DMA5_CNT1,
138 .cnt2_reg = DMA5_CNT2,
139 },
140 [SRAM_CH06] = {
141 .name = "TS2 C",
142 .cmds_start = 0x10140,
143 .ctrl_start = 0x10440,
144 .cdt = 0x105e0,
145 .fifo_start = 0x6000,
146 .fifo_size = 0x1000,
147 .ptr1_reg = DMA5_PTR1,
148 .ptr2_reg = DMA5_PTR2,
149 .cnt1_reg = DMA5_CNT1,
150 .cnt2_reg = DMA5_CNT2,
151 },
152 [SRAM_CH07] = {
153 .name = "ch7",
154 .cmds_start = 0x0,
155 .ctrl_start = 0x0,
156 .cdt = 0x0,
157 .fifo_start = 0x0,
158 .fifo_size = 0x0,
159 .ptr1_reg = DMA6_PTR1,
160 .ptr2_reg = DMA6_PTR2,
161 .cnt1_reg = DMA6_CNT1,
162 .cnt2_reg = DMA6_CNT2,
163 },
164 [SRAM_CH08] = {
165 .name = "ch8",
166 .cmds_start = 0x0,
167 .ctrl_start = 0x0,
168 .cdt = 0x0,
169 .fifo_start = 0x0,
170 .fifo_size = 0x0,
171 .ptr1_reg = DMA7_PTR1,
172 .ptr2_reg = DMA7_PTR2,
173 .cnt1_reg = DMA7_CNT1,
174 .cnt2_reg = DMA7_CNT2,
175 },
176 [SRAM_CH09] = {
177 .name = "ch9",
178 .cmds_start = 0x0,
179 .ctrl_start = 0x0,
180 .cdt = 0x0,
181 .fifo_start = 0x0,
182 .fifo_size = 0x0,
183 .ptr1_reg = DMA8_PTR1,
184 .ptr2_reg = DMA8_PTR2,
185 .cnt1_reg = DMA8_CNT1,
186 .cnt2_reg = DMA8_CNT2,
187 },
188};
189
79static struct sram_channel cx23887_sram_channels[] = { 190static struct sram_channel cx23887_sram_channels[] = {
80 [SRAM_CH01] = { 191 [SRAM_CH01] = {
81 .name = "VID A", 192 .name = "VID A",
@@ -104,8 +215,8 @@ static struct sram_channel cx23887_sram_channels[] = {
104 [SRAM_CH03] = { 215 [SRAM_CH03] = {
105 .name = "TS1 B", 216 .name = "TS1 B",
106 .cmds_start = 0x100A0, 217 .cmds_start = 0x100A0,
107 .ctrl_start = 0x10780, 218 .ctrl_start = 0x10630,
108 .cdt = 0x10400, 219 .cdt = 0x10870,
109 .fifo_start = 0x5000, 220 .fifo_start = 0x5000,
110 .fifo_size = 0x1000, 221 .fifo_size = 0x1000,
111 .ptr1_reg = DMA3_PTR1, 222 .ptr1_reg = DMA3_PTR1,
@@ -140,7 +251,7 @@ static struct sram_channel cx23887_sram_channels[] = {
140 [SRAM_CH06] = { 251 [SRAM_CH06] = {
141 .name = "TS2 C", 252 .name = "TS2 C",
142 .cmds_start = 0x10140, 253 .cmds_start = 0x10140,
143 .ctrl_start = 0x10680, 254 .ctrl_start = 0x10670,
144 .cdt = 0x108d0, 255 .cdt = 0x108d0,
145 .fifo_start = 0x6000, 256 .fifo_start = 0x6000,
146 .fifo_size = 0x1000, 257 .fifo_size = 0x1000,
@@ -460,6 +571,7 @@ static void cx23885_reset(struct cx23885_dev *dev)
460 cx_write(AUDIO_INT_INT_STAT, 0xffffffff); 571 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
461 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff); 572 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
462 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000); 573 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
574 cx_write(PAD_CTRL, 0x00500300);
463 575
464 mdelay(100); 576 mdelay(100);
465 577
@@ -625,7 +737,6 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
625 atomic_inc(&dev->refcount); 737 atomic_inc(&dev->refcount);
626 738
627 dev->nr = cx23885_devcount++; 739 dev->nr = cx23885_devcount++;
628 dev->sram_channels = cx23887_sram_channels;
629 sprintf(dev->name, "cx23885[%d]", dev->nr); 740 sprintf(dev->name, "cx23885[%d]", dev->nr);
630 741
631 mutex_lock(&devlist); 742 mutex_lock(&devlist);
@@ -637,11 +748,13 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
637 dev->bridge = CX23885_BRIDGE_887; 748 dev->bridge = CX23885_BRIDGE_887;
638 /* Apply a sensible clock frequency for the PCIe bridge */ 749 /* Apply a sensible clock frequency for the PCIe bridge */
639 dev->clk_freq = 25000000; 750 dev->clk_freq = 25000000;
751 dev->sram_channels = cx23887_sram_channels;
640 } else 752 } else
641 if(dev->pci->device == 0x8852) { 753 if(dev->pci->device == 0x8852) {
642 dev->bridge = CX23885_BRIDGE_885; 754 dev->bridge = CX23885_BRIDGE_885;
643 /* Apply a sensible clock frequency for the PCIe bridge */ 755 /* Apply a sensible clock frequency for the PCIe bridge */
644 dev->clk_freq = 28000000; 756 dev->clk_freq = 28000000;
757 dev->sram_channels = cx23885_sram_channels;
645 } else 758 } else
646 BUG(); 759 BUG();
647 760
@@ -1010,8 +1123,9 @@ static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1010 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl)); 1123 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1011 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__, 1124 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
1012 port->reg_dma_ctl, cx_read(port->reg_dma_ctl)); 1125 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1013 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__, 1126 if (port->reg_src_sel)
1014 port->reg_src_sel, cx_read(port->reg_src_sel)); 1127 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
1128 port->reg_src_sel, cx_read(port->reg_src_sel));
1015 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__, 1129 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
1016 port->reg_lngth, cx_read(port->reg_lngth)); 1130 port->reg_lngth, cx_read(port->reg_lngth));
1017 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__, 1131 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
@@ -1042,6 +1156,9 @@ static int cx23885_start_dma(struct cx23885_tsport *port,
1042 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__, 1156 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1043 buf->vb.width, buf->vb.height, buf->vb.field); 1157 buf->vb.width, buf->vb.height, buf->vb.field);
1044 1158
1159 /* Stop the fifo and risc engine for this port */
1160 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1161
1045 /* setup fifo + format */ 1162 /* setup fifo + format */
1046 cx23885_sram_channel_setup(dev, 1163 cx23885_sram_channel_setup(dev,
1047 &dev->sram_channels[ port->sram_chno ], 1164 &dev->sram_channels[ port->sram_chno ],
@@ -1083,7 +1200,21 @@ static int cx23885_start_dma(struct cx23885_tsport *port,
1083 cx_write(port->reg_gpcnt_ctl, 3); 1200 cx_write(port->reg_gpcnt_ctl, 3);
1084 q->count = 1; 1201 q->count = 1;
1085 1202
1086 if (cx23885_boards[dev->board].portb & CX23885_MPEG_ENCODER) { 1203 /* Set VIDB pins to input */
1204 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1205 reg = cx_read(PAD_CTRL);
1206 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1207 cx_write(PAD_CTRL, reg);
1208 }
1209
1210 /* Set VIDC pins to input */
1211 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1212 reg = cx_read(PAD_CTRL);
1213 reg &= ~0x4; /* Clear TS2_SOP_OE */
1214 cx_write(PAD_CTRL, reg);
1215 }
1216
1217 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1087 1218
1088 reg = cx_read(PAD_CTRL); 1219 reg = cx_read(PAD_CTRL);
1089 reg = reg & ~0x1; /* Clear TS1_OE */ 1220 reg = reg & ~0x1; /* Clear TS1_OE */
@@ -1133,7 +1264,7 @@ static int cx23885_stop_dma(struct cx23885_tsport *port)
1133 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val); 1264 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1134 cx_clear(port->reg_dma_ctl, port->dma_ctl_val); 1265 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1135 1266
1136 if (cx23885_boards[dev->board].portb & CX23885_MPEG_ENCODER) { 1267 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1137 1268
1138 reg = cx_read(PAD_CTRL); 1269 reg = cx_read(PAD_CTRL);
1139 1270
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-25 22:40:57 -0400