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-rw-r--r--drivers/media/video/cx18/cx18-driver.c17
-rw-r--r--drivers/media/video/cx18/cx18-driver.h20
-rw-r--r--drivers/media/video/cx18/cx18-dvb.c23
-rw-r--r--drivers/media/video/cx18/cx18-dvb.h1
-rw-r--r--drivers/media/video/cx18/cx18-io.c17
-rw-r--r--drivers/media/video/cx18/cx18-io.h17
-rw-r--r--drivers/media/video/cx18/cx18-irq.c96
-rw-r--r--drivers/media/video/cx18/cx18-irq.h4
-rw-r--r--drivers/media/video/cx18/cx18-mailbox.c6
-rw-r--r--drivers/media/video/cx18/cx18-queue.c14
-rw-r--r--drivers/media/video/cx18/cx18-scb.h40
11 files changed, 169 insertions, 86 deletions
diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c
index 7a1a7830a6b3..7874d9790a51 100644
--- a/drivers/media/video/cx18/cx18-driver.c
+++ b/drivers/media/video/cx18/cx18-driver.c
@@ -448,7 +448,14 @@ static int __devinit cx18_init_struct1(struct cx18 *cx)
448 mutex_init(&cx->gpio_lock); 448 mutex_init(&cx->gpio_lock);
449 449
450 spin_lock_init(&cx->lock); 450 spin_lock_init(&cx->lock);
451 spin_lock_init(&cx->dma_reg_lock); 451
452 cx->work_queue = create_singlethread_workqueue(cx->name);
453 if (cx->work_queue == NULL) {
454 CX18_ERR("Could not create work queue\n");
455 return -1;
456 }
457
458 INIT_WORK(&cx->work, cx18_work_handler);
452 459
453 /* start counting open_id at 1 */ 460 /* start counting open_id at 1 */
454 cx->open_id = 1; 461 cx->open_id = 1;
@@ -581,10 +588,10 @@ static void cx18_load_and_init_modules(struct cx18 *cx)
581 588
582#ifdef MODULE 589#ifdef MODULE
583 /* load modules */ 590 /* load modules */
584#ifndef CONFIG_MEDIA_TUNER 591#ifdef CONFIG_MEDIA_TUNER_MODULE
585 hw = cx18_request_module(cx, hw, "tuner", CX18_HW_TUNER); 592 hw = cx18_request_module(cx, hw, "tuner", CX18_HW_TUNER);
586#endif 593#endif
587#ifndef CONFIG_VIDEO_CS5345 594#ifdef CONFIG_VIDEO_CS5345_MODULE
588 hw = cx18_request_module(cx, hw, "cs5345", CX18_HW_CS5345); 595 hw = cx18_request_module(cx, hw, "cs5345", CX18_HW_CS5345);
589#endif 596#endif
590#endif 597#endif
@@ -832,6 +839,7 @@ free_map:
832free_mem: 839free_mem:
833 release_mem_region(cx->base_addr, CX18_MEM_SIZE); 840 release_mem_region(cx->base_addr, CX18_MEM_SIZE);
834free_workqueue: 841free_workqueue:
842 destroy_workqueue(cx->work_queue);
835err: 843err:
836 if (retval == 0) 844 if (retval == 0)
837 retval = -ENODEV; 845 retval = -ENODEV;
@@ -932,6 +940,9 @@ static void cx18_remove(struct pci_dev *pci_dev)
932 940
933 cx18_halt_firmware(cx); 941 cx18_halt_firmware(cx);
934 942
943 flush_workqueue(cx->work_queue);
944 destroy_workqueue(cx->work_queue);
945
935 cx18_streams_cleanup(cx, 1); 946 cx18_streams_cleanup(cx, 1);
936 947
937 exit_cx18_i2c(cx); 948 exit_cx18_i2c(cx);
diff --git a/drivers/media/video/cx18/cx18-driver.h b/drivers/media/video/cx18/cx18-driver.h
index a4b1708fafe7..bbdd5f25041d 100644
--- a/drivers/media/video/cx18/cx18-driver.h
+++ b/drivers/media/video/cx18/cx18-driver.h
@@ -199,12 +199,15 @@ struct cx18_options {
199#define CX18_F_S_APPL_IO 8 /* this stream is used read/written by an application */ 199#define CX18_F_S_APPL_IO 8 /* this stream is used read/written by an application */
200 200
201/* per-cx18, i_flags */ 201/* per-cx18, i_flags */
202#define CX18_F_I_LOADED_FW 0 /* Loaded the firmware the first time */ 202#define CX18_F_I_LOADED_FW 0 /* Loaded firmware 1st time */
203#define CX18_F_I_EOS 4 /* End of encoder stream reached */ 203#define CX18_F_I_EOS 4 /* End of encoder stream */
204#define CX18_F_I_RADIO_USER 5 /* The radio tuner is selected */ 204#define CX18_F_I_RADIO_USER 5 /* radio tuner is selected */
205#define CX18_F_I_ENC_PAUSED 13 /* the encoder is paused */ 205#define CX18_F_I_ENC_PAUSED 13 /* the encoder is paused */
206#define CX18_F_I_INITED 21 /* set after first open */ 206#define CX18_F_I_HAVE_WORK 15 /* there is work to be done */
207#define CX18_F_I_FAILED 22 /* set if first open failed */ 207#define CX18_F_I_WORK_HANDLER_DVB 18 /* work to be done for DVB */
208#define CX18_F_I_INITED 21 /* set after first open */
209#define CX18_F_I_FAILED 22 /* set if first open failed */
210#define CX18_F_I_WORK_INITED 23 /* worker thread initialized */
208 211
209/* These are the VBI types as they appear in the embedded VBI private packets. */ 212/* These are the VBI types as they appear in the embedded VBI private packets. */
210#define CX18_SLICED_TYPE_TELETEXT_B (1) 213#define CX18_SLICED_TYPE_TELETEXT_B (1)
@@ -402,8 +405,6 @@ struct cx18 {
402 spinlock_t lock; /* lock access to this struct */ 405 spinlock_t lock; /* lock access to this struct */
403 int search_pack_header; 406 int search_pack_header;
404 407
405 spinlock_t dma_reg_lock; /* lock access to DMA engine registers */
406
407 int open_id; /* incremented each time an open occurs, used as 408 int open_id; /* incremented each time an open occurs, used as
408 unique ID. Starts at 1, so 0 can be used as 409 unique ID. Starts at 1, so 0 can be used as
409 uninitialized value in the stream->id. */ 410 uninitialized value in the stream->id. */
@@ -433,6 +434,9 @@ struct cx18 {
433 /* when the current DMA is finished this queue is woken up */ 434 /* when the current DMA is finished this queue is woken up */
434 wait_queue_head_t dma_waitq; 435 wait_queue_head_t dma_waitq;
435 436
437 struct workqueue_struct *work_queue;
438 struct work_struct work;
439
436 /* i2c */ 440 /* i2c */
437 struct i2c_adapter i2c_adap[2]; 441 struct i2c_adapter i2c_adap[2];
438 struct i2c_algo_bit_data i2c_algo[2]; 442 struct i2c_algo_bit_data i2c_algo[2];
diff --git a/drivers/media/video/cx18/cx18-dvb.c b/drivers/media/video/cx18/cx18-dvb.c
index afc694e7bdb2..4542e2e5e3d7 100644
--- a/drivers/media/video/cx18/cx18-dvb.c
+++ b/drivers/media/video/cx18/cx18-dvb.c
@@ -23,6 +23,8 @@
23#include "cx18-dvb.h" 23#include "cx18-dvb.h"
24#include "cx18-io.h" 24#include "cx18-io.h"
25#include "cx18-streams.h" 25#include "cx18-streams.h"
26#include "cx18-queue.h"
27#include "cx18-scb.h"
26#include "cx18-cards.h" 28#include "cx18-cards.h"
27#include "s5h1409.h" 29#include "s5h1409.h"
28#include "mxl5005s.h" 30#include "mxl5005s.h"
@@ -300,3 +302,24 @@ static int dvb_register(struct cx18_stream *stream)
300 302
301 return ret; 303 return ret;
302} 304}
305
306void cx18_dvb_work_handler(struct cx18 *cx)
307{
308 struct cx18_buffer *buf;
309 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_TS];
310
311 while ((buf = cx18_dequeue(s, &s->q_full)) != NULL) {
312 if (s->dvb.enabled)
313 dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
314 buf->bytesused);
315
316 cx18_enqueue(s, buf, &s->q_free);
317 cx18_buf_sync_for_device(s, buf);
318 if (s->handle == CX18_INVALID_TASK_HANDLE) /* FIXME: improve */
319 continue;
320
321 cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle,
322 (void __iomem *)&cx->scb->cpu_mdl[buf->id] - cx->enc_mem,
323 1, buf->id, s->buf_size);
324 }
325}
diff --git a/drivers/media/video/cx18/cx18-dvb.h b/drivers/media/video/cx18/cx18-dvb.h
index bf8d8f6f5455..bbdcefc87f28 100644
--- a/drivers/media/video/cx18/cx18-dvb.h
+++ b/drivers/media/video/cx18/cx18-dvb.h
@@ -23,3 +23,4 @@
23 23
24int cx18_dvb_register(struct cx18_stream *stream); 24int cx18_dvb_register(struct cx18_stream *stream);
25void cx18_dvb_unregister(struct cx18_stream *stream); 25void cx18_dvb_unregister(struct cx18_stream *stream);
26void cx18_dvb_work_handler(struct cx18 *cx);
diff --git a/drivers/media/video/cx18/cx18-io.c b/drivers/media/video/cx18/cx18-io.c
index 700ab9439c16..220fae8d4ad7 100644
--- a/drivers/media/video/cx18/cx18-io.c
+++ b/drivers/media/video/cx18/cx18-io.c
@@ -88,6 +88,19 @@ void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
88 cx18_log_write_retries(cx, i, addr); 88 cx18_log_write_retries(cx, i, addr);
89} 89}
90 90
91void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
92 u32 eval, u32 mask)
93{
94 int i;
95 eval &= mask;
96 for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
97 cx18_writel_noretry(cx, val, addr);
98 if (eval == (cx18_readl_noretry(cx, addr) & mask))
99 break;
100 }
101 cx18_log_write_retries(cx, i, addr);
102}
103
91void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr) 104void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
92{ 105{
93 int i; 106 int i;
@@ -218,7 +231,7 @@ void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
218void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) 231void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
219{ 232{
220 u32 r; 233 u32 r;
221 cx18_write_reg(cx, val, SW1_INT_STATUS); 234 cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
222 r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); 235 r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
223 cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI); 236 cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI);
224} 237}
@@ -233,7 +246,7 @@ void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
233void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) 246void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
234{ 247{
235 u32 r; 248 u32 r;
236 cx18_write_reg(cx, val, SW2_INT_STATUS); 249 cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
237 r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); 250 r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
238 cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI); 251 cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI);
239} 252}
diff --git a/drivers/media/video/cx18/cx18-io.h b/drivers/media/video/cx18/cx18-io.h
index 287a5e8bf67b..425244453ea7 100644
--- a/drivers/media/video/cx18/cx18-io.h
+++ b/drivers/media/video/cx18/cx18-io.h
@@ -133,6 +133,8 @@ static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
133 cx18_writel_noretry(cx, val, addr); 133 cx18_writel_noretry(cx, val, addr);
134} 134}
135 135
136void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
137 u32 eval, u32 mask);
136 138
137static inline 139static inline
138void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr) 140void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr)
@@ -271,6 +273,21 @@ static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
271 cx18_write_reg_noretry(cx, val, reg); 273 cx18_write_reg_noretry(cx, val, reg);
272} 274}
273 275
276static inline void _cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg,
277 u32 eval, u32 mask)
278{
279 _cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask);
280}
281
282static inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg,
283 u32 eval, u32 mask)
284{
285 if (cx18_retry_mmio)
286 _cx18_write_reg_expect(cx, val, reg, eval, mask);
287 else
288 cx18_write_reg_noretry(cx, val, reg);
289}
290
274 291
275static inline u32 cx18_read_reg_noretry(struct cx18 *cx, u32 reg) 292static inline u32 cx18_read_reg_noretry(struct cx18 *cx, u32 reg)
276{ 293{
diff --git a/drivers/media/video/cx18/cx18-irq.c b/drivers/media/video/cx18/cx18-irq.c
index 360330f5463f..5fbfbd0f1493 100644
--- a/drivers/media/video/cx18/cx18-irq.c
+++ b/drivers/media/video/cx18/cx18-irq.c
@@ -29,8 +29,20 @@
29#include "cx18-mailbox.h" 29#include "cx18-mailbox.h"
30#include "cx18-vbi.h" 30#include "cx18-vbi.h"
31#include "cx18-scb.h" 31#include "cx18-scb.h"
32#include "cx18-dvb.h"
32 33
33#define DMA_MAGIC_COOKIE 0x000001fe 34void cx18_work_handler(struct work_struct *work)
35{
36 struct cx18 *cx = container_of(work, struct cx18, work);
37 if (test_and_clear_bit(CX18_F_I_WORK_INITED, &cx->i_flags)) {
38 struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 };
39 /* This thread must use the FIFO scheduler as it
40 * is realtime sensitive. */
41 sched_setscheduler(current, SCHED_FIFO, &param);
42 }
43 if (test_and_clear_bit(CX18_F_I_WORK_HANDLER_DVB, &cx->i_flags))
44 cx18_dvb_work_handler(cx);
45}
34 46
35static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb) 47static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb)
36{ 48{
@@ -67,17 +79,11 @@ static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb)
67 if (buf) { 79 if (buf) {
68 cx18_buf_sync_for_cpu(s, buf); 80 cx18_buf_sync_for_cpu(s, buf);
69 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) { 81 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
70 /* process the buffer here */ 82 CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n",
71 CX18_DEBUG_HI_DMA("TS recv and sent bytesused=%d\n",
72 buf->bytesused);
73
74 dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
75 buf->bytesused); 83 buf->bytesused);
76 84
77 cx18_buf_sync_for_device(s, buf); 85 set_bit(CX18_F_I_WORK_HANDLER_DVB, &cx->i_flags);
78 cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle, 86 set_bit(CX18_F_I_HAVE_WORK, &cx->i_flags);
79 (void __iomem *)&cx->scb->cpu_mdl[buf->id] - cx->enc_mem,
80 1, buf->id, s->buf_size);
81 } else 87 } else
82 set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags); 88 set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags);
83 } else { 89 } else {
@@ -109,7 +115,7 @@ static void epu_debug(struct cx18 *cx, struct cx18_mailbox *mb)
109 CX18_INFO("FW version: %s\n", p - 1); 115 CX18_INFO("FW version: %s\n", p - 1);
110} 116}
111 117
112static void hpu_cmd(struct cx18 *cx, u32 sw1) 118static void epu_cmd(struct cx18 *cx, u32 sw1)
113{ 119{
114 struct cx18_mailbox mb; 120 struct cx18_mailbox mb;
115 121
@@ -125,12 +131,31 @@ static void hpu_cmd(struct cx18 *cx, u32 sw1)
125 epu_debug(cx, &mb); 131 epu_debug(cx, &mb);
126 break; 132 break;
127 default: 133 default:
128 CX18_WARN("Unexpected mailbox command %08x\n", mb.cmd); 134 CX18_WARN("Unknown CPU_TO_EPU mailbox command %#08x\n",
135 mb.cmd);
129 break; 136 break;
130 } 137 }
131 } 138 }
132 if (sw1 & (IRQ_APU_TO_EPU | IRQ_HPU_TO_EPU)) 139
133 CX18_WARN("Unexpected interrupt %08x\n", sw1); 140 if (sw1 & IRQ_APU_TO_EPU) {
141 cx18_memcpy_fromio(cx, &mb, &cx->scb->apu2epu_mb, sizeof(mb));
142 CX18_WARN("Unknown APU_TO_EPU mailbox command %#08x\n", mb.cmd);
143 }
144
145 if (sw1 & IRQ_HPU_TO_EPU) {
146 cx18_memcpy_fromio(cx, &mb, &cx->scb->hpu2epu_mb, sizeof(mb));
147 CX18_WARN("Unknown HPU_TO_EPU mailbox command %#08x\n", mb.cmd);
148 }
149}
150
151static void xpu_ack(struct cx18 *cx, u32 sw2)
152{
153 if (sw2 & IRQ_CPU_TO_EPU_ACK)
154 wake_up(&cx->mb_cpu_waitq);
155 if (sw2 & IRQ_APU_TO_EPU_ACK)
156 wake_up(&cx->mb_apu_waitq);
157 if (sw2 & IRQ_HPU_TO_EPU_ACK)
158 wake_up(&cx->mb_hpu_waitq);
134} 159}
135 160
136irqreturn_t cx18_irq_handler(int irq, void *dev_id) 161irqreturn_t cx18_irq_handler(int irq, void *dev_id)
@@ -140,43 +165,36 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id)
140 u32 sw2, sw2_mask; 165 u32 sw2, sw2_mask;
141 u32 hw2, hw2_mask; 166 u32 hw2, hw2_mask;
142 167
143 spin_lock(&cx->dma_reg_lock); 168 sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
144 169 sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask;
170 sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
171 sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask;
145 hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI); 172 hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI);
146 hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask; 173 hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask;
147 sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU_ACK;
148 sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask;
149 sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU;
150 sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask;
151 174
152 cx18_write_reg(cx, sw2&sw2_mask, SW2_INT_STATUS); 175 if (sw1)
153 cx18_write_reg(cx, sw1&sw1_mask, SW1_INT_STATUS); 176 cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1);
154 cx18_write_reg(cx, hw2&hw2_mask, HW2_INT_CLR_STATUS); 177 if (sw2)
178 cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2);
179 if (hw2)
180 cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2);
155 181
156 if (sw1 || sw2 || hw2) 182 if (sw1 || sw2 || hw2)
157 CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2); 183 CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2);
158 184
159 /* To do: interrupt-based I2C handling 185 /* To do: interrupt-based I2C handling
160 if (hw2 & 0x00c00000) { 186 if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) {
161 } 187 }
162 */ 188 */
163 189
164 if (sw2) { 190 if (sw2)
165 if (sw2 & (cx18_readl(cx, &cx->scb->cpu2hpu_irq_ack) | 191 xpu_ack(cx, sw2);
166 cx18_readl(cx, &cx->scb->cpu2epu_irq_ack)))
167 wake_up(&cx->mb_cpu_waitq);
168 if (sw2 & (cx18_readl(cx, &cx->scb->apu2hpu_irq_ack) |
169 cx18_readl(cx, &cx->scb->apu2epu_irq_ack)))
170 wake_up(&cx->mb_apu_waitq);
171 if (sw2 & cx18_readl(cx, &cx->scb->epu2hpu_irq_ack))
172 wake_up(&cx->mb_epu_waitq);
173 if (sw2 & cx18_readl(cx, &cx->scb->hpu2epu_irq_ack))
174 wake_up(&cx->mb_hpu_waitq);
175 }
176 192
177 if (sw1) 193 if (sw1)
178 hpu_cmd(cx, sw1); 194 epu_cmd(cx, sw1);
179 spin_unlock(&cx->dma_reg_lock); 195
196 if (test_and_clear_bit(CX18_F_I_HAVE_WORK, &cx->i_flags))
197 queue_work(cx->work_queue, &cx->work);
180 198
181 return (hw2 | sw1 | sw2) ? IRQ_HANDLED : IRQ_NONE; 199 return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE;
182} 200}
diff --git a/drivers/media/video/cx18/cx18-irq.h b/drivers/media/video/cx18/cx18-irq.h
index 379f704f5cba..6173ca3bc9e4 100644
--- a/drivers/media/video/cx18/cx18-irq.h
+++ b/drivers/media/video/cx18/cx18-irq.h
@@ -32,6 +32,4 @@
32 32
33irqreturn_t cx18_irq_handler(int irq, void *dev_id); 33irqreturn_t cx18_irq_handler(int irq, void *dev_id);
34 34
35void cx18_irq_work_handler(struct work_struct *work); 35void cx18_work_handler(struct work_struct *work);
36void cx18_dma_stream_dec_prepare(struct cx18_stream *s, u32 offset, int lock);
37void cx18_unfinished_dma(unsigned long arg);
diff --git a/drivers/media/video/cx18/cx18-mailbox.c b/drivers/media/video/cx18/cx18-mailbox.c
index 9d18dd22de76..acff7dfb60df 100644
--- a/drivers/media/video/cx18/cx18-mailbox.c
+++ b/drivers/media/video/cx18/cx18-mailbox.c
@@ -83,7 +83,7 @@ static const struct cx18_api_info api_info[] = {
83 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0), 83 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
84 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST), 84 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
85 API_ENTRY(CPU, CX18_APU_RESETAI, API_FAST), 85 API_ENTRY(CPU, CX18_APU_RESETAI, API_FAST),
86 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, 0), 86 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
87 API_ENTRY(0, 0, 0), 87 API_ENTRY(0, 0, 0),
88}; 88};
89 89
@@ -176,7 +176,7 @@ long cx18_mb_ack(struct cx18 *cx, const struct cx18_mailbox *mb)
176 176
177 cx18_setup_page(cx, SCB_OFFSET); 177 cx18_setup_page(cx, SCB_OFFSET);
178 cx18_write_sync(cx, mb->request, &ack_mb->ack); 178 cx18_write_sync(cx, mb->request, &ack_mb->ack);
179 cx18_write_reg(cx, ack_irq, SW2_INT_SET); 179 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
180 return 0; 180 return 0;
181} 181}
182 182
@@ -225,7 +225,7 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
225 } 225 }
226 if (info->flags & API_FAST) 226 if (info->flags & API_FAST)
227 timeout /= 2; 227 timeout /= 2;
228 cx18_write_reg(cx, irq, SW1_INT_SET); 228 cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
229 229
230 while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request) 230 while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request)
231 && cnt < 660) { 231 && cnt < 660) {
diff --git a/drivers/media/video/cx18/cx18-queue.c b/drivers/media/video/cx18/cx18-queue.c
index a33ba04a2686..174682c2582f 100644
--- a/drivers/media/video/cx18/cx18-queue.c
+++ b/drivers/media/video/cx18/cx18-queue.c
@@ -88,15 +88,13 @@ struct cx18_buffer *cx18_queue_get_buf_irq(struct cx18_stream *s, u32 id,
88 88
89 if (buf->id != id) 89 if (buf->id != id)
90 continue; 90 continue;
91
91 buf->bytesused = bytesused; 92 buf->bytesused = bytesused;
92 /* the transport buffers are handled differently, 93 atomic_dec(&s->q_free.buffers);
93 they are not moved to the full queue */ 94 atomic_inc(&s->q_full.buffers);
94 if (s->type != CX18_ENC_STREAM_TYPE_TS) { 95 s->q_full.bytesused += buf->bytesused;
95 atomic_dec(&s->q_free.buffers); 96 list_move_tail(&buf->list, &s->q_full.list);
96 atomic_inc(&s->q_full.buffers); 97
97 s->q_full.bytesused += buf->bytesused;
98 list_move_tail(&buf->list, &s->q_full.list);
99 }
100 spin_unlock(&s->qlock); 98 spin_unlock(&s->qlock);
101 return buf; 99 return buf;
102 } 100 }
diff --git a/drivers/media/video/cx18/cx18-scb.h b/drivers/media/video/cx18/cx18-scb.h
index 86b4cb15d163..594713bbed68 100644
--- a/drivers/media/video/cx18/cx18-scb.h
+++ b/drivers/media/video/cx18/cx18-scb.h
@@ -128,22 +128,22 @@ struct cx18_scb {
128 u32 apu2cpu_irq; 128 u32 apu2cpu_irq;
129 /* Value to write to register SW2 register set (0xC7003140) after the 129 /* Value to write to register SW2 register set (0xC7003140) after the
130 command is cleared */ 130 command is cleared */
131 u32 apu2cpu_irq_ack; 131 u32 cpu2apu_irq_ack;
132 u32 reserved2[13]; 132 u32 reserved2[13];
133 133
134 u32 hpu2cpu_mb_offset; 134 u32 hpu2cpu_mb_offset;
135 u32 hpu2cpu_irq; 135 u32 hpu2cpu_irq;
136 u32 hpu2cpu_irq_ack; 136 u32 cpu2hpu_irq_ack;
137 u32 reserved3[13]; 137 u32 reserved3[13];
138 138
139 u32 ppu2cpu_mb_offset; 139 u32 ppu2cpu_mb_offset;
140 u32 ppu2cpu_irq; 140 u32 ppu2cpu_irq;
141 u32 ppu2cpu_irq_ack; 141 u32 cpu2ppu_irq_ack;
142 u32 reserved4[13]; 142 u32 reserved4[13];
143 143
144 u32 epu2cpu_mb_offset; 144 u32 epu2cpu_mb_offset;
145 u32 epu2cpu_irq; 145 u32 epu2cpu_irq;
146 u32 epu2cpu_irq_ack; 146 u32 cpu2epu_irq_ack;
147 u32 reserved5[13]; 147 u32 reserved5[13];
148 u32 reserved6[8]; 148 u32 reserved6[8];
149 149
@@ -153,22 +153,22 @@ struct cx18_scb {
153 u32 reserved11[7]; 153 u32 reserved11[7];
154 u32 cpu2apu_mb_offset; 154 u32 cpu2apu_mb_offset;
155 u32 cpu2apu_irq; 155 u32 cpu2apu_irq;
156 u32 cpu2apu_irq_ack; 156 u32 apu2cpu_irq_ack;
157 u32 reserved12[13]; 157 u32 reserved12[13];
158 158
159 u32 hpu2apu_mb_offset; 159 u32 hpu2apu_mb_offset;
160 u32 hpu2apu_irq; 160 u32 hpu2apu_irq;
161 u32 hpu2apu_irq_ack; 161 u32 apu2hpu_irq_ack;
162 u32 reserved13[13]; 162 u32 reserved13[13];
163 163
164 u32 ppu2apu_mb_offset; 164 u32 ppu2apu_mb_offset;
165 u32 ppu2apu_irq; 165 u32 ppu2apu_irq;
166 u32 ppu2apu_irq_ack; 166 u32 apu2ppu_irq_ack;
167 u32 reserved14[13]; 167 u32 reserved14[13];
168 168
169 u32 epu2apu_mb_offset; 169 u32 epu2apu_mb_offset;
170 u32 epu2apu_irq; 170 u32 epu2apu_irq;
171 u32 epu2apu_irq_ack; 171 u32 apu2epu_irq_ack;
172 u32 reserved15[13]; 172 u32 reserved15[13];
173 u32 reserved16[8]; 173 u32 reserved16[8];
174 174
@@ -178,22 +178,22 @@ struct cx18_scb {
178 u32 reserved21[7]; 178 u32 reserved21[7];
179 u32 cpu2hpu_mb_offset; 179 u32 cpu2hpu_mb_offset;
180 u32 cpu2hpu_irq; 180 u32 cpu2hpu_irq;
181 u32 cpu2hpu_irq_ack; 181 u32 hpu2cpu_irq_ack;
182 u32 reserved22[13]; 182 u32 reserved22[13];
183 183
184 u32 apu2hpu_mb_offset; 184 u32 apu2hpu_mb_offset;
185 u32 apu2hpu_irq; 185 u32 apu2hpu_irq;
186 u32 apu2hpu_irq_ack; 186 u32 hpu2apu_irq_ack;
187 u32 reserved23[13]; 187 u32 reserved23[13];
188 188
189 u32 ppu2hpu_mb_offset; 189 u32 ppu2hpu_mb_offset;
190 u32 ppu2hpu_irq; 190 u32 ppu2hpu_irq;
191 u32 ppu2hpu_irq_ack; 191 u32 hpu2ppu_irq_ack;
192 u32 reserved24[13]; 192 u32 reserved24[13];
193 193
194 u32 epu2hpu_mb_offset; 194 u32 epu2hpu_mb_offset;
195 u32 epu2hpu_irq; 195 u32 epu2hpu_irq;
196 u32 epu2hpu_irq_ack; 196 u32 hpu2epu_irq_ack;
197 u32 reserved25[13]; 197 u32 reserved25[13];
198 u32 reserved26[8]; 198 u32 reserved26[8];
199 199
@@ -203,22 +203,22 @@ struct cx18_scb {
203 u32 reserved31[7]; 203 u32 reserved31[7];
204 u32 cpu2ppu_mb_offset; 204 u32 cpu2ppu_mb_offset;
205 u32 cpu2ppu_irq; 205 u32 cpu2ppu_irq;
206 u32 cpu2ppu_irq_ack; 206 u32 ppu2cpu_irq_ack;
207 u32 reserved32[13]; 207 u32 reserved32[13];
208 208
209 u32 apu2ppu_mb_offset; 209 u32 apu2ppu_mb_offset;
210 u32 apu2ppu_irq; 210 u32 apu2ppu_irq;
211 u32 apu2ppu_irq_ack; 211 u32 ppu2apu_irq_ack;
212 u32 reserved33[13]; 212 u32 reserved33[13];
213 213
214 u32 hpu2ppu_mb_offset; 214 u32 hpu2ppu_mb_offset;
215 u32 hpu2ppu_irq; 215 u32 hpu2ppu_irq;
216 u32 hpu2ppu_irq_ack; 216 u32 ppu2hpu_irq_ack;
217 u32 reserved34[13]; 217 u32 reserved34[13];
218 218
219 u32 epu2ppu_mb_offset; 219 u32 epu2ppu_mb_offset;
220 u32 epu2ppu_irq; 220 u32 epu2ppu_irq;
221 u32 epu2ppu_irq_ack; 221 u32 ppu2epu_irq_ack;
222 u32 reserved35[13]; 222 u32 reserved35[13];
223 u32 reserved36[8]; 223 u32 reserved36[8];
224 224
@@ -228,22 +228,22 @@ struct cx18_scb {
228 u32 reserved41[7]; 228 u32 reserved41[7];
229 u32 cpu2epu_mb_offset; 229 u32 cpu2epu_mb_offset;
230 u32 cpu2epu_irq; 230 u32 cpu2epu_irq;
231 u32 cpu2epu_irq_ack; 231 u32 epu2cpu_irq_ack;
232 u32 reserved42[13]; 232 u32 reserved42[13];
233 233
234 u32 apu2epu_mb_offset; 234 u32 apu2epu_mb_offset;
235 u32 apu2epu_irq; 235 u32 apu2epu_irq;
236 u32 apu2epu_irq_ack; 236 u32 epu2apu_irq_ack;
237 u32 reserved43[13]; 237 u32 reserved43[13];
238 238
239 u32 hpu2epu_mb_offset; 239 u32 hpu2epu_mb_offset;
240 u32 hpu2epu_irq; 240 u32 hpu2epu_irq;
241 u32 hpu2epu_irq_ack; 241 u32 epu2hpu_irq_ack;
242 u32 reserved44[13]; 242 u32 reserved44[13];
243 243
244 u32 ppu2epu_mb_offset; 244 u32 ppu2epu_mb_offset;
245 u32 ppu2epu_irq; 245 u32 ppu2epu_irq;
246 u32 ppu2epu_irq_ack; 246 u32 epu2ppu_irq_ack;
247 u32 reserved45[13]; 247 u32 reserved45[13];
248 u32 reserved46[8]; 248 u32 reserved46[8];
249 249