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path: root/drivers/media/usb/au0828/au0828-cards.c
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Diffstat (limited to 'drivers/media/usb/au0828/au0828-cards.c')
-rw-r--r--drivers/media/usb/au0828/au0828-cards.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/media/usb/au0828/au0828-cards.c b/drivers/media/usb/au0828/au0828-cards.c
index 7fdadf9bc90b..3a7924044a87 100644
--- a/drivers/media/usb/au0828/au0828-cards.c
+++ b/drivers/media/usb/au0828/au0828-cards.c
@@ -46,7 +46,7 @@ struct au0828_board au0828_boards[] = {
46 .name = "Hauppauge HVR850", 46 .name = "Hauppauge HVR850",
47 .tuner_type = TUNER_XC5000, 47 .tuner_type = TUNER_XC5000,
48 .tuner_addr = 0x61, 48 .tuner_addr = 0x61,
49 .i2c_clk_divider = AU0828_I2C_CLK_20KHZ, 49 .i2c_clk_divider = AU0828_I2C_CLK_250KHZ,
50 .input = { 50 .input = {
51 { 51 {
52 .type = AU0828_VMUX_TELEVISION, 52 .type = AU0828_VMUX_TELEVISION,
@@ -77,7 +77,7 @@ struct au0828_board au0828_boards[] = {
77 stretch fits inside of a normal clock cycle, or else the 77 stretch fits inside of a normal clock cycle, or else the
78 au0828 fails to set the STOP bit. A 30 KHz clock puts the 78 au0828 fails to set the STOP bit. A 30 KHz clock puts the
79 clock pulse width at 18us */ 79 clock pulse width at 18us */
80 .i2c_clk_divider = AU0828_I2C_CLK_20KHZ, 80 .i2c_clk_divider = AU0828_I2C_CLK_250KHZ,
81 .input = { 81 .input = {
82 { 82 {
83 .type = AU0828_VMUX_TELEVISION, 83 .type = AU0828_VMUX_TELEVISION,
@@ -108,7 +108,7 @@ struct au0828_board au0828_boards[] = {
108 .name = "DViCO FusionHDTV USB", 108 .name = "DViCO FusionHDTV USB",
109 .tuner_type = UNSET, 109 .tuner_type = UNSET,
110 .tuner_addr = ADDR_UNSET, 110 .tuner_addr = ADDR_UNSET,
111 .i2c_clk_divider = AU0828_I2C_CLK_20KHZ, 111 .i2c_clk_divider = AU0828_I2C_CLK_250KHZ,
112 }, 112 },
113 [AU0828_BOARD_HAUPPAUGE_WOODBURY] = { 113 [AU0828_BOARD_HAUPPAUGE_WOODBURY] = {
114 .name = "Hauppauge Woodbury", 114 .name = "Hauppauge Woodbury",