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-rw-r--r--drivers/media/dvb/ngene/ngene.h859
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diff --git a/drivers/media/dvb/ngene/ngene.h b/drivers/media/dvb/ngene/ngene.h
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1/*
2 * ngene.h: nGene PCIe bridge driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#ifndef _NGENE_H_
25#define _NGENE_H_
26
27#include <linux/types.h>
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/i2c.h>
31#include <asm/dma.h>
32#include <linux/scatterlist.h>
33
34#include <linux/dvb/frontend.h>
35
36#include "dmxdev.h"
37#include "dvbdev.h"
38#include "dvb_demux.h"
39#include "dvb_frontend.h"
40#include "dvb_ringbuffer.h"
41
42#define NGENE_VID 0x18c3
43#define NGENE_PID 0x0720
44
45#ifndef VIDEO_CAP_VC1
46#define VIDEO_CAP_AVC 128
47#define VIDEO_CAP_H264 128
48#define VIDEO_CAP_VC1 256
49#define VIDEO_CAP_WMV9 256
50#define VIDEO_CAP_MPEG4 512
51#endif
52
53enum STREAM {
54 STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */
55 STREAM_VIDEOIN2,
56 STREAM_AUDIOIN1, /* I2S or SPI Input */
57 STREAM_AUDIOIN2,
58 STREAM_AUDIOOUT,
59 MAX_STREAM
60};
61
62enum SMODE_BITS {
63 SMODE_AUDIO_SPDIF = 0x20,
64 SMODE_AVSYNC = 0x10,
65 SMODE_TRANSPORT_STREAM = 0x08,
66 SMODE_AUDIO_CAPTURE = 0x04,
67 SMODE_VBI_CAPTURE = 0x02,
68 SMODE_VIDEO_CAPTURE = 0x01
69};
70
71enum STREAM_FLAG_BITS {
72 SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */
73 SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */
74 SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */
75 SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */
76 SFLAG_COLORBAR = 0x04, /* Select colorbar */
77};
78
79#define PROGRAM_ROM 0x0000
80#define PROGRAM_SRAM 0x1000
81#define PERIPHERALS0 0x8000
82#define PERIPHERALS1 0x9000
83#define SHARED_BUFFER 0xC000
84
85#define HOST_TO_NGENE (SHARED_BUFFER+0x0000)
86#define NGENE_TO_HOST (SHARED_BUFFER+0x0100)
87#define NGENE_COMMAND (SHARED_BUFFER+0x0200)
88#define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
89#define NGENE_STATUS (SHARED_BUFFER+0x0208)
90#define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)
91#define NGENE_EVENT (SHARED_BUFFER+0x0210)
92#define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)
93#define VARIABLES (SHARED_BUFFER+0x0210)
94
95#define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)
96#define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)
97#define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)
98
99#define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)
100#define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)
101#define EEPROM_AREA (SHARED_BUFFER+0x0A00)
102
103#define SG_V_IN_1 (SHARED_BUFFER+0x0A80)
104#define SG_VBI_1 (SHARED_BUFFER+0x0B00)
105#define SG_A_IN_1 (SHARED_BUFFER+0x0B80)
106#define SG_V_IN_2 (SHARED_BUFFER+0x0C00)
107#define SG_VBI_2 (SHARED_BUFFER+0x0C80)
108#define SG_A_IN_2 (SHARED_BUFFER+0x0D00)
109#define SG_V_OUT (SHARED_BUFFER+0x0D80)
110#define SG_A_OUT2 (SHARED_BUFFER+0x0E00)
111
112#define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)
113#define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)
114#define DATA_A_OUT (SHARED_BUFFER+0x0F80)
115#define DATA_V_IN_1 (SHARED_BUFFER+0x1000)
116#define DATA_V_IN_2 (SHARED_BUFFER+0x2000)
117#define DATA_V_OUT (SHARED_BUFFER+0x3000)
118
119#define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)
120
121#define TIMESTAMPS 0xA000
122#define SCRATCHPAD 0xA080
123#define FORCE_INT 0xA088
124#define FORCE_NMI 0xA090
125#define INT_STATUS 0xA0A0
126
127#define DEV_VER 0x9004
128
129#define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
130
131struct SG_ADDR {
132 u64 start;
133 u64 curr;
134 u16 curr_ptr;
135 u16 elements;
136 u32 pad[3];
137} __attribute__ ((__packed__));
138
139struct SHARED_MEMORY {
140 /* C000 */
141 u32 HostToNgene[64];
142
143 /* C100 */
144 u32 NgeneToHost[64];
145
146 /* C200 */
147 u64 NgeneCommand;
148 u64 NgeneStatus;
149 u64 NgeneEvent;
150
151 /* C210 */
152 u8 pad1[0xc260 - 0xc218];
153
154 /* C260 */
155 u32 IntCounts;
156 u32 IntEnable;
157
158 /* C268 */
159 u8 pad2[0xd000 - 0xc268];
160
161} __attribute__ ((__packed__));
162
163struct BUFFER_STREAM_RESULTS {
164 u32 Clock; /* Stream time in 100ns units */
165 u16 RemainingLines; /* Remaining lines in this field.
166 0 for complete field */
167 u8 FieldCount; /* Video field number */
168 u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
169 Bit 0 = FieldID */
170 u16 BlockCount; /* Audio block count (unused) */
171 u8 Reserved[2];
172 u32 DTOUpdate;
173} __attribute__ ((__packed__));
174
175struct HW_SCATTER_GATHER_ELEMENT {
176 u64 Address;
177 u32 Length;
178 u32 Reserved;
179} __attribute__ ((__packed__));
180
181struct BUFFER_HEADER {
182 u64 Next;
183 struct BUFFER_STREAM_RESULTS SR;
184
185 u32 Number_of_entries_1;
186 u32 Reserved5;
187 u64 Address_of_first_entry_1;
188
189 u32 Number_of_entries_2;
190 u32 Reserved7;
191 u64 Address_of_first_entry_2;
192} __attribute__ ((__packed__));
193
194struct EVENT_BUFFER {
195 u32 TimeStamp;
196 u8 GPIOStatus;
197 u8 UARTStatus;
198 u8 RXCharacter;
199 u8 EventStatus;
200 u32 Reserved[2];
201} __attribute__ ((__packed__));
202
203/* Firmware commands. */
204
205enum OPCODES {
206 CMD_NOP = 0,
207 CMD_FWLOAD_PREPARE = 0x01,
208 CMD_FWLOAD_FINISH = 0x02,
209 CMD_I2C_READ = 0x03,
210 CMD_I2C_WRITE = 0x04,
211
212 CMD_I2C_WRITE_NOSTOP = 0x05,
213 CMD_I2C_CONTINUE_WRITE = 0x06,
214 CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,
215
216 CMD_DEBUG_OUTPUT = 0x09,
217
218 CMD_CONTROL = 0x10,
219 CMD_CONFIGURE_BUFFER = 0x11,
220 CMD_CONFIGURE_FREE_BUFFER = 0x12,
221
222 CMD_SPI_READ = 0x13,
223 CMD_SPI_WRITE = 0x14,
224
225 CMD_MEM_READ = 0x20,
226 CMD_MEM_WRITE = 0x21,
227 CMD_SFR_READ = 0x22,
228 CMD_SFR_WRITE = 0x23,
229 CMD_IRAM_READ = 0x24,
230 CMD_IRAM_WRITE = 0x25,
231 CMD_SET_GPIO_PIN = 0x26,
232 CMD_SET_GPIO_INT = 0x27,
233 CMD_CONFIGURE_UART = 0x28,
234 CMD_WRITE_UART = 0x29,
235 MAX_CMD
236};
237
238enum RESPONSES {
239 OK = 0,
240 ERROR = 1
241};
242
243struct FW_HEADER {
244 u8 Opcode;
245 u8 Length;
246} __attribute__ ((__packed__));
247
248struct FW_I2C_WRITE {
249 struct FW_HEADER hdr;
250 u8 Device;
251 u8 Data[250];
252} __attribute__ ((__packed__));
253
254struct FW_I2C_CONTINUE_WRITE {
255 struct FW_HEADER hdr;
256 u8 Data[250];
257} __attribute__ ((__packed__));
258
259struct FW_I2C_READ {
260 struct FW_HEADER hdr;
261 u8 Device;
262 u8 Data[252]; /* followed by two bytes of read data count */
263} __attribute__ ((__packed__));
264
265struct FW_SPI_WRITE {
266 struct FW_HEADER hdr;
267 u8 ModeSelect;
268 u8 Data[250];
269} __attribute__ ((__packed__));
270
271struct FW_SPI_READ {
272 struct FW_HEADER hdr;
273 u8 ModeSelect;
274 u8 Data[252]; /* followed by two bytes of read data count */
275} __attribute__ ((__packed__));
276
277struct FW_FWLOAD_PREPARE {
278 struct FW_HEADER hdr;
279} __attribute__ ((__packed__));
280
281struct FW_FWLOAD_FINISH {
282 struct FW_HEADER hdr;
283 u16 Address; /* address of final block */
284 u16 Length;
285} __attribute__ ((__packed__));
286
287/*
288 * Meaning of FW_STREAM_CONTROL::Mode bits:
289 * Bit 7: Loopback PEXin to PEXout using TVOut channel
290 * Bit 6: AVLOOP
291 * Bit 5: Audio select; 0=I2S, 1=SPDIF
292 * Bit 4: AVSYNC
293 * Bit 3: Enable transport stream
294 * Bit 2: Enable audio capture
295 * Bit 1: Enable ITU-Video VBI capture
296 * Bit 0: Enable ITU-Video capture
297 *
298 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
299 * Bit 7: continuous capture
300 * Bit 6: capture one field
301 * Bit 5: capture one frame
302 * Bit 4: unused
303 * Bit 3: starting field; 0=odd, 1=even
304 * Bit 2: sample size; 0=8-bit, 1=10-bit
305 * Bit 1: data format; 0=UYVY, 1=YUY2
306 * Bit 0: resets buffer pointers
307*/
308
309enum FSC_MODE_BITS {
310 SMODE_LOOPBACK = 0x80,
311 SMODE_AVLOOP = 0x40,
312 _SMODE_AUDIO_SPDIF = 0x20,
313 _SMODE_AVSYNC = 0x10,
314 _SMODE_TRANSPORT_STREAM = 0x08,
315 _SMODE_AUDIO_CAPTURE = 0x04,
316 _SMODE_VBI_CAPTURE = 0x02,
317 _SMODE_VIDEO_CAPTURE = 0x01
318};
319
320
321/* Meaning of FW_STREAM_CONTROL::Stream bits:
322 * Bit 3: Audio sample count: 0 = relative, 1 = absolute
323 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
324 * Bits 1-0: stream select, UVI1, UVI2, TVOUT
325 */
326
327struct FW_STREAM_CONTROL {
328 struct FW_HEADER hdr;
329 u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */
330 u8 Control; /* Value written to UVI1_CTL */
331 u8 Mode; /* Controls clock source */
332 u8 SetupDataLen; /* Length of setup data, MSB=1 write
333 backwards */
334 u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer
335 for TS and Audio */
336 u64 Buffer_Address; /* Address of first buffer header */
337 u16 BytesPerVideoLine;
338 u16 MaxLinesPerField;
339 u16 MinLinesPerField;
340 u16 Reserved_1;
341 u16 BytesPerVBILine;
342 u16 MaxVBILinesPerField;
343 u16 MinVBILinesPerField;
344 u16 SetupDataAddr; /* ngene relative address of setup data */
345 u8 SetupData[32]; /* setup data */
346} __attribute__((__packed__));
347
348#define AUDIO_BLOCK_SIZE 256
349#define TS_BLOCK_SIZE 256
350
351struct FW_MEM_READ {
352 struct FW_HEADER hdr;
353 u16 address;
354} __attribute__ ((__packed__));
355
356struct FW_MEM_WRITE {
357 struct FW_HEADER hdr;
358 u16 address;
359 u8 data;
360} __attribute__ ((__packed__));
361
362struct FW_SFR_IRAM_READ {
363 struct FW_HEADER hdr;
364 u8 address;
365} __attribute__ ((__packed__));
366
367struct FW_SFR_IRAM_WRITE {
368 struct FW_HEADER hdr;
369 u8 address;
370 u8 data;
371} __attribute__ ((__packed__));
372
373struct FW_SET_GPIO_PIN {
374 struct FW_HEADER hdr;
375 u8 select;
376} __attribute__ ((__packed__));
377
378struct FW_SET_GPIO_INT {
379 struct FW_HEADER hdr;
380 u8 select;
381} __attribute__ ((__packed__));
382
383struct FW_SET_DEBUGMODE {
384 struct FW_HEADER hdr;
385 u8 debug_flags;
386} __attribute__ ((__packed__));
387
388struct FW_CONFIGURE_BUFFERS {
389 struct FW_HEADER hdr;
390 u8 config;
391} __attribute__ ((__packed__));
392
393enum _BUFFER_CONFIGS {
394 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */
395 BUFFER_CONFIG_4422 = 0,
396 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */
397 BUFFER_CONFIG_3333 = 1,
398 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */
399 BUFFER_CONFIG_8022 = 2,
400 BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */
401};
402
403struct FW_CONFIGURE_FREE_BUFFERS {
404 struct FW_HEADER hdr;
405 u8 UVI1_BufferLength;
406 u8 UVI2_BufferLength;
407 u8 TVO_BufferLength;
408 u8 AUD1_BufferLength;
409 u8 AUD2_BufferLength;
410 u8 TVA_BufferLength;
411} __attribute__ ((__packed__));
412
413struct FW_CONFIGURE_UART {
414 struct FW_HEADER hdr;
415 u8 UartControl;
416} __attribute__ ((__packed__));
417
418enum _UART_CONFIG {
419 _UART_BAUDRATE_19200 = 0,
420 _UART_BAUDRATE_9600 = 1,
421 _UART_BAUDRATE_4800 = 2,
422 _UART_BAUDRATE_2400 = 3,
423 _UART_RX_ENABLE = 0x40,
424 _UART_TX_ENABLE = 0x80,
425};
426
427struct FW_WRITE_UART {
428 struct FW_HEADER hdr;
429 u8 Data[252];
430} __attribute__ ((__packed__));
431
432
433struct ngene_command {
434 u32 in_len;
435 u32 out_len;
436 union {
437 u32 raw[64];
438 u8 raw8[256];
439 struct FW_HEADER hdr;
440 struct FW_I2C_WRITE I2CWrite;
441 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite;
442 struct FW_I2C_READ I2CRead;
443 struct FW_STREAM_CONTROL StreamControl;
444 struct FW_FWLOAD_PREPARE FWLoadPrepare;
445 struct FW_FWLOAD_FINISH FWLoadFinish;
446 struct FW_MEM_READ MemoryRead;
447 struct FW_MEM_WRITE MemoryWrite;
448 struct FW_SFR_IRAM_READ SfrIramRead;
449 struct FW_SFR_IRAM_WRITE SfrIramWrite;
450 struct FW_SPI_WRITE SPIWrite;
451 struct FW_SPI_READ SPIRead;
452 struct FW_SET_GPIO_PIN SetGpioPin;
453 struct FW_SET_GPIO_INT SetGpioInt;
454 struct FW_SET_DEBUGMODE SetDebugMode;
455 struct FW_CONFIGURE_BUFFERS ConfigureBuffers;
456 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;
457 struct FW_CONFIGURE_UART ConfigureUart;
458 struct FW_WRITE_UART WriteUart;
459 } cmd;
460} __attribute__ ((__packed__));
461
462#define NGENE_INTERFACE_VERSION 0x103
463#define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */
464#define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */
465#define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */
466#define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */
467#define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page
468 Max: (1920x1080i60) */
469
470#define OVERFLOW_BUFFER_SIZE (8192)
471
472#define RING_SIZE_VIDEO 4
473#define RING_SIZE_AUDIO 8
474#define RING_SIZE_TS 8
475
476#define NUM_SCATTER_GATHER_ENTRIES 8
477
478#define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
479 RING_SIZE_VIDEO * 2) + \
480 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
481 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
482 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
483 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
484 (RING_SIZE_TS * PAGE_SIZE * 4) + \
485 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
486
487#define EVENT_QUEUE_SIZE 16
488
489/* Gathers the current state of a single channel. */
490
491struct SBufferHeader {
492 struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */
493 struct SBufferHeader *Next;
494 void *Buffer1;
495 struct HW_SCATTER_GATHER_ELEMENT *scList1;
496 void *Buffer2;
497 struct HW_SCATTER_GATHER_ELEMENT *scList2;
498};
499
500/* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
501#define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
502
503enum HWSTATE {
504 HWSTATE_STOP,
505 HWSTATE_STARTUP,
506 HWSTATE_RUN,
507 HWSTATE_PAUSE,
508};
509
510enum KSSTATE {
511 KSSTATE_STOP,
512 KSSTATE_ACQUIRE,
513 KSSTATE_PAUSE,
514 KSSTATE_RUN,
515};
516
517struct SRingBufferDescriptor {
518 struct SBufferHeader *Head; /* Points to first buffer in ring buffer
519 structure*/
520 u64 PAHead; /* Physical address of first buffer */
521 u32 MemSize; /* Memory size of allocated ring buffers
522 (needed for freeing) */
523 u32 NumBuffers; /* Number of buffers in the ring */
524 u32 Buffer1Length; /* Allocated length of Buffer 1 */
525 u32 Buffer2Length; /* Allocated length of Buffer 2 */
526 void *SCListMem; /* Memory to hold scatter gather lists for this
527 ring */
528 u64 PASCListMem; /* Physical address .. */
529 u32 SCListMemSize; /* Size of this memory */
530};
531
532enum STREAMMODEFLAGS {
533 StreamMode_NONE = 0, /* Stream not used */
534 StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
535 StreamMode_TSIN = 2, /* Transport stream input (all) */
536 StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
537 (only stream 0) */
538 StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */
539};
540
541
542enum BufferExchangeFlags {
543 BEF_EVEN_FIELD = 0x00000001,
544 BEF_CONTINUATION = 0x00000002,
545 BEF_MORE_DATA = 0x00000004,
546 BEF_OVERFLOW = 0x00000008,
547 DF_SWAP32 = 0x00010000,
548};
549
550typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);
551
552struct MICI_STREAMINFO {
553 IBufferExchange *pExchange;
554 IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */
555 u8 Stream;
556 u8 Flags;
557 u8 Mode;
558 u8 Reserved;
559 u16 nLinesVideo;
560 u16 nBytesPerLineVideo;
561 u16 nLinesVBI;
562 u16 nBytesPerLineVBI;
563 u32 CaptureLength; /* Used for audio and transport stream */
564};
565
566/****************************************************************************/
567/* STRUCTS ******************************************************************/
568/****************************************************************************/
569
570/* sound hardware definition */
571#define MIXER_ADDR_TVTUNER 0
572#define MIXER_ADDR_LAST 0
573
574struct ngene_channel;
575
576/*struct sound chip*/
577
578struct mychip {
579 struct ngene_channel *chan;
580 struct snd_card *card;
581 struct pci_dev *pci;
582 struct snd_pcm_substream *substream;
583 struct snd_pcm *pcm;
584 unsigned long port;
585 int irq;
586 spinlock_t mixer_lock;
587 spinlock_t lock;
588 int mixer_volume[MIXER_ADDR_LAST + 1][2];
589 int capture_source[MIXER_ADDR_LAST + 1][2];
590};
591
592#ifdef NGENE_V4L
593struct ngene_overlay {
594 int tvnorm;
595 struct v4l2_rect w;
596 enum v4l2_field field;
597 struct v4l2_clip *clips;
598 int nclips;
599 int setup_ok;
600};
601
602struct ngene_tvnorm {
603 int v4l2_id;
604 char *name;
605 u16 swidth, sheight; /* scaled standard width, height */
606 int tuner_norm;
607 int soundstd;
608};
609
610struct ngene_vopen {
611 struct ngene_channel *ch;
612 enum v4l2_priority prio;
613 int width;
614 int height;
615 int depth;
616 struct videobuf_queue vbuf_q;
617 struct videobuf_queue vbi;
618 int fourcc;
619 int picxcount;
620 int resources;
621 enum v4l2_buf_type type;
622 const struct ngene_format *fmt;
623
624 const struct ngene_format *ovfmt;
625 struct ngene_overlay ov;
626};
627#endif
628
629struct ngene_channel {
630 struct device device;
631 struct i2c_adapter i2c_adapter;
632
633 struct ngene *dev;
634 int number;
635 int type;
636 int mode;
637
638 struct dvb_frontend *fe;
639 struct dmxdev dmxdev;
640 struct dvb_demux demux;
641 struct dmx_frontend hw_frontend;
642 struct dmx_frontend mem_frontend;
643 int users;
644 struct video_device *v4l_dev;
645 struct tasklet_struct demux_tasklet;
646
647 struct SBufferHeader *nextBuffer;
648 enum KSSTATE State;
649 enum HWSTATE HWState;
650 u8 Stream;
651 u8 Flags;
652 u8 Mode;
653 IBufferExchange *pBufferExchange;
654 IBufferExchange *pBufferExchange2;
655
656 spinlock_t state_lock;
657 u16 nLines;
658 u16 nBytesPerLine;
659 u16 nVBILines;
660 u16 nBytesPerVBILine;
661 u16 itumode;
662 u32 Capture1Length;
663 u32 Capture2Length;
664 struct SRingBufferDescriptor RingBuffer;
665 struct SRingBufferDescriptor TSRingBuffer;
666 struct SRingBufferDescriptor TSIdleBuffer;
667
668 u32 DataFormatFlags;
669
670 int AudioDTOUpdated;
671 u32 AudioDTOValue;
672
673 int (*set_tone)(struct dvb_frontend *, fe_sec_tone_mode_t);
674 u8 lnbh;
675
676 /* stuff from analog driver */
677
678 int minor;
679 struct mychip *mychip;
680 struct snd_card *soundcard;
681 u8 *evenbuffer;
682 u8 dma_on;
683 int soundstreamon;
684 int audiomute;
685 int soundbuffisallocated;
686 int sndbuffflag;
687 int tun_rdy;
688 int dec_rdy;
689 int tun_dec_rdy;
690 int lastbufferflag;
691
692 struct ngene_tvnorm *tvnorms;
693 int tvnorm_num;
694 int tvnorm;
695
696#ifdef NGENE_V4L
697 int videousers;
698 struct v4l2_prio_state prio;
699 struct ngene_vopen init;
700 int resources;
701 struct v4l2_framebuffer fbuf;
702 struct ngene_buffer *screen; /* overlay */
703 struct list_head capture; /* video capture queue */
704 spinlock_t s_lock;
705 struct semaphore reslock;
706#endif
707
708 int running;
709};
710
711struct ngene;
712
713typedef void (rx_cb_t)(struct ngene *, u32, u8);
714typedef void (tx_cb_t)(struct ngene *, u32);
715
716struct ngene {
717 int nr;
718 struct pci_dev *pci_dev;
719 unsigned char *iomem;
720
721 /*struct i2c_adapter i2c_adapter;*/
722
723 u32 device_version;
724 u32 fw_interface_version;
725 u32 icounts;
726
727 u8 *CmdDoneByte;
728 int BootFirmware;
729 void *OverflowBuffer;
730 dma_addr_t PAOverflowBuffer;
731 void *FWInterfaceBuffer;
732 dma_addr_t PAFWInterfaceBuffer;
733 u8 *ngenetohost;
734 u8 *hosttongene;
735
736 struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE];
737 int EventQueueOverflowCount;
738 int EventQueueOverflowFlag;
739 struct tasklet_struct event_tasklet;
740 struct EVENT_BUFFER *EventBuffer;
741 int EventQueueWriteIndex;
742 int EventQueueReadIndex;
743
744 wait_queue_head_t cmd_wq;
745 int cmd_done;
746 struct semaphore cmd_mutex;
747 struct semaphore stream_mutex;
748 struct semaphore pll_mutex;
749 struct semaphore i2c_switch_mutex;
750 int i2c_current_channel;
751 int i2c_current_bus;
752 spinlock_t cmd_lock;
753
754 struct dvb_adapter adapter[MAX_STREAM];
755 struct ngene_channel channel[MAX_STREAM];
756
757 struct ngene_info *card_info;
758
759 tx_cb_t *TxEventNotify;
760 rx_cb_t *RxEventNotify;
761 int tx_busy;
762 wait_queue_head_t tx_wq;
763 wait_queue_head_t rx_wq;
764#define UART_RBUF_LEN 4096
765 u8 uart_rbuf[UART_RBUF_LEN];
766 int uart_rp, uart_wp;
767
768 u8 *tsout_buf;
769#define TSOUT_BUF_SIZE (512*188*8)
770 struct dvb_ringbuffer tsout_rbuf;
771
772 u8 *ain_buf;
773#define AIN_BUF_SIZE (128*1024)
774 struct dvb_ringbuffer ain_rbuf;
775
776
777 u8 *vin_buf;
778#define VIN_BUF_SIZE (4*1920*1080)
779 struct dvb_ringbuffer vin_rbuf;
780
781 unsigned long exp_val;
782 int prev_cmd;
783};
784
785struct ngene_info {
786 int type;
787#define NGENE_APP 0
788#define NGENE_TERRATEC 1
789#define NGENE_SIDEWINDER 2
790#define NGENE_RACER 3
791#define NGENE_VIPER 4
792#define NGENE_PYTHON 5
793#define NGENE_VBOX_V1 6
794#define NGENE_VBOX_V2 7
795
796 int fw_version;
797 char *name;
798
799 int io_type[MAX_STREAM];
800#define NGENE_IO_NONE 0
801#define NGENE_IO_TV 1
802#define NGENE_IO_HDTV 2
803#define NGENE_IO_TSIN 4
804#define NGENE_IO_TSOUT 8
805#define NGENE_IO_AIN 16
806
807 void *fe_config[4];
808 void *tuner_config[4];
809
810 int (*demod_attach[4])(struct ngene_channel *);
811 int (*tuner_attach[4])(struct ngene_channel *);
812
813 u8 avf[4];
814 u8 msp[4];
815 u8 demoda[4];
816 u8 lnb[4];
817 int i2c_access;
818 u8 ntsc;
819 u8 tsf[4];
820 u8 i2s[4];
821
822 int (*gate_ctrl)(struct dvb_frontend *, int);
823 int (*switch_ctrl)(struct ngene_channel *, int, int);
824};
825
826#ifdef NGENE_V4L
827struct ngene_format{
828 char *name;
829 int fourcc; /* video4linux 2 */
830 int btformat; /* BT848_COLOR_FMT_* */
831 int format;
832 int btswap; /* BT848_COLOR_CTL_* */
833 int depth; /* bit/pixel */
834 int flags;
835 int hshift, vshift; /* for planar modes */
836 int palette;
837};
838
839#define RESOURCE_OVERLAY 1
840#define RESOURCE_VIDEO 2
841#define RESOURCE_VBI 4
842
843struct ngene_buffer {
844 /* common v4l buffer stuff -- must be first */
845 struct videobuf_buffer vb;
846
847 /* ngene specific */
848 const struct ngene_format *fmt;
849 int tvnorm;
850 int btformat;
851 int btswap;
852};
853#endif
854
855
856#endif
857
858/* LocalWords: Endif
859 */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-17 02:12:20 -0500