73 files changed, 13138 insertions, 6172 deletions

diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index d7c4837fa71c..cd7f9b7cbffa 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -201,6 +201,21 @@ config DVB_SI21XX
         help
           A DVB-S tuner module. Say Y when you want to support this frontend.
 
+config DVB_DS3000
+        tristate "Montage Tehnology DS3000 based"
+        depends on DVB_CORE && I2C
+        default m if DVB_FE_CUSTOMISE
+        help
+          A DVB-S/S2 tuner module. Say Y when you want to support this frontend.
+
+config DVB_MB86A16
+        tristate "Fujitsu MB86A16 based"
+        depends on DVB_CORE && I2C
+        default m if DVB_FE_CUSTOMISE
+        help
+          A DVB-S/DSS Direct Conversion reveiver.
+          Say Y when you want to support this frontend.
+
 comment "DVB-T (terrestrial) frontends"
         depends on DVB_CORE
 
@@ -342,6 +357,13 @@ config DVB_AF9013
         help
           Say Y when you want to support this frontend.
 
+config DVB_EC100
+        tristate "E3C EC100"
+        depends on DVB_CORE && I2C
+        default m if DVB_FE_CUSTOMISE
+        help
+          Say Y when you want to support this frontend.
+
 comment "DVB-C (cable) frontends"
         depends on DVB_CORE
 
@@ -512,6 +534,15 @@ config DVB_TUNER_DIB0070
           This device is only used inside a SiP called together with a
           demodulator for now.
 
+config DVB_TUNER_DIB0090
+        tristate "DiBcom DiB0090 silicon base-band tuner"
+        depends on I2C
+        default m if DVB_FE_CUSTOMISE
+        help
+          A driver for the silicon baseband tuner DiB0090 from DiBcom.
+          This device is only used inside a SiP called together with a
+          demodulator for now.
+
 comment "SEC control devices for DVB-S"
         depends on DVB_CORE
 
@@ -557,6 +588,24 @@ config DVB_LGS8GXX
         help
           A DMB-TH tuner module. Say Y when you want to support this frontend.
 
+config DVB_ATBM8830
+        tristate "AltoBeam ATBM8830/8831 DMB-TH demodulator"
+        depends on DVB_CORE && I2C
+        default m if DVB_FE_CUSTOMISE
+        help
+          A DMB-TH tuner module. Say Y when you want to support this frontend.
+
+config DVB_TDA665x
+        tristate "TDA665x tuner"
+        depends on DVB_CORE && I2C
+        default m if DVB_FE_CUSTOMISE
+        help
+          Support for tuner modules based on Philips TDA6650/TDA6651 chips.
+          Say Y when you want to support this chip.
+
+          Currently supported tuners:
+          * Panasonic ENV57H12D5 (ET-50DT)
+
 comment "Tools to develop new frontends"
 
 config DVB_DUMMY_FE
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index 3523767e7a76..874e8ada4d1d 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_DVB_TDA10086) += tda10086.o
 obj-$(CONFIG_DVB_TDA826X) += tda826x.o
 obj-$(CONFIG_DVB_TDA8261) += tda8261.o
 obj-$(CONFIG_DVB_TUNER_DIB0070) += dib0070.o
+obj-$(CONFIG_DVB_TUNER_DIB0090) += dib0090.o
 obj-$(CONFIG_DVB_TUA6100) += tua6100.o
 obj-$(CONFIG_DVB_S5H1409) += s5h1409.o
 obj-$(CONFIG_DVB_TUNER_ITD1000) += itd1000.o
@@ -63,7 +64,9 @@ obj-$(CONFIG_DVB_TDA10048) += tda10048.o
 obj-$(CONFIG_DVB_TUNER_CX24113) += cx24113.o
 obj-$(CONFIG_DVB_S5H1411) += s5h1411.o
 obj-$(CONFIG_DVB_LGS8GL5) += lgs8gl5.o
+obj-$(CONFIG_DVB_TDA665x) += tda665x.o
 obj-$(CONFIG_DVB_LGS8GXX) += lgs8gxx.o
+obj-$(CONFIG_DVB_ATBM8830) += atbm8830.o
 obj-$(CONFIG_DVB_DUMMY_FE) += dvb_dummy_fe.o
 obj-$(CONFIG_DVB_AF9013) += af9013.o
 obj-$(CONFIG_DVB_CX24116) += cx24116.o
@@ -76,3 +79,6 @@ obj-$(CONFIG_DVB_STV0900) += stv0900.o
 obj-$(CONFIG_DVB_STV090x) += stv090x.o
 obj-$(CONFIG_DVB_STV6110x) += stv6110x.o
 obj-$(CONFIG_DVB_ISL6423) += isl6423.o
+obj-$(CONFIG_DVB_EC100) += ec100.o
+obj-$(CONFIG_DVB_DS3000) += ds3000.o
+obj-$(CONFIG_DVB_MB86A16) += mb86a16.o
diff --git a/drivers/media/dvb/frontends/af9013.h b/drivers/media/dvb/frontends/af9013.h
index 28b90c91c766..e90fa92b1c1d 100644
--- a/drivers/media/dvb/frontends/af9013.h
+++ b/drivers/media/dvb/frontends/af9013.h
@@ -44,6 +44,7 @@ enum af9013_tuner {
         AF9013_TUNER_MT2060_2   = 147, /* Microtune */
         AF9013_TUNER_TDA18271   = 156, /* NXP */
         AF9013_TUNER_QT1010A    = 162, /* Quantek */
+        AF9013_TUNER_TDA18218   = 179, /* NXP */
 };
 
 /* AF9013/5 GPIOs (mostly guessed)
diff --git a/drivers/media/dvb/frontends/atbm8830.c b/drivers/media/dvb/frontends/atbm8830.c
new file mode 100644
index 000000000000..43aac2f85c2e
--- /dev/null
+++ b/drivers/media/dvb/frontends/atbm8830.c
@@ -0,0 +1,511 @@
+/*
+ *    Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
+ *    ATBM8830, ATBM8831
+ *
+ *    Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/div64.h>
+#include "dvb_frontend.h"
+
+#include "atbm8830.h"
+#include "atbm8830_priv.h"
+
+#define dprintk(args...) \
+        do { \
+                if (debug) \
+                        printk(KERN_DEBUG "atbm8830: " args); \
+        } while (0)
+
+static int debug;
+
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
+
+static int atbm8830_write_reg(struct atbm_state *priv, u16 reg, u8 data)
+{
+        int ret = 0;
+        u8 dev_addr;
+        u8 buf1[] = { reg >> 8, reg & 0xFF };
+        u8 buf2[] = { data };
+        struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
+        struct i2c_msg msg2 = { .flags = 0, .buf = buf2, .len = 1 };
+
+        dev_addr = priv->config->demod_address;
+        msg1.addr = dev_addr;
+        msg2.addr = dev_addr;
+
+        if (debug >= 2)
+                printk(KERN_DEBUG "%s: reg=0x%04X, data=0x%02X\n",
+                        __func__, reg, data);
+
+        ret = i2c_transfer(priv->i2c, &msg1, 1);
+        if (ret != 1)
+                return -EIO;
+
+        ret = i2c_transfer(priv->i2c, &msg2, 1);
+        return (ret != 1) ? -EIO : 0;
+}
+
+static int atbm8830_read_reg(struct atbm_state *priv, u16 reg, u8 *p_data)
+{
+        int ret;
+        u8 dev_addr;
+
+        u8 buf1[] = { reg >> 8, reg & 0xFF };
+        u8 buf2[] = { 0 };
+        struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
+        struct i2c_msg msg2 = { .flags = I2C_M_RD, .buf = buf2, .len = 1 };
+
+        dev_addr = priv->config->demod_address;
+        msg1.addr = dev_addr;
+        msg2.addr = dev_addr;
+
+        ret = i2c_transfer(priv->i2c, &msg1, 1);
+        if (ret != 1) {
+                dprintk(KERN_DEBUG "%s: error reg=0x%04x, ret=%i\n",
+                        __func__, reg, ret);
+                return -EIO;
+        }
+
+        ret = i2c_transfer(priv->i2c, &msg2, 1);
+        if (ret != 1)
+                return -EIO;
+
+        *p_data = buf2[0];
+        if (debug >= 2)
+                printk(KERN_DEBUG "%s: reg=0x%04X, data=0x%02X\n",
+                        __func__, reg, buf2[0]);
+
+        return 0;
+}
+
+/* Lock register latch so that multi-register read is atomic */
+static inline int atbm8830_reglatch_lock(struct atbm_state *priv, int lock)
+{
+        return atbm8830_write_reg(priv, REG_READ_LATCH, lock ? 1 : 0);
+}
+
+static int set_osc_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
+{
+        u32 val;
+        u64 t;
+
+        /* 0x100000 * freq / 30.4MHz */
+        t = (u64)0x100000 * freq;
+        do_div(t, 30400);
+        val = t;
+
+        atbm8830_write_reg(priv, REG_OSC_CLK, val);
+        atbm8830_write_reg(priv, REG_OSC_CLK + 1, val >> 8);
+        atbm8830_write_reg(priv, REG_OSC_CLK + 2, val >> 16);
+
+        return 0;
+}
+
+static int set_if_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
+{
+
+        u32 fs = priv->config->osc_clk_freq;
+        u64 t;
+        u32 val;
+        u8 dat;
+
+        if (freq != 0) {
+                /* 2 * PI * (freq - fs) / fs * (2 ^ 22) */
+                t = (u64) 2 * 31416 * (freq - fs);
+                t <<= 22;
+                do_div(t, fs);
+                do_div(t, 1000);
+                val = t;
+
+                atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 1);
+                atbm8830_write_reg(priv, REG_IF_FREQ, val);
+                atbm8830_write_reg(priv, REG_IF_FREQ+1, val >> 8);
+                atbm8830_write_reg(priv, REG_IF_FREQ+2, val >> 16);
+
+                atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
+                dat &= 0xFC;
+                atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
+        } else {
+                /* Zero IF */
+                atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 0);
+
+                atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
+                dat &= 0xFC;
+                dat |= 0x02;
+                atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
+
+                if (priv->config->zif_swap_iq)
+                        atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x03);
+                else
+                        atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x01);
+        }
+
+        return 0;
+}
+
+static int is_locked(struct atbm_state *priv, u8 *locked)
+{
+        u8 status;
+
+        atbm8830_read_reg(priv, REG_LOCK_STATUS, &status);
+
+        if (locked != NULL)
+                *locked = (status == 1);
+        return 0;
+}
+
+static int set_agc_config(struct atbm_state *priv,
+        u8 min, u8 max, u8 hold_loop)
+{
+        /* no effect if both min and max are zero */
+        if (!min && !max)
+            return 0;
+
+        atbm8830_write_reg(priv, REG_AGC_MIN, min);
+        atbm8830_write_reg(priv, REG_AGC_MAX, max);
+        atbm8830_write_reg(priv, REG_AGC_HOLD_LOOP, hold_loop);
+
+        return 0;
+}
+
+static int set_static_channel_mode(struct atbm_state *priv)
+{
+        int i;
+
+        for (i = 0; i < 5; i++)
+                atbm8830_write_reg(priv, 0x099B + i, 0x08);
+
+        atbm8830_write_reg(priv, 0x095B, 0x7F);
+        atbm8830_write_reg(priv, 0x09CB, 0x01);
+        atbm8830_write_reg(priv, 0x09CC, 0x7F);
+        atbm8830_write_reg(priv, 0x09CD, 0x7F);
+        atbm8830_write_reg(priv, 0x0E01, 0x20);
+
+        /* For single carrier */
+        atbm8830_write_reg(priv, 0x0B03, 0x0A);
+        atbm8830_write_reg(priv, 0x0935, 0x10);
+        atbm8830_write_reg(priv, 0x0936, 0x08);
+        atbm8830_write_reg(priv, 0x093E, 0x08);
+        atbm8830_write_reg(priv, 0x096E, 0x06);
+
+        /* frame_count_max0 */
+        atbm8830_write_reg(priv, 0x0B09, 0x00);
+        /* frame_count_max1 */
+        atbm8830_write_reg(priv, 0x0B0A, 0x08);
+
+        return 0;
+}
+
+static int set_ts_config(struct atbm_state *priv)
+{
+        const struct atbm8830_config *cfg = priv->config;
+
+        /*Set parallel/serial ts mode*/
+        atbm8830_write_reg(priv, REG_TS_SERIAL, cfg->serial_ts ? 1 : 0);
+        atbm8830_write_reg(priv, REG_TS_CLK_MODE, cfg->serial_ts ? 1 : 0);
+        /*Set ts sampling edge*/
+        atbm8830_write_reg(priv, REG_TS_SAMPLE_EDGE,
+                cfg->ts_sampling_edge ? 1 : 0);
+        /*Set ts clock freerun*/
+        atbm8830_write_reg(priv, REG_TS_CLK_FREERUN,
+                cfg->ts_clk_gated ? 0 : 1);
+
+        return 0;
+}
+
+static int atbm8830_init(struct dvb_frontend *fe)
+{
+        struct atbm_state *priv = fe->demodulator_priv;
+        const struct atbm8830_config *cfg = priv->config;
+
+        /*Set oscillator frequency*/
+        set_osc_freq(priv, cfg->osc_clk_freq);
+
+        /*Set IF frequency*/
+        set_if_freq(priv, cfg->if_freq);
+
+        /*Set AGC Config*/
+        set_agc_config(priv, cfg->agc_min, cfg->agc_max,
+                cfg->agc_hold_loop);
+
+        /*Set static channel mode*/
+        set_static_channel_mode(priv);
+
+        set_ts_config(priv);
+        /*Turn off DSP reset*/
+        atbm8830_write_reg(priv, 0x000A, 0);
+
+        /*SW version test*/
+        atbm8830_write_reg(priv, 0x020C, 11);
+
+        /* Run */
+        atbm8830_write_reg(priv, REG_DEMOD_RUN, 1);
+
+        return 0;
+}
+
+
+static void atbm8830_release(struct dvb_frontend *fe)
+{
+        struct atbm_state *state = fe->demodulator_priv;
+        dprintk("%s\n", __func__);
+
+        kfree(state);
+}
+
+static int atbm8830_set_fe(struct dvb_frontend *fe,
+                          struct dvb_frontend_parameters *fe_params)
+{
+        struct atbm_state *priv = fe->demodulator_priv;
+        int i;
+        u8 locked = 0;
+        dprintk("%s\n", __func__);
+
+        /* set frequency */
+        if (fe->ops.tuner_ops.set_params) {
+                if (fe->ops.i2c_gate_ctrl)
+                        fe->ops.i2c_gate_ctrl(fe, 1);
+                fe->ops.tuner_ops.set_params(fe, fe_params);
+                if (fe->ops.i2c_gate_ctrl)
+                        fe->ops.i2c_gate_ctrl(fe, 0);
+        }
+
+        /* start auto lock */
+        for (i = 0; i < 10; i++) {
+                mdelay(100);
+                dprintk("Try %d\n", i);
+                is_locked(priv, &locked);
+                if (locked != 0) {
+                        dprintk("ATBM8830 locked!\n");
+                        break;
+                }
+        }
+
+        return 0;
+}
+
+static int atbm8830_get_fe(struct dvb_frontend *fe,
+                          struct dvb_frontend_parameters *fe_params)
+{
+        dprintk("%s\n", __func__);
+
+        /* TODO: get real readings from device */
+        /* inversion status */
+        fe_params->inversion = INVERSION_OFF;
+
+        /* bandwidth */
+        fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
+
+        fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
+        fe_params->u.ofdm.code_rate_LP = FEC_AUTO;
+
+        fe_params->u.ofdm.constellation = QAM_AUTO;
+
+        /* transmission mode */
+        fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
+
+        /* guard interval */
+        fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
+
+        /* hierarchy */
+        fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
+
+        return 0;
+}
+
+static int atbm8830_get_tune_settings(struct dvb_frontend *fe,
+        struct dvb_frontend_tune_settings *fesettings)
+{
+        fesettings->min_delay_ms = 0;
+        fesettings->step_size = 0;
+        fesettings->max_drift = 0;
+        return 0;
+}
+
+static int atbm8830_read_status(struct dvb_frontend *fe, fe_status_t *fe_status)
+{
+        struct atbm_state *priv = fe->demodulator_priv;
+        u8 locked = 0;
+        u8 agc_locked = 0;
+
+        dprintk("%s\n", __func__);
+        *fe_status = 0;
+
+        is_locked(priv, &locked);
+        if (locked) {
+                *fe_status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
+                        FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+        }
+        dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
+
+        atbm8830_read_reg(priv, REG_AGC_LOCK, &agc_locked);
+        dprintk("AGC Lock: %d\n", agc_locked);
+
+        return 0;
+}
+
+static int atbm8830_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+        struct atbm_state *priv = fe->demodulator_priv;
+        u32 frame_err;
+        u8 t;
+
+        dprintk("%s\n", __func__);
+
+        atbm8830_reglatch_lock(priv, 1);
+
+        atbm8830_read_reg(priv, REG_FRAME_ERR_CNT + 1, &t);
+        frame_err = t & 0x7F;
+        frame_err <<= 8;
+        atbm8830_read_reg(priv, REG_FRAME_ERR_CNT, &t);
+        frame_err |= t;
+
+        atbm8830_reglatch_lock(priv, 0);
+
+        *ber = frame_err * 100 / 32767;
+
+        dprintk("%s: ber=0x%x\n", __func__, *ber);
+        return 0;
+}
+
+static int atbm8830_read_signal_strength(struct dvb_frontend *fe, u16 *signal)
+{
+        struct atbm_state *priv = fe->demodulator_priv;
+        u32 pwm;
+        u8 t;
+
+        dprintk("%s\n", __func__);
+        atbm8830_reglatch_lock(priv, 1);
+
+        atbm8830_read_reg(priv, REG_AGC_PWM_VAL + 1, &t);
+        pwm = t & 0x03;
+        pwm <<= 8;
+        atbm8830_read_reg(priv, REG_AGC_PWM_VAL, &t);
+        pwm |= t;
+
+        atbm8830_reglatch_lock(priv, 0);
+
+        dprintk("AGC PWM = 0x%02X\n", pwm);
+        pwm = 0x400 - pwm;
+
+        *signal = pwm * 0x10000 / 0x400;
+
+        return 0;
+}
+
+static int atbm8830_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+        dprintk("%s\n", __func__);
+        *snr = 0;
+        return 0;
+}
+
+static int atbm8830_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+        dprintk("%s\n", __func__);
+        *ucblocks = 0;
+        return 0;
+}
+
+static int atbm8830_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
+{
+        struct atbm_state *priv = fe->demodulator_priv;
+
+        return atbm8830_write_reg(priv, REG_I2C_GATE, enable ? 1 : 0);
+}
+
+static struct dvb_frontend_ops atbm8830_ops = {
+        .info = {
+                .name = "AltoBeam ATBM8830/8831 DMB-TH",
+                .type = FE_OFDM,
+                .frequency_min = 474000000,
+                .frequency_max = 858000000,
+                .frequency_stepsize = 10000,
+                .caps =
+                        FE_CAN_FEC_AUTO |
+                        FE_CAN_QAM_AUTO |
+                        FE_CAN_TRANSMISSION_MODE_AUTO |
+                        FE_CAN_GUARD_INTERVAL_AUTO
+        },
+
+        .release = atbm8830_release,
+
+        .init = atbm8830_init,
+        .sleep = NULL,
+        .write = NULL,
+        .i2c_gate_ctrl = atbm8830_i2c_gate_ctrl,
+
+        .set_frontend = atbm8830_set_fe,
+        .get_frontend = atbm8830_get_fe,
+        .get_tune_settings = atbm8830_get_tune_settings,
+
+        .read_status = atbm8830_read_status,
+        .read_ber = atbm8830_read_ber,
+        .read_signal_strength = atbm8830_read_signal_strength,
+        .read_snr = atbm8830_read_snr,
+        .read_ucblocks = atbm8830_read_ucblocks,
+};
+
+struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
+        struct i2c_adapter *i2c)
+{
+        struct atbm_state *priv = NULL;
+        u8 data = 0;
+
+        dprintk("%s()\n", __func__);
+
+        if (config == NULL || i2c == NULL)
+                return NULL;
+
+        priv = kzalloc(sizeof(struct atbm_state), GFP_KERNEL);
+        if (priv == NULL)
+                goto error_out;
+
+        priv->config = config;
+        priv->i2c = i2c;
+
+        /* check if the demod is there */
+        if (atbm8830_read_reg(priv, REG_CHIP_ID, &data) != 0) {
+                dprintk("%s atbm8830/8831 not found at i2c addr 0x%02X\n",
+                        __func__, priv->config->demod_address);
+                goto error_out;
+        }
+        dprintk("atbm8830 chip id: 0x%02X\n", data);
+
+        memcpy(&priv->frontend.ops, &atbm8830_ops,
+               sizeof(struct dvb_frontend_ops));
+        priv->frontend.demodulator_priv = priv;
+
+        atbm8830_init(&priv->frontend);
+
+        atbm8830_i2c_gate_ctrl(&priv->frontend, 1);
+
+        return &priv->frontend;
+
+error_out:
+        dprintk("%s() error_out\n", __func__);
+        kfree(priv);
+        return NULL;
+
+}
+EXPORT_SYMBOL(atbm8830_attach);
+
+MODULE_DESCRIPTION("AltoBeam ATBM8830/8831 GB20600 demodulator driver");
+MODULE_AUTHOR("David T. L. Wong <davidtlwong@gmail.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/atbm8830.h b/drivers/media/dvb/frontends/atbm8830.h
new file mode 100644
index 000000000000..e8149f393300
--- /dev/null
+++ b/drivers/media/dvb/frontends/atbm8830.h
@@ -0,0 +1,76 @@
+/*
+ *    Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
+ *    ATBM8830, ATBM8831
+ *
+ *    Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ATBM8830_H__
+#define __ATBM8830_H__
+
+#include <linux/dvb/frontend.h>
+#include <linux/i2c.h>
+
+#define ATBM8830_PROD_8830 0
+#define ATBM8830_PROD_8831 1
+
+struct atbm8830_config {
+
+        /* product type */
+        u8 prod;
+
+        /* the demodulator's i2c address */
+        u8 demod_address;
+
+        /* parallel or serial transport stream */
+        u8 serial_ts;
+
+        /* transport stream clock output only when receving valid stream */
+        u8 ts_clk_gated;
+
+        /* Decoder sample TS data at rising edge of clock */
+        u8 ts_sampling_edge;
+
+        /* Oscillator clock frequency */
+        u32 osc_clk_freq; /* in kHz */
+
+        /* IF frequency */
+        u32 if_freq; /* in kHz */
+
+        /* Swap I/Q for zero IF */
+        u8 zif_swap_iq;
+
+        /* Tuner AGC settings */
+        u8 agc_min;
+        u8 agc_max;
+        u8 agc_hold_loop;
+};
+
+#if defined(CONFIG_DVB_ATBM8830) || \
+        (defined(CONFIG_DVB_ATBM8830_MODULE) && defined(MODULE))
+extern struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
+                struct i2c_adapter *i2c);
+#else
+static inline
+struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
+                struct i2c_adapter *i2c) {
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return NULL;
+}
+#endif /* CONFIG_DVB_ATBM8830 */
+
+#endif /* __ATBM8830_H__ */
diff --git a/drivers/media/dvb/frontends/atbm8830_priv.h b/drivers/media/dvb/frontends/atbm8830_priv.h
new file mode 100644
index 000000000000..ce960f76092a
--- /dev/null
+++ b/drivers/media/dvb/frontends/atbm8830_priv.h
@@ -0,0 +1,75 @@
+/*
+ *    Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
+ *    ATBM8830, ATBM8831
+ *
+ *    Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+ 
+#ifndef __ATBM8830_PRIV_H
+#define __ATBM8830_PRIV_H
+
+struct atbm_state {
+        struct i2c_adapter *i2c;
+        /* configuration settings */
+        const struct atbm8830_config *config;
+        struct dvb_frontend frontend;
+};
+
+#define REG_CHIP_ID     0x0000
+#define REG_TUNER_BASEBAND      0x0001
+#define REG_DEMOD_RUN   0x0004
+#define REG_DSP_RESET   0x0005
+#define REG_RAM_RESET   0x0006
+#define REG_ADC_RESET   0x0007
+#define REG_TSPORT_RESET        0x0008
+#define REG_BLKERR_POL  0x000C
+#define REG_I2C_GATE    0x0103
+#define REG_TS_SAMPLE_EDGE      0x0301
+#define REG_TS_PKT_LEN_204      0x0302
+#define REG_TS_PKT_LEN_AUTO     0x0303
+#define REG_TS_SERIAL   0x0305
+#define REG_TS_CLK_FREERUN      0x0306
+#define REG_TS_VALID_MODE       0x0307
+#define REG_TS_CLK_MODE 0x030B /* 1 for serial, 0 for parallel */
+
+#define REG_TS_ERRBIT_USE       0x030C
+#define REG_LOCK_STATUS 0x030D
+#define REG_ADC_CONFIG  0x0602
+#define REG_CARRIER_OFFSET      0x0827 /* 0x0827-0x0829 little endian */
+#define REG_DETECTED_PN_MODE    0x082D
+#define REG_READ_LATCH  0x084D
+#define REG_IF_FREQ     0x0A00 /* 0x0A00-0x0A02 little endian */
+#define REG_OSC_CLK     0x0A03 /* 0x0A03-0x0A05 little endian */
+#define REG_BYPASS_CCI  0x0A06
+#define REG_ANALOG_LUMA_DETECTED        0x0A25
+#define REG_ANALOG_AUDIO_DETECTED       0x0A26
+#define REG_ANALOG_CHROMA_DETECTED      0x0A39
+#define REG_FRAME_ERR_CNT       0x0B04
+#define REG_USE_EXT_ADC 0x0C00
+#define REG_SWAP_I_Q    0x0C01
+#define REG_TPS_MANUAL  0x0D01
+#define REG_TPS_CONFIG  0x0D02
+#define REG_BYPASS_DEINTERLEAVER        0x0E00
+#define REG_AGC_TARGET  0x1003 /* 0x1003-0x1005 little endian */
+#define REG_AGC_MIN     0x1020
+#define REG_AGC_MAX     0x1023
+#define REG_AGC_LOCK    0x1027
+#define REG_AGC_PWM_VAL 0x1028 /* 0x1028-0x1029 little endian */
+#define REG_AGC_HOLD_LOOP       0x1031
+
+#endif
+
diff --git a/drivers/media/dvb/frontends/au8522_decoder.c b/drivers/media/dvb/frontends/au8522_decoder.c
index 74981ee923c8..24268ef2753d 100644
--- a/drivers/media/dvb/frontends/au8522_decoder.c
+++ b/drivers/media/dvb/frontends/au8522_decoder.c
@@ -23,7 +23,6 @@
 /* Developer notes:
  *
  * VBI support is not yet working
- * Saturation and hue setting are not yet working
  * Enough is implemented here for CVBS and S-Video inputs, but the actual
  *  analog demodulator code isn't implemented (not needed for xc5000 since it
  *  has its own demodulator and outputs CVBS)
@@ -63,7 +62,7 @@ struct au8522_register_config {
    The values are as follows from left to right
    0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13"
 */
-struct au8522_register_config filter_coef[] = {
+static const struct au8522_register_config filter_coef[] = {
         {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
         {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
         {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
@@ -105,7 +104,7 @@ struct au8522_register_config filter_coef[] = {
    0="SIF" 1="ATVRF/ATVRF13"
    Note: the "ATVRF/ATVRF13" mode has never been tested
 */
-struct au8522_register_config lpfilter_coef[] = {
+static const struct au8522_register_config lpfilter_coef[] = {
         {0x060b, {0x21, 0x0b} },
         {0x060c, {0xad, 0xad} },
         {0x060d, {0x70, 0xf0} },
@@ -236,8 +235,10 @@ static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode)
         state->contrast = 0x79;
         au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
         au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
+        state->saturation = 0x80;
         au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
         au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
+        state->hue = 0x00;
 
         /* Other decoder registers */
         au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
@@ -315,7 +316,7 @@ static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode)
         if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 ||
             input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) {
                 /* Despite what the table says, for the HVR-950q we still need
-                   to be in CVBS mode for the S-Video input (reason uknown). */
+                   to be in CVBS mode for the S-Video input (reason unknown). */
                 /* filter_coef_type = 3; */
                 filter_coef_type = 5;
         } else {
@@ -504,7 +505,19 @@ static int au8522_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
                                 ctrl->value);
                 break;
         case V4L2_CID_SATURATION:
+                state->saturation = ctrl->value;
+                au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
+                                ctrl->value);
+                au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
+                                ctrl->value);
+                break;
         case V4L2_CID_HUE:
+                state->hue = ctrl->value;
+                au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
+                                ctrl->value >> 8);
+                au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
+                                ctrl->value & 0xFF);
+                break;
         case V4L2_CID_AUDIO_VOLUME:
         case V4L2_CID_AUDIO_BASS:
         case V4L2_CID_AUDIO_TREBLE:
@@ -534,7 +547,11 @@ static int au8522_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
                 ctrl->value = state->contrast;
                 break;
         case V4L2_CID_SATURATION:
+                ctrl->value = state->saturation;
+                break;
         case V4L2_CID_HUE:
+                ctrl->value = state->hue;
+                break;
         case V4L2_CID_AUDIO_VOLUME:
         case V4L2_CID_AUDIO_BASS:
         case V4L2_CID_AUDIO_TREBLE:
@@ -632,8 +649,9 @@ static int au8522_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
         case V4L2_CID_BRIGHTNESS:
                 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
         case V4L2_CID_SATURATION:
+                return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
         case V4L2_CID_HUE:
-                /* Not yet implemented */
+                return v4l2_ctrl_query_fill(qc, -32768, 32768, 1, 0);
         default:
                 break;
         }
diff --git a/drivers/media/dvb/frontends/au8522_dig.c b/drivers/media/dvb/frontends/au8522_dig.c
index 956b80f4979c..a1fed0fa8ed4 100644
--- a/drivers/media/dvb/frontends/au8522_dig.c
+++ b/drivers/media/dvb/frontends/au8522_dig.c
@@ -23,7 +23,6 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/string.h>
-#include <linux/slab.h>
 #include <linux/delay.h>
 #include "dvb_frontend.h"
 #include "au8522.h"
diff --git a/drivers/media/dvb/frontends/au8522_priv.h b/drivers/media/dvb/frontends/au8522_priv.h
index f328f2b3ad3d..c74c4e72fe91 100644
--- a/drivers/media/dvb/frontends/au8522_priv.h
+++ b/drivers/media/dvb/frontends/au8522_priv.h
@@ -62,6 +62,8 @@ struct au8522_state {
         u32 rev;
         u8 brightness;
         u8 contrast;
+        u8 saturation;
+        s16 hue;
 };
 
 /* These are routines shared by both the VSB/QAM demodulator and the analog
diff --git a/drivers/media/dvb/frontends/cx24110.c b/drivers/media/dvb/frontends/cx24110.c
index ffbcfabd83f0..00a4e8f03304 100644
--- a/drivers/media/dvb/frontends/cx24110.c
+++ b/drivers/media/dvb/frontends/cx24110.c
@@ -1,4 +1,4 @@
-        /*
+/*
     cx24110 - Single Chip Satellite Channel Receiver driver module
 
     Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on
@@ -96,7 +96,7 @@ static struct {u8 reg; u8 data;} cx24110_regdata[]=
          {0x42,0x00}, /* @ middle bytes " */
          {0x43,0x00}, /* @ LSB          " */
                       /* leave the carrier tracking loop parameters on default */
-                      /* leave the bit timing loop parameters at gefault */
+                      /* leave the bit timing loop parameters at default */
          {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
                       /* the cx24108 data sheet for symbol rates above 15MS/s */
          {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
diff --git a/drivers/media/dvb/frontends/cx24113.c b/drivers/media/dvb/frontends/cx24113.c
index 075b2b57cf09..e9ee55592fd3 100644
--- a/drivers/media/dvb/frontends/cx24113.c
+++ b/drivers/media/dvb/frontends/cx24113.c
@@ -589,7 +589,7 @@ struct dvb_frontend *cx24113_attach(struct dvb_frontend *fe,
                 info("detected CX24113 variant\n");
                 break;
         case REV_CX24113:
-                info("sucessfully detected\n");
+                info("successfully detected\n");
                 break;
         default:
                 err("unsupported device id: %x\n", state->rev);
diff --git a/drivers/media/dvb/frontends/dib0070.c b/drivers/media/dvb/frontends/dib0070.c
index 2be17b93e0bd..d4e466a90e43 100644
--- a/drivers/media/dvb/frontends/dib0070.c
+++ b/drivers/media/dvb/frontends/dib0070.c
@@ -25,6 +25,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/slab.h>
 #include <linux/i2c.h>
 
 #include "dvb_frontend.h"
@@ -49,21 +50,6 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
 #define DIB0070_P1G  0x03
 #define DIB0070S_P1A 0x02
 
-enum frontend_tune_state {
-        CT_TUNER_START = 10,
-        CT_TUNER_STEP_0,
-        CT_TUNER_STEP_1,
-        CT_TUNER_STEP_2,
-        CT_TUNER_STEP_3,
-        CT_TUNER_STEP_4,
-        CT_TUNER_STEP_5,
-        CT_TUNER_STEP_6,
-        CT_TUNER_STEP_7,
-        CT_TUNER_STOP,
-};
-
-#define FE_CALLBACK_TIME_NEVER 0xffffffff
-
 struct dib0070_state {
         struct i2c_adapter *i2c;
         struct dvb_frontend *fe;
@@ -71,10 +57,10 @@ struct dib0070_state {
         u16 wbd_ff_offset;
         u8 revision;
 
-        enum frontend_tune_state tune_state;
-        u32 current_rf;
+    enum frontend_tune_state tune_state;
+    u32 current_rf;
 
-        /* for the captrim binary search */
+    /* for the captrim binary search */
         s8 step;
         u16 adc_diff;
 
@@ -85,7 +71,7 @@ struct dib0070_state {
         const struct dib0070_tuning *current_tune_table_index;
         const struct dib0070_lna_match *lna_match;
 
-        u8 wbd_gain_current;
+    u8  wbd_gain_current;
         u16 wbd_offset_3_3[2];
 };
 
@@ -93,8 +79,8 @@ static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg)
 {
         u8 b[2];
         struct i2c_msg msg[2] = {
-                {.addr = state->cfg->i2c_address,.flags = 0,.buf = &reg,.len = 1},
-                {.addr = state->cfg->i2c_address,.flags = I2C_M_RD,.buf = b,.len = 2},
+                { .addr = state->cfg->i2c_address, .flags = 0,        .buf = &reg, .len = 1 },
+                { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = b,  .len = 2 },
         };
         if (i2c_transfer(state->i2c, msg, 2) != 2) {
                 printk(KERN_WARNING "DiB0070 I2C read failed\n");
@@ -106,7 +92,7 @@ static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg)
 static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
 {
         u8 b[3] = { reg, val >> 8, val & 0xff };
-        struct i2c_msg msg = {.addr = state->cfg->i2c_address,.flags = 0,.buf = b,.len = 3 };
+        struct i2c_msg msg = { .addr = state->cfg->i2c_address, .flags = 0, .buf = b, .len = 3 };
         if (i2c_transfer(state->i2c, &msg, 1) != 1) {
                 printk(KERN_WARNING "DiB0070 I2C write failed\n");
                 return -EREMOTEIO;
@@ -124,30 +110,30 @@ static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
 
 static int dib0070_set_bandwidth(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
 {
-        struct dib0070_state *state = fe->tuner_priv;
-        u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
-
-        if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 7000)
-                tmp |= (0 << 14);
-        else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 6000)
-                tmp |= (1 << 14);
-        else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 5000)
-                tmp |= (2 << 14);
-        else
-                tmp |= (3 << 14);
-
-        dib0070_write_reg(state, 0x02, tmp);
-
-        /* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */
-        if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
-                u16 value = dib0070_read_reg(state, 0x17);
-
-                dib0070_write_reg(state, 0x17, value & 0xfffc);
-                tmp = dib0070_read_reg(state, 0x01) & 0x01ff;
-                dib0070_write_reg(state, 0x01, tmp | (60 << 9));
-
-                dib0070_write_reg(state, 0x17, value);
-        }
+    struct dib0070_state *state = fe->tuner_priv;
+    u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
+
+    if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 7000)
+        tmp |= (0 << 14);
+    else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 6000)
+        tmp |= (1 << 14);
+    else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 5000)
+        tmp |= (2 << 14);
+    else
+        tmp |= (3 << 14);
+
+    dib0070_write_reg(state, 0x02, tmp);
+
+    /* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */
+    if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
+        u16 value = dib0070_read_reg(state, 0x17);
+
+        dib0070_write_reg(state, 0x17, value & 0xfffc);
+        tmp = dib0070_read_reg(state, 0x01) & 0x01ff;
+        dib0070_write_reg(state, 0x01, tmp | (60 << 9));
+
+        dib0070_write_reg(state, 0x17, value);
+    }
         return 0;
 }
 
@@ -160,14 +146,14 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
         if (*tune_state == CT_TUNER_STEP_0) {
 
                 dib0070_write_reg(state, 0x0f, 0xed10);
-                dib0070_write_reg(state, 0x17, 0x0034);
+                dib0070_write_reg(state, 0x17,    0x0034);
 
                 dib0070_write_reg(state, 0x18, 0x0032);
                 state->step = state->captrim = state->fcaptrim = 64;
                 state->adc_diff = 3000;
                 ret = 20;
 
-                *tune_state = CT_TUNER_STEP_1;
+        *tune_state = CT_TUNER_STEP_1;
         } else if (*tune_state == CT_TUNER_STEP_1) {
                 state->step /= 2;
                 dib0070_write_reg(state, 0x14, state->lo4 | state->captrim);
@@ -178,7 +164,7 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
 
                 adc = dib0070_read_reg(state, 0x19);
 
-                dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc * (u32) 1800 / (u32) 1024);
+                dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024);
 
                 if (adc >= 400) {
                         adc -= 400;
@@ -193,6 +179,8 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
                         state->adc_diff = adc;
                         state->fcaptrim = state->captrim;
 
+
+
                 }
                 state->captrim += (step_sign * state->step);
 
@@ -213,7 +201,7 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
 static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt)
 {
         struct dib0070_state *state = fe->tuner_priv;
-        u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
+    u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
         dprintk("CTRL_LO5: 0x%x", lo5);
         return dib0070_write_reg(state, 0x15, lo5);
 }
@@ -227,99 +215,99 @@ void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
                 dib0070_write_reg(state, 0x1a, 0x0000);
         } else {
                 dib0070_write_reg(state, 0x1b, 0x4112);
-                if (state->cfg->vga_filter != 0) {
-                        dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
-                        dprintk("vga filter register is set to %x", state->cfg->vga_filter);
-                } else
-                        dib0070_write_reg(state, 0x1a, 0x0009);
+        if (state->cfg->vga_filter != 0) {
+                dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
+                dprintk("vga filter register is set to %x", state->cfg->vga_filter);
+        } else
+                dib0070_write_reg(state, 0x1a, 0x0009);
         }
 }
 
 EXPORT_SYMBOL(dib0070_ctrl_agc_filter);
 struct dib0070_tuning {
-        u32 max_freq;           /* for every frequency less than or equal to that field: this information is correct */
-        u8 switch_trim;
-        u8 vco_band;
-        u8 hfdiv;
-        u8 vco_multi;
-        u8 presc;
-        u8 wbdmux;
-        u16 tuner_enable;
+    u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
+    u8 switch_trim;
+    u8 vco_band;
+    u8 hfdiv;
+    u8 vco_multi;
+    u8 presc;
+    u8 wbdmux;
+    u16 tuner_enable;
 };
 
 struct dib0070_lna_match {
-        u32 max_freq;           /* for every frequency less than or equal to that field: this information is correct */
-        u8 lna_band;
+    u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
+    u8 lna_band;
 };
 
 static const struct dib0070_tuning dib0070s_tuning_table[] = {
-        {570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800},    /* UHF */
-        {700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800},
-        {863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800},
-        {1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400},   /* LBAND */
-        {1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400},
-        {2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400},
-        {0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000},        /* SBAND */
+    {     570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800 }, /* UHF */
+    {     700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800 },
+    {     863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800 },
+    {    1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND */
+    {    1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
+    {    2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
+    { 0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000 }, /* SBAND */
 };
 
 static const struct dib0070_tuning dib0070_tuning_table[] = {
-        {115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000},   /* FM below 92MHz cannot be tuned */
-        {179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000},   /* VHF */
-        {189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000},
-        {250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000},
-        {569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800},    /* UHF */
-        {699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800},
-        {863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800},
-        {0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400},        /* LBAND or everything higher than UHF */
+    {     115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000 }, /* FM below 92MHz cannot be tuned */
+    {     179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000 }, /* VHF */
+    {     189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 },
+    {     250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 },
+    {     569999, 2, 1, 5,  6, 2, 2, 0x4000 | 0x0800 }, /* UHF */
+    {     699999, 2, 0, 1,  4, 2, 2, 0x4000 | 0x0800 },
+    {     863999, 2, 1, 1,  4, 2, 2, 0x4000 | 0x0800 },
+    { 0xffffffff, 0, 1, 0,  2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */
 };
 
 static const struct dib0070_lna_match dib0070_lna_flip_chip[] = {
-        {180000, 0},            /* VHF */
-        {188000, 1},
-        {196400, 2},
-        {250000, 3},
-        {550000, 0},            /* UHF */
-        {590000, 1},
-        {666000, 3},
-        {864000, 5},
-        {1500000, 0},           /* LBAND or everything higher than UHF */
-        {1600000, 1},
-        {2000000, 3},
-        {0xffffffff, 7},
+    {     180000, 0 }, /* VHF */
+    {     188000, 1 },
+    {     196400, 2 },
+    {     250000, 3 },
+    {     550000, 0 }, /* UHF */
+    {     590000, 1 },
+    {     666000, 3 },
+    {     864000, 5 },
+    {    1500000, 0 }, /* LBAND or everything higher than UHF */
+    {    1600000, 1 },
+    {    2000000, 3 },
+    { 0xffffffff, 7 },
 };
 
 static const struct dib0070_lna_match dib0070_lna[] = {
-        {180000, 0},            /* VHF */
-        {188000, 1},
-        {196400, 2},
-        {250000, 3},
-        {550000, 2},            /* UHF */
-        {650000, 3},
-        {750000, 5},
-        {850000, 6},
-        {864000, 7},
-        {1500000, 0},           /* LBAND or everything higher than UHF */
-        {1600000, 1},
-        {2000000, 3},
-        {0xffffffff, 7},
+    {     180000, 0 }, /* VHF */
+    {     188000, 1 },
+    {     196400, 2 },
+    {     250000, 3 },
+    {     550000, 2 }, /* UHF */
+    {     650000, 3 },
+    {     750000, 5 },
+    {     850000, 6 },
+    {     864000, 7 },
+    {    1500000, 0 }, /* LBAND or everything higher than UHF */
+    {    1600000, 1 },
+    {    2000000, 3 },
+    { 0xffffffff, 7 },
 };
 
-#define LPF     100             // define for the loop filter 100kHz by default 16-07-06
+#define LPF     100
 static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
 {
-        struct dib0070_state *state = fe->tuner_priv;
+    struct dib0070_state *state = fe->tuner_priv;
 
-        const struct dib0070_tuning *tune;
-        const struct dib0070_lna_match *lna_match;
+    const struct dib0070_tuning *tune;
+    const struct dib0070_lna_match *lna_match;
 
-        enum frontend_tune_state *tune_state = &state->tune_state;
-        int ret = 10;           /* 1ms is the default delay most of the time */
+    enum frontend_tune_state *tune_state = &state->tune_state;
+    int ret = 10; /* 1ms is the default delay most of the time */
 
-        u8 band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000);
-        u32 freq = fe->dtv_property_cache.frequency / 1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf);
+    u8  band = (u8)BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency/1000);
+    u32 freq = fe->dtv_property_cache.frequency/1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf);
 
 #ifdef CONFIG_SYS_ISDBT
-        if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
+    if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
                 if (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2)
                      && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
                     || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
@@ -328,172 +316,180 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par
                         && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))))
                         freq += 850;
 #endif
+    if (state->current_rf != freq) {
+
+        switch (state->revision) {
+        case DIB0070S_P1A:
+            tune = dib0070s_tuning_table;
+            lna_match = dib0070_lna;
+            break;
+        default:
+            tune = dib0070_tuning_table;
+            if (state->cfg->flip_chip)
+                lna_match = dib0070_lna_flip_chip;
+            else
+                lna_match = dib0070_lna;
+            break;
+        }
+        while (freq > tune->max_freq) /* find the right one */
+            tune++;
+        while (freq > lna_match->max_freq) /* find the right one */
+            lna_match++;
+
+        state->current_tune_table_index = tune;
+        state->lna_match = lna_match;
+    }
+
+    if (*tune_state == CT_TUNER_START) {
+        dprintk("Tuning for Band: %hd (%d kHz)", band, freq);
         if (state->current_rf != freq) {
+                u8 REFDIV;
+                u32 FBDiv, Rest, FREF, VCOF_kHz;
+                u8 Den;
+
+                state->current_rf = freq;
+                state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
+
+
+                dib0070_write_reg(state, 0x17, 0x30);
+
+
+                VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
+
+                switch (band) {
+                case BAND_VHF:
+                        REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
+                        break;
+                case BAND_FM:
+                        REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
+                        break;
+                default:
+                        REFDIV = (u8) (state->cfg->clock_khz  / 10000);
+                        break;
+                }
+                FREF = state->cfg->clock_khz / REFDIV;
+
+
 
                 switch (state->revision) {
                 case DIB0070S_P1A:
-                        tune = dib0070s_tuning_table;
-                        lna_match = dib0070_lna;
+                        FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
+                        Rest  = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
                         break;
+
+                case DIB0070_P1G:
+                case DIB0070_P1F:
                 default:
-                        tune = dib0070_tuning_table;
-                        if (state->cfg->flip_chip)
-                                lna_match = dib0070_lna_flip_chip;
-                        else
-                                lna_match = dib0070_lna;
+                        FBDiv = (freq / (FREF / 2));
+                        Rest  = 2 * freq - FBDiv * FREF;
                         break;
                 }
-                while (freq > tune->max_freq)   /* find the right one */
-                        tune++;
-                while (freq > lna_match->max_freq)      /* find the right one */
-                        lna_match++;
 
-                state->current_tune_table_index = tune;
-                state->lna_match = lna_match;
-        }
+                if (Rest < LPF)
+                        Rest = 0;
+                else if (Rest < 2 * LPF)
+                        Rest = 2 * LPF;
+                else if (Rest > (FREF - LPF)) {
+                        Rest = 0;
+                        FBDiv += 1;
+                } else if (Rest > (FREF - 2 * LPF))
+                        Rest = FREF - 2 * LPF;
+                Rest = (Rest * 6528) / (FREF / 10);
+
+                Den = 1;
+                if (Rest > 0) {
+                        state->lo4 |= (1 << 14) | (1 << 12);
+                        Den = 255;
+                }
+
 
-        if (*tune_state == CT_TUNER_START) {
-                dprintk("Tuning for Band: %hd (%d kHz)", band, freq);
-                if (state->current_rf != freq) {
-                        u8 REFDIV;
-                        u32 FBDiv, Rest, FREF, VCOF_kHz;
-                        u8 Den;
-
-                        state->current_rf = freq;
-                        state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
-
-                        dib0070_write_reg(state, 0x17, 0x30);
-
-                        VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
-
-                        switch (band) {
-                        case BAND_VHF:
-                                REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
-                                break;
-                        case BAND_FM:
-                                REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
-                                break;
-                        default:
-                                REFDIV = (u8) (state->cfg->clock_khz / 10000);
-                                break;
-                        }
-                        FREF = state->cfg->clock_khz / REFDIV;
-
-                        switch (state->revision) {
-                        case DIB0070S_P1A:
-                                FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
-                                Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
-                                break;
-
-                        case DIB0070_P1G:
-                        case DIB0070_P1F:
-                        default:
-                                FBDiv = (freq / (FREF / 2));
-                                Rest = 2 * freq - FBDiv * FREF;
-                                break;
-                        }
-
-                        if (Rest < LPF)
-                                Rest = 0;
-                        else if (Rest < 2 * LPF)
-                                Rest = 2 * LPF;
-                        else if (Rest > (FREF - LPF)) {
-                                Rest = 0;
-                                FBDiv += 1;
-                        } else if (Rest > (FREF - 2 * LPF))
-                                Rest = FREF - 2 * LPF;
-                        Rest = (Rest * 6528) / (FREF / 10);
-
-                        Den = 1;
-                        if (Rest > 0) {
-                                state->lo4 |= (1 << 14) | (1 << 12);
-                                Den = 255;
-                        }
-
-                        dib0070_write_reg(state, 0x11, (u16) FBDiv);
-                        dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
-                        dib0070_write_reg(state, 0x13, (u16) Rest);
-
-                        if (state->revision == DIB0070S_P1A) {
-
-                                if (band == BAND_SBAND) {
-                                        dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
-                                        dib0070_write_reg(state, 0x1d, 0xFFFF);
-                                } else
-                                        dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
-                        }
-
-                        dib0070_write_reg(state, 0x20,
-                                          0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
-
-                        dprintk("REFDIV: %hd, FREF: %d", REFDIV, FREF);
-                        dprintk("FBDIV: %d, Rest: %d", FBDiv, Rest);
-                        dprintk("Num: %hd, Den: %hd, SD: %hd", (u16) Rest, Den, (state->lo4 >> 12) & 0x1);
-                        dprintk("HFDIV code: %hd", state->current_tune_table_index->hfdiv);
-                        dprintk("VCO = %hd", state->current_tune_table_index->vco_band);
-                        dprintk("VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq);
-
-                        *tune_state = CT_TUNER_STEP_0;
-                } else {        /* we are already tuned to this frequency - the configuration is correct  */
-                        ret = 50;       /* wakeup time */
-                        *tune_state = CT_TUNER_STEP_5;
+                dib0070_write_reg(state, 0x11, (u16)FBDiv);
+                dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
+                dib0070_write_reg(state, 0x13, (u16) Rest);
+
+                if (state->revision == DIB0070S_P1A) {
+
+                        if (band == BAND_SBAND) {
+                                dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
+                                dib0070_write_reg(state, 0x1d, 0xFFFF);
+                        } else
+                                dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
                 }
-        } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
 
-                ret = dib0070_captrim(state, tune_state);
+                dib0070_write_reg(state, 0x20,
+                        0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
 
-        } else if (*tune_state == CT_TUNER_STEP_4) {
-                const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
-                if (tmp != NULL) {
-                        while (freq / 1000 > tmp->freq) /* find the right one */
-                                tmp++;
-                        dib0070_write_reg(state, 0x0f,
-                                          (0 << 15) | (1 << 14) | (3 << 12) | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) | (state->
-                                                                                                                                current_tune_table_index->
-                                                                                                                                wbdmux << 0));
-                        state->wbd_gain_current = tmp->wbd_gain_val;
-                } else {
+                dprintk("REFDIV: %hd, FREF: %d", REFDIV, FREF);
+                dprintk("FBDIV: %d, Rest: %d", FBDiv, Rest);
+                dprintk("Num: %hd, Den: %hd, SD: %hd", (u16) Rest, Den, (state->lo4 >> 12) & 0x1);
+                dprintk("HFDIV code: %hd", state->current_tune_table_index->hfdiv);
+                dprintk("VCO = %hd", state->current_tune_table_index->vco_band);
+                dprintk("VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq);
+
+                *tune_state = CT_TUNER_STEP_0;
+        } else { /* we are already tuned to this frequency - the configuration is correct  */
+                ret = 50; /* wakeup time */
+                *tune_state = CT_TUNER_STEP_5;
+        }
+    } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
+
+        ret = dib0070_captrim(state, tune_state);
+
+    } else if (*tune_state == CT_TUNER_STEP_4) {
+        const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
+        if (tmp != NULL) {
+                while (freq/1000 > tmp->freq) /* find the right one */
+                        tmp++;
+                dib0070_write_reg(state, 0x0f,
+                        (0 << 15) | (1 << 14) | (3 << 12)
+                        | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7)
+                        | (state->current_tune_table_index->wbdmux << 0));
+                state->wbd_gain_current = tmp->wbd_gain_val;
+        } else {
                         dib0070_write_reg(state, 0x0f,
                                           (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index->
                                                                                                                 wbdmux << 0));
-                        state->wbd_gain_current = 6;
-                }
+            state->wbd_gain_current = 6;
+        }
 
-                dib0070_write_reg(state, 0x06, 0x3fff);
+        dib0070_write_reg(state, 0x06, 0x3fff);
                 dib0070_write_reg(state, 0x07,
                                   (state->current_tune_table_index->switch_trim << 11) | (7 << 8) | (state->lna_match->lna_band << 3) | (3 << 0));
-                dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
-                dib0070_write_reg(state, 0x0d, 0x0d80);
+        dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
+        dib0070_write_reg(state, 0x0d, 0x0d80);
 
-                dib0070_write_reg(state, 0x18, 0x07ff);
-                dib0070_write_reg(state, 0x17, 0x0033);
 
-                *tune_state = CT_TUNER_STEP_5;
-        } else if (*tune_state == CT_TUNER_STEP_5) {
-                dib0070_set_bandwidth(fe, ch);
-                *tune_state = CT_TUNER_STOP;
-        } else {
-                ret = FE_CALLBACK_TIME_NEVER;   /* tuner finished, time to call again infinite */
-        }
-        return ret;
+        dib0070_write_reg(state, 0x18,   0x07ff);
+        dib0070_write_reg(state, 0x17, 0x0033);
+
+
+        *tune_state = CT_TUNER_STEP_5;
+    } else if (*tune_state == CT_TUNER_STEP_5) {
+        dib0070_set_bandwidth(fe, ch);
+        *tune_state = CT_TUNER_STOP;
+    } else {
+        ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */
+    }
+    return ret;
 }
 
+
 static int dib0070_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
 {
-        struct dib0070_state *state = fe->tuner_priv;
-        uint32_t ret;
+    struct dib0070_state *state = fe->tuner_priv;
+    uint32_t ret;
 
-        state->tune_state = CT_TUNER_START;
+    state->tune_state = CT_TUNER_START;
 
-        do {
-                ret = dib0070_tune_digital(fe, p);
-                if (ret != FE_CALLBACK_TIME_NEVER)
-                        msleep(ret / 10);
-                else
-                        break;
-        } while (state->tune_state != CT_TUNER_STOP);
+    do {
+        ret = dib0070_tune_digital(fe, p);
+        if (ret != FE_CALLBACK_TIME_NEVER)
+                msleep(ret/10);
+        else
+            break;
+    } while (state->tune_state != CT_TUNER_STOP);
 
-        return 0;
+    return 0;
 }
 
 static int dib0070_wakeup(struct dvb_frontend *fe)
@@ -512,92 +508,113 @@ static int dib0070_sleep(struct dvb_frontend *fe)
         return 0;
 }
 
-static const u16 dib0070_p1f_defaults[] = {
+u8 dib0070_get_rf_output(struct dvb_frontend *fe)
+{
+        struct dib0070_state *state = fe->tuner_priv;
+        return (dib0070_read_reg(state, 0x07) >> 11) & 0x3;
+}
+EXPORT_SYMBOL(dib0070_get_rf_output);
+
+int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no)
+{
+        struct dib0070_state *state = fe->tuner_priv;
+        u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff;
+        if (no > 3)
+                no = 3;
+        if (no < 1)
+                no = 1;
+        return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));
+}
+EXPORT_SYMBOL(dib0070_set_rf_output);
+
+static const u16 dib0070_p1f_defaults[] =
+
+{
         7, 0x02,
-        0x0008,
-        0x0000,
-        0x0000,
-        0x0000,
-        0x0000,
-        0x0002,
-        0x0100,
+                0x0008,
+                0x0000,
+                0x0000,
+                0x0000,
+                0x0000,
+                0x0002,
+                0x0100,
 
         3, 0x0d,
-        0x0d80,
-        0x0001,
-        0x0000,
+                0x0d80,
+                0x0001,
+                0x0000,
 
         4, 0x11,
-        0x0000,
-        0x0103,
-        0x0000,
-        0x0000,
+                0x0000,
+                0x0103,
+                0x0000,
+                0x0000,
 
         3, 0x16,
-        0x0004 | 0x0040,
-        0x0030,
-        0x07ff,
+                0x0004 | 0x0040,
+                0x0030,
+                0x07ff,
 
         6, 0x1b,
-        0x4112,
-        0xff00,
-        0xc07f,
-        0x0000,
-        0x0180,
-        0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
+                0x4112,
+                0xff00,
+                0xc07f,
+                0x0000,
+                0x0180,
+                0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
 
         0,
 };
 
 static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain)
 {
-        u16 tuner_en = dib0070_read_reg(state, 0x20);
-        u16 offset;
-
-        dib0070_write_reg(state, 0x18, 0x07ff);
-        dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
-        dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
-        msleep(9);
-        offset = dib0070_read_reg(state, 0x19);
-        dib0070_write_reg(state, 0x20, tuner_en);
-        return offset;
+    u16 tuner_en = dib0070_read_reg(state, 0x20);
+    u16 offset;
+
+    dib0070_write_reg(state, 0x18, 0x07ff);
+    dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
+    dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
+    msleep(9);
+    offset = dib0070_read_reg(state, 0x19);
+    dib0070_write_reg(state, 0x20, tuner_en);
+    return offset;
 }
 
 static void dib0070_wbd_offset_calibration(struct dib0070_state *state)
 {
-        u8 gain;
-        for (gain = 6; gain < 8; gain++) {
-                state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
-                dprintk("Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain - 6]);
-        }
+    u8 gain;
+    for (gain = 6; gain < 8; gain++) {
+        state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
+        dprintk("Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]);
+    }
 }
 
 u16 dib0070_wbd_offset(struct dvb_frontend *fe)
 {
-        struct dib0070_state *state = fe->tuner_priv;
-        const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
-        u32 freq = fe->dtv_property_cache.frequency / 1000;
-
-        if (tmp != NULL) {
-                while (freq / 1000 > tmp->freq) /* find the right one */
-                        tmp++;
-                state->wbd_gain_current = tmp->wbd_gain_val;
+    struct dib0070_state *state = fe->tuner_priv;
+    const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
+    u32 freq = fe->dtv_property_cache.frequency/1000;
+
+    if (tmp != NULL) {
+        while (freq/1000 > tmp->freq) /* find the right one */
+            tmp++;
+        state->wbd_gain_current = tmp->wbd_gain_val;
         } else
-                state->wbd_gain_current = 6;
+        state->wbd_gain_current = 6;
 
-        return state->wbd_offset_3_3[state->wbd_gain_current - 6];
+    return state->wbd_offset_3_3[state->wbd_gain_current - 6];
 }
-
 EXPORT_SYMBOL(dib0070_wbd_offset);
 
 #define pgm_read_word(w) (*w)
 static int dib0070_reset(struct dvb_frontend *fe)
 {
-        struct dib0070_state *state = fe->tuner_priv;
+    struct dib0070_state *state = fe->tuner_priv;
         u16 l, r, *n;
 
         HARD_RESET(state);
 
+
 #ifndef FORCE_SBAND_TUNER
         if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1)
                 state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff;
@@ -605,7 +622,7 @@ static int dib0070_reset(struct dvb_frontend *fe)
 #else
 #warning forcing SBAND
 #endif
-        state->revision = DIB0070S_P1A;
+                state->revision = DIB0070S_P1A;
 
         /* P1F or not */
         dprintk("Revision: %x", state->revision);
@@ -620,7 +637,7 @@ static int dib0070_reset(struct dvb_frontend *fe)
         while (l) {
                 r = pgm_read_word(n++);
                 do {
-                        dib0070_write_reg(state, (u8) r, pgm_read_word(n++));
+                        dib0070_write_reg(state, (u8)r, pgm_read_word(n++));
                         r++;
                 } while (--l);
                 l = pgm_read_word(n++);
@@ -633,6 +650,7 @@ static int dib0070_reset(struct dvb_frontend *fe)
         else
                 r = 2;
 
+
         r |= state->cfg->osc_buffer_state << 3;
 
         dib0070_write_reg(state, 0x10, r);
@@ -643,16 +661,24 @@ static int dib0070_reset(struct dvb_frontend *fe)
                 dib0070_write_reg(state, 0x02, r | (1 << 5));
         }
 
-        if (state->revision == DIB0070S_P1A)
-                dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
-        else
+    if (state->revision == DIB0070S_P1A)
+        dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
+    else
                 dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump, state->cfg->enable_third_order_filter);
 
         dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);
 
-        dib0070_wbd_offset_calibration(state);
+    dib0070_wbd_offset_calibration(state);
 
-        return 0;
+    return 0;
+}
+
+static int dib0070_get_frequency(struct dvb_frontend *fe, u32 *frequency)
+{
+    struct dib0070_state *state = fe->tuner_priv;
+
+    *frequency = 1000 * state->current_rf;
+    return 0;
 }
 
 static int dib0070_release(struct dvb_frontend *fe)
@@ -664,18 +690,18 @@ static int dib0070_release(struct dvb_frontend *fe)
 
 static const struct dvb_tuner_ops dib0070_ops = {
         .info = {
-                 .name = "DiBcom DiB0070",
-                 .frequency_min = 45000000,
-                 .frequency_max = 860000000,
-                 .frequency_step = 1000,
-                 },
-        .release = dib0070_release,
-
-        .init = dib0070_wakeup,
-        .sleep = dib0070_sleep,
-        .set_params = dib0070_tune,
-
-//      .get_frequency = dib0070_get_frequency,
+                .name           = "DiBcom DiB0070",
+                .frequency_min  =  45000000,
+                .frequency_max  = 860000000,
+                .frequency_step =      1000,
+        },
+        .release       = dib0070_release,
+
+        .init          = dib0070_wakeup,
+        .sleep         = dib0070_sleep,
+        .set_params    = dib0070_tune,
+
+        .get_frequency = dib0070_get_frequency,
 //      .get_bandwidth = dib0070_get_bandwidth
 };
 
@@ -687,7 +713,7 @@ struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter
 
         state->cfg = cfg;
         state->i2c = i2c;
-        state->fe = fe;
+        state->fe  = fe;
         fe->tuner_priv = state;
 
         if (dib0070_reset(fe) != 0)
@@ -699,12 +725,11 @@ struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter
         fe->tuner_priv = state;
         return fe;
 
- free_mem:
+free_mem:
         kfree(state);
         fe->tuner_priv = NULL;
         return NULL;
 }
-
 EXPORT_SYMBOL(dib0070_attach);
 
 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
diff --git a/drivers/media/dvb/frontends/dib0070.h b/drivers/media/dvb/frontends/dib0070.h
index eec9e52ffa75..45c31fae3967 100644
--- a/drivers/media/dvb/frontends/dib0070.h
+++ b/drivers/media/dvb/frontends/dib0070.h
@@ -52,6 +52,8 @@ struct dib0070_config {
 extern struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg);
 extern u16 dib0070_wbd_offset(struct dvb_frontend *);
 extern void dib0070_ctrl_agc_filter(struct dvb_frontend *, u8 open);
+extern u8 dib0070_get_rf_output(struct dvb_frontend *fe);
+extern int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no);
 #else
 static inline struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
 {
@@ -62,7 +64,7 @@ static inline struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struc
 static inline u16 dib0070_wbd_offset(struct dvb_frontend *fe)
 {
         printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-        return -ENODEV;
+        return 0;
 }
 
 static inline void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
diff --git a/drivers/media/dvb/frontends/dib0090.c b/drivers/media/dvb/frontends/dib0090.c
new file mode 100644
index 000000000000..65240b7801e8
--- /dev/null
+++ b/drivers/media/dvb/frontends/dib0090.c
@@ -0,0 +1,1523 @@
+/*
+ * Linux-DVB Driver for DiBcom's DiB0090 base-band RF Tuner.
+ *
+ * Copyright (C) 2005-9 DiBcom (http://www.dibcom.fr/)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * This code is more or less generated from another driver, please
+ * excuse some codingstyle oddities.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+
+#include "dvb_frontend.h"
+
+#include "dib0090.h"
+#include "dibx000_common.h"
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
+
+#define dprintk(args...) do { \
+        if (debug) { \
+                printk(KERN_DEBUG "DiB0090: "); \
+                printk(args); \
+                printk("\n"); \
+        } \
+} while (0)
+
+#define CONFIG_SYS_ISDBT
+#define CONFIG_BAND_CBAND
+#define CONFIG_BAND_VHF
+#define CONFIG_BAND_UHF
+#define CONFIG_DIB0090_USE_PWM_AGC
+
+#define EN_LNA0      0x8000
+#define EN_LNA1      0x4000
+#define EN_LNA2      0x2000
+#define EN_LNA3      0x1000
+#define EN_MIX0      0x0800
+#define EN_MIX1      0x0400
+#define EN_MIX2      0x0200
+#define EN_MIX3      0x0100
+#define EN_IQADC     0x0040
+#define EN_PLL       0x0020
+#define EN_TX        0x0010
+#define EN_BB        0x0008
+#define EN_LO        0x0004
+#define EN_BIAS      0x0001
+
+#define EN_IQANA     0x0002
+#define EN_DIGCLK    0x0080     /* not in the 0x24 reg, only in 0x1b */
+#define EN_CRYSTAL   0x0002
+
+#define EN_UHF           0x22E9
+#define EN_VHF           0x44E9
+#define EN_LBD           0x11E9
+#define EN_SBD           0x44E9
+#define EN_CAB           0x88E9
+
+#define pgm_read_word(w) (*w)
+
+struct dc_calibration;
+
+struct dib0090_tuning {
+        u32 max_freq;           /* for every frequency less than or equal to that field: this information is correct */
+        u8 switch_trim;
+        u8 lna_tune;
+        u8 lna_bias;
+        u16 v2i;
+        u16 mix;
+        u16 load;
+        u16 tuner_enable;
+};
+
+struct dib0090_pll {
+        u32 max_freq;           /* for every frequency less than or equal to that field: this information is correct */
+        u8 vco_band;
+        u8 hfdiv_code;
+        u8 hfdiv;
+        u8 topresc;
+};
+
+struct dib0090_state {
+        struct i2c_adapter *i2c;
+        struct dvb_frontend *fe;
+        const struct dib0090_config *config;
+
+        u8 current_band;
+        u16 revision;
+        enum frontend_tune_state tune_state;
+        u32 current_rf;
+
+        u16 wbd_offset;
+        s16 wbd_target;         /* in dB */
+
+        s16 rf_gain_limit;      /* take-over-point: where to split between bb and rf gain */
+        s16 current_gain;       /* keeps the currently programmed gain */
+        u8 agc_step;            /* new binary search */
+
+        u16 gain[2];            /* for channel monitoring */
+
+        const u16 *rf_ramp;
+        const u16 *bb_ramp;
+
+        /* for the software AGC ramps */
+        u16 bb_1_def;
+        u16 rf_lt_def;
+        u16 gain_reg[4];
+
+        /* for the captrim/dc-offset search */
+        s8 step;
+        s16 adc_diff;
+        s16 min_adc_diff;
+
+        s8 captrim;
+        s8 fcaptrim;
+
+        const struct dc_calibration *dc;
+        u16 bb6, bb7;
+
+        const struct dib0090_tuning *current_tune_table_index;
+        const struct dib0090_pll *current_pll_table_index;
+
+        u8 tuner_is_tuned;
+        u8 agc_freeze;
+
+        u8 reset;
+};
+
+static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
+{
+        u8 b[2];
+        struct i2c_msg msg[2] = {
+                {.addr = state->config->i2c_address, .flags = 0, .buf = &reg, .len = 1},
+                {.addr = state->config->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2},
+        };
+        if (i2c_transfer(state->i2c, msg, 2) != 2) {
+                printk(KERN_WARNING "DiB0090 I2C read failed\n");
+                return 0;
+        }
+        return (b[0] << 8) | b[1];
+}
+
+static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
+{
+        u8 b[3] = { reg & 0xff, val >> 8, val & 0xff };
+        struct i2c_msg msg = {.addr = state->config->i2c_address, .flags = 0, .buf = b, .len = 3 };
+        if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+                printk(KERN_WARNING "DiB0090 I2C write failed\n");
+                return -EREMOTEIO;
+        }
+        return 0;
+}
+
+#define HARD_RESET(state) do {  if (cfg->reset) {  if (cfg->sleep) cfg->sleep(fe, 0); msleep(10);  cfg->reset(fe, 1); msleep(10);  cfg->reset(fe, 0); msleep(10);  }  } while (0)
+#define ADC_TARGET -220
+#define GAIN_ALPHA 5
+#define WBD_ALPHA 6
+#define LPF     100
+static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b, u8 c)
+{
+        do {
+                dib0090_write_reg(state, r++, *b++);
+        } while (--c);
+}
+
+static u16 dib0090_identify(struct dvb_frontend *fe)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+        u16 v;
+
+        v = dib0090_read_reg(state, 0x1a);
+
+#ifdef FIRMWARE_FIREFLY
+        /* pll is not locked locked */
+        if (!(v & 0x800))
+                dprintk("FE%d : Identification : pll is not yet locked", fe->id);
+#endif
+
+        /* without PLL lock info */
+        v &= 0x3ff;
+        dprintk("P/V: %04x:", v);
+
+        if ((v >> 8) & 0xf)
+                dprintk("FE%d : Product ID = 0x%x : KROSUS", fe->id, (v >> 8) & 0xf);
+        else
+                return 0xff;
+
+        v &= 0xff;
+        if (((v >> 5) & 0x7) == 0x1)
+                dprintk("FE%d : MP001 : 9090/8096", fe->id);
+        else if (((v >> 5) & 0x7) == 0x4)
+                dprintk("FE%d : MP005 : Single Sband", fe->id);
+        else if (((v >> 5) & 0x7) == 0x6)
+                dprintk("FE%d : MP008 : diversity VHF-UHF-LBAND", fe->id);
+        else if (((v >> 5) & 0x7) == 0x7)
+                dprintk("FE%d : MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND", fe->id);
+        else
+                return 0xff;
+
+        /* revision only */
+        if ((v & 0x1f) == 0x3)
+                dprintk("FE%d : P1-D/E/F detected", fe->id);
+        else if ((v & 0x1f) == 0x1)
+                dprintk("FE%d : P1C detected", fe->id);
+        else if ((v & 0x1f) == 0x0) {
+#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
+                dprintk("FE%d : P1-A/B detected: using previous driver - support will be removed soon", fe->id);
+                dib0090_p1b_register(fe);
+#else
+                dprintk("FE%d : P1-A/B detected: driver is deactivated - not available", fe->id);
+                return 0xff;
+#endif
+        }
+
+        return v;
+}
+
+static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+
+        HARD_RESET(state);
+
+        dib0090_write_reg(state, 0x24, EN_PLL);
+        dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL);        /* PLL, DIG_CLK and CRYSTAL remain */
+
+        /* adcClkOutRatio=8->7, release reset */
+        dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
+        if (cfg->clkoutdrive != 0)
+                dib0090_write_reg(state, 0x23,
+                                  (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (cfg->clkoutdrive << 5) | (cfg->
+                                                                                                                                           clkouttobamse
+                                                                                                                                           << 4) | (0
+                                                                                                                                                    <<
+                                                                                                                                                    2)
+                                  | (0));
+        else
+                dib0090_write_reg(state, 0x23,
+                                  (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (7 << 5) | (cfg->
+                                                                                                                            clkouttobamse << 4) | (0
+                                                                                                                                                   <<
+                                                                                                                                                   2)
+                                  | (0));
+
+        /* enable pll, de-activate reset, ratio: 2/1 = 60MHz */
+        dib0090_write_reg(state, 0x21,
+                          (cfg->io.pll_bypass << 15) | (1 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv));
+
+}
+
+static int dib0090_wakeup(struct dvb_frontend *fe)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+        if (state->config->sleep)
+                state->config->sleep(fe, 0);
+        return 0;
+}
+
+static int dib0090_sleep(struct dvb_frontend *fe)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+        if (state->config->sleep)
+                state->config->sleep(fe, 1);
+        return 0;
+}
+
+void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+        if (fast)
+                dib0090_write_reg(state, 0x04, 0);
+        else
+                dib0090_write_reg(state, 0x04, 1);
+}
+EXPORT_SYMBOL(dib0090_dcc_freq);
+
+static const u16 rf_ramp_pwm_cband[] = {
+        0,                      /* max RF gain in 10th of dB */
+        0,                      /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
+        0,                      /* ramp_max = maximum X used on the ramp */
+        (0 << 10) | 0,          /* 0x2c, LNA 1 = 0dB */
+        (0 << 10) | 0,          /* 0x2d, LNA 1 */
+        (0 << 10) | 0,          /* 0x2e, LNA 2 = 0dB */
+        (0 << 10) | 0,          /* 0x2f, LNA 2 */
+        (0 << 10) | 0,          /* 0x30, LNA 3 = 0dB */
+        (0 << 10) | 0,          /* 0x31, LNA 3 */
+        (0 << 10) | 0,          /* GAIN_4_1, LNA 4 = 0dB */
+        (0 << 10) | 0,          /* GAIN_4_2, LNA 4 */
+};
+
+static const u16 rf_ramp_vhf[] = {
+        412,                    /* max RF gain in 10th of dB */
+        132, 307, 127,          /* LNA1,  13.2dB */
+        105, 412, 255,          /* LNA2,  10.5dB */
+        50, 50, 127,            /* LNA3,  5dB */
+        125, 175, 127,          /* LNA4,  12.5dB */
+        0, 0, 127,              /* CBAND, 0dB */
+};
+
+static const u16 rf_ramp_uhf[] = {
+        412,                    /* max RF gain in 10th of dB */
+        132, 307, 127,          /* LNA1  : total gain = 13.2dB, point on the ramp where this amp is full gain, value to write to get full gain */
+        105, 412, 255,          /* LNA2  : 10.5 dB */
+        50, 50, 127,            /* LNA3  :  5.0 dB */
+        125, 175, 127,          /* LNA4  : 12.5 dB */
+        0, 0, 127,              /* CBAND :  0.0 dB */
+};
+
+static const u16 rf_ramp_cband[] = {
+        332,                    /* max RF gain in 10th of dB */
+        132, 252, 127,          /* LNA1,  dB */
+        80, 332, 255,           /* LNA2,  dB */
+        0, 0, 127,              /* LNA3,  dB */
+        0, 0, 127,              /* LNA4,  dB */
+        120, 120, 127,          /* LT1 CBAND */
+};
+
+static const u16 rf_ramp_pwm_vhf[] = {
+        404,                    /* max RF gain in 10th of dB */
+        25,                     /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
+        1011,                   /* ramp_max = maximum X used on the ramp */
+        (6 << 10) | 417,        /* 0x2c, LNA 1 = 13.2dB */
+        (0 << 10) | 756,        /* 0x2d, LNA 1 */
+        (16 << 10) | 756,       /* 0x2e, LNA 2 = 10.5dB */
+        (0 << 10) | 1011,       /* 0x2f, LNA 2 */
+        (16 << 10) | 290,       /* 0x30, LNA 3 = 5dB */
+        (0 << 10) | 417,        /* 0x31, LNA 3 */
+        (7 << 10) | 0,          /* GAIN_4_1, LNA 4 = 12.5dB */
+        (0 << 10) | 290,        /* GAIN_4_2, LNA 4 */
+};
+
+static const u16 rf_ramp_pwm_uhf[] = {
+        404,                    /* max RF gain in 10th of dB */
+        25,                     /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
+        1011,                   /* ramp_max = maximum X used on the ramp */
+        (6 << 10) | 417,        /* 0x2c, LNA 1 = 13.2dB */
+        (0 << 10) | 756,        /* 0x2d, LNA 1 */
+        (16 << 10) | 756,       /* 0x2e, LNA 2 = 10.5dB */
+        (0 << 10) | 1011,       /* 0x2f, LNA 2 */
+        (16 << 10) | 0,         /* 0x30, LNA 3 = 5dB */
+        (0 << 10) | 127,        /* 0x31, LNA 3 */
+        (7 << 10) | 127,        /* GAIN_4_1, LNA 4 = 12.5dB */
+        (0 << 10) | 417,        /* GAIN_4_2, LNA 4 */
+};
+
+static const u16 bb_ramp_boost[] = {
+        550,                    /* max BB gain in 10th of dB */
+        260, 260, 26,           /* BB1, 26dB */
+        290, 550, 29,           /* BB2, 29dB */
+};
+
+static const u16 bb_ramp_pwm_normal[] = {
+        500,                    /* max RF gain in 10th of dB */
+        8,                      /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x34 */
+        400,
+        (2 << 9) | 0,           /* 0x35 = 21dB */
+        (0 << 9) | 168,         /* 0x36 */
+        (2 << 9) | 168,         /* 0x37 = 29dB */
+        (0 << 9) | 400,         /* 0x38 */
+};
+
+struct slope {
+        int16_t range;
+        int16_t slope;
+};
+static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val)
+{
+        u8 i;
+        u16 rest;
+        u16 ret = 0;
+        for (i = 0; i < num; i++) {
+                if (val > slopes[i].range)
+                        rest = slopes[i].range;
+                else
+                        rest = val;
+                ret += (rest * slopes[i].slope) / slopes[i].range;
+                val -= rest;
+        }
+        return ret;
+}
+
+static const struct slope dib0090_wbd_slopes[3] = {
+        {66, 120},              /* -64,-52: offset -   65 */
+        {600, 170},             /* -52,-35: 65     -  665 */
+        {170, 250},             /* -45,-10: 665    - 835 */
+};
+
+static s16 dib0090_wbd_to_db(struct dib0090_state *state, u16 wbd)
+{
+        wbd &= 0x3ff;
+        if (wbd < state->wbd_offset)
+                wbd = 0;
+        else
+                wbd -= state->wbd_offset;
+        /* -64dB is the floor */
+        return -640 + (s16) slopes_to_scale(dib0090_wbd_slopes, ARRAY_SIZE(dib0090_wbd_slopes), wbd);
+}
+
+static void dib0090_wbd_target(struct dib0090_state *state, u32 rf)
+{
+        u16 offset = 250;
+
+        /* TODO : DAB digital N+/-1 interferer perfs : offset = 10 */
+
+        if (state->current_band == BAND_VHF)
+                offset = 650;
+#ifndef FIRMWARE_FIREFLY
+        if (state->current_band == BAND_VHF)
+                offset = state->config->wbd_vhf_offset;
+        if (state->current_band == BAND_CBAND)
+                offset = state->config->wbd_cband_offset;
+#endif
+
+        state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + offset);
+        dprintk("wbd-target: %d dB", (u32) state->wbd_target);
+}
+
+static const int gain_reg_addr[4] = {
+        0x08, 0x0a, 0x0f, 0x01
+};
+
+static void dib0090_gain_apply(struct dib0090_state *state, s16 gain_delta, s16 top_delta, u8 force)
+{
+        u16 rf, bb, ref;
+        u16 i, v, gain_reg[4] = { 0 }, gain;
+        const u16 *g;
+
+        if (top_delta < -511)
+                top_delta = -511;
+        if (top_delta > 511)
+                top_delta = 511;
+
+        if (force) {
+                top_delta *= (1 << WBD_ALPHA);
+                gain_delta *= (1 << GAIN_ALPHA);
+        }
+
+        if (top_delta >= ((s16) (state->rf_ramp[0] << WBD_ALPHA) - state->rf_gain_limit))       /* overflow */
+                state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;
+        else
+                state->rf_gain_limit += top_delta;
+
+        if (state->rf_gain_limit < 0)   /*underflow */
+                state->rf_gain_limit = 0;
+
+        /* use gain as a temporary variable and correct current_gain */
+        gain = ((state->rf_gain_limit >> WBD_ALPHA) + state->bb_ramp[0]) << GAIN_ALPHA;
+        if (gain_delta >= ((s16) gain - state->current_gain))   /* overflow */
+                state->current_gain = gain;
+        else
+                state->current_gain += gain_delta;
+        /* cannot be less than 0 (only if gain_delta is less than 0 we can have current_gain < 0) */
+        if (state->current_gain < 0)
+                state->current_gain = 0;
+
+        /* now split total gain to rf and bb gain */
+        gain = state->current_gain >> GAIN_ALPHA;
+
+        /* requested gain is bigger than rf gain limit - ACI/WBD adjustment */
+        if (gain > (state->rf_gain_limit >> WBD_ALPHA)) {
+                rf = state->rf_gain_limit >> WBD_ALPHA;
+                bb = gain - rf;
+                if (bb > state->bb_ramp[0])
+                        bb = state->bb_ramp[0];
+        } else {                /* high signal level -> all gains put on RF */
+                rf = gain;
+                bb = 0;
+        }
+
+        state->gain[0] = rf;
+        state->gain[1] = bb;
+
+        /* software ramp */
+        /* Start with RF gains */
+        g = state->rf_ramp + 1; /* point on RF LNA1 max gain */
+        ref = rf;
+        for (i = 0; i < 7; i++) {       /* Go over all amplifiers => 5RF amps + 2 BB amps = 7 amps */
+                if (g[0] == 0 || ref < (g[1] - g[0]))   /* if total gain of the current amp is null or this amp is not concerned because it starts to work from an higher gain value */
+                        v = 0;  /* force the gain to write for the current amp to be null */
+                else if (ref >= g[1])   /* Gain to set is higher than the high working point of this amp */
+                        v = g[2];       /* force this amp to be full gain */
+                else            /* compute the value to set to this amp because we are somewhere in his range */
+                        v = ((ref - (g[1] - g[0])) * g[2]) / g[0];
+
+                if (i == 0)     /* LNA 1 reg mapping */
+                        gain_reg[0] = v;
+                else if (i == 1)        /* LNA 2 reg mapping */
+                        gain_reg[0] |= v << 7;
+                else if (i == 2)        /* LNA 3 reg mapping */
+                        gain_reg[1] = v;
+                else if (i == 3)        /* LNA 4 reg mapping */
+                        gain_reg[1] |= v << 7;
+                else if (i == 4)        /* CBAND LNA reg mapping */
+                        gain_reg[2] = v | state->rf_lt_def;
+                else if (i == 5)        /* BB gain 1 reg mapping */
+                        gain_reg[3] = v << 3;
+                else if (i == 6)        /* BB gain 2 reg mapping */
+                        gain_reg[3] |= v << 8;
+
+                g += 3;         /* go to next gain bloc */
+
+                /* When RF is finished, start with BB */
+                if (i == 4) {
+                        g = state->bb_ramp + 1; /* point on BB gain 1 max gain */
+                        ref = bb;
+                }
+        }
+        gain_reg[3] |= state->bb_1_def;
+        gain_reg[3] |= ((bb % 10) * 100) / 125;
+
+#ifdef DEBUG_AGC
+        dprintk("GA CALC: DB: %3d(rf) + %3d(bb) = %3d gain_reg[0]=%04x gain_reg[1]=%04x gain_reg[2]=%04x gain_reg[0]=%04x", rf, bb, rf + bb,
+                gain_reg[0], gain_reg[1], gain_reg[2], gain_reg[3]);
+#endif
+
+        /* Write the amplifier regs */
+        for (i = 0; i < 4; i++) {
+                v = gain_reg[i];
+                if (force || state->gain_reg[i] != v) {
+                        state->gain_reg[i] = v;
+                        dib0090_write_reg(state, gain_reg_addr[i], v);
+                }
+        }
+}
+
+static void dib0090_set_boost(struct dib0090_state *state, int onoff)
+{
+        state->bb_1_def &= 0xdfff;
+        state->bb_1_def |= onoff << 13;
+}
+
+static void dib0090_set_rframp(struct dib0090_state *state, const u16 * cfg)
+{
+        state->rf_ramp = cfg;
+}
+
+static void dib0090_set_rframp_pwm(struct dib0090_state *state, const u16 * cfg)
+{
+        state->rf_ramp = cfg;
+
+        dib0090_write_reg(state, 0x2a, 0xffff);
+
+        dprintk("total RF gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x2a));
+
+        dib0090_write_regs(state, 0x2c, cfg + 3, 6);
+        dib0090_write_regs(state, 0x3e, cfg + 9, 2);
+}
+
+static void dib0090_set_bbramp(struct dib0090_state *state, const u16 * cfg)
+{
+        state->bb_ramp = cfg;
+        dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */
+}
+
+static void dib0090_set_bbramp_pwm(struct dib0090_state *state, const u16 * cfg)
+{
+        state->bb_ramp = cfg;
+
+        dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */
+
+        dib0090_write_reg(state, 0x33, 0xffff);
+        dprintk("total BB gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x33));
+        dib0090_write_regs(state, 0x35, cfg + 3, 4);
+}
+
+void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+        /* reset the AGC */
+
+        if (state->config->use_pwm_agc) {
+#ifdef CONFIG_BAND_SBAND
+                if (state->current_band == BAND_SBAND) {
+                        dib0090_set_rframp_pwm(state, rf_ramp_pwm_sband);
+                        dib0090_set_bbramp_pwm(state, bb_ramp_pwm_boost);
+                } else
+#endif
+#ifdef CONFIG_BAND_CBAND
+                if (state->current_band == BAND_CBAND) {
+                        dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband);
+                        dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+                } else
+#endif
+#ifdef CONFIG_BAND_VHF
+                if (state->current_band == BAND_VHF) {
+                        dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf);
+                        dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+                } else
+#endif
+                {
+                        dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf);
+                        dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+                }
+
+                if (state->rf_ramp[0] != 0)
+                        dib0090_write_reg(state, 0x32, (3 << 11));
+                else
+                        dib0090_write_reg(state, 0x32, (0 << 11));
+
+                dib0090_write_reg(state, 0x39, (1 << 10));
+        }
+}
+EXPORT_SYMBOL(dib0090_pwm_gain_reset);
+
+int dib0090_gain_control(struct dvb_frontend *fe)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+        enum frontend_tune_state *tune_state = &state->tune_state;
+        int ret = 10;
+
+        u16 wbd_val = 0;
+        u8 apply_gain_immediatly = 1;
+        s16 wbd_error = 0, adc_error = 0;
+
+        if (*tune_state == CT_AGC_START) {
+                state->agc_freeze = 0;
+                dib0090_write_reg(state, 0x04, 0x0);
+
+#ifdef CONFIG_BAND_SBAND
+                if (state->current_band == BAND_SBAND) {
+                        dib0090_set_rframp(state, rf_ramp_sband);
+                        dib0090_set_bbramp(state, bb_ramp_boost);
+                } else
+#endif
+#ifdef CONFIG_BAND_VHF
+                if (state->current_band == BAND_VHF) {
+                        dib0090_set_rframp(state, rf_ramp_vhf);
+                        dib0090_set_bbramp(state, bb_ramp_boost);
+                } else
+#endif
+#ifdef CONFIG_BAND_CBAND
+                if (state->current_band == BAND_CBAND) {
+                        dib0090_set_rframp(state, rf_ramp_cband);
+                        dib0090_set_bbramp(state, bb_ramp_boost);
+                } else
+#endif
+                {
+                        dib0090_set_rframp(state, rf_ramp_uhf);
+                        dib0090_set_bbramp(state, bb_ramp_boost);
+                }
+
+                dib0090_write_reg(state, 0x32, 0);
+                dib0090_write_reg(state, 0x39, 0);
+
+                dib0090_wbd_target(state, state->current_rf);
+
+                state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;
+                state->current_gain = ((state->rf_ramp[0] + state->bb_ramp[0]) / 2) << GAIN_ALPHA;
+
+                *tune_state = CT_AGC_STEP_0;
+        } else if (!state->agc_freeze) {
+                s16 wbd;
+
+                int adc;
+                wbd_val = dib0090_read_reg(state, 0x1d);
+
+                /* read and calc the wbd power */
+                wbd = dib0090_wbd_to_db(state, wbd_val);
+                wbd_error = state->wbd_target - wbd;
+
+                if (*tune_state == CT_AGC_STEP_0) {
+                        if (wbd_error < 0 && state->rf_gain_limit > 0) {
+#ifdef CONFIG_BAND_CBAND
+                                /* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */
+                                u8 ltg2 = (state->rf_lt_def >> 10) & 0x7;
+                                if (state->current_band == BAND_CBAND && ltg2) {
+                                        ltg2 >>= 1;
+                                        state->rf_lt_def &= ltg2 << 10; /* reduce in 3 steps from 7 to 0 */
+                                }
+#endif
+                        } else {
+                                state->agc_step = 0;
+                                *tune_state = CT_AGC_STEP_1;
+                        }
+                } else {
+                        /* calc the adc power */
+                        adc = state->config->get_adc_power(fe);
+                        adc = (adc * ((s32) 355774) + (((s32) 1) << 20)) >> 21; /* included in [0:-700] */
+
+                        adc_error = (s16) (((s32) ADC_TARGET) - adc);
+#ifdef CONFIG_STANDARD_DAB
+                        if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB)
+                                adc_error += 130;
+#endif
+#ifdef CONFIG_STANDARD_DVBT
+                        if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT &&
+                            (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16))
+                                adc_error += 60;
+#endif
+#ifdef CONFIG_SYS_ISDBT
+                        if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count >
+                                                                                               0)
+                                                                                              &&
+                                                                                              ((state->fe->dtv_property_cache.layer[0].modulation ==
+                                                                                                QAM_64)
+                                                                                               || (state->fe->dtv_property_cache.layer[0].
+                                                                                                   modulation == QAM_16)))
+                                                                                             ||
+                                                                                             ((state->fe->dtv_property_cache.layer[1].segment_count >
+                                                                                               0)
+                                                                                              &&
+                                                                                              ((state->fe->dtv_property_cache.layer[1].modulation ==
+                                                                                                QAM_64)
+                                                                                               || (state->fe->dtv_property_cache.layer[1].
+                                                                                                   modulation == QAM_16)))
+                                                                                             ||
+                                                                                             ((state->fe->dtv_property_cache.layer[2].segment_count >
+                                                                                               0)
+                                                                                              &&
+                                                                                              ((state->fe->dtv_property_cache.layer[2].modulation ==
+                                                                                                QAM_64)
+                                                                                               || (state->fe->dtv_property_cache.layer[2].
+                                                                                                   modulation == QAM_16)))
+                            )
+                            )
+                                adc_error += 60;
+#endif
+
+                        if (*tune_state == CT_AGC_STEP_1) {     /* quickly go to the correct range of the ADC power */
+                                if (ABS(adc_error) < 50 || state->agc_step++ > 5) {
+
+#ifdef CONFIG_STANDARD_DAB
+                                        if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) {
+                                                dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63));      /* cap value = 63 : narrow BB filter : Fc = 1.8MHz */
+                                                dib0090_write_reg(state, 0x04, 0x0);
+                                        } else
+#endif
+                                        {
+                                                dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32));
+                                                dib0090_write_reg(state, 0x04, 0x01);   /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fast */
+                                        }
+
+                                        *tune_state = CT_AGC_STOP;
+                                }
+                        } else {
+                                /* everything higher than or equal to CT_AGC_STOP means tracking */
+                                ret = 100;      /* 10ms interval */
+                                apply_gain_immediatly = 0;
+                        }
+                }
+#ifdef DEBUG_AGC
+                dprintk
+                    ("FE: %d, tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
+                     (u32) fe->id, (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
+                     (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
+#endif
+        }
+
+        /* apply gain */
+        if (!state->agc_freeze)
+                dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
+        return ret;
+}
+EXPORT_SYMBOL(dib0090_gain_control);
+
+void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+        if (rf)
+                *rf = state->gain[0];
+        if (bb)
+                *bb = state->gain[1];
+        if (rf_gain_limit)
+                *rf_gain_limit = state->rf_gain_limit;
+        if (rflt)
+                *rflt = (state->rf_lt_def >> 10) & 0x7;
+}
+EXPORT_SYMBOL(dib0090_get_current_gain);
+
+u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner)
+{
+        struct dib0090_state *st = tuner->tuner_priv;
+        return st->wbd_offset;
+}
+EXPORT_SYMBOL(dib0090_get_wbd_offset);
+
+static const u16 dib0090_defaults[] = {
+
+        25, 0x01,
+        0x0000,
+        0x99a0,
+        0x6008,
+        0x0000,
+        0x8acb,
+        0x0000,
+        0x0405,
+        0x0000,
+        0x0000,
+        0x0000,
+        0xb802,
+        0x0300,
+        0x2d12,
+        0xbac0,
+        0x7c00,
+        0xdbb9,
+        0x0954,
+        0x0743,
+        0x8000,
+        0x0001,
+        0x0040,
+        0x0100,
+        0x0000,
+        0xe910,
+        0x149e,
+
+        1, 0x1c,
+        0xff2d,
+
+        1, 0x39,
+        0x0000,
+
+        1, 0x1b,
+        EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL,
+        2, 0x1e,
+        0x07FF,
+        0x0007,
+
+        1, 0x24,
+        EN_UHF | EN_CRYSTAL,
+
+        2, 0x3c,
+        0x3ff,
+        0x111,
+        0
+};
+
+static int dib0090_reset(struct dvb_frontend *fe)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+        u16 l, r, *n;
+
+        dib0090_reset_digital(fe, state->config);
+        state->revision = dib0090_identify(fe);
+
+        /* Revision definition */
+        if (state->revision == 0xff)
+                return -EINVAL;
+#ifdef EFUSE
+        else if ((state->revision & 0x1f) >= 3) /* Update the efuse : Only available for KROSUS > P1C */
+                dib0090_set_EFUSE(state);
+#endif
+
+#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
+        if (!(state->revision & 0x1))   /* it is P1B - reset is already done */
+                return 0;
+#endif
+
+        /* Upload the default values */
+        n = (u16 *) dib0090_defaults;
+        l = pgm_read_word(n++);
+        while (l) {
+                r = pgm_read_word(n++);
+                do {
+                        /* DEBUG_TUNER */
+                        /* dprintk("%d, %d, %d", l, r, pgm_read_word(n)); */
+                        dib0090_write_reg(state, r, pgm_read_word(n++));
+                        r++;
+                } while (--l);
+                l = pgm_read_word(n++);
+        }
+
+        /* Congigure in function of the crystal */
+        if (state->config->io.clock_khz >= 24000)
+                l = 1;
+        else
+                l = 2;
+        dib0090_write_reg(state, 0x14, l);
+        dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);
+
+        state->reset = 3;       /* enable iq-offset-calibration and wbd-calibration when tuning next time */
+
+        return 0;
+}
+
+#define steps(u) (((u) > 15) ? ((u)-16) : (u))
+#define INTERN_WAIT 10
+static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state)
+{
+        int ret = INTERN_WAIT * 10;
+
+        switch (*tune_state) {
+        case CT_TUNER_STEP_2:
+                /* Turns to positive */
+                dib0090_write_reg(state, 0x1f, 0x7);
+                *tune_state = CT_TUNER_STEP_3;
+                break;
+
+        case CT_TUNER_STEP_3:
+                state->adc_diff = dib0090_read_reg(state, 0x1d);
+
+                /* Turns to negative */
+                dib0090_write_reg(state, 0x1f, 0x4);
+                *tune_state = CT_TUNER_STEP_4;
+                break;
+
+        case CT_TUNER_STEP_4:
+                state->adc_diff -= dib0090_read_reg(state, 0x1d);
+                *tune_state = CT_TUNER_STEP_5;
+                ret = 0;
+                break;
+
+        default:
+                break;
+        }
+
+        return ret;
+}
+
+struct dc_calibration {
+        uint8_t addr;
+        uint8_t offset;
+        uint8_t pga:1;
+        uint16_t bb1;
+        uint8_t i:1;
+};
+
+static const struct dc_calibration dc_table[] = {
+        /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
+        {0x06, 5, 1, (1 << 13) | (0 << 8) | (26 << 3), 1},
+        {0x07, 11, 1, (1 << 13) | (0 << 8) | (26 << 3), 0},
+        /* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
+        {0x06, 0, 0, (1 << 13) | (29 << 8) | (26 << 3), 1},
+        {0x06, 10, 0, (1 << 13) | (29 << 8) | (26 << 3), 0},
+        {0},
+};
+
+static void dib0090_set_trim(struct dib0090_state *state)
+{
+        u16 *val;
+
+        if (state->dc->addr == 0x07)
+                val = &state->bb7;
+        else
+                val = &state->bb6;
+
+        *val &= ~(0x1f << state->dc->offset);
+        *val |= state->step << state->dc->offset;
+
+        dib0090_write_reg(state, state->dc->addr, *val);
+}
+
+static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
+{
+        int ret = 0;
+
+        switch (*tune_state) {
+
+        case CT_TUNER_START:
+                /* init */
+                dprintk("Internal DC calibration");
+
+                /* the LNA is off */
+                dib0090_write_reg(state, 0x24, 0x02ed);
+
+                /* force vcm2 = 0.8V */
+                state->bb6 = 0;
+                state->bb7 = 0x040d;
+
+                state->dc = dc_table;
+
+                *tune_state = CT_TUNER_STEP_0;
+
+                /* fall through */
+
+        case CT_TUNER_STEP_0:
+                dib0090_write_reg(state, 0x01, state->dc->bb1);
+                dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
+
+                state->step = 0;
+
+                state->min_adc_diff = 1023;
+
+                *tune_state = CT_TUNER_STEP_1;
+                ret = 50;
+                break;
+
+        case CT_TUNER_STEP_1:
+                dib0090_set_trim(state);
+
+                *tune_state = CT_TUNER_STEP_2;
+                break;
+
+        case CT_TUNER_STEP_2:
+        case CT_TUNER_STEP_3:
+        case CT_TUNER_STEP_4:
+                ret = dib0090_get_offset(state, tune_state);
+                break;
+
+        case CT_TUNER_STEP_5:   /* found an offset */
+                dprintk("FE%d: IQC read=%d, current=%x", state->fe->id, (u32) state->adc_diff, state->step);
+
+                /* first turn for this frequency */
+                if (state->step == 0) {
+                        if (state->dc->pga && state->adc_diff < 0)
+                                state->step = 0x10;
+                        if (state->dc->pga == 0 && state->adc_diff > 0)
+                                state->step = 0x10;
+                }
+
+                state->adc_diff = ABS(state->adc_diff);
+
+                if (state->adc_diff < state->min_adc_diff && steps(state->step) < 15) { /* stop search when the delta to 0 is increasing */
+                        state->step++;
+                        state->min_adc_diff = state->adc_diff;
+                        *tune_state = CT_TUNER_STEP_1;
+                } else {
+
+                        /* the minimum was what we have seen in the step before */
+                        state->step--;
+                        dib0090_set_trim(state);
+
+                        dprintk("FE%d: BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->fe->id, state->dc->addr, state->adc_diff,
+                                state->step);
+
+                        state->dc++;
+                        if (state->dc->addr == 0)       /* done */
+                                *tune_state = CT_TUNER_STEP_6;
+                        else
+                                *tune_state = CT_TUNER_STEP_0;
+
+                }
+                break;
+
+        case CT_TUNER_STEP_6:
+                dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);
+                dib0090_write_reg(state, 0x1f, 0x7);
+                *tune_state = CT_TUNER_START;   /* reset done -> real tuning can now begin */
+                state->reset &= ~0x1;
+        default:
+                break;
+        }
+        return ret;
+}
+
+static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
+{
+        switch (*tune_state) {
+        case CT_TUNER_START:
+                /* WBD-mode=log, Bias=2, Gain=6, Testmode=1, en=1, WBDMUX=1 */
+                dib0090_write_reg(state, 0x10, 0xdb09 | (1 << 10));
+                dib0090_write_reg(state, 0x24, EN_UHF & 0x0fff);
+
+                *tune_state = CT_TUNER_STEP_0;
+                return 90;      /* wait for the WBDMUX to switch and for the ADC to sample */
+        case CT_TUNER_STEP_0:
+                state->wbd_offset = dib0090_read_reg(state, 0x1d);
+                dprintk("WBD calibration offset = %d", state->wbd_offset);
+
+                *tune_state = CT_TUNER_START;   /* reset done -> real tuning can now begin */
+                state->reset &= ~0x2;
+                break;
+        default:
+                break;
+        }
+        return 0;
+}
+
+static void dib0090_set_bandwidth(struct dib0090_state *state)
+{
+        u16 tmp;
+
+        if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 5000)
+                tmp = (3 << 14);
+        else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 6000)
+                tmp = (2 << 14);
+        else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 7000)
+                tmp = (1 << 14);
+        else
+                tmp = (0 << 14);
+
+        state->bb_1_def &= 0x3fff;
+        state->bb_1_def |= tmp;
+
+        dib0090_write_reg(state, 0x01, state->bb_1_def);        /* be sure that we have the right bb-filter */
+}
+
+static const struct dib0090_pll dib0090_pll_table[] = {
+#ifdef CONFIG_BAND_CBAND
+        {56000, 0, 9, 48, 6},
+        {70000, 1, 9, 48, 6},
+        {87000, 0, 8, 32, 4},
+        {105000, 1, 8, 32, 4},
+        {115000, 0, 7, 24, 6},
+        {140000, 1, 7, 24, 6},
+        {170000, 0, 6, 16, 4},
+#endif
+#ifdef CONFIG_BAND_VHF
+        {200000, 1, 6, 16, 4},
+        {230000, 0, 5, 12, 6},
+        {280000, 1, 5, 12, 6},
+        {340000, 0, 4, 8, 4},
+        {380000, 1, 4, 8, 4},
+        {450000, 0, 3, 6, 6},
+#endif
+#ifdef CONFIG_BAND_UHF
+        {580000, 1, 3, 6, 6},
+        {700000, 0, 2, 4, 4},
+        {860000, 1, 2, 4, 4},
+#endif
+#ifdef CONFIG_BAND_LBAND
+        {1800000, 1, 0, 2, 4},
+#endif
+#ifdef CONFIG_BAND_SBAND
+        {2900000, 0, 14, 1, 4},
+#endif
+};
+
+static const struct dib0090_tuning dib0090_tuning_table_fm_vhf_on_cband[] = {
+
+#ifdef CONFIG_BAND_CBAND
+        {184000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
+        {227000, 4, 3, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
+        {380000, 4, 7, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
+#endif
+#ifdef CONFIG_BAND_UHF
+        {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+        {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+        {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+        {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+        {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+        {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+#endif
+#ifdef CONFIG_BAND_LBAND
+        {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+        {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+        {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+#endif
+#ifdef CONFIG_BAND_SBAND
+        {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
+        {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
+#endif
+};
+
+static const struct dib0090_tuning dib0090_tuning_table[] = {
+
+#ifdef CONFIG_BAND_CBAND
+        {170000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
+#endif
+#ifdef CONFIG_BAND_VHF
+        {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
+        {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
+        {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
+#endif
+#ifdef CONFIG_BAND_UHF
+        {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+        {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+        {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+        {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+        {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+        {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+#endif
+#ifdef CONFIG_BAND_LBAND
+        {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+        {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+        {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+#endif
+#ifdef CONFIG_BAND_SBAND
+        {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
+        {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
+#endif
+};
+
+#define WBD     0x781           /* 1 1 1 1 0000 0 0 1 */
+static int dib0090_tune(struct dvb_frontend *fe)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+        const struct dib0090_tuning *tune = state->current_tune_table_index;
+        const struct dib0090_pll *pll = state->current_pll_table_index;
+        enum frontend_tune_state *tune_state = &state->tune_state;
+
+        u32 rf;
+        u16 lo4 = 0xe900, lo5, lo6, Den;
+        u32 FBDiv, Rest, FREF, VCOF_kHz = 0;
+        u16 tmp, adc;
+        int8_t step_sign;
+        int ret = 10;           /* 1ms is the default delay most of the time */
+        u8 c, i;
+
+        state->current_band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000);
+        rf = fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
+                                                        BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->freq_offset_khz_vhf);
+        /* in any case we first need to do a reset if needed */
+        if (state->reset & 0x1)
+                return dib0090_dc_offset_calibration(state, tune_state);
+        else if (state->reset & 0x2)
+                return dib0090_wbd_calibration(state, tune_state);
+
+    /************************* VCO ***************************/
+        /* Default values for FG                                 */
+        /* from these are needed :                               */
+        /* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv             */
+
+#ifdef CONFIG_SYS_ISDBT
+        if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
+                rf += 850;
+#endif
+
+        if (state->current_rf != rf) {
+                state->tuner_is_tuned = 0;
+
+                tune = dib0090_tuning_table;
+
+                tmp = (state->revision >> 5) & 0x7;
+                if (tmp == 0x4 || tmp == 0x7) {
+                        /* CBAND tuner version for VHF */
+                        if (state->current_band == BAND_FM || state->current_band == BAND_VHF) {
+                                /* Force CBAND */
+                                state->current_band = BAND_CBAND;
+                                tune = dib0090_tuning_table_fm_vhf_on_cband;
+                        }
+                }
+
+                pll = dib0090_pll_table;
+                /* Look for the interval */
+                while (rf > tune->max_freq)
+                        tune++;
+                while (rf > pll->max_freq)
+                        pll++;
+                state->current_tune_table_index = tune;
+                state->current_pll_table_index = pll;
+        }
+
+        if (*tune_state == CT_TUNER_START) {
+
+                if (state->tuner_is_tuned == 0)
+                        state->current_rf = 0;
+
+                if (state->current_rf != rf) {
+
+                        dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
+
+                        /* external loop filter, otherwise:
+                         * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4;
+                         * lo6 = 0x0e34 */
+                        if (pll->vco_band)
+                                lo5 = 0x049e;
+                        else if (state->config->analog_output)
+                                lo5 = 0x041d;
+                        else
+                                lo5 = 0x041c;
+
+                        lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7);  /* bit 15 is the split to the slave, we do not do it here */
+
+                        if (!state->config->io.pll_int_loop_filt)
+                                lo6 = 0xff28;
+                        else
+                                lo6 = (state->config->io.pll_int_loop_filt << 3);
+
+                        VCOF_kHz = (pll->hfdiv * rf) * 2;
+
+                        FREF = state->config->io.clock_khz;
+
+                        FBDiv = (VCOF_kHz / pll->topresc / FREF);
+                        Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF;
+
+                        if (Rest < LPF)
+                                Rest = 0;
+                        else if (Rest < 2 * LPF)
+                                Rest = 2 * LPF;
+                        else if (Rest > (FREF - LPF)) {
+                                Rest = 0;
+                                FBDiv += 1;
+                        } else if (Rest > (FREF - 2 * LPF))
+                                Rest = FREF - 2 * LPF;
+                        Rest = (Rest * 6528) / (FREF / 10);
+
+                        Den = 1;
+
+                        dprintk(" *****  ******* Rest value = %d", Rest);
+
+                        if (Rest > 0) {
+                                if (state->config->analog_output)
+                                        lo6 |= (1 << 2) | 2;
+                                else
+                                        lo6 |= (1 << 2) | 1;
+                                Den = 255;
+                        }
+#ifdef CONFIG_BAND_SBAND
+                        if (state->current_band == BAND_SBAND)
+                                lo6 &= 0xfffb;
+#endif
+
+                        dib0090_write_reg(state, 0x15, (u16) FBDiv);
+
+                        dib0090_write_reg(state, 0x16, (Den << 8) | 1);
+
+                        dib0090_write_reg(state, 0x17, (u16) Rest);
+
+                        dib0090_write_reg(state, 0x19, lo5);
+
+                        dib0090_write_reg(state, 0x1c, lo6);
+
+                        lo6 = tune->tuner_enable;
+                        if (state->config->analog_output)
+                                lo6 = (lo6 & 0xff9f) | 0x2;
+
+                        dib0090_write_reg(state, 0x24, lo6 | EN_LO
+#ifdef CONFIG_DIB0090_USE_PWM_AGC
+                                          | state->config->use_pwm_agc * EN_CRYSTAL
+#endif
+                            );
+
+                        state->current_rf = rf;
+
+                        /* prepare a complete captrim */
+                        state->step = state->captrim = state->fcaptrim = 64;
+
+                } else {        /* we are already tuned to this frequency - the configuration is correct  */
+
+                        /* do a minimal captrim even if the frequency has not changed */
+                        state->step = 4;
+                        state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
+                }
+                state->adc_diff = 3000;
+
+                dib0090_write_reg(state, 0x10, 0x2B1);
+
+                dib0090_write_reg(state, 0x1e, 0x0032);
+
+                ret = 20;
+                *tune_state = CT_TUNER_STEP_1;
+        } else if (*tune_state == CT_TUNER_STEP_0) {
+                /* nothing */
+        } else if (*tune_state == CT_TUNER_STEP_1) {
+                state->step /= 2;
+                dib0090_write_reg(state, 0x18, lo4 | state->captrim);
+                *tune_state = CT_TUNER_STEP_2;
+        } else if (*tune_state == CT_TUNER_STEP_2) {
+
+                adc = dib0090_read_reg(state, 0x1d);
+                dprintk("FE %d CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) fe->id, (u32) state->captrim, (u32) adc,
+                        (u32) (adc) * (u32) 1800 / (u32) 1024);
+
+                if (adc >= 400) {
+                        adc -= 400;
+                        step_sign = -1;
+                } else {
+                        adc = 400 - adc;
+                        step_sign = 1;
+                }
+
+                if (adc < state->adc_diff) {
+                        dprintk("FE %d CAPTRIM=%d is closer to target (%d/%d)", (u32) fe->id, (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
+                        state->adc_diff = adc;
+                        state->fcaptrim = state->captrim;
+
+                }
+
+                state->captrim += step_sign * state->step;
+                if (state->step >= 1)
+                        *tune_state = CT_TUNER_STEP_1;
+                else
+                        *tune_state = CT_TUNER_STEP_3;
+
+                ret = 15;
+        } else if (*tune_state == CT_TUNER_STEP_3) {
+                /*write the final cptrim config */
+                dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
+
+#ifdef CONFIG_TUNER_DIB0090_CAPTRIM_MEMORY
+                state->memory[state->memory_index].cap = state->fcaptrim;
+#endif
+
+                *tune_state = CT_TUNER_STEP_4;
+        } else if (*tune_state == CT_TUNER_STEP_4) {
+                dib0090_write_reg(state, 0x1e, 0x07ff);
+
+                dprintk("FE %d Final Captrim: %d", (u32) fe->id, (u32) state->fcaptrim);
+                dprintk("FE %d HFDIV code: %d", (u32) fe->id, (u32) pll->hfdiv_code);
+                dprintk("FE %d VCO = %d", (u32) fe->id, (u32) pll->vco_band);
+                dprintk("FE %d VCOF in kHz: %d ((%d*%d) << 1))", (u32) fe->id, (u32) ((pll->hfdiv * rf) * 2), (u32) pll->hfdiv, (u32) rf);
+                dprintk("FE %d REFDIV: %d, FREF: %d", (u32) fe->id, (u32) 1, (u32) state->config->io.clock_khz);
+                dprintk("FE %d FBDIV: %d, Rest: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
+                dprintk("FE %d Num: %d, Den: %d, SD: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x17),
+                        (u32) (dib0090_read_reg(state, 0x16) >> 8), (u32) dib0090_read_reg(state, 0x1c) & 0x3);
+
+                c = 4;
+                i = 3;
+#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
+                if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND)) {
+                        c = 2;
+                        i = 2;
+                }
+#endif
+                dib0090_write_reg(state, 0x10, (c << 13) | (i << 11) | (WBD
+#ifdef CONFIG_DIB0090_USE_PWM_AGC
+                                                                        | (state->config->use_pwm_agc << 1)
+#endif
+                                  ));
+                dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | (tune->lna_bias << 0));
+                dib0090_write_reg(state, 0x0c, tune->v2i);
+                dib0090_write_reg(state, 0x0d, tune->mix);
+                dib0090_write_reg(state, 0x0e, tune->load);
+
+                *tune_state = CT_TUNER_STEP_5;
+        } else if (*tune_state == CT_TUNER_STEP_5) {
+
+                /* initialize the lt gain register */
+                state->rf_lt_def = 0x7c00;
+                dib0090_write_reg(state, 0x0f, state->rf_lt_def);
+
+                dib0090_set_bandwidth(state);
+                state->tuner_is_tuned = 1;
+                *tune_state = CT_TUNER_STOP;
+        } else
+                ret = FE_CALLBACK_TIME_NEVER;
+        return ret;
+}
+
+static int dib0090_release(struct dvb_frontend *fe)
+{
+        kfree(fe->tuner_priv);
+        fe->tuner_priv = NULL;
+        return 0;
+}
+
+enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+
+        return state->tune_state;
+}
+EXPORT_SYMBOL(dib0090_get_tune_state);
+
+int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+
+        state->tune_state = tune_state;
+        return 0;
+}
+EXPORT_SYMBOL(dib0090_set_tune_state);
+
+static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+
+        *frequency = 1000 * state->current_rf;
+        return 0;
+}
+
+static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
+{
+        struct dib0090_state *state = fe->tuner_priv;
+        uint32_t ret;
+
+        state->tune_state = CT_TUNER_START;
+
+        do {
+                ret = dib0090_tune(fe);
+                if (ret != FE_CALLBACK_TIME_NEVER)
+                        msleep(ret / 10);
+                else
+                        break;
+        } while (state->tune_state != CT_TUNER_STOP);
+
+        return 0;
+}
+
+static const struct dvb_tuner_ops dib0090_ops = {
+        .info = {
+                 .name = "DiBcom DiB0090",
+                 .frequency_min = 45000000,
+                 .frequency_max = 860000000,
+                 .frequency_step = 1000,
+                 },
+        .release = dib0090_release,
+
+        .init = dib0090_wakeup,
+        .sleep = dib0090_sleep,
+        .set_params = dib0090_set_params,
+        .get_frequency = dib0090_get_frequency,
+};
+
+struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
+{
+        struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL);
+        if (st == NULL)
+                return NULL;
+
+        st->config = config;
+        st->i2c = i2c;
+        st->fe = fe;
+        fe->tuner_priv = st;
+
+        if (dib0090_reset(fe) != 0)
+                goto free_mem;
+
+        printk(KERN_INFO "DiB0090: successfully identified\n");
+        memcpy(&fe->ops.tuner_ops, &dib0090_ops, sizeof(struct dvb_tuner_ops));
+
+        return fe;
+ free_mem:
+        kfree(st);
+        fe->tuner_priv = NULL;
+        return NULL;
+}
+EXPORT_SYMBOL(dib0090_register);
+
+MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
+MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>");
+MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib0090.h b/drivers/media/dvb/frontends/dib0090.h
new file mode 100644
index 000000000000..aa7711e88776
--- /dev/null
+++ b/drivers/media/dvb/frontends/dib0090.h
@@ -0,0 +1,108 @@
+/*
+ * Linux-DVB Driver for DiBcom's DiB0090 base-band RF Tuner.
+ *
+ * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
+ *
+ * This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License as
+ *      published by the Free Software Foundation, version 2.
+ */
+#ifndef DIB0090_H
+#define DIB0090_H
+
+struct dvb_frontend;
+struct i2c_adapter;
+
+#define DEFAULT_DIB0090_I2C_ADDRESS 0x60
+
+struct dib0090_io_config {
+        u32 clock_khz;
+
+        u8 pll_bypass:1;
+        u8 pll_range:1;
+        u8 pll_prediv:6;
+        u8 pll_loopdiv:6;
+
+        u8 adc_clock_ratio;     /* valid is 8, 7 ,6 */
+        u16 pll_int_loop_filt;
+};
+
+struct dib0090_config {
+        struct dib0090_io_config io;
+        int (*reset) (struct dvb_frontend *, int);
+        int (*sleep) (struct dvb_frontend *, int);
+
+        /*  offset in kHz */
+        int freq_offset_khz_uhf;
+        int freq_offset_khz_vhf;
+
+        int (*get_adc_power) (struct dvb_frontend *);
+
+        u8 clkouttobamse:1;     /* activate or deactivate clock output */
+        u8 analog_output;
+
+        u8 i2c_address;
+        /* add drives and other things if necessary */
+        u16 wbd_vhf_offset;
+        u16 wbd_cband_offset;
+        u8 use_pwm_agc;
+        u8 clkoutdrive;
+};
+
+#if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE))
+extern struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
+extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast);
+extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe);
+extern u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner);
+extern int dib0090_gain_control(struct dvb_frontend *fe);
+extern enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe);
+extern int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state);
+extern void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt);
+#else
+static inline struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0090_config *config)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return NULL;
+}
+
+static inline void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+}
+
+static inline void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+}
+
+static inline u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return 0;
+}
+
+static inline int dib0090_gain_control(struct dvb_frontend *fe)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return -ENODEV;
+}
+
+static inline enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return CT_DONE;
+}
+
+static inline int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return -ENODEV;
+}
+
+static inline void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+}
+#endif
+
+#endif
diff --git a/drivers/media/dvb/frontends/dib3000mb.c b/drivers/media/dvb/frontends/dib3000mb.c
index 136b9d2164d7..ad4c8cfd8090 100644
--- a/drivers/media/dvb/frontends/dib3000mb.c
+++ b/drivers/media/dvb/frontends/dib3000mb.c
@@ -154,7 +154,7 @@ static int dib3000mb_set_frontend(struct dvb_frontend* fe,
                         case BANDWIDTH_AUTO:
                                 return -EOPNOTSUPP;
                         default:
-                                err("unkown bandwidth value.");
+                                err("unknown bandwidth value.");
                                 return -EINVAL;
                 }
         }
diff --git a/drivers/media/dvb/frontends/dib3000mc.c b/drivers/media/dvb/frontends/dib3000mc.c
index fa851601e7d4..40a099810279 100644
--- a/drivers/media/dvb/frontends/dib3000mc.c
+++ b/drivers/media/dvb/frontends/dib3000mc.c
@@ -12,6 +12,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/slab.h>
 #include <linux/i2c.h>
 
 #include "dvb_frontend.h"
diff --git a/drivers/media/dvb/frontends/dib7000m.c b/drivers/media/dvb/frontends/dib7000m.c
index 0109720353bd..0f09fd31cb29 100644
--- a/drivers/media/dvb/frontends/dib7000m.c
+++ b/drivers/media/dvb/frontends/dib7000m.c
@@ -9,6 +9,7 @@
  *      published by the Free Software Foundation, version 2.
  */
 #include <linux/kernel.h>
+#include <linux/slab.h>
 #include <linux/i2c.h>
 
 #include "dvb_frontend.h"
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
index 0781f94e05d2..85468a45c344 100644
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ b/drivers/media/dvb/frontends/dib7000p.c
@@ -8,6 +8,7 @@
  *      published by the Free Software Foundation, version 2.
  */
 #include <linux/kernel.h>
+#include <linux/slab.h>
 #include <linux/i2c.h>
 
 #include "dvb_math.h"
@@ -108,7 +109,7 @@ static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
 
         outreg = 0;
         fifo_threshold = 1792;
-        smo_mode = (dib7000p_read_word(state, 235) & 0x0010) | (1 << 1);
+        smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
 
         dprintk( "setting output mode for demod %p to %d",
                         &state->demod, mode);
@@ -162,18 +163,19 @@ static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
         if (state->div_force_off) {
                 dprintk( "diversity combination deactivated - forced by COFDM parameters");
                 onoff = 0;
-        }
+                dib7000p_write_word(state, 207, 0);
+        } else
+                dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
+
         state->div_state = (u8)onoff;
 
         if (onoff) {
                 dib7000p_write_word(state, 204, 6);
                 dib7000p_write_word(state, 205, 16);
                 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
-                dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
         } else {
                 dib7000p_write_word(state, 204, 1);
                 dib7000p_write_word(state, 205, 0);
-                dib7000p_write_word(state, 207, 0);
         }
 
         return 0;
@@ -1188,7 +1190,7 @@ static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat)
                 *stat |= FE_HAS_VITERBI;
         if (lock & 0x0010)
                 *stat |= FE_HAS_SYNC;
-        if (lock & 0x0008)
+    if ((lock & 0x0038) == 0x38)
                 *stat |= FE_HAS_LOCK;
 
         return 0;
@@ -1302,6 +1304,24 @@ struct i2c_adapter * dib7000p_get_i2c_master(struct dvb_frontend *demod, enum di
 }
 EXPORT_SYMBOL(dib7000p_get_i2c_master);
 
+int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
+{
+    struct dib7000p_state *state = fe->demodulator_priv;
+    u16 val = dib7000p_read_word(state, 235) & 0xffef;
+    val |= (onoff & 0x1) << 4;
+    dprintk("PID filter enabled %d", onoff);
+    return dib7000p_write_word(state, 235, val);
+}
+EXPORT_SYMBOL(dib7000p_pid_filter_ctrl);
+
+int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
+{
+    struct dib7000p_state *state = fe->demodulator_priv;
+    dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
+    return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
+}
+EXPORT_SYMBOL(dib7000p_pid_filter);
+
 int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
 {
         struct dib7000p_state st = { .i2c_adap = i2c };
@@ -1314,8 +1334,10 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
                 /* designated i2c address */
                 new_addr          = (0x40 + k) << 1;
                 st.i2c_addr = new_addr;
+                dib7000p_write_word(&st, 1287, 0x0003); /* sram lead in, rdy */
                 if (dib7000p_identify(&st) != 0) {
                         st.i2c_addr = default_addr;
+                        dib7000p_write_word(&st, 1287, 0x0003); /* sram lead in, rdy */
                         if (dib7000p_identify(&st) != 0) {
                                 dprintk("DiB7000P #%d: not identified\n", k);
                                 return -EIO;
@@ -1372,6 +1394,8 @@ struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
         demod->demodulator_priv = st;
         memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
 
+    dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
+
         if (dib7000p_identify(st) != 0)
                 goto error;
 
diff --git a/drivers/media/dvb/frontends/dib7000p.h b/drivers/media/dvb/frontends/dib7000p.h
index 02a4c82f0c70..805dd13a97ee 100644
--- a/drivers/media/dvb/frontends/dib7000p.h
+++ b/drivers/media/dvb/frontends/dib7000p.h
@@ -51,6 +51,8 @@ extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c,
 extern int dib7000p_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
 extern int dib7000p_set_wbd_ref(struct dvb_frontend *, u16 value);
 extern int dib7000pc_detection(struct i2c_adapter *i2c_adap);
+extern int dib7000p_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
+extern int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff);
 #else
 static inline
 struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
@@ -95,6 +97,17 @@ static inline int dib7000pc_detection(struct i2c_adapter *i2c_adap)
         printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
         return -ENODEV;
 }
+static inline int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
+{
+    printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+    return -ENODEV;
+}
+
+static inline int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, uint8_t onoff)
+{
+    printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+    return -ENODEV;
+}
 #endif
 
 #endif
diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c
index 852c790d09d9..df17b91b3250 100644
--- a/drivers/media/dvb/frontends/dib8000.c
+++ b/drivers/media/dvb/frontends/dib8000.c
@@ -8,6 +8,7 @@
  *  published by the Free Software Foundation, version 2.
  */
 #include <linux/kernel.h>
+#include <linux/slab.h>
 #include <linux/i2c.h>
 #include "dvb_math.h"
 
@@ -28,18 +29,6 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
 
 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB8000: "); printk(args); printk("\n"); } } while (0)
 
-enum frontend_tune_state {
-        CT_AGC_START = 20,
-        CT_AGC_STEP_0,
-        CT_AGC_STEP_1,
-        CT_AGC_STEP_2,
-        CT_AGC_STEP_3,
-        CT_AGC_STEP_4,
-        CT_AGC_STOP,
-
-        CT_DEMOD_START = 30,
-};
-
 #define FE_STATUS_TUNE_FAILED 0
 
 struct i2c_device {
@@ -133,104 +122,104 @@ static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
         return dib8000_i2c_write16(&state->i2c, reg, val);
 }
 
-const int16_t coeff_2k_sb_1seg_dqpsk[8] = {
+static const int16_t coeff_2k_sb_1seg_dqpsk[8] = {
         (769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c,
             (920 << 5) | 0x09
 };
 
-const int16_t coeff_2k_sb_1seg[8] = {
+static const int16_t coeff_2k_sb_1seg[8] = {
         (692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f
 };
 
-const int16_t coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
+static const int16_t coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
         (832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
             (-931 << 5) | 0x0f
 };
 
-const int16_t coeff_2k_sb_3seg_0dqpsk[8] = {
+static const int16_t coeff_2k_sb_3seg_0dqpsk[8] = {
         (622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e,
             (982 << 5) | 0x0c
 };
 
-const int16_t coeff_2k_sb_3seg_1dqpsk[8] = {
+static const int16_t coeff_2k_sb_3seg_1dqpsk[8] = {
         (699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
             (-720 << 5) | 0x0d
 };
 
-const int16_t coeff_2k_sb_3seg[8] = {
+static const int16_t coeff_2k_sb_3seg[8] = {
         (664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
             (-610 << 5) | 0x0a
 };
 
-const int16_t coeff_4k_sb_1seg_dqpsk[8] = {
+static const int16_t coeff_4k_sb_1seg_dqpsk[8] = {
         (-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
             (-922 << 5) | 0x0d
 };
 
-const int16_t coeff_4k_sb_1seg[8] = {
+static const int16_t coeff_4k_sb_1seg[8] = {
         (638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
             (-655 << 5) | 0x0a
 };
 
-const int16_t coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
+static const int16_t coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
         (-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
             (-958 << 5) | 0x13
 };
 
-const int16_t coeff_4k_sb_3seg_0dqpsk[8] = {
+static const int16_t coeff_4k_sb_3seg_0dqpsk[8] = {
         (-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
             (-568 << 5) | 0x0f
 };
 
-const int16_t coeff_4k_sb_3seg_1dqpsk[8] = {
+static const int16_t coeff_4k_sb_3seg_1dqpsk[8] = {
         (-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
             (-848 << 5) | 0x13
 };
 
-const int16_t coeff_4k_sb_3seg[8] = {
+static const int16_t coeff_4k_sb_3seg[8] = {
         (612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
             (-869 << 5) | 0x13
 };
 
-const int16_t coeff_8k_sb_1seg_dqpsk[8] = {
+static const int16_t coeff_8k_sb_1seg_dqpsk[8] = {
         (-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
             (-598 << 5) | 0x10
 };
 
-const int16_t coeff_8k_sb_1seg[8] = {
+static const int16_t coeff_8k_sb_1seg[8] = {
         (673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f,
             (585 << 5) | 0x0f
 };
 
-const int16_t coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
+static const int16_t coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
         (863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18,
             (0 << 5) | 0x14
 };
 
-const int16_t coeff_8k_sb_3seg_0dqpsk[8] = {
+static const int16_t coeff_8k_sb_3seg_0dqpsk[8] = {
         (-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
             (-877 << 5) | 0x15
 };
 
-const int16_t coeff_8k_sb_3seg_1dqpsk[8] = {
+static const int16_t coeff_8k_sb_3seg_1dqpsk[8] = {
         (-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
             (-921 << 5) | 0x14
 };
 
-const int16_t coeff_8k_sb_3seg[8] = {
+static const int16_t coeff_8k_sb_3seg[8] = {
         (514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15,
             (690 << 5) | 0x14
 };
 
-const int16_t ana_fe_coeff_3seg[24] = {
+static const int16_t ana_fe_coeff_3seg[24] = {
         81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017
 };
 
-const int16_t ana_fe_coeff_1seg[24] = {
+static const int16_t ana_fe_coeff_1seg[24] = {
         249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003
 };
 
-const int16_t ana_fe_coeff_13seg[24] = {
+static const int16_t ana_fe_coeff_13seg[24] = {
         396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
 };
 
@@ -852,6 +841,14 @@ static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
         return 0;
 }
 
+void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
+{
+        struct dib8000_state *state = fe->demodulator_priv;
+        dib8000_set_adc_state(state, DIBX000_ADC_ON);
+        dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
+}
+EXPORT_SYMBOL(dib8000_pwm_agc_reset);
+
 static int dib8000_agc_soft_split(struct dib8000_state *state)
 {
         u16 agc, split_offset;
@@ -939,6 +936,32 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
 
 }
 
+static const int32_t lut_1000ln_mant[] =
+{
+        908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
+};
+
+int32_t dib8000_get_adc_power(struct dvb_frontend *fe, uint8_t mode)
+{
+    struct dib8000_state *state = fe->demodulator_priv;
+    uint32_t ix = 0, tmp_val = 0, exp = 0, mant = 0;
+    int32_t val;
+
+    val = dib8000_read32(state, 384);
+    /* mode = 1 : ln_agcpower calc using mant-exp conversion and mantis look up table */
+    if (mode) {
+        tmp_val = val;
+        while (tmp_val >>= 1)
+                exp++;
+        mant = (val * 1000 / (1<<exp));
+        ix = (uint8_t)((mant-1000)/100); /* index of the LUT */
+        val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); /* 1000 * ln(adcpower_real) ; 693 = 1000ln(2) ; 6908 = 1000*ln(1000) ; 20 comes from adc_real = adc_pow_int / 2**20 */
+        val = (val*256)/1000;
+    }
+    return val;
+}
+EXPORT_SYMBOL(dib8000_get_adc_power);
+
 static void dib8000_update_timf(struct dib8000_state *state)
 {
         u32 timf = state->timf = dib8000_read32(state, 435);
@@ -954,7 +977,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
         u8 guard, crate, constellation, timeI;
         u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
         u16 i, coeff[4], P_cfr_left_edge = 0, P_cfr_right_edge = 0, seg_mask13 = 0x1fff;        // All 13 segments enabled
-        const s16 *ncoeff, *ana_fe;
+        const s16 *ncoeff = NULL, *ana_fe;
         u16 tmcc_pow = 0;
         u16 coff_pow = 0x2800;
         u16 init_prbs = 0xfff;
@@ -1401,10 +1424,9 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
                         }
                         break;
                 }
-        }
-        if (state->fe.dtv_property_cache.isdbt_sb_mode == 1)
                 for (i = 0; i < 8; i++)
                         dib8000_write_word(state, 343 + i, ncoeff[i]);
+        }
 
         // P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5
         dib8000_write_word(state, 351,
@@ -1854,6 +1876,24 @@ static int dib8000_sleep(struct dvb_frontend *fe)
         }
 }
 
+enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
+{
+        struct dib8000_state *state = fe->demodulator_priv;
+        return state->tune_state;
+}
+EXPORT_SYMBOL(dib8000_get_tune_state);
+
+int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
+{
+        struct dib8000_state *state = fe->demodulator_priv;
+        state->tune_state = tune_state;
+        return 0;
+}
+EXPORT_SYMBOL(dib8000_set_tune_state);
+
+
+
+
 static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
 {
         struct dib8000_state *state = fe->demodulator_priv;
@@ -1960,6 +2000,8 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
         struct dib8000_state *state = fe->demodulator_priv;
         int time, ret;
 
+        fe->dtv_property_cache.delivery_system = SYS_ISDBT;
+
         dib8000_set_output_mode(state, OUTMODE_HIGH_Z);
 
         if (fe->ops.tuner_ops.set_params)
@@ -2043,29 +2085,31 @@ static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
 
         *stat = 0;
 
-        if ((lock >> 14) & 1)   // AGC
+        if ((lock >> 13) & 1)
                 *stat |= FE_HAS_SIGNAL;
 
-        if ((lock >> 8) & 1)    // Equal
+        if ((lock >> 8) & 1) /* Equal */
                 *stat |= FE_HAS_CARRIER;
 
-        if ((lock >> 3) & 1)    // TMCC_SYNC
+        if (((lock >> 1) & 0xf) == 0xf) /* TMCC_SYNC */
                 *stat |= FE_HAS_SYNC;
 
-        if ((lock >> 5) & 7)    // FEC MPEG
+        if (((lock >> 12) & 1) && ((lock >> 5) & 7)) /* FEC MPEG */
                 *stat |= FE_HAS_LOCK;
 
-        lock = dib8000_read_word(state, 554);   // Viterbi Layer A
-        if (lock & 0x01)
-                *stat |= FE_HAS_VITERBI;
+        if ((lock >> 12) & 1) {
+                lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
+                if (lock & 0x01)
+                        *stat |= FE_HAS_VITERBI;
 
-        lock = dib8000_read_word(state, 555);   // Viterbi Layer B
-        if (lock & 0x01)
-                *stat |= FE_HAS_VITERBI;
+                lock = dib8000_read_word(state, 555); /* Viterbi Layer B */
+                if (lock & 0x01)
+                        *stat |= FE_HAS_VITERBI;
 
-        lock = dib8000_read_word(state, 556);   // Viterbi Layer C
-        if (lock & 0x01)
-                *stat |= FE_HAS_VITERBI;
+                lock = dib8000_read_word(state, 556); /* Viterbi Layer C */
+                if (lock & 0x01)
+                        *stat |= FE_HAS_VITERBI;
+        }
 
         return 0;
 }
@@ -2121,7 +2165,7 @@ static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
         else
                 result -= intlog10(2) * 10 * noise_exp - 100;
 
-        *snr = result / (1 << 24);
+        *snr = result / ((1 << 24) / 10);
         return 0;
 }
 
@@ -2195,6 +2239,25 @@ struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000
 
 EXPORT_SYMBOL(dib8000_get_i2c_master);
 
+int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
+{
+        struct dib8000_state *st = fe->demodulator_priv;
+    u16 val = dib8000_read_word(st, 299) & 0xffef;
+    val |= (onoff & 0x1) << 4;
+
+    dprintk("pid filter enabled %d", onoff);
+    return dib8000_write_word(st, 299, val);
+}
+EXPORT_SYMBOL(dib8000_pid_filter_ctrl);
+
+int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
+{
+        struct dib8000_state *st = fe->demodulator_priv;
+    dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
+    return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
+}
+EXPORT_SYMBOL(dib8000_pid_filter);
+
 static const struct dvb_frontend_ops dib8000_ops = {
         .info = {
                  .name = "DiBcom 8000 ISDB-T",
diff --git a/drivers/media/dvb/frontends/dib8000.h b/drivers/media/dvb/frontends/dib8000.h
index a86de340dd54..b1ee20799639 100644
--- a/drivers/media/dvb/frontends/dib8000.h
+++ b/drivers/media/dvb/frontends/dib8000.h
@@ -44,6 +44,12 @@ extern int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u
 
 extern int dib8000_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
 extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value);
+extern int dib8000_pid_filter_ctrl(struct dvb_frontend *, u8 onoff);
+extern int dib8000_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
+extern int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state);
+extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe);
+extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe);
+extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode);
 #else
 static inline struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
 {
@@ -57,23 +63,53 @@ static inline struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe
         return NULL;
 }
 
-int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr)
+static inline int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr)
 {
         printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
         return -ENODEV;
 }
 
-int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
+static inline int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
 {
         printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
         return -ENODEV;
 }
 
-int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
+static inline int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
 {
         printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
         return -ENODEV;
 }
+
+static inline int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return -ENODEV;
+}
+
+static inline int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return -ENODEV;
+}
+static inline int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return -ENODEV;
+}
+static inline enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return CT_SHUTDOWN;
+}
+static inline void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+}
+static inline s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+}
 #endif
 
 #endif
diff --git a/drivers/media/dvb/frontends/dibx000_common.c b/drivers/media/dvb/frontends/dibx000_common.c
index 4efca30d2127..980e02f1575e 100644
--- a/drivers/media/dvb/frontends/dibx000_common.c
+++ b/drivers/media/dvb/frontends/dibx000_common.c
@@ -6,7 +6,7 @@ static int debug;
 module_param(debug, int, 0644);
 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
 
-#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiBX000: "); printk(args); } } while (0)
+#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiBX000: "); printk(args); printk("\n"); } } while (0)
 
 static int dibx000_write_word(struct dibx000_i2c_master *mst, u16 reg, u16 val)
 {
@@ -25,7 +25,7 @@ static int dibx000_i2c_select_interface(struct dibx000_i2c_master *mst,
                                         enum dibx000_i2c_interface intf)
 {
         if (mst->device_rev > DIB3000MC && mst->selected_interface != intf) {
-                dprintk("selecting interface: %d\n", intf);
+                dprintk("selecting interface: %d", intf);
                 mst->selected_interface = intf;
                 return dibx000_write_word(mst, mst->base_reg + 4, intf);
         }
@@ -171,9 +171,18 @@ void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst)
 {
         i2c_del_adapter(&mst->gated_tuner_i2c_adap);
 }
-
 EXPORT_SYMBOL(dibx000_exit_i2c_master);
 
+
+u32 systime(void)
+{
+    struct timespec t;
+
+    t = current_kernel_time();
+    return (t.tv_sec * 10000) + (t.tv_nsec / 100000);
+}
+EXPORT_SYMBOL(systime);
+
 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
 MODULE_DESCRIPTION("Common function the DiBcom demodulator family");
 MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dibx000_common.h b/drivers/media/dvb/frontends/dibx000_common.h
index 5be10eca07c0..4f5d141a308d 100644
--- a/drivers/media/dvb/frontends/dibx000_common.h
+++ b/drivers/media/dvb/frontends/dibx000_common.h
@@ -36,13 +36,17 @@ extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
 extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
 extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
 
+extern u32 systime(void);
+
 #define BAND_LBAND 0x01
 #define BAND_UHF   0x02
 #define BAND_VHF   0x04
 #define BAND_SBAND 0x08
-#define BAND_FM    0x10
+#define BAND_FM    0x10
+#define BAND_CBAND 0x20
 
-#define BAND_OF_FREQUENCY(freq_kHz) ( (freq_kHz) <= 115000 ? BAND_FM : \
+#define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
+                                                                        (freq_kHz) <= 115000 ? BAND_FM : \
                                                                         (freq_kHz) <= 250000 ? BAND_VHF : \
                                                                         (freq_kHz) <= 863000 ? BAND_UHF : \
                                                                         (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
@@ -149,4 +153,67 @@ enum dibx000_adc_states {
 #define OUTMODE_MPEG2_FIFO          5
 #define OUTMODE_ANALOG_ADC          6
 
+enum frontend_tune_state {
+    CT_TUNER_START = 10,
+    CT_TUNER_STEP_0,
+    CT_TUNER_STEP_1,
+    CT_TUNER_STEP_2,
+    CT_TUNER_STEP_3,
+    CT_TUNER_STEP_4,
+    CT_TUNER_STEP_5,
+    CT_TUNER_STEP_6,
+    CT_TUNER_STEP_7,
+    CT_TUNER_STOP,
+
+    CT_AGC_START = 20,
+    CT_AGC_STEP_0,
+    CT_AGC_STEP_1,
+    CT_AGC_STEP_2,
+    CT_AGC_STEP_3,
+    CT_AGC_STEP_4,
+    CT_AGC_STOP,
+
+        CT_DEMOD_START = 30,
+    CT_DEMOD_STEP_1,
+    CT_DEMOD_STEP_2,
+    CT_DEMOD_STEP_3,
+    CT_DEMOD_STEP_4,
+    CT_DEMOD_STEP_5,
+    CT_DEMOD_STEP_6,
+    CT_DEMOD_STEP_7,
+    CT_DEMOD_STEP_8,
+    CT_DEMOD_STEP_9,
+    CT_DEMOD_STEP_10,
+    CT_DEMOD_SEARCH_NEXT = 41,
+    CT_DEMOD_STEP_LOCKED,
+    CT_DEMOD_STOP,
+
+    CT_DONE = 100,
+    CT_SHUTDOWN,
+
+};
+
+struct dvb_frontend_parametersContext {
+#define CHANNEL_STATUS_PARAMETERS_UNKNOWN   0x01
+#define CHANNEL_STATUS_PARAMETERS_SET       0x02
+    u8 status;
+    u32 tune_time_estimation[2];
+    s32 tps_available;
+    u16 tps[9];
+};
+
+#define FE_STATUS_TUNE_FAILED          0
+#define FE_STATUS_TUNE_TIMED_OUT      -1
+#define FE_STATUS_TUNE_TIME_TOO_SHORT -2
+#define FE_STATUS_TUNE_PENDING        -3
+#define FE_STATUS_STD_SUCCESS         -4
+#define FE_STATUS_FFT_SUCCESS         -5
+#define FE_STATUS_DEMOD_SUCCESS       -6
+#define FE_STATUS_LOCKED              -7
+#define FE_STATUS_DATA_LOCKED         -8
+
+#define FE_CALLBACK_TIME_NEVER 0xffffffff
+
+#define ABS(x) ((x < 0) ? (-x) : (x))
+
 #endif
diff --git a/drivers/media/dvb/frontends/drx397xD.c b/drivers/media/dvb/frontends/drx397xD.c
index 010075535221..f74cca6dc26b 100644
--- a/drivers/media/dvb/frontends/drx397xD.c
+++ b/drivers/media/dvb/frontends/drx397xD.c
@@ -26,6 +26,7 @@
 #include <linux/delay.h>
 #include <linux/string.h>
 #include <linux/firmware.h>
+#include <linux/slab.h>
 #include <asm/div64.h>
 
 #include "dvb_frontend.h"
@@ -81,7 +82,7 @@ static struct {
 #include "drx397xD_fw.h"
 };
 
-/* use only with writer lock aquired */
+/* use only with writer lock acquired */
 static void _drx_release_fw(struct drx397xD_state *s, enum fw_ix ix)
 {
         memset(&fw[ix].data[0], 0, sizeof(fw[0].data));
diff --git a/drivers/media/dvb/frontends/ds3000.c b/drivers/media/dvb/frontends/ds3000.c
new file mode 100644
index 000000000000..cff3535566fe
--- /dev/null
+++ b/drivers/media/dvb/frontends/ds3000.c
@@ -0,0 +1,1367 @@
+/*
+    Montage Technology DS3000/TS2020 - DVBS/S2 Demodulator/Tuner driver
+    Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
+
+    Copyright (C) 2009 TurboSight.com
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/firmware.h>
+
+#include "dvb_frontend.h"
+#include "ds3000.h"
+
+static int debug;
+
+#define dprintk(args...) \
+        do { \
+                if (debug) \
+                        printk(args); \
+        } while (0)
+
+/* as of March 2009 current DS3000 firmware version is 1.78 */
+/* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
+#define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
+
+#define DS3000_SAMPLE_RATE 96000 /* in kHz */
+#define DS3000_XTAL_FREQ   27000 /* in kHz */
+
+/* Register values to initialise the demod in DVB-S mode */
+static u8 ds3000_dvbs_init_tab[] = {
+        0x23, 0x05,
+        0x08, 0x03,
+        0x0c, 0x00,
+        0x21, 0x54,
+        0x25, 0x82,
+        0x27, 0x31,
+        0x30, 0x08,
+        0x31, 0x40,
+        0x32, 0x32,
+        0x33, 0x35,
+        0x35, 0xff,
+        0x3a, 0x00,
+        0x37, 0x10,
+        0x38, 0x10,
+        0x39, 0x02,
+        0x42, 0x60,
+        0x4a, 0x40,
+        0x4b, 0x04,
+        0x4d, 0x91,
+        0x5d, 0xc8,
+        0x50, 0x77,
+        0x51, 0x77,
+        0x52, 0x36,
+        0x53, 0x36,
+        0x56, 0x01,
+        0x63, 0x43,
+        0x64, 0x30,
+        0x65, 0x40,
+        0x68, 0x26,
+        0x69, 0x4c,
+        0x70, 0x20,
+        0x71, 0x70,
+        0x72, 0x04,
+        0x73, 0x00,
+        0x70, 0x40,
+        0x71, 0x70,
+        0x72, 0x04,
+        0x73, 0x00,
+        0x70, 0x60,
+        0x71, 0x70,
+        0x72, 0x04,
+        0x73, 0x00,
+        0x70, 0x80,
+        0x71, 0x70,
+        0x72, 0x04,
+        0x73, 0x00,
+        0x70, 0xa0,
+        0x71, 0x70,
+        0x72, 0x04,
+        0x73, 0x00,
+        0x70, 0x1f,
+        0x76, 0x00,
+        0x77, 0xd1,
+        0x78, 0x0c,
+        0x79, 0x80,
+        0x7f, 0x04,
+        0x7c, 0x00,
+        0x80, 0x86,
+        0x81, 0xa6,
+        0x85, 0x04,
+        0xcd, 0xf4,
+        0x90, 0x33,
+        0xa0, 0x44,
+        0xc0, 0x18,
+        0xc3, 0x10,
+        0xc4, 0x08,
+        0xc5, 0x80,
+        0xc6, 0x80,
+        0xc7, 0x0a,
+        0xc8, 0x1a,
+        0xc9, 0x80,
+        0xfe, 0x92,
+        0xe0, 0xf8,
+        0xe6, 0x8b,
+        0xd0, 0x40,
+        0xf8, 0x20,
+        0xfa, 0x0f,
+        0xfd, 0x20,
+        0xad, 0x20,
+        0xae, 0x07,
+        0xb8, 0x00,
+};
+
+/* Register values to initialise the demod in DVB-S2 mode */
+static u8 ds3000_dvbs2_init_tab[] = {
+        0x23, 0x0f,
+        0x08, 0x07,
+        0x0c, 0x00,
+        0x21, 0x54,
+        0x25, 0x82,
+        0x27, 0x31,
+        0x30, 0x08,
+        0x31, 0x32,
+        0x32, 0x32,
+        0x33, 0x35,
+        0x35, 0xff,
+        0x3a, 0x00,
+        0x37, 0x10,
+        0x38, 0x10,
+        0x39, 0x02,
+        0x42, 0x60,
+        0x4a, 0x80,
+        0x4b, 0x04,
+        0x4d, 0x81,
+        0x5d, 0x88,
+        0x50, 0x36,
+        0x51, 0x36,
+        0x52, 0x36,
+        0x53, 0x36,
+        0x63, 0x60,
+        0x64, 0x10,
+        0x65, 0x10,
+        0x68, 0x04,
+        0x69, 0x29,
+        0x70, 0x20,
+        0x71, 0x70,
+        0x72, 0x04,
+        0x73, 0x00,
+        0x70, 0x40,
+        0x71, 0x70,
+        0x72, 0x04,
+        0x73, 0x00,
+        0x70, 0x60,
+        0x71, 0x70,
+        0x72, 0x04,
+        0x73, 0x00,
+        0x70, 0x80,
+        0x71, 0x70,
+        0x72, 0x04,
+        0x73, 0x00,
+        0x70, 0xa0,
+        0x71, 0x70,
+        0x72, 0x04,
+        0x73, 0x00,
+        0x70, 0x1f,
+        0xa0, 0x44,
+        0xc0, 0x08,
+        0xc1, 0x10,
+        0xc2, 0x08,
+        0xc3, 0x10,
+        0xc4, 0x08,
+        0xc5, 0xf0,
+        0xc6, 0xf0,
+        0xc7, 0x0a,
+        0xc8, 0x1a,
+        0xc9, 0x80,
+        0xca, 0x23,
+        0xcb, 0x24,
+        0xce, 0x74,
+        0x90, 0x03,
+        0x76, 0x80,
+        0x77, 0x42,
+        0x78, 0x0a,
+        0x79, 0x80,
+        0xad, 0x40,
+        0xae, 0x07,
+        0x7f, 0xd4,
+        0x7c, 0x00,
+        0x80, 0xa8,
+        0x81, 0xda,
+        0x7c, 0x01,
+        0x80, 0xda,
+        0x81, 0xec,
+        0x7c, 0x02,
+        0x80, 0xca,
+        0x81, 0xeb,
+        0x7c, 0x03,
+        0x80, 0xba,
+        0x81, 0xdb,
+        0x85, 0x08,
+        0x86, 0x00,
+        0x87, 0x02,
+        0x89, 0x80,
+        0x8b, 0x44,
+        0x8c, 0xaa,
+        0x8a, 0x10,
+        0xba, 0x00,
+        0xf5, 0x04,
+        0xfe, 0x44,
+        0xd2, 0x32,
+        0xb8, 0x00,
+};
+
+/* DS3000 doesn't need some parameters as input and auto-detects them */
+/* save input from the application of those parameters */
+struct ds3000_tuning {
+        u32 frequency;
+        u32 symbol_rate;
+        fe_spectral_inversion_t inversion;
+        enum fe_code_rate fec;
+
+        /* input values */
+        u8 inversion_val;
+        fe_modulation_t delivery;
+        u8 rolloff;
+};
+
+struct ds3000_state {
+        struct i2c_adapter *i2c;
+        const struct ds3000_config *config;
+
+        struct dvb_frontend frontend;
+
+        struct ds3000_tuning dcur;
+        struct ds3000_tuning dnxt;
+
+        u8 skip_fw_load;
+
+        /* previous uncorrected block counter for DVB-S2 */
+        u16 prevUCBS2;
+};
+
+static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
+{
+        u8 buf[] = { reg, data };
+        struct i2c_msg msg = { .addr = state->config->demod_address,
+                .flags = 0, .buf = buf, .len = 2 };
+        int err;
+
+        dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
+
+        err = i2c_transfer(state->i2c, &msg, 1);
+        if (err != 1) {
+                printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
+                         " value == 0x%02x)\n", __func__, err, reg, data);
+                return -EREMOTEIO;
+        }
+
+        return 0;
+}
+
+static int ds3000_tuner_writereg(struct ds3000_state *state, int reg, int data)
+{
+        u8 buf[] = { reg, data };
+        struct i2c_msg msg = { .addr = 0x60,
+                .flags = 0, .buf = buf, .len = 2 };
+        int err;
+
+        dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
+
+        ds3000_writereg(state, 0x03, 0x11);
+        err = i2c_transfer(state->i2c, &msg, 1);
+        if (err != 1) {
+                printk("%s: writereg error(err == %i, reg == 0x%02x,"
+                         " value == 0x%02x)\n", __func__, err, reg, data);
+                return -EREMOTEIO;
+        }
+
+        return 0;
+}
+
+/* I2C write for 8k firmware load */
+static int ds3000_writeFW(struct ds3000_state *state, int reg,
+                                const u8 *data, u16 len)
+{
+        int i, ret = -EREMOTEIO;
+        struct i2c_msg msg;
+        u8 *buf;
+
+        buf = kmalloc(3, GFP_KERNEL);
+        if (buf == NULL) {
+                printk(KERN_ERR "Unable to kmalloc\n");
+                ret = -ENOMEM;
+                goto error;
+        }
+
+        *(buf) = reg;
+
+        msg.addr = state->config->demod_address;
+        msg.flags = 0;
+        msg.buf = buf;
+        msg.len = 3;
+
+        for (i = 0; i < len; i += 2) {
+                memcpy(buf + 1, data + i, 2);
+
+                dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
+
+                ret = i2c_transfer(state->i2c, &msg, 1);
+                if (ret != 1) {
+                        printk(KERN_ERR "%s: write error(err == %i, "
+                                "reg == 0x%02x\n", __func__, ret, reg);
+                        ret = -EREMOTEIO;
+                }
+        }
+
+error:
+        kfree(buf);
+
+        return ret;
+}
+
+static int ds3000_readreg(struct ds3000_state *state, u8 reg)
+{
+        int ret;
+        u8 b0[] = { reg };
+        u8 b1[] = { 0 };
+        struct i2c_msg msg[] = {
+                {
+                        .addr = state->config->demod_address,
+                        .flags = 0,
+                        .buf = b0,
+                        .len = 1
+                }, {
+                        .addr = state->config->demod_address,
+                        .flags = I2C_M_RD,
+                        .buf = b1,
+                        .len = 1
+                }
+        };
+
+        ret = i2c_transfer(state->i2c, msg, 2);
+
+        if (ret != 2) {
+                printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
+                return ret;
+        }
+
+        dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
+
+        return b1[0];
+}
+
+static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
+{
+        int ret;
+        u8 b0[] = { reg };
+        u8 b1[] = { 0 };
+        struct i2c_msg msg[] = {
+                {
+                        .addr = 0x60,
+                        .flags = 0,
+                        .buf = b0,
+                        .len = 1
+                }, {
+                        .addr = 0x60,
+                        .flags = I2C_M_RD,
+                        .buf = b1,
+                        .len = 1
+                }
+        };
+
+        ds3000_writereg(state, 0x03, 0x12);
+        ret = i2c_transfer(state->i2c, msg, 2);
+
+        if (ret != 2) {
+                printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
+                return ret;
+        }
+
+        dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
+
+        return b1[0];
+}
+
+static int ds3000_set_inversion(struct ds3000_state *state,
+                                        fe_spectral_inversion_t inversion)
+{
+        dprintk("%s(%d)\n", __func__, inversion);
+
+        switch (inversion) {
+        case INVERSION_OFF:
+        case INVERSION_ON:
+        case INVERSION_AUTO:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        state->dnxt.inversion = inversion;
+
+        return 0;
+}
+
+static int ds3000_set_symbolrate(struct ds3000_state *state, u32 rate)
+{
+        int ret = 0;
+
+        dprintk("%s()\n", __func__);
+
+        dprintk("%s() symbol_rate = %d\n", __func__, state->dnxt.symbol_rate);
+
+        /*  check if symbol rate is within limits */
+        if ((state->dnxt.symbol_rate >
+                                state->frontend.ops.info.symbol_rate_max) ||
+            (state->dnxt.symbol_rate <
+                                state->frontend.ops.info.symbol_rate_min))
+                ret = -EOPNOTSUPP;
+
+        state->dnxt.symbol_rate = rate;
+
+        return ret;
+}
+
+static int ds3000_load_firmware(struct dvb_frontend *fe,
+                                        const struct firmware *fw);
+
+static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        const struct firmware *fw;
+        int ret = 0;
+
+        dprintk("%s()\n", __func__);
+
+        if (ds3000_readreg(state, 0xb2) <= 0)
+                return ret;
+
+        if (state->skip_fw_load)
+                return 0;
+        /* Load firmware */
+        /* request the firmware, this will block until someone uploads it */
+        printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
+                                DS3000_DEFAULT_FIRMWARE);
+        ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
+                                state->i2c->dev.parent);
+        printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
+        if (ret) {
+                printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
+                                "found?)\n", __func__);
+                return ret;
+        }
+
+        /* Make sure we don't recurse back through here during loading */
+        state->skip_fw_load = 1;
+
+        ret = ds3000_load_firmware(fe, fw);
+        if (ret)
+                printk("%s: Writing firmware to device failed\n", __func__);
+
+        release_firmware(fw);
+
+        dprintk("%s: Firmware upload %s\n", __func__,
+                        ret == 0 ? "complete" : "failed");
+
+        /* Ensure firmware is always loaded if required */
+        state->skip_fw_load = 0;
+
+        return ret;
+}
+
+static int ds3000_load_firmware(struct dvb_frontend *fe,
+                                        const struct firmware *fw)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+
+        dprintk("%s\n", __func__);
+        dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
+                        fw->size,
+                        fw->data[0],
+                        fw->data[1],
+                        fw->data[fw->size - 2],
+                        fw->data[fw->size - 1]);
+
+        /* Begin the firmware load process */
+        ds3000_writereg(state, 0xb2, 0x01);
+        /* write the entire firmware */
+        ds3000_writeFW(state, 0xb0, fw->data, fw->size);
+        ds3000_writereg(state, 0xb2, 0x00);
+
+        return 0;
+}
+
+static void ds3000_dump_registers(struct dvb_frontend *fe)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        int x, y, reg = 0, val;
+
+        for (y = 0; y < 16; y++) {
+                dprintk("%s: %02x: ", __func__, y);
+                for (x = 0; x < 16; x++) {
+                        reg = (y << 4) + x;
+                        val = ds3000_readreg(state, reg);
+                        if (x != 15)
+                                dprintk("%02x ",  val);
+                        else
+                                dprintk("%02x\n", val);
+                }
+        }
+        dprintk("%s: -- DS3000 DUMP DONE --\n", __func__);
+}
+
+static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+        int lock;
+
+        *status = 0;
+
+        switch (c->delivery_system) {
+        case SYS_DVBS:
+                lock = ds3000_readreg(state, 0xd1);
+                if ((lock & 0x07) == 0x07)
+                        *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
+                                FE_HAS_VITERBI | FE_HAS_SYNC |
+                                FE_HAS_LOCK;
+
+                break;
+        case SYS_DVBS2:
+                lock = ds3000_readreg(state, 0x0d);
+                if ((lock & 0x8f) == 0x8f)
+                        *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
+                                FE_HAS_VITERBI | FE_HAS_SYNC |
+                                FE_HAS_LOCK;
+
+                break;
+        default:
+                return 1;
+        }
+
+        dprintk("%s: status = 0x%02x\n", __func__, lock);
+
+        return 0;
+}
+
+#define FE_IS_TUNED (FE_HAS_SIGNAL + FE_HAS_LOCK)
+static int ds3000_is_tuned(struct dvb_frontend *fe)
+{
+        fe_status_t tunerstat;
+
+        ds3000_read_status(fe, &tunerstat);
+
+        return ((tunerstat & FE_IS_TUNED) == FE_IS_TUNED);
+}
+
+/* read DS3000 BER value */
+static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+        u8 data;
+        u32 ber_reading, lpdc_frames;
+
+        dprintk("%s()\n", __func__);
+
+        switch (c->delivery_system) {
+        case SYS_DVBS:
+                /* set the number of bytes checked during
+                BER estimation */
+                ds3000_writereg(state, 0xf9, 0x04);
+                /* read BER estimation status */
+                data = ds3000_readreg(state, 0xf8);
+                /* check if BER estimation is ready */
+                if ((data & 0x10) == 0) {
+                        /* this is the number of error bits,
+                        to calculate the bit error rate
+                        divide to 8388608 */
+                        *ber = (ds3000_readreg(state, 0xf7) << 8) |
+                                ds3000_readreg(state, 0xf6);
+                        /* start counting error bits */
+                        /* need to be set twice
+                        otherwise it fails sometimes */
+                        data |= 0x10;
+                        ds3000_writereg(state, 0xf8, data);
+                        ds3000_writereg(state, 0xf8, data);
+                } else
+                        /* used to indicate that BER estimation
+                        is not ready, i.e. BER is unknown */
+                        *ber = 0xffffffff;
+                break;
+        case SYS_DVBS2:
+                /* read the number of LPDC decoded frames */
+                lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
+                                (ds3000_readreg(state, 0xd6) << 8) |
+                                ds3000_readreg(state, 0xd5);
+                /* read the number of packets with bad CRC */
+                ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
+                                ds3000_readreg(state, 0xf7);
+                if (lpdc_frames > 750) {
+                        /* clear LPDC frame counters */
+                        ds3000_writereg(state, 0xd1, 0x01);
+                        /* clear bad packets counter */
+                        ds3000_writereg(state, 0xf9, 0x01);
+                        /* enable bad packets counter */
+                        ds3000_writereg(state, 0xf9, 0x00);
+                        /* enable LPDC frame counters */
+                        ds3000_writereg(state, 0xd1, 0x00);
+                        *ber = ber_reading;
+                } else
+                        /* used to indicate that BER estimation is not ready,
+                        i.e. BER is unknown */
+                        *ber = 0xffffffff;
+                break;
+        default:
+                return 1;
+        }
+
+        return 0;
+}
+
+/* read TS2020 signal strength */
+static int ds3000_read_signal_strength(struct dvb_frontend *fe,
+                                                u16 *signal_strength)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        u16 sig_reading, sig_strength;
+        u8 rfgain, bbgain;
+
+        dprintk("%s()\n", __func__);
+
+        rfgain = ds3000_tuner_readreg(state, 0x3d) & 0x1f;
+        bbgain = ds3000_tuner_readreg(state, 0x21) & 0x1f;
+
+        if (rfgain > 15)
+                rfgain = 15;
+        if (bbgain > 13)
+                bbgain = 13;
+
+        sig_reading = rfgain * 2 + bbgain * 3;
+
+        sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
+
+        /* cook the value to be suitable for szap-s2 human readable output */
+        *signal_strength = sig_strength * 1000;
+
+        dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n", __func__,
+                        sig_reading, *signal_strength);
+
+        return 0;
+}
+
+/* calculate DS3000 snr value in dB */
+static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+        u8 snr_reading, snr_value;
+        u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
+        static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
+                0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
+                0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
+                0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
+        };
+        static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
+                0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
+                0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
+                0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
+                0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
+                0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
+                0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
+                0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
+                0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
+                0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
+                0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
+                0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
+                0x49e9, 0x4a20, 0x4a57
+        };
+
+        dprintk("%s()\n", __func__);
+
+        switch (c->delivery_system) {
+        case SYS_DVBS:
+                snr_reading = ds3000_readreg(state, 0xff);
+                snr_reading /= 8;
+                if (snr_reading == 0)
+                        *snr = 0x0000;
+                else {
+                        if (snr_reading > 20)
+                                snr_reading = 20;
+                        snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
+                        /* cook the value to be suitable for szap-s2
+                        human readable output */
+                        *snr = snr_value * 8 * 655;
+                }
+                dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
+                                snr_reading, *snr);
+                break;
+        case SYS_DVBS2:
+                dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
+                                (ds3000_readreg(state, 0x8d) << 4);
+                dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
+                tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
+                if (dvbs2_signal_reading == 0) {
+                        *snr = 0x0000;
+                        return 0;
+                }
+                if (dvbs2_noise_reading == 0) {
+                        snr_value = 0x0013;
+                        /* cook the value to be suitable for szap-s2
+                        human readable output */
+                        *snr = 0xffff;
+                        return 0;
+                }
+                if (tmp > dvbs2_noise_reading) {
+                        snr_reading = tmp / dvbs2_noise_reading;
+                        if (snr_reading > 80)
+                                snr_reading = 80;
+                        snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
+                        /* cook the value to be suitable for szap-s2
+                        human readable output */
+                        *snr = snr_value * 5 * 655;
+                } else {
+                        snr_reading = dvbs2_noise_reading / tmp;
+                        if (snr_reading > 80)
+                                snr_reading = 80;
+                        *snr = -(dvbs2_snr_tab[snr_reading] / 1000);
+                }
+                dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
+                                snr_reading, *snr);
+                break;
+        default:
+                return 1;
+        }
+
+        return 0;
+}
+
+/* read DS3000 uncorrected blocks */
+static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+        u8 data;
+        u16 _ucblocks;
+
+        dprintk("%s()\n", __func__);
+
+        switch (c->delivery_system) {
+        case SYS_DVBS:
+                *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
+                                ds3000_readreg(state, 0xf4);
+                data = ds3000_readreg(state, 0xf8);
+                /* clear packet counters */
+                data &= ~0x20;
+                ds3000_writereg(state, 0xf8, data);
+                /* enable packet counters */
+                data |= 0x20;
+                ds3000_writereg(state, 0xf8, data);
+                break;
+        case SYS_DVBS2:
+                _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
+                                ds3000_readreg(state, 0xe1);
+                if (_ucblocks > state->prevUCBS2)
+                        *ucblocks = _ucblocks - state->prevUCBS2;
+                else
+                        *ucblocks = state->prevUCBS2 - _ucblocks;
+                state->prevUCBS2 = _ucblocks;
+                break;
+        default:
+                return 1;
+        }
+
+        return 0;
+}
+
+/* Overwrite the current tuning params, we are about to tune */
+static void ds3000_clone_params(struct dvb_frontend *fe)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        memcpy(&state->dcur, &state->dnxt, sizeof(state->dcur));
+}
+
+static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        u8 data;
+
+        dprintk("%s(%d)\n", __func__, tone);
+        if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
+                printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
+                return -EINVAL;
+        }
+
+        data = ds3000_readreg(state, 0xa2);
+        data &= ~0xc0;
+        ds3000_writereg(state, 0xa2, data);
+
+        switch (tone) {
+        case SEC_TONE_ON:
+                dprintk("%s: setting tone on\n", __func__);
+                data = ds3000_readreg(state, 0xa1);
+                data &= ~0x43;
+                data |= 0x04;
+                ds3000_writereg(state, 0xa1, data);
+                break;
+        case SEC_TONE_OFF:
+                dprintk("%s: setting tone off\n", __func__);
+                data = ds3000_readreg(state, 0xa2);
+                data |= 0x80;
+                ds3000_writereg(state, 0xa2, data);
+                break;
+        }
+
+        return 0;
+}
+
+static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
+                                struct dvb_diseqc_master_cmd *d)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        int i;
+        u8 data;
+
+        /* Dump DiSEqC message */
+        dprintk("%s(", __func__);
+        for (i = 0 ; i < d->msg_len;) {
+                dprintk("0x%02x", d->msg[i]);
+                if (++i < d->msg_len)
+                        dprintk(", ");
+        }
+
+        /* enable DiSEqC message send pin */
+        data = ds3000_readreg(state, 0xa2);
+        data &= ~0xc0;
+        ds3000_writereg(state, 0xa2, data);
+
+        /* DiSEqC message */
+        for (i = 0; i < d->msg_len; i++)
+                ds3000_writereg(state, 0xa3 + i, d->msg[i]);
+
+        data = ds3000_readreg(state, 0xa1);
+        /* clear DiSEqC message length and status,
+        enable DiSEqC message send */
+        data &= ~0xf8;
+        /* set DiSEqC mode, modulation active during 33 pulses,
+        set DiSEqC message length */
+        data |= ((d->msg_len - 1) << 3) | 0x07;
+        ds3000_writereg(state, 0xa1, data);
+
+        /* wait up to 150ms for DiSEqC transmission to complete */
+        for (i = 0; i < 15; i++) {
+                data = ds3000_readreg(state, 0xa1);
+                if ((data & 0x40) == 0)
+                        break;
+                msleep(10);
+        }
+
+        /* DiSEqC timeout after 150ms */
+        if (i == 15) {
+                data = ds3000_readreg(state, 0xa1);
+                data &= ~0x80;
+                data |= 0x40;
+                ds3000_writereg(state, 0xa1, data);
+
+                data = ds3000_readreg(state, 0xa2);
+                data &= ~0xc0;
+                data |= 0x80;
+                ds3000_writereg(state, 0xa2, data);
+
+                return 1;
+        }
+
+        data = ds3000_readreg(state, 0xa2);
+        data &= ~0xc0;
+        data |= 0x80;
+        ds3000_writereg(state, 0xa2, data);
+
+        return 0;
+}
+
+/* Send DiSEqC burst */
+static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
+                                        fe_sec_mini_cmd_t burst)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        int i;
+        u8 data;
+
+        dprintk("%s()\n", __func__);
+
+        data = ds3000_readreg(state, 0xa2);
+        data &= ~0xc0;
+        ds3000_writereg(state, 0xa2, data);
+
+        /* DiSEqC burst */
+        if (burst == SEC_MINI_A)
+                /* Unmodulated tone burst */
+                ds3000_writereg(state, 0xa1, 0x02);
+        else if (burst == SEC_MINI_B)
+                /* Modulated tone burst */
+                ds3000_writereg(state, 0xa1, 0x01);
+        else
+                return -EINVAL;
+
+        msleep(13);
+        for (i = 0; i < 5; i++) {
+                data = ds3000_readreg(state, 0xa1);
+                if ((data & 0x40) == 0)
+                        break;
+                msleep(1);
+        }
+
+        if (i == 5) {
+                data = ds3000_readreg(state, 0xa1);
+                data &= ~0x80;
+                data |= 0x40;
+                ds3000_writereg(state, 0xa1, data);
+
+                data = ds3000_readreg(state, 0xa2);
+                data &= ~0xc0;
+                data |= 0x80;
+                ds3000_writereg(state, 0xa2, data);
+
+                return 1;
+        }
+
+        data = ds3000_readreg(state, 0xa2);
+        data &= ~0xc0;
+        data |= 0x80;
+        ds3000_writereg(state, 0xa2, data);
+
+        return 0;
+}
+
+static void ds3000_release(struct dvb_frontend *fe)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        dprintk("%s\n", __func__);
+        kfree(state);
+}
+
+static struct dvb_frontend_ops ds3000_ops;
+
+struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
+                                    struct i2c_adapter *i2c)
+{
+        struct ds3000_state *state = NULL;
+        int ret;
+
+        dprintk("%s\n", __func__);
+
+        /* allocate memory for the internal state */
+        state = kmalloc(sizeof(struct ds3000_state), GFP_KERNEL);
+        if (state == NULL) {
+                printk(KERN_ERR "Unable to kmalloc\n");
+                goto error2;
+        }
+
+        /* setup the state */
+        memset(state, 0, sizeof(struct ds3000_state));
+
+        state->config = config;
+        state->i2c = i2c;
+        state->prevUCBS2 = 0;
+
+        /* check if the demod is present */
+        ret = ds3000_readreg(state, 0x00) & 0xfe;
+        if (ret != 0xe0) {
+                printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
+                goto error3;
+        }
+
+        printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
+                        ds3000_readreg(state, 0x02),
+                        ds3000_readreg(state, 0x01));
+
+        memcpy(&state->frontend.ops, &ds3000_ops,
+                        sizeof(struct dvb_frontend_ops));
+        state->frontend.demodulator_priv = state;
+        return &state->frontend;
+
+error3:
+        kfree(state);
+error2:
+        return NULL;
+}
+EXPORT_SYMBOL(ds3000_attach);
+
+static int ds3000_set_property(struct dvb_frontend *fe,
+        struct dtv_property *tvp)
+{
+        dprintk("%s(..)\n", __func__);
+        return 0;
+}
+
+static int ds3000_get_property(struct dvb_frontend *fe,
+        struct dtv_property *tvp)
+{
+        dprintk("%s(..)\n", __func__);
+        return 0;
+}
+
+static int ds3000_tune(struct dvb_frontend *fe,
+                                struct dvb_frontend_parameters *p)
+{
+        struct ds3000_state *state = fe->demodulator_priv;
+        struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+
+        int ret = 0, retune, i;
+        u8 status, mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf;
+        u16 value, ndiv;
+        u32 f3db;
+
+        dprintk("%s() ", __func__);
+
+        /* Load the firmware if required */
+        ret = ds3000_firmware_ondemand(fe);
+        if (ret != 0) {
+                printk(KERN_ERR "%s: Unable initialise the firmware\n",
+                                                                __func__);
+                return ret;
+        }
+
+        state->dnxt.delivery = c->modulation;
+        state->dnxt.frequency = c->frequency;
+        state->dnxt.rolloff = 2; /* fixme */
+        state->dnxt.fec = c->fec_inner;
+
+        ret = ds3000_set_inversion(state, p->inversion);
+        if (ret !=  0)
+                return ret;
+
+        ret = ds3000_set_symbolrate(state, c->symbol_rate);
+        if (ret !=  0)
+                return ret;
+
+        /* discard the 'current' tuning parameters and prepare to tune */
+        ds3000_clone_params(fe);
+
+        retune = 1;     /* try 1 times */
+        dprintk("%s:   retune = %d\n", __func__, retune);
+        dprintk("%s:   frequency   = %d\n", __func__, state->dcur.frequency);
+        dprintk("%s:   symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
+        dprintk("%s:   FEC       = %d \n", __func__,
+                state->dcur.fec);
+        dprintk("%s:   Inversion   = %d\n", __func__, state->dcur.inversion);
+
+        do {
+                /* Reset status register */
+                status = 0;
+                /* Tune */
+                /* TS2020 init */
+                ds3000_tuner_writereg(state, 0x42, 0x73);
+                ds3000_tuner_writereg(state, 0x05, 0x01);
+                ds3000_tuner_writereg(state, 0x62, 0xf5);
+                /* unknown */
+                ds3000_tuner_writereg(state, 0x07, 0x02);
+                ds3000_tuner_writereg(state, 0x10, 0x00);
+                ds3000_tuner_writereg(state, 0x60, 0x79);
+                ds3000_tuner_writereg(state, 0x08, 0x01);
+                ds3000_tuner_writereg(state, 0x00, 0x01);
+                /* calculate and set freq divider */
+                if (state->dcur.frequency < 1146000) {
+                        ds3000_tuner_writereg(state, 0x10, 0x11);
+                        ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
+                                        (DS3000_XTAL_FREQ / 2)) /
+                                        DS3000_XTAL_FREQ - 1024;
+                } else {
+                        ds3000_tuner_writereg(state, 0x10, 0x01);
+                        ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
+                                        (DS3000_XTAL_FREQ / 2)) /
+                                        DS3000_XTAL_FREQ - 1024;
+                }
+
+                ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
+                ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
+
+                /* set pll */
+                ds3000_tuner_writereg(state, 0x03, 0x06);
+                ds3000_tuner_writereg(state, 0x51, 0x0f);
+                ds3000_tuner_writereg(state, 0x51, 0x1f);
+                ds3000_tuner_writereg(state, 0x50, 0x10);
+                ds3000_tuner_writereg(state, 0x50, 0x00);
+                msleep(5);
+
+                /* unknown */
+                ds3000_tuner_writereg(state, 0x51, 0x17);
+                ds3000_tuner_writereg(state, 0x51, 0x1f);
+                ds3000_tuner_writereg(state, 0x50, 0x08);
+                ds3000_tuner_writereg(state, 0x50, 0x00);
+                msleep(5);
+
+                value = ds3000_tuner_readreg(state, 0x3d);
+                value &= 0x0f;
+                if ((value > 4) && (value < 15)) {
+                        value -= 3;
+                        if (value < 4)
+                                value = 4;
+                        value = ((value << 3) | 0x01) & 0x79;
+                }
+
+                ds3000_tuner_writereg(state, 0x60, value);
+                ds3000_tuner_writereg(state, 0x51, 0x17);
+                ds3000_tuner_writereg(state, 0x51, 0x1f);
+                ds3000_tuner_writereg(state, 0x50, 0x08);
+                ds3000_tuner_writereg(state, 0x50, 0x00);
+
+                /* set low-pass filter period */
+                ds3000_tuner_writereg(state, 0x04, 0x2e);
+                ds3000_tuner_writereg(state, 0x51, 0x1b);
+                ds3000_tuner_writereg(state, 0x51, 0x1f);
+                ds3000_tuner_writereg(state, 0x50, 0x04);
+                ds3000_tuner_writereg(state, 0x50, 0x00);
+                msleep(5);
+
+                f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;
+                if ((state->dcur.symbol_rate / 1000) < 5000)
+                        f3db += 3000;
+                if (f3db < 7000)
+                        f3db = 7000;
+                if (f3db > 40000)
+                        f3db = 40000;
+
+                /* set low-pass filter baseband */
+                value = ds3000_tuner_readreg(state, 0x26);
+                mlpf = 0x2e * 207 / ((value << 1) + 151);
+                mlpf_max = mlpf * 135 / 100;
+                mlpf_min = mlpf * 78 / 100;
+                if (mlpf_max > 63)
+                        mlpf_max = 63;
+
+                /* rounded to the closest integer */
+                nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
+                                / (2766 * DS3000_XTAL_FREQ);
+                if (nlpf > 23)
+                        nlpf = 23;
+                if (nlpf < 1)
+                        nlpf = 1;
+
+                /* rounded to the closest integer */
+                mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
+                                (1000 * f3db / 2)) / (1000 * f3db);
+
+                if (mlpf_new < mlpf_min) {
+                        nlpf++;
+                        mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
+                                        (1000 * f3db / 2)) / (1000 * f3db);
+                }
+
+                if (mlpf_new > mlpf_max)
+                        mlpf_new = mlpf_max;
+
+                ds3000_tuner_writereg(state, 0x04, mlpf_new);
+                ds3000_tuner_writereg(state, 0x06, nlpf);
+                ds3000_tuner_writereg(state, 0x51, 0x1b);
+                ds3000_tuner_writereg(state, 0x51, 0x1f);
+                ds3000_tuner_writereg(state, 0x50, 0x04);
+                ds3000_tuner_writereg(state, 0x50, 0x00);
+                msleep(5);
+
+                /* unknown */
+                ds3000_tuner_writereg(state, 0x51, 0x1e);
+                ds3000_tuner_writereg(state, 0x51, 0x1f);
+                ds3000_tuner_writereg(state, 0x50, 0x01);
+                ds3000_tuner_writereg(state, 0x50, 0x00);
+                msleep(60);
+
+                /* ds3000 global reset */
+                ds3000_writereg(state, 0x07, 0x80);
+                ds3000_writereg(state, 0x07, 0x00);
+                /* ds3000 build-in uC reset */
+                ds3000_writereg(state, 0xb2, 0x01);
+                /* ds3000 software reset */
+                ds3000_writereg(state, 0x00, 0x01);
+
+                switch (c->delivery_system) {
+                case SYS_DVBS:
+                        /* initialise the demod in DVB-S mode */
+                        for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
+                                ds3000_writereg(state,
+                                        ds3000_dvbs_init_tab[i],
+                                        ds3000_dvbs_init_tab[i + 1]);
+                        value = ds3000_readreg(state, 0xfe);
+                        value &= 0xc0;
+                        value |= 0x1b;
+                        ds3000_writereg(state, 0xfe, value);
+                        break;
+                case SYS_DVBS2:
+                        /* initialise the demod in DVB-S2 mode */
+                        for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
+                                ds3000_writereg(state,
+                                        ds3000_dvbs2_init_tab[i],
+                                        ds3000_dvbs2_init_tab[i + 1]);
+                        ds3000_writereg(state, 0xfe, 0x54);
+                        break;
+                default:
+                        return 1;
+                }
+
+                /* enable 27MHz clock output */
+                ds3000_writereg(state, 0x29, 0x80);
+                /* enable ac coupling */
+                ds3000_writereg(state, 0x25, 0x8a);
+
+                /* enhance symbol rate performance */
+                if ((state->dcur.symbol_rate / 1000) <= 5000) {
+                        value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
+                        if (value % 2 != 0)
+                                value++;
+                        ds3000_writereg(state, 0xc3, 0x0d);
+                        ds3000_writereg(state, 0xc8, value);
+                        ds3000_writereg(state, 0xc4, 0x10);
+                        ds3000_writereg(state, 0xc7, 0x0e);
+                } else if ((state->dcur.symbol_rate / 1000) <= 10000) {
+                        value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
+                        if (value % 2 != 0)
+                                value++;
+                        ds3000_writereg(state, 0xc3, 0x07);
+                        ds3000_writereg(state, 0xc8, value);
+                        ds3000_writereg(state, 0xc4, 0x09);
+                        ds3000_writereg(state, 0xc7, 0x12);
+                } else if ((state->dcur.symbol_rate / 1000) <= 20000) {
+                        value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
+                        ds3000_writereg(state, 0xc3, value);
+                        ds3000_writereg(state, 0xc8, 0x0e);
+                        ds3000_writereg(state, 0xc4, 0x07);
+                        ds3000_writereg(state, 0xc7, 0x18);
+                } else {
+                        value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
+                        ds3000_writereg(state, 0xc3, value);
+                        ds3000_writereg(state, 0xc8, 0x0a);
+                        ds3000_writereg(state, 0xc4, 0x05);
+                        ds3000_writereg(state, 0xc7, 0x24);
+                }
+
+                /* normalized symbol rate rounded to the closest integer */
+                value = (((state->dcur.symbol_rate / 1000) << 16) +
+                                (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
+                ds3000_writereg(state, 0x61, value & 0x00ff);
+                ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
+
+                /* co-channel interference cancellation disabled */
+                ds3000_writereg(state, 0x56, 0x00);
+
+                /* equalizer disabled */
+                ds3000_writereg(state, 0x76, 0x00);
+
+                /*ds3000_writereg(state, 0x08, 0x03);
+                ds3000_writereg(state, 0xfd, 0x22);
+                ds3000_writereg(state, 0x08, 0x07);
+                ds3000_writereg(state, 0xfd, 0x42);
+                ds3000_writereg(state, 0x08, 0x07);*/
+
+                /* ds3000 out of software reset */
+                ds3000_writereg(state, 0x00, 0x00);
+                /* start ds3000 build-in uC */
+                ds3000_writereg(state, 0xb2, 0x00);
+
+                /* TODO: calculate and set carrier offset */
+
+                /* wait before retrying */
+                for (i = 0; i < 30 ; i++) {
+                        if (ds3000_is_tuned(fe)) {
+                                dprintk("%s: Tuned\n", __func__);
+                                ds3000_dump_registers(fe);
+                                goto tuned;
+                        }
+                        msleep(1);
+                }
+
+                dprintk("%s: Not tuned\n", __func__);
+                ds3000_dump_registers(fe);
+
+        } while (--retune);
+
+tuned:
+        return ret;
+}
+
+static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
+{
+        dprintk("%s()\n", __func__);
+        return DVBFE_ALGO_SW;
+}
+
+/*
+ * Initialise or wake up device
+ *
+ * Power config will reset and load initial firmware if required
+ */
+static int ds3000_initfe(struct dvb_frontend *fe)
+{
+        dprintk("%s()\n", __func__);
+        return 0;
+}
+
+/* Put device to sleep */
+static int ds3000_sleep(struct dvb_frontend *fe)
+{
+        dprintk("%s()\n", __func__);
+        return 0;
+}
+
+static struct dvb_frontend_ops ds3000_ops = {
+
+        .info = {
+                .name = "Montage Technology DS3000/TS2020",
+                .type = FE_QPSK,
+                .frequency_min = 950000,
+                .frequency_max = 2150000,
+                .frequency_stepsize = 1011, /* kHz for QPSK frontends */
+                .frequency_tolerance = 5000,
+                .symbol_rate_min = 1000000,
+                .symbol_rate_max = 45000000,
+                .caps = FE_CAN_INVERSION_AUTO |
+                        FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+                        FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
+                        FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+                        FE_CAN_2G_MODULATION |
+                        FE_CAN_QPSK | FE_CAN_RECOVER
+        },
+
+        .release = ds3000_release,
+
+        .init = ds3000_initfe,
+        .sleep = ds3000_sleep,
+        .read_status = ds3000_read_status,
+        .read_ber = ds3000_read_ber,
+        .read_signal_strength = ds3000_read_signal_strength,
+        .read_snr = ds3000_read_snr,
+        .read_ucblocks = ds3000_read_ucblocks,
+        .set_tone = ds3000_set_tone,
+        .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
+        .diseqc_send_burst = ds3000_diseqc_send_burst,
+        .get_frontend_algo = ds3000_get_algo,
+
+        .set_property = ds3000_set_property,
+        .get_property = ds3000_get_property,
+        .set_frontend = ds3000_tune,
+};
+
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
+
+MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
+                        "DS3000/TS2020 hardware");
+MODULE_AUTHOR("Konstantin Dimitrov");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/ds3000.h b/drivers/media/dvb/frontends/ds3000.h
new file mode 100644
index 000000000000..67f67038740a
--- /dev/null
+++ b/drivers/media/dvb/frontends/ds3000.h
@@ -0,0 +1,45 @@
+/*
+    Montage Technology DS3000/TS2020 - DVBS/S2 Satellite demod/tuner driver
+    Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
+
+    Copyright (C) 2009 TurboSight.com
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef DS3000_H
+#define DS3000_H
+
+#include <linux/dvb/frontend.h>
+
+struct ds3000_config {
+        /* the demodulator's i2c address */
+        u8 demod_address;
+};
+
+#if defined(CONFIG_DVB_DS3000) || \
+                        (defined(CONFIG_DVB_DS3000_MODULE) && defined(MODULE))
+extern struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
+                                        struct i2c_adapter *i2c);
+#else
+static inline
+struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
+                                        struct i2c_adapter *i2c)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return NULL;
+}
+#endif /* CONFIG_DVB_DS3000 */
+#endif /* DS3000_H */
diff --git a/drivers/media/dvb/frontends/dvb-pll.c b/drivers/media/dvb/frontends/dvb-pll.c
index 6d865d6161d7..4d4d0bb5920a 100644
--- a/drivers/media/dvb/frontends/dvb-pll.c
+++ b/drivers/media/dvb/frontends/dvb-pll.c
@@ -18,6 +18,7 @@
  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/dvb/frontend.h>
 #include <asm/types.h>
diff --git a/drivers/media/dvb/frontends/ec100.c b/drivers/media/dvb/frontends/ec100.c
new file mode 100644
index 000000000000..2414dc6ee5d9
--- /dev/null
+++ b/drivers/media/dvb/frontends/ec100.c
@@ -0,0 +1,335 @@
+/*
+ * E3C EC100 demodulator driver
+ *
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include "dvb_frontend.h"
+#include "ec100_priv.h"
+#include "ec100.h"
+
+int ec100_debug;
+module_param_named(debug, ec100_debug, int, 0644);
+MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
+
+struct ec100_state {
+        struct i2c_adapter *i2c;
+        struct dvb_frontend frontend;
+        struct ec100_config config;
+
+        u16 ber;
+};
+
+/* write single register */
+static int ec100_write_reg(struct ec100_state *state, u8 reg, u8 val)
+{
+        u8 buf[2] = {reg, val};
+        struct i2c_msg msg = {
+                .addr = state->config.demod_address,
+                .flags = 0,
+                .len = 2,
+                .buf = buf};
+
+        if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+                warn("I2C write failed reg:%02x", reg);
+                return -EREMOTEIO;
+        }
+        return 0;
+}
+
+/* read single register */
+static int ec100_read_reg(struct ec100_state *state, u8 reg, u8 *val)
+{
+        struct i2c_msg msg[2] = {
+                {
+                        .addr = state->config.demod_address,
+                        .flags = 0,
+                        .len = 1,
+                        .buf = &reg
+                }, {
+                        .addr = state->config.demod_address,
+                        .flags = I2C_M_RD,
+                        .len = 1,
+                        .buf = val
+                }
+        };
+
+        if (i2c_transfer(state->i2c, msg, 2) != 2) {
+                warn("I2C read failed reg:%02x", reg);
+                return -EREMOTEIO;
+        }
+        return 0;
+}
+
+static int ec100_set_frontend(struct dvb_frontend *fe,
+        struct dvb_frontend_parameters *params)
+{
+        struct ec100_state *state = fe->demodulator_priv;
+        int ret;
+        u8 tmp, tmp2;
+
+        deb_info("%s: freq:%d bw:%d\n", __func__, params->frequency,
+                params->u.ofdm.bandwidth);
+
+        /* program tuner */
+        if (fe->ops.tuner_ops.set_params)
+                fe->ops.tuner_ops.set_params(fe, params);
+
+        ret = ec100_write_reg(state, 0x04, 0x06);
+        if (ret)
+                goto error;
+        ret = ec100_write_reg(state, 0x67, 0x58);
+        if (ret)
+                goto error;
+        ret = ec100_write_reg(state, 0x05, 0x18);
+        if (ret)
+                goto error;
+
+        /* reg/bw |   6  |   7  |   8
+           -------+------+------+------
+           A 0x1b | 0xa1 | 0xe7 | 0x2c
+           A 0x1c | 0x55 | 0x63 | 0x72
+           -------+------+------+------
+           B 0x1b | 0xb7 | 0x00 | 0x49
+           B 0x1c | 0x55 | 0x64 | 0x72 */
+
+        switch (params->u.ofdm.bandwidth) {
+        case BANDWIDTH_6_MHZ:
+                tmp = 0xb7;
+                tmp2 = 0x55;
+                break;
+        case BANDWIDTH_7_MHZ:
+                tmp = 0x00;
+                tmp2 = 0x64;
+                break;
+        case BANDWIDTH_8_MHZ:
+        default:
+                tmp = 0x49;
+                tmp2 = 0x72;
+        }
+
+        ret = ec100_write_reg(state, 0x1b, tmp);
+        if (ret)
+                goto error;
+        ret = ec100_write_reg(state, 0x1c, tmp2);
+        if (ret)
+                goto error;
+
+        ret = ec100_write_reg(state, 0x0c, 0xbb); /* if freq */
+        if (ret)
+                goto error;
+        ret = ec100_write_reg(state, 0x0d, 0x31); /* if freq */
+        if (ret)
+                goto error;
+
+        ret = ec100_write_reg(state, 0x08, 0x24);
+        if (ret)
+                goto error;
+
+        ret = ec100_write_reg(state, 0x00, 0x00); /* go */
+        if (ret)
+                goto error;
+        ret = ec100_write_reg(state, 0x00, 0x20); /* go */
+        if (ret)
+                goto error;
+
+        return ret;
+error:
+        deb_info("%s: failed:%d\n", __func__, ret);
+        return ret;
+}
+
+static int ec100_get_tune_settings(struct dvb_frontend *fe,
+        struct dvb_frontend_tune_settings *fesettings)
+{
+        fesettings->min_delay_ms = 300;
+        fesettings->step_size = 0;
+        fesettings->max_drift = 0;
+
+        return 0;
+}
+
+static int ec100_read_status(struct dvb_frontend *fe, fe_status_t *status)
+{
+        struct ec100_state *state = fe->demodulator_priv;
+        int ret;
+        u8 tmp;
+        *status = 0;
+
+        ret = ec100_read_reg(state, 0x42, &tmp);
+        if (ret)
+                goto error;
+
+        if (tmp & 0x80) {
+                /* bit7 set - have lock */
+                *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
+                        FE_HAS_SYNC | FE_HAS_LOCK;
+        } else {
+                ret = ec100_read_reg(state, 0x01, &tmp);
+                if (ret)
+                        goto error;
+
+                if (tmp & 0x10) {
+                        /* bit4 set - have signal */
+                        *status |= FE_HAS_SIGNAL;
+                        if (!(tmp & 0x01)) {
+                                /* bit0 clear - have ~valid signal */
+                                *status |= FE_HAS_CARRIER |  FE_HAS_VITERBI;
+                        }
+                }
+        }
+
+        return ret;
+error:
+        deb_info("%s: failed:%d\n", __func__, ret);
+        return ret;
+}
+
+static int ec100_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+        struct ec100_state *state = fe->demodulator_priv;
+        int ret;
+        u8 tmp, tmp2;
+        u16 ber2;
+
+        *ber = 0;
+
+        ret = ec100_read_reg(state, 0x65, &tmp);
+        if (ret)
+                goto error;
+        ret = ec100_read_reg(state, 0x66, &tmp2);
+        if (ret)
+                goto error;
+
+        ber2 = (tmp2 << 8) | tmp;
+
+        /* if counter overflow or clear */
+        if (ber2 < state->ber)
+                *ber = ber2;
+        else
+                *ber = ber2 - state->ber;
+
+        state->ber = ber2;
+
+        return ret;
+error:
+        deb_info("%s: failed:%d\n", __func__, ret);
+        return ret;
+}
+
+static int ec100_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
+{
+        struct ec100_state *state = fe->demodulator_priv;
+        int ret;
+        u8 tmp;
+
+        ret = ec100_read_reg(state, 0x24, &tmp);
+        if (ret) {
+                *strength = 0;
+                goto error;
+        }
+
+        *strength = ((tmp << 8) | tmp);
+
+        return ret;
+error:
+        deb_info("%s: failed:%d\n", __func__, ret);
+        return ret;
+}
+
+static int ec100_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+        *snr = 0;
+        return 0;
+}
+
+static int ec100_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+        *ucblocks = 0;
+        return 0;
+}
+
+static void ec100_release(struct dvb_frontend *fe)
+{
+        struct ec100_state *state = fe->demodulator_priv;
+        kfree(state);
+}
+
+static struct dvb_frontend_ops ec100_ops;
+
+struct dvb_frontend *ec100_attach(const struct ec100_config *config,
+        struct i2c_adapter *i2c)
+{
+        int ret;
+        struct ec100_state *state = NULL;
+        u8 tmp;
+
+        /* allocate memory for the internal state */
+        state = kzalloc(sizeof(struct ec100_state), GFP_KERNEL);
+        if (state == NULL)
+                goto error;
+
+        /* setup the state */
+        state->i2c = i2c;
+        memcpy(&state->config, config, sizeof(struct ec100_config));
+
+        /* check if the demod is there */
+        ret = ec100_read_reg(state, 0x33, &tmp);
+        if (ret || tmp != 0x0b)
+                goto error;
+
+        /* create dvb_frontend */
+        memcpy(&state->frontend.ops, &ec100_ops,
+                sizeof(struct dvb_frontend_ops));
+        state->frontend.demodulator_priv = state;
+
+        return &state->frontend;
+error:
+        kfree(state);
+        return NULL;
+}
+EXPORT_SYMBOL(ec100_attach);
+
+static struct dvb_frontend_ops ec100_ops = {
+        .info = {
+                .name = "E3C EC100 DVB-T",
+                .type = FE_OFDM,
+                .caps =
+                        FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+                        FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+                        FE_CAN_QPSK | FE_CAN_QAM_16 |
+                        FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
+                        FE_CAN_TRANSMISSION_MODE_AUTO |
+                        FE_CAN_GUARD_INTERVAL_AUTO |
+                        FE_CAN_HIERARCHY_AUTO |
+                        FE_CAN_MUTE_TS
+        },
+
+        .release = ec100_release,
+        .set_frontend = ec100_set_frontend,
+        .get_tune_settings = ec100_get_tune_settings,
+        .read_status = ec100_read_status,
+        .read_ber = ec100_read_ber,
+        .read_signal_strength = ec100_read_signal_strength,
+        .read_snr = ec100_read_snr,
+        .read_ucblocks = ec100_read_ucblocks,
+};
+
+MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
+MODULE_DESCRIPTION("E3C EC100 DVB-T demodulator driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/ec100.h b/drivers/media/dvb/frontends/ec100.h
new file mode 100644
index 000000000000..ee8e52417958
--- /dev/null
+++ b/drivers/media/dvb/frontends/ec100.h
@@ -0,0 +1,46 @@
+/*
+ * E3C EC100 demodulator driver
+ *
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef EC100_H
+#define EC100_H
+
+#include <linux/dvb/frontend.h>
+
+struct ec100_config {
+        /* demodulator's I2C address */
+        u8 demod_address;
+};
+
+
+#if defined(CONFIG_DVB_EC100) || \
+        (defined(CONFIG_DVB_EC100_MODULE) && defined(MODULE))
+extern struct dvb_frontend *ec100_attach(const struct ec100_config *config,
+        struct i2c_adapter *i2c);
+#else
+static inline struct dvb_frontend *ec100_attach(
+        const struct ec100_config *config, struct i2c_adapter *i2c)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return NULL;
+}
+#endif
+
+#endif /* EC100_H */
diff --git a/drivers/media/dvb/frontends/ec100_priv.h b/drivers/media/dvb/frontends/ec100_priv.h
new file mode 100644
index 000000000000..5c990144bc47
--- /dev/null
+++ b/drivers/media/dvb/frontends/ec100_priv.h
@@ -0,0 +1,39 @@
+/*
+ * E3C EC100 demodulator driver
+ *
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef EC100_PRIV
+#define EC100_PRIV
+
+#define LOG_PREFIX "ec100"
+
+#define dprintk(var, level, args...) \
+        do { if ((var & level)) printk(args); } while (0)
+
+#define deb_info(args...) dprintk(ec100_debug, 0x01, args)
+
+#undef err
+#define err(f, arg...)  printk(KERN_ERR     LOG_PREFIX": " f "\n" , ## arg)
+#undef info
+#define info(f, arg...) printk(KERN_INFO    LOG_PREFIX": " f "\n" , ## arg)
+#undef warn
+#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
+
+#endif /* EC100_PRIV */
diff --git a/drivers/media/dvb/frontends/itd1000.c b/drivers/media/dvb/frontends/itd1000.c
index 600dad6b41ea..f7a40a18777a 100644
--- a/drivers/media/dvb/frontends/itd1000.c
+++ b/drivers/media/dvb/frontends/itd1000.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/dvb/frontend.h>
 #include <linux/i2c.h>
+#include <linux/slab.h>
 
 #include "dvb_frontend.h"
 
diff --git a/drivers/media/dvb/frontends/l64781.c b/drivers/media/dvb/frontends/l64781.c
index 3051b64aa17c..445fa1068064 100644
--- a/drivers/media/dvb/frontends/l64781.c
+++ b/drivers/media/dvb/frontends/l64781.c
@@ -192,8 +192,8 @@ static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_pa
         spi_bias *= qam_tab[p->constellation];
         spi_bias /= p->code_rate_HP + 1;
         spi_bias /= (guard_tab[p->guard_interval] + 32);
-        spi_bias *= 1000ULL;
-        spi_bias /= 1000ULL + ppm/1000;
+        spi_bias *= 1000;
+        spi_bias /= 1000 + ppm/1000;
         spi_bias *= p->code_rate_HP;
 
         val0x04 = (p->transmission_mode << 2) | p->guard_interval;
diff --git a/drivers/media/dvb/frontends/lgdt3304.c b/drivers/media/dvb/frontends/lgdt3304.c
index e334b5d4e578..45a529b06b9d 100644
--- a/drivers/media/dvb/frontends/lgdt3304.c
+++ b/drivers/media/dvb/frontends/lgdt3304.c
@@ -7,6 +7,7 @@
 
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/delay.h>
 #include "dvb_frontend.h"
 #include "lgdt3304.h"
diff --git a/drivers/media/dvb/frontends/lgdt3305.c b/drivers/media/dvb/frontends/lgdt3305.c
index fde8c59700fb..d69c775f8645 100644
--- a/drivers/media/dvb/frontends/lgdt3305.c
+++ b/drivers/media/dvb/frontends/lgdt3305.c
@@ -21,6 +21,7 @@
 
 #include <asm/div64.h>
 #include <linux/dvb/frontend.h>
+#include <linux/slab.h>
 #include "dvb_math.h"
 #include "lgdt3305.h"
 
diff --git a/drivers/media/dvb/frontends/lgdt3305.h b/drivers/media/dvb/frontends/lgdt3305.h
index 4fa6e52d1fe8..9cb11c9cae53 100644
--- a/drivers/media/dvb/frontends/lgdt3305.h
+++ b/drivers/media/dvb/frontends/lgdt3305.h
@@ -54,13 +54,13 @@ struct lgdt3305_config {
         u16 usref_qam256; /* default: 0x2a80 */
 
         /* disable i2c repeater - 0:repeater enabled 1:repeater disabled */
-        int deny_i2c_rptr:1;
+        unsigned int deny_i2c_rptr:1;
 
         /* spectral inversion - 0:disabled 1:enabled */
-        int spectral_inversion:1;
+        unsigned int spectral_inversion:1;
 
         /* use RF AGC loop - 0:disabled 1:enabled */
-        int rf_agc_loop:1;
+        unsigned int rf_agc_loop:1;
 
         enum lgdt3305_mpeg_mode mpeg_mode;
         enum lgdt3305_tp_clock_edge tpclk_edge;
diff --git a/drivers/media/dvb/frontends/lgdt330x.c b/drivers/media/dvb/frontends/lgdt330x.c
index 056387b41a8f..43971e63baa7 100644
--- a/drivers/media/dvb/frontends/lgdt330x.c
+++ b/drivers/media/dvb/frontends/lgdt330x.c
@@ -479,7 +479,7 @@ static int lgdt3302_read_status(struct dvb_frontend* fe, fe_status_t* status)
         switch (state->current_modulation) {
         case QAM_256:
         case QAM_64:
-                /* Need to undestand why there are 3 lock levels here */
+                /* Need to understand why there are 3 lock levels here */
                 if ((buf[0] & 0x07) == 0x07)
                         *status |= FE_HAS_CARRIER;
                 break;
@@ -520,7 +520,7 @@ static int lgdt3303_read_status(struct dvb_frontend* fe, fe_status_t* status)
         switch (state->current_modulation) {
         case QAM_256:
         case QAM_64:
-                /* Need to undestand why there are 3 lock levels here */
+                /* Need to understand why there are 3 lock levels here */
                 if ((buf[0] & 0x07) == 0x07)
                         *status |= FE_HAS_CARRIER;
                 else
diff --git a/drivers/media/dvb/frontends/lgs8gxx.c b/drivers/media/dvb/frontends/lgs8gxx.c
index eabcadc425d5..dee53960e7e8 100644
--- a/drivers/media/dvb/frontends/lgs8gxx.c
+++ b/drivers/media/dvb/frontends/lgs8gxx.c
@@ -199,7 +199,7 @@ static int lgs8gxx_set_if_freq(struct lgs8gxx_state *priv, u32 freq /*in kHz*/)
 
         val = freq;
         if (freq != 0) {
-                val *= (u64)1 << 32;
+                val <<= 32;
                 if (if_clk != 0)
                         do_div(val, if_clk);
                 v32 = val & 0xFFFFFFFF;
@@ -246,7 +246,7 @@ static int lgs8gxx_get_afc_phase(struct lgs8gxx_state *priv)
 
         val = v32;
         val *= priv->config->if_clk_freq;
-        val /= (u64)1 << 32;
+        val >>= 32;
         dprintk("AFC = %u kHz\n", (u32)val);
         return 0;
 }
diff --git a/drivers/media/dvb/frontends/lnbp21.c b/drivers/media/dvb/frontends/lnbp21.c
index 71f607fe8fc7..13437259eeac 100644
--- a/drivers/media/dvb/frontends/lnbp21.c
+++ b/drivers/media/dvb/frontends/lnbp21.c
@@ -1,7 +1,7 @@
 /*
  * lnbp21.c - driver for lnb supply and control ic lnbp21
  *
- * Copyright (C) 2006 Oliver Endriss
+ * Copyright (C) 2006, 2009 Oliver Endriss <o.endriss@gmx.de>
  * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
  *
  * This program is free software; you can redistribute it and/or
@@ -91,6 +91,31 @@ static int lnbp21_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
         return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO;
 }
 
+static int lnbp21_set_tone(struct dvb_frontend *fe,
+                                fe_sec_tone_mode_t tone)
+{
+        struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv;
+        struct i2c_msg msg = {  .addr = lnbp21->i2c_addr, .flags = 0,
+                                .buf = &lnbp21->config,
+                                .len = sizeof(lnbp21->config) };
+
+        switch (tone) {
+        case SEC_TONE_OFF:
+                lnbp21->config &= ~LNBP21_TEN;
+                break;
+        case SEC_TONE_ON:
+                lnbp21->config |= LNBP21_TEN;
+                break;
+        default:
+                return -EINVAL;
+        };
+
+        lnbp21->config |= lnbp21->override_or;
+        lnbp21->config &= lnbp21->override_and;
+
+        return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO;
+}
+
 static void lnbp21_release(struct dvb_frontend *fe)
 {
         /* LNBP power off */
@@ -133,6 +158,8 @@ static struct dvb_frontend *lnbx2x_attach(struct dvb_frontend *fe,
         /* override frontend ops */
         fe->ops.set_voltage = lnbp21_set_voltage;
         fe->ops.enable_high_lnb_voltage = lnbp21_enable_high_lnb_voltage;
+        if (!(override_clear & LNBH24_TEN)) /*22kHz logic controlled by demod*/
+                fe->ops.set_tone = lnbp21_set_tone;
         printk(KERN_INFO "LNBx2x attached on addr=%x\n", lnbp21->i2c_addr);
 
         return fe;
diff --git a/drivers/media/dvb/frontends/mb86a16.c b/drivers/media/dvb/frontends/mb86a16.c
new file mode 100644
index 000000000000..599d1aa519a3
--- /dev/null
+++ b/drivers/media/dvb/frontends/mb86a16.c
@@ -0,0 +1,1879 @@
+/*
+        Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
+
+        Copyright (C) Manu Abraham (abraham.manu@gmail.com)
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/slab.h>
+
+#include "dvb_frontend.h"
+#include "mb86a16.h"
+#include "mb86a16_priv.h"
+
+unsigned int verbose = 5;
+module_param(verbose, int, 0644);
+
+#define ABS(x)          ((x) < 0 ? (-x) : (x))
+
+struct mb86a16_state {
+        struct i2c_adapter              *i2c_adap;
+        const struct mb86a16_config     *config;
+        struct dvb_frontend             frontend;
+
+        /* tuning parameters */
+        int                             frequency;
+        int                             srate;
+
+        /* Internal stuff */
+        int                             master_clk;
+        int                             deci;
+        int                             csel;
+        int                             rsel;
+};
+
+#define MB86A16_ERROR           0
+#define MB86A16_NOTICE          1
+#define MB86A16_INFO            2
+#define MB86A16_DEBUG           3
+
+#define dprintk(x, y, z, format, arg...) do {                                           \
+        if (z) {                                                                        \
+                if      ((x > MB86A16_ERROR) && (x > y))                                \
+                        printk(KERN_ERR "%s: " format "\n", __func__, ##arg);           \
+                else if ((x > MB86A16_NOTICE) && (x > y))                               \
+                        printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg);        \
+                else if ((x > MB86A16_INFO) && (x > y))                                 \
+                        printk(KERN_INFO "%s: " format "\n", __func__, ##arg);          \
+                else if ((x > MB86A16_DEBUG) && (x > y))                                \
+                        printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg);         \
+        } else {                                                                        \
+                if (x > y)                                                              \
+                        printk(format, ##arg);                                          \
+        }                                                                               \
+} while (0)
+
+#define TRACE_IN        dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
+#define TRACE_OUT       dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
+
+static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
+{
+        int ret;
+        u8 buf[] = { reg, val };
+
+        struct i2c_msg msg = {
+                .addr = state->config->demod_address,
+                .flags = 0,
+                .buf = buf,
+                .len = 2
+        };
+
+        dprintk(verbose, MB86A16_DEBUG, 1,
+                "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
+                state->config->demod_address, buf[0], buf[1]);
+
+        ret = i2c_transfer(state->i2c_adap, &msg, 1);
+
+        return (ret != 1) ? -EREMOTEIO : 0;
+}
+
+static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
+{
+        int ret;
+        u8 b0[] = { reg };
+        u8 b1[] = { 0 };
+
+        struct i2c_msg msg[] = {
+                {
+                        .addr = state->config->demod_address,
+                        .flags = 0,
+                        .buf = b0,
+                        .len = 1
+                }, {
+                        .addr = state->config->demod_address,
+                        .flags = I2C_M_RD,
+                        .buf = b1,
+                        .len = 1
+                }
+        };
+        ret = i2c_transfer(state->i2c_adap, msg, 2);
+        if (ret != 2) {
+                dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=0x%i)",
+                        reg, ret);
+
+                return -EREMOTEIO;
+        }
+        *val = b1[0];
+
+        return ret;
+}
+
+static int CNTM_set(struct mb86a16_state *state,
+                    unsigned char timint1,
+                    unsigned char timint2,
+                    unsigned char cnext)
+{
+        unsigned char val;
+
+        val = (timint1 << 4) | (timint2 << 2) | cnext;
+        if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
+                goto err;
+
+        return 0;
+
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int smrt_set(struct mb86a16_state *state, int rate)
+{
+        int tmp ;
+        int m ;
+        unsigned char STOFS0, STOFS1;
+
+        m = 1 << state->deci;
+        tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
+
+        STOFS0 = tmp & 0x0ff;
+        STOFS1 = (tmp & 0xf00) >> 8;
+
+        if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
+                                       (state->csel << 1) |
+                                        state->rsel) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -1;
+}
+
+static int srst(struct mb86a16_state *state)
+{
+        if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+
+}
+
+static int afcex_data_set(struct mb86a16_state *state,
+                          unsigned char AFCEX_L,
+                          unsigned char AFCEX_H)
+{
+        if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+
+        return -1;
+}
+
+static int afcofs_data_set(struct mb86a16_state *state,
+                           unsigned char AFCEX_L,
+                           unsigned char AFCEX_H)
+{
+        if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
+                goto err;
+        if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int stlp_set(struct mb86a16_state *state,
+                    unsigned char STRAS,
+                    unsigned char STRBS)
+{
+        if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
+{
+        if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int initial_set(struct mb86a16_state *state)
+{
+        if (stlp_set(state, 5, 7))
+                goto err;
+
+        udelay(100);
+        if (afcex_data_set(state, 0, 0))
+                goto err;
+
+        udelay(100);
+        if (afcofs_data_set(state, 0, 0))
+                goto err;
+
+        udelay(100);
+        if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
+                goto err;
+        if (mb86a16_write(state, 0x2f, 0x21) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
+                goto err;
+        if (mb86a16_write(state, 0x54, 0xff) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
+                goto err;
+
+        return 0;
+
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int S01T_set(struct mb86a16_state *state,
+                    unsigned char s1t,
+                    unsigned s0t)
+{
+        if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+
+static int EN_set(struct mb86a16_state *state,
+                  int cren,
+                  int afcen)
+{
+        unsigned char val;
+
+        val = 0x7a | (cren << 7) | (afcen << 2);
+        if (mb86a16_write(state, 0x49, val) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int AFCEXEN_set(struct mb86a16_state *state,
+                       int afcexen,
+                       int smrt)
+{
+        unsigned char AFCA ;
+
+        if (smrt > 18875)
+                AFCA = 4;
+        else if (smrt > 9375)
+                AFCA = 3;
+        else if (smrt > 2250)
+                AFCA = 2;
+        else
+                AFCA = 1;
+
+        if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
+                goto err;
+
+        return 0;
+
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int DAGC_data_set(struct mb86a16_state *state,
+                         unsigned char DAGCA,
+                         unsigned char DAGCW)
+{
+        if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
+                goto err;
+
+        return 0;
+
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static void smrt_info_get(struct mb86a16_state *state, int rate)
+{
+        if (rate >= 37501) {
+                state->deci = 0; state->csel = 0; state->rsel = 0;
+        } else if (rate >= 30001) {
+                state->deci = 0; state->csel = 0; state->rsel = 1;
+        } else if (rate >= 26251) {
+                state->deci = 0; state->csel = 1; state->rsel = 0;
+        } else if (rate >= 22501) {
+                state->deci = 0; state->csel = 1; state->rsel = 1;
+        } else if (rate >= 18751) {
+                state->deci = 1; state->csel = 0; state->rsel = 0;
+        } else if (rate >= 15001) {
+                state->deci = 1; state->csel = 0; state->rsel = 1;
+        } else if (rate >= 13126) {
+                state->deci = 1; state->csel = 1; state->rsel = 0;
+        } else if (rate >= 11251) {
+                state->deci = 1; state->csel = 1; state->rsel = 1;
+        } else if (rate >= 9376) {
+                state->deci = 2; state->csel = 0; state->rsel = 0;
+        } else if (rate >= 7501) {
+                state->deci = 2; state->csel = 0; state->rsel = 1;
+        } else if (rate >= 6563) {
+                state->deci = 2; state->csel = 1; state->rsel = 0;
+        } else if (rate >= 5626) {
+                state->deci = 2; state->csel = 1; state->rsel = 1;
+        } else if (rate >= 4688) {
+                state->deci = 3; state->csel = 0; state->rsel = 0;
+        } else if (rate >= 3751) {
+                state->deci = 3; state->csel = 0; state->rsel = 1;
+        } else if (rate >= 3282) {
+                state->deci = 3; state->csel = 1; state->rsel = 0;
+        } else if (rate >= 2814) {
+                state->deci = 3; state->csel = 1; state->rsel = 1;
+        } else if (rate >= 2344) {
+                state->deci = 4; state->csel = 0; state->rsel = 0;
+        } else if (rate >= 1876) {
+                state->deci = 4; state->csel = 0; state->rsel = 1;
+        } else if (rate >= 1641) {
+                state->deci = 4; state->csel = 1; state->rsel = 0;
+        } else if (rate >= 1407) {
+                state->deci = 4; state->csel = 1; state->rsel = 1;
+        } else if (rate >= 1172) {
+                state->deci = 5; state->csel = 0; state->rsel = 0;
+        } else if (rate >=  939) {
+                state->deci = 5; state->csel = 0; state->rsel = 1;
+        } else if (rate >=  821) {
+                state->deci = 5; state->csel = 1; state->rsel = 0;
+        } else {
+                state->deci = 5; state->csel = 1; state->rsel = 1;
+        }
+
+        if (state->csel == 0)
+                state->master_clk = 92000;
+        else
+                state->master_clk = 61333;
+
+}
+
+static int signal_det(struct mb86a16_state *state,
+                      int smrt,
+                      unsigned char *SIG)
+{
+
+        int ret ;
+        int smrtd ;
+        int wait_sym ;
+
+        u32 wait_t;
+        unsigned char S[3] ;
+        int i ;
+
+        if (*SIG > 45) {
+                if (CNTM_set(state, 2, 1, 2) < 0) {
+                        dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
+                        return -1;
+                }
+                wait_sym = 40000;
+        } else {
+                if (CNTM_set(state, 3, 1, 2) < 0) {
+                        dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
+                        return -1;
+                }
+                wait_sym = 80000;
+        }
+        for (i = 0; i < 3; i++) {
+                if (i == 0)
+                        smrtd = smrt * 98 / 100;
+                else if (i == 1)
+                        smrtd = smrt;
+                else
+                        smrtd = smrt * 102 / 100;
+                smrt_info_get(state, smrtd);
+                smrt_set(state, smrtd);
+                srst(state);
+                wait_t = (wait_sym + 99 * smrtd / 100) / smrtd;
+                if (wait_t == 0)
+                        wait_t = 1;
+                msleep_interruptible(10);
+                if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
+                        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+                        return -EREMOTEIO;
+                }
+        }
+        if ((S[1] > S[0] * 112 / 100) &&
+            (S[1] > S[2] * 112 / 100)) {
+
+                ret = 1;
+        } else {
+                ret = 0;
+        }
+        *SIG = S[1];
+
+        if (CNTM_set(state, 0, 1, 2) < 0) {
+                dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
+                return -1;
+        }
+
+        return ret;
+}
+
+static int rf_val_set(struct mb86a16_state *state,
+                      int f,
+                      int smrt,
+                      unsigned char R)
+{
+        unsigned char C, F, B;
+        int M;
+        unsigned char rf_val[5];
+        int ack = -1;
+
+        if (smrt > 37750)
+                C = 1;
+        else if (smrt > 18875)
+                C = 2;
+        else if (smrt > 5500)
+                C = 3;
+        else
+                C = 4;
+
+        if (smrt > 30500)
+                F = 3;
+        else if (smrt > 9375)
+                F = 1;
+        else if (smrt > 4625)
+                F = 0;
+        else
+                F = 2;
+
+        if (f < 1060)
+                B = 0;
+        else if (f < 1175)
+                B = 1;
+        else if (f < 1305)
+                B = 2;
+        else if (f < 1435)
+                B = 3;
+        else if (f < 1570)
+                B = 4;
+        else if (f < 1715)
+                B = 5;
+        else if (f < 1845)
+                B = 6;
+        else if (f < 1980)
+                B = 7;
+        else if (f < 2080)
+                B = 8;
+        else
+                B = 9;
+
+        M = f * (1 << R) / 2;
+
+        rf_val[0] = 0x01 | (C << 3) | (F << 1);
+        rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
+        rf_val[2] = (M & 0x00ff0) >> 4;
+        rf_val[3] = ((M & 0x0000f) << 4) | B;
+
+        /* Frequency Set */
+        if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
+                ack = 0;
+        if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
+                ack = 0;
+        if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
+                ack = 0;
+        if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
+                ack = 0;
+        if (mb86a16_write(state, 0x25, 0x01) < 0)
+                ack = 0;
+        if (ack == 0) {
+                dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
+                return -EREMOTEIO;
+        }
+
+        return 0;
+}
+
+static int afcerr_chk(struct mb86a16_state *state)
+{
+        unsigned char AFCM_L, AFCM_H ;
+        int AFCM ;
+        int afcm, afcerr ;
+
+        if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
+                goto err;
+        if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
+                goto err;
+
+        AFCM = (AFCM_H << 8) + AFCM_L;
+
+        if (AFCM > 2048)
+                afcm = AFCM - 4096;
+        else
+                afcm = AFCM;
+        afcerr = afcm * state->master_clk / 8192;
+
+        return afcerr;
+
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int dagcm_val_get(struct mb86a16_state *state)
+{
+        int DAGCM;
+        unsigned char DAGCM_H, DAGCM_L;
+
+        if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
+                goto err;
+        if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
+                goto err;
+
+        DAGCM = (DAGCM_H << 8) + DAGCM_L;
+
+        return DAGCM;
+
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int mb86a16_read_status(struct dvb_frontend *fe, fe_status_t *status)
+{
+        u8 stat, stat2;
+        struct mb86a16_state *state = fe->demodulator_priv;
+
+        *status = 0;
+
+        if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2)
+                goto err;
+        if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2)
+                goto err;
+        if ((stat > 25) && (stat2 > 25))
+                *status |= FE_HAS_SIGNAL;
+        if ((stat > 45) && (stat2 > 45))
+                *status |= FE_HAS_CARRIER;
+
+        if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2)
+                goto err;
+
+        if (stat & 0x01)
+                *status |= FE_HAS_SYNC;
+        if (stat & 0x01)
+                *status |= FE_HAS_VITERBI;
+
+        if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2)
+                goto err;
+
+        if ((stat & 0x0f) && (*status & FE_HAS_VITERBI))
+                *status |= FE_HAS_LOCK;
+
+        return 0;
+
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int sync_chk(struct mb86a16_state *state,
+                    unsigned char *VIRM)
+{
+        unsigned char val;
+        int sync;
+
+        if (mb86a16_read(state, 0x0d, &val) != 2)
+                goto err;
+
+        dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
+        sync = val & 0x01;
+        *VIRM = (val & 0x1c) >> 2;
+
+        return sync;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+
+}
+
+static int freqerr_chk(struct mb86a16_state *state,
+                       int fTP,
+                       int smrt,
+                       int unit)
+{
+        unsigned char CRM, AFCML, AFCMH;
+        unsigned char temp1, temp2, temp3;
+        int crm, afcm, AFCM;
+        int crrerr, afcerr;             /* kHz */
+        int frqerr;                     /* MHz */
+        int afcen, afcexen = 0;
+        int R, M, fOSC, fOSC_OFS;
+
+        if (mb86a16_read(state, 0x43, &CRM) != 2)
+                goto err;
+
+        if (CRM > 127)
+                crm = CRM - 256;
+        else
+                crm = CRM;
+
+        crrerr = smrt * crm / 256;
+        if (mb86a16_read(state, 0x49, &temp1) != 2)
+                goto err;
+
+        afcen = (temp1 & 0x04) >> 2;
+        if (afcen == 0) {
+                if (mb86a16_read(state, 0x2a, &temp1) != 2)
+                        goto err;
+                afcexen = (temp1 & 0x20) >> 5;
+        }
+
+        if (afcen == 1) {
+                if (mb86a16_read(state, 0x0e, &AFCML) != 2)
+                        goto err;
+                if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
+                        goto err;
+        } else if (afcexen == 1) {
+                if (mb86a16_read(state, 0x2b, &AFCML) != 2)
+                        goto err;
+                if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
+                        goto err;
+        }
+        if ((afcen == 1) || (afcexen == 1)) {
+                smrt_info_get(state, smrt);
+                AFCM = ((AFCMH & 0x01) << 8) + AFCML;
+                if (AFCM > 255)
+                        afcm = AFCM - 512;
+                else
+                        afcm = AFCM;
+
+                afcerr = afcm * state->master_clk / 8192;
+        } else
+                afcerr = 0;
+
+        if (mb86a16_read(state, 0x22, &temp1) != 2)
+                goto err;
+        if (mb86a16_read(state, 0x23, &temp2) != 2)
+                goto err;
+        if (mb86a16_read(state, 0x24, &temp3) != 2)
+                goto err;
+
+        R = (temp1 & 0xe0) >> 5;
+        M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
+        if (R == 0)
+                fOSC = 2 * M;
+        else
+                fOSC = M;
+
+        fOSC_OFS = fOSC - fTP;
+
+        if (unit == 0) {        /* MHz */
+                if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
+                        frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
+                else
+                        frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
+        } else {        /* kHz */
+                frqerr = crrerr + afcerr + fOSC_OFS * 1000;
+        }
+
+        return frqerr;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
+{
+        unsigned char R;
+
+        if (smrt > 9375)
+                R = 0;
+        else
+                R = 1;
+
+        return R;
+}
+
+static void swp_info_get(struct mb86a16_state *state,
+                         int fOSC_start,
+                         int smrt,
+                         int v, int R,
+                         int swp_ofs,
+                         int *fOSC,
+                         int *afcex_freq,
+                         unsigned char *AFCEX_L,
+                         unsigned char *AFCEX_H)
+{
+        int AFCEX ;
+        int crnt_swp_freq ;
+
+        crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
+
+        if (R == 0)
+                *fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
+        else
+                *fOSC = (crnt_swp_freq + 500) / 1000;
+
+        if (*fOSC >= crnt_swp_freq)
+                *afcex_freq = *fOSC * 1000 - crnt_swp_freq;
+        else
+                *afcex_freq = crnt_swp_freq - *fOSC * 1000;
+
+        AFCEX = *afcex_freq * 8192 / state->master_clk;
+        *AFCEX_L =  AFCEX & 0x00ff;
+        *AFCEX_H = (AFCEX & 0x0f00) >> 8;
+}
+
+
+static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V,  int vmax, int vmin,
+                               int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
+{
+        int swp_freq ;
+
+        if ((i % 2 == 1) && (v <= vmax)) {
+                /* positive v (case 1) */
+                if ((v - 1 == vmin)                             &&
+                    (*(V + 30 + v) >= 0)                        &&
+                    (*(V + 30 + v - 1) >= 0)                    &&
+                    (*(V + 30 + v - 1) > *(V + 30 + v))         &&
+                    (*(V + 30 + v - 1) > SIGMIN)) {
+
+                        swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
+                        *SIG1 = *(V + 30 + v - 1);
+                } else if ((v == vmax)                          &&
+                           (*(V + 30 + v) >= 0)                 &&
+                           (*(V + 30 + v - 1) >= 0)             &&
+                           (*(V + 30 + v) > *(V + 30 + v - 1))  &&
+                           (*(V + 30 + v) > SIGMIN)) {
+                        /* (case 2) */
+                        swp_freq = fOSC * 1000 + afcex_freq;
+                        *SIG1 = *(V + 30 + v);
+                } else if ((*(V + 30 + v) > 0)                  &&
+                           (*(V + 30 + v - 1) > 0)              &&
+                           (*(V + 30 + v - 2) > 0)              &&
+                           (*(V + 30 + v - 3) > 0)              &&
+                           (*(V + 30 + v - 1) > *(V + 30 + v))  &&
+                           (*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
+                           ((*(V + 30 + v - 1) > SIGMIN)        ||
+                           (*(V + 30 + v - 2) > SIGMIN))) {
+                        /* (case 3) */
+                        if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
+                                swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
+                                *SIG1 = *(V + 30 + v - 1);
+                        } else {
+                                swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
+                                *SIG1 = *(V + 30 + v - 2);
+                        }
+                } else if ((v == vmax)                          &&
+                           (*(V + 30 + v) >= 0)                 &&
+                           (*(V + 30 + v - 1) >= 0)             &&
+                           (*(V + 30 + v - 2) >= 0)             &&
+                           (*(V + 30 + v) > *(V + 30 + v - 2))  &&
+                           (*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
+                           ((*(V + 30 + v) > SIGMIN)            ||
+                           (*(V + 30 + v - 1) > SIGMIN))) {
+                        /* (case 4) */
+                        if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
+                                swp_freq = fOSC * 1000 + afcex_freq;
+                                *SIG1 = *(V + 30 + v);
+                        } else {
+                                swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
+                                *SIG1 = *(V + 30 + v - 1);
+                        }
+                } else  {
+                        swp_freq = -1 ;
+                }
+        } else if ((i % 2 == 0) && (v >= vmin)) {
+                /* Negative v (case 1) */
+                if ((*(V + 30 + v) > 0)                         &&
+                    (*(V + 30 + v + 1) > 0)                     &&
+                    (*(V + 30 + v + 2) > 0)                     &&
+                    (*(V + 30 + v + 1) > *(V + 30 + v))         &&
+                    (*(V + 30 + v + 1) > *(V + 30 + v + 2))     &&
+                    (*(V + 30 + v + 1) > SIGMIN)) {
+
+                        swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
+                        *SIG1 = *(V + 30 + v + 1);
+                } else if ((v + 1 == vmax)                      &&
+                           (*(V + 30 + v) >= 0)                 &&
+                           (*(V + 30 + v + 1) >= 0)             &&
+                           (*(V + 30 + v + 1) > *(V + 30 + v))  &&
+                           (*(V + 30 + v + 1) > SIGMIN)) {
+                        /* (case 2) */
+                        swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
+                        *SIG1 = *(V + 30 + v);
+                } else if ((v == vmin)                          &&
+                           (*(V + 30 + v) > 0)                  &&
+                           (*(V + 30 + v + 1) > 0)              &&
+                           (*(V + 30 + v + 2) > 0)              &&
+                           (*(V + 30 + v) > *(V + 30 + v + 1))  &&
+                           (*(V + 30 + v) > *(V + 30 + v + 2))  &&
+                           (*(V + 30 + v) > SIGMIN)) {
+                        /* (case 3) */
+                        swp_freq = fOSC * 1000 + afcex_freq;
+                        *SIG1 = *(V + 30 + v);
+                } else if ((*(V + 30 + v) >= 0)                 &&
+                           (*(V + 30 + v + 1) >= 0)             &&
+                           (*(V + 30 + v + 2) >= 0)             &&
+                           (*(V + 30 + v + 3) >= 0)             &&
+                           (*(V + 30 + v + 1) > *(V + 30 + v))  &&
+                           (*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
+                           ((*(V + 30 + v + 1) > SIGMIN)        ||
+                            (*(V + 30 + v + 2) > SIGMIN))) {
+                        /* (case 4) */
+                        if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
+                                swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
+                                *SIG1 = *(V + 30 + v + 1);
+                        } else {
+                                swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
+                                *SIG1 = *(V + 30 + v + 2);
+                        }
+                } else if ((*(V + 30 + v) >= 0)                 &&
+                           (*(V + 30 + v + 1) >= 0)             &&
+                           (*(V + 30 + v + 2) >= 0)             &&
+                           (*(V + 30 + v + 3) >= 0)             &&
+                           (*(V + 30 + v) > *(V + 30 + v + 2))  &&
+                           (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
+                           (*(V + 30 + v) > *(V + 30 + v + 3))  &&
+                           (*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
+                           ((*(V + 30 + v) > SIGMIN)            ||
+                            (*(V + 30 + v + 1) > SIGMIN))) {
+                        /* (case 5) */
+                        if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
+                                swp_freq = fOSC * 1000 + afcex_freq;
+                                *SIG1 = *(V + 30 + v);
+                        } else {
+                                swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
+                                *SIG1 = *(V + 30 + v + 1);
+                        }
+                } else if ((v + 2 == vmin)                      &&
+                           (*(V + 30 + v) >= 0)                 &&
+                           (*(V + 30 + v + 1) >= 0)             &&
+                           (*(V + 30 + v + 2) >= 0)             &&
+                           (*(V + 30 + v + 1) > *(V + 30 + v))  &&
+                           (*(V + 30 + v + 2) > *(V + 30 + v))  &&
+                           ((*(V + 30 + v + 1) > SIGMIN)        ||
+                            (*(V + 30 + v + 2) > SIGMIN))) {
+                        /* (case 6) */
+                        if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
+                                swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
+                                *SIG1 = *(V + 30 + v + 1);
+                        } else {
+                                swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
+                                *SIG1 = *(V + 30 + v + 2);
+                        }
+                } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
+                        swp_freq = fOSC * 1000;
+                        *SIG1 = *(V + 30 + v);
+                } else
+                        swp_freq = -1;
+        } else
+                swp_freq = -1;
+
+        return swp_freq;
+}
+
+static void swp_info_get2(struct mb86a16_state *state,
+                          int smrt,
+                          int R,
+                          int swp_freq,
+                          int *afcex_freq,
+                          int *fOSC,
+                          unsigned char *AFCEX_L,
+                          unsigned char *AFCEX_H)
+{
+        int AFCEX ;
+
+        if (R == 0)
+                *fOSC = (swp_freq + 1000) / 2000 * 2;
+        else
+                *fOSC = (swp_freq + 500) / 1000;
+
+        if (*fOSC >= swp_freq)
+                *afcex_freq = *fOSC * 1000 - swp_freq;
+        else
+                *afcex_freq = swp_freq - *fOSC * 1000;
+
+        AFCEX = *afcex_freq * 8192 / state->master_clk;
+        *AFCEX_L =  AFCEX & 0x00ff;
+        *AFCEX_H = (AFCEX & 0x0f00) >> 8;
+}
+
+static void afcex_info_get(struct mb86a16_state *state,
+                           int afcex_freq,
+                           unsigned char *AFCEX_L,
+                           unsigned char *AFCEX_H)
+{
+        int AFCEX ;
+
+        AFCEX = afcex_freq * 8192 / state->master_clk;
+        *AFCEX_L =  AFCEX & 0x00ff;
+        *AFCEX_H = (AFCEX & 0x0f00) >> 8;
+}
+
+static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
+{
+        /* SLOCK0 = 0 */
+        if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
+                dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+                return -EREMOTEIO;
+        }
+
+        return 0;
+}
+
+static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
+{
+        /* Viterbi Rate, IQ Settings */
+        if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
+                dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+                return -EREMOTEIO;
+        }
+
+        return 0;
+}
+
+static int FEC_srst(struct mb86a16_state *state)
+{
+        if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
+                dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+                return -EREMOTEIO;
+        }
+
+        return 0;
+}
+
+static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
+{
+        if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
+                dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+                return -EREMOTEIO;
+        }
+
+        return 0;
+}
+
+static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
+{
+        if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
+                dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+                return -EREMOTEIO;
+        }
+
+        return 0;
+}
+
+
+static int mb86a16_set_fe(struct mb86a16_state *state)
+{
+        u8 agcval, cnmval;
+
+        int i, j;
+        int fOSC = 0;
+        int fOSC_start = 0;
+        int wait_t;
+        int fcp;
+        int swp_ofs;
+        int V[60];
+        u8 SIG1MIN;
+
+        unsigned char CREN, AFCEN, AFCEXEN;
+        unsigned char SIG1;
+        unsigned char TIMINT1, TIMINT2, TIMEXT;
+        unsigned char S0T, S1T;
+        unsigned char S2T;
+/*      unsigned char S2T, S3T; */
+        unsigned char S4T, S5T;
+        unsigned char AFCEX_L, AFCEX_H;
+        unsigned char R;
+        unsigned char VIRM;
+        unsigned char ETH, VIA;
+        unsigned char junk;
+
+        int loop;
+        int ftemp;
+        int v, vmax, vmin;
+        int vmax_his, vmin_his;
+        int swp_freq, prev_swp_freq[20];
+        int prev_freq_num;
+        int signal_dupl;
+        int afcex_freq;
+        int signal;
+        int afcerr;
+        int temp_freq, delta_freq;
+        int dagcm[4];
+        int smrt_d;
+/*      int freq_err; */
+        int n;
+        int ret = -1;
+        int sync;
+
+        dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
+
+        fcp = 3000;
+        swp_ofs = state->srate / 4;
+
+        for (i = 0; i < 60; i++)
+                V[i] = -1;
+
+        for (i = 0; i < 20; i++)
+                prev_swp_freq[i] = 0;
+
+        SIG1MIN = 25;
+
+        for (n = 0; ((n < 3) && (ret == -1)); n++) {
+                SEQ_set(state, 0);
+                iq_vt_set(state, 0);
+
+                CREN = 0;
+                AFCEN = 0;
+                AFCEXEN = 1;
+                TIMINT1 = 0;
+                TIMINT2 = 1;
+                TIMEXT = 2;
+                S1T = 0;
+                S0T = 0;
+
+                if (initial_set(state) < 0) {
+                        dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
+                        return -1;
+                }
+                if (DAGC_data_set(state, 3, 2) < 0) {
+                        dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
+                        return -1;
+                }
+                if (EN_set(state, CREN, AFCEN) < 0) {
+                        dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
+                        return -1; /* (0, 0) */
+                }
+                if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
+                        dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
+                        return -1; /* (1, smrt) = (1, symbolrate) */
+                }
+                if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
+                        dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
+                        return -1; /* (0, 1, 2) */
+                }
+                if (S01T_set(state, S1T, S0T) < 0) {
+                        dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
+                        return -1; /* (0, 0) */
+                }
+                smrt_info_get(state, state->srate);
+                if (smrt_set(state, state->srate) < 0) {
+                        dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
+                        return -1;
+                }
+
+                R = vco_dev_get(state, state->srate);
+                if (R == 1)
+                        fOSC_start = state->frequency;
+
+                else if (R == 0) {
+                        if (state->frequency % 2 == 0) {
+                                fOSC_start = state->frequency;
+                        } else {
+                                fOSC_start = state->frequency + 1;
+                                if (fOSC_start > 2150)
+                                        fOSC_start = state->frequency - 1;
+                        }
+                }
+                loop = 1;
+                ftemp = fOSC_start * 1000;
+                vmax = 0 ;
+                while (loop == 1) {
+                        ftemp = ftemp + swp_ofs;
+                        vmax++;
+
+                        /* Upper bound */
+                        if (ftemp > 2150000) {
+                                loop = 0;
+                                vmax--;
+                        } else {
+                                if ((ftemp == 2150000) ||
+                                    (ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
+                                        loop = 0;
+                        }
+                }
+
+                loop = 1;
+                ftemp = fOSC_start * 1000;
+                vmin = 0 ;
+                while (loop == 1) {
+                        ftemp = ftemp - swp_ofs;
+                        vmin--;
+
+                        /* Lower bound */
+                        if (ftemp < 950000) {
+                                loop = 0;
+                                vmin++;
+                        } else {
+                                if ((ftemp == 950000) ||
+                                    (state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
+                                        loop = 0;
+                        }
+                }
+
+                wait_t = (8000 + state->srate / 2) / state->srate;
+                if (wait_t == 0)
+                        wait_t = 1;
+
+                i = 0;
+                j = 0;
+                prev_freq_num = 0;
+                loop = 1;
+                signal = 0;
+                vmax_his = 0;
+                vmin_his = 0;
+                v = 0;
+
+                while (loop == 1) {
+                        swp_info_get(state, fOSC_start, state->srate,
+                                     v, R, swp_ofs, &fOSC,
+                                     &afcex_freq, &AFCEX_L, &AFCEX_H);
+
+                        udelay(100);
+                        if (rf_val_set(state, fOSC, state->srate, R) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
+                                return -1;
+                        }
+                        udelay(100);
+                        if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
+                                return -1;
+                        }
+                        if (srst(state) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "srst error");
+                                return -1;
+                        }
+                        msleep_interruptible(wait_t);
+
+                        if (mb86a16_read(state, 0x37, &SIG1) != 2) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+                                return -1;
+                        }
+                        V[30 + v] = SIG1 ;
+                        swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
+                                                      SIG1MIN, fOSC, afcex_freq,
+                                                      swp_ofs, &SIG1);  /* changed */
+
+                        signal_dupl = 0;
+                        for (j = 0; j < prev_freq_num; j++) {
+                                if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
+                                        signal_dupl = 1;
+                                        dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
+                                }
+                        }
+                        if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
+                                dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
+                                prev_swp_freq[prev_freq_num] = swp_freq;
+                                prev_freq_num++;
+                                swp_info_get2(state, state->srate, R, swp_freq,
+                                              &afcex_freq, &fOSC,
+                                              &AFCEX_L, &AFCEX_H);
+
+                                if (rf_val_set(state, fOSC, state->srate, R) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
+                                        return -1;
+                                }
+                                if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
+                                        return -1;
+                                }
+                                signal = signal_det(state, state->srate, &SIG1);
+                                if (signal == 1) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
+                                        loop = 0;
+                                } else {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
+                                        smrt_info_get(state, state->srate);
+                                        if (smrt_set(state, state->srate) < 0) {
+                                                dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
+                                                return -1;
+                                        }
+                                }
+                        }
+                        if (v > vmax)
+                                vmax_his = 1 ;
+                        if (v < vmin)
+                                vmin_his = 1 ;
+                        i++;
+
+                        if ((i % 2 == 1) && (vmax_his == 1))
+                                i++;
+                        if ((i % 2 == 0) && (vmin_his == 1))
+                                i++;
+
+                        if (i % 2 == 1)
+                                v = (i + 1) / 2;
+                        else
+                                v = -i / 2;
+
+                        if ((vmax_his == 1) && (vmin_his == 1))
+                                loop = 0 ;
+                }
+
+                if (signal == 1) {
+                        dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
+                        S1T = 7 ;
+                        S0T = 1 ;
+                        CREN = 0 ;
+                        AFCEN = 1 ;
+                        AFCEXEN = 0 ;
+
+                        if (S01T_set(state, S1T, S0T) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
+                                return -1;
+                        }
+                        smrt_info_get(state, state->srate);
+                        if (smrt_set(state, state->srate) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
+                                return -1;
+                        }
+                        if (EN_set(state, CREN, AFCEN) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
+                                return -1;
+                        }
+                        if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
+                                return -1;
+                        }
+                        afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
+                        if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
+                                return -1;
+                        }
+                        if (srst(state) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "srst error");
+                                return -1;
+                        }
+                        /* delay 4~200 */
+                        wait_t = 200000 / state->master_clk + 200000 / state->srate;
+                        msleep(wait_t);
+                        afcerr = afcerr_chk(state);
+                        if (afcerr == -1)
+                                return -1;
+
+                        swp_freq = fOSC * 1000 + afcerr ;
+                        AFCEXEN = 1 ;
+                        if (state->srate >= 1500)
+                                smrt_d = state->srate / 3;
+                        else
+                                smrt_d = state->srate / 2;
+                        smrt_info_get(state, smrt_d);
+                        if (smrt_set(state, smrt_d) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
+                                return -1;
+                        }
+                        if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
+                                return -1;
+                        }
+                        R = vco_dev_get(state, smrt_d);
+                        if (DAGC_data_set(state, 2, 0) < 0) {
+                                dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
+                                return -1;
+                        }
+                        for (i = 0; i < 3; i++) {
+                                temp_freq = swp_freq + (i - 1) * state->srate / 8;
+                                swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
+                                if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
+                                        return -1;
+                                }
+                                if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
+                                        return -1;
+                                }
+                                wait_t = 200000 / state->master_clk + 40000 / smrt_d;
+                                msleep(wait_t);
+                                dagcm[i] = dagcm_val_get(state);
+                        }
+                        if ((dagcm[0] > dagcm[1]) &&
+                            (dagcm[0] > dagcm[2]) &&
+                            (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
+
+                                temp_freq = swp_freq - 2 * state->srate / 8;
+                                swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
+                                if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
+                                        return -1;
+                                }
+                                if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
+                                        return -1;
+                                }
+                                wait_t = 200000 / state->master_clk + 40000 / smrt_d;
+                                msleep(wait_t);
+                                dagcm[3] = dagcm_val_get(state);
+                                if (dagcm[3] > dagcm[1])
+                                        delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
+                                else
+                                        delta_freq = 0;
+                        } else if ((dagcm[2] > dagcm[1]) &&
+                                   (dagcm[2] > dagcm[0]) &&
+                                   (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
+
+                                temp_freq = swp_freq + 2 * state->srate / 8;
+                                swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
+                                if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
+                                        return -1;
+                                }
+                                if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
+                                        return -1;
+                                }
+                                wait_t = 200000 / state->master_clk + 40000 / smrt_d;
+                                msleep(wait_t);
+                                dagcm[3] = dagcm_val_get(state);
+                                if (dagcm[3] > dagcm[1])
+                                        delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
+                                else
+                                        delta_freq = 0 ;
+
+                        } else {
+                                delta_freq = 0 ;
+                        }
+                        dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
+                        swp_freq += delta_freq;
+                        dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
+                        if (ABS(state->frequency * 1000 - swp_freq) > 3800) {
+                                dprintk(verbose, MB86A16_INFO, 1, "NO  --  SIGNAL !");
+                        } else {
+
+                                S1T = 0;
+                                S0T = 3;
+                                CREN = 1;
+                                AFCEN = 0;
+                                AFCEXEN = 1;
+
+                                if (S01T_set(state, S1T, S0T) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
+                                        return -1;
+                                }
+                                if (DAGC_data_set(state, 0, 0) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
+                                        return -1;
+                                }
+                                R = vco_dev_get(state, state->srate);
+                                smrt_info_get(state, state->srate);
+                                if (smrt_set(state, state->srate) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
+                                        return -1;
+                                }
+                                if (EN_set(state, CREN, AFCEN) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
+                                        return -1;
+                                }
+                                if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
+                                        return -1;
+                                }
+                                swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
+                                if (rf_val_set(state, fOSC, state->srate, R) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
+                                        return -1;
+                                }
+                                if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
+                                        return -1;
+                                }
+                                if (srst(state) < 0) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "srst error");
+                                        return -1;
+                                }
+                                wait_t = 7 + (10000 + state->srate / 2) / state->srate;
+                                if (wait_t == 0)
+                                        wait_t = 1;
+                                msleep_interruptible(wait_t);
+                                if (mb86a16_read(state, 0x37, &SIG1) != 2) {
+                                        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+                                        return -EREMOTEIO;
+                                }
+
+                                if (SIG1 > 110) {
+                                        S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
+                                        wait_t = 7 + (917504 + state->srate / 2) / state->srate;
+                                } else if (SIG1 > 105) {
+                                        S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
+                                        wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
+                                } else if (SIG1 > 85) {
+                                        S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
+                                        wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
+                                } else if (SIG1 > 65) {
+                                        S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
+                                        wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
+                                } else {
+                                        S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
+                                        wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
+                                }
+                                wait_t *= 2; /* FOS */
+                                S2T_set(state, S2T);
+                                S45T_set(state, S4T, S5T);
+                                Vi_set(state, ETH, VIA);
+                                srst(state);
+                                msleep_interruptible(wait_t);
+                                sync = sync_chk(state, &VIRM);
+                                dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
+                                if (VIRM) {
+                                        if (VIRM == 4) {
+                                                /* 5/6 */
+                                                if (SIG1 > 110)
+                                                        wait_t = (786432 + state->srate / 2) / state->srate;
+                                                else
+                                                        wait_t = (1572864 + state->srate / 2) / state->srate;
+                                                if (state->srate < 5000)
+                                                        /* FIXME ! , should be a long wait ! */
+                                                        msleep_interruptible(wait_t);
+                                                else
+                                                        msleep_interruptible(wait_t);
+
+                                                if (sync_chk(state, &junk) == 0) {
+                                                        iq_vt_set(state, 1);
+                                                        FEC_srst(state);
+                                                }
+                                        }
+                                        /* 1/2, 2/3, 3/4, 7/8 */
+                                        if (SIG1 > 110)
+                                                wait_t = (786432 + state->srate / 2) / state->srate;
+                                        else
+                                                wait_t = (1572864 + state->srate / 2) / state->srate;
+                                        msleep_interruptible(wait_t);
+                                        SEQ_set(state, 1);
+                                } else {
+                                        dprintk(verbose, MB86A16_INFO, 1, "NO  -- SYNC");
+                                        SEQ_set(state, 1);
+                                        ret = -1;
+                                }
+                        }
+                } else {
+                        dprintk(verbose, MB86A16_INFO, 1, "NO  -- SIGNAL");
+                        ret = -1;
+                }
+
+                sync = sync_chk(state, &junk);
+                if (sync) {
+                        dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
+                        freqerr_chk(state, state->frequency, state->srate, 1);
+                        ret = 0;
+                        break;
+                }
+        }
+
+        mb86a16_read(state, 0x15, &agcval);
+        mb86a16_read(state, 0x26, &cnmval);
+        dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
+
+        return ret;
+}
+
+static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
+                                   struct dvb_diseqc_master_cmd *cmd)
+{
+        struct mb86a16_state *state = fe->demodulator_priv;
+        int i;
+        u8 regs;
+
+        if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
+                goto err;
+
+        regs = 0x18;
+
+        if (cmd->msg_len > 5 || cmd->msg_len < 4)
+                return -EINVAL;
+
+        for (i = 0; i < cmd->msg_len; i++) {
+                if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
+                        goto err;
+
+                regs++;
+        }
+        i += 0x90;
+
+        msleep_interruptible(10);
+
+        if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
+                goto err;
+        if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
+                goto err;
+
+        return 0;
+
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
+{
+        struct mb86a16_state *state = fe->demodulator_priv;
+
+        switch (burst) {
+        case SEC_MINI_A:
+                if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
+                                                       MB86A16_DCC1_TBEN  |
+                                                       MB86A16_DCC1_TBO) < 0)
+                        goto err;
+                if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
+                        goto err;
+                break;
+        case SEC_MINI_B:
+                if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
+                                                       MB86A16_DCC1_TBEN) < 0)
+                        goto err;
+                if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
+                        goto err;
+                break;
+        }
+
+        return 0;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int mb86a16_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
+{
+        struct mb86a16_state *state = fe->demodulator_priv;
+
+        switch (tone) {
+        case SEC_TONE_ON:
+                if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
+                        goto err;
+                if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
+                                                       MB86A16_DCC1_CTOE) < 0)
+
+                        goto err;
+                if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
+                        goto err;
+                break;
+        case SEC_TONE_OFF:
+                if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
+                        goto err;
+                if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
+                        goto err;
+                if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
+                        goto err;
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe,
+                                        struct dvb_frontend_parameters *p)
+{
+        struct mb86a16_state *state = fe->demodulator_priv;
+
+        state->frequency = p->frequency / 1000;
+        state->srate = p->u.qpsk.symbol_rate / 1000;
+
+        if (!mb86a16_set_fe(state)) {
+                dprintk(verbose, MB86A16_ERROR, 1, "Succesfully acquired LOCK");
+                return DVBFE_ALGO_SEARCH_SUCCESS;
+        }
+
+        dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!");
+        return DVBFE_ALGO_SEARCH_FAILED;
+}
+
+static void mb86a16_release(struct dvb_frontend *fe)
+{
+        struct mb86a16_state *state = fe->demodulator_priv;
+        kfree(state);
+}
+
+static int mb86a16_init(struct dvb_frontend *fe)
+{
+        return 0;
+}
+
+static int mb86a16_sleep(struct dvb_frontend *fe)
+{
+        return 0;
+}
+
+static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+        u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst;
+        u32 timer;
+
+        struct mb86a16_state *state = fe->demodulator_priv;
+
+        *ber = 0;
+        if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2)
+                goto err;
+        if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2)
+                goto err;
+        if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2)
+                goto err;
+        if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2)
+                goto err;
+        if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2)
+                goto err;
+        /* BER monitor invalid when BER_EN = 0  */
+        if (ber_mon & 0x04) {
+                /* coarse, fast calculation     */
+                *ber = ber_tab & 0x1f;
+                dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber);
+                if (ber_mon & 0x01) {
+                        /*
+                         * BER_SEL = 1, The monitored BER is the estimated
+                         * value with a Reed-Solomon decoder error amount at
+                         * the deinterleaver output.
+                         * monitored BER is expressed as a 20 bit output in total
+                         */
+                        ber_rst = ber_mon >> 3;
+                        *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
+                        if (ber_rst == 0)
+                                timer =  12500000;
+                        if (ber_rst == 1)
+                                timer =  25000000;
+                        if (ber_rst == 2)
+                                timer =  50000000;
+                        if (ber_rst == 3)
+                                timer = 100000000;
+
+                        *ber /= timer;
+                        dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
+                } else {
+                        /*
+                         * BER_SEL = 0, The monitored BER is the estimated
+                         * value with a Viterbi decoder error amount at the
+                         * QPSK demodulator output.
+                         * monitored BER is expressed as a 24 bit output in total
+                         */
+                        ber_tim = ber_mon >> 1;
+                        *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
+                        if (ber_tim == 0)
+                                timer = 16;
+                        if (ber_tim == 1)
+                                timer = 24;
+
+                        *ber /= 2 ^ timer;
+                        dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
+                }
+        }
+        return 0;
+err:
+        dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+        return -EREMOTEIO;
+}
+
+static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
+{
+        u8 agcm = 0;
+        struct mb86a16_state *state = fe->demodulator_priv;
+
+        *strength = 0;
+        if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) {
+                dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+                return -EREMOTEIO;
+        }
+
+        *strength = ((0xff - agcm) * 100) / 256;
+        dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength);
+        *strength = (0xffff - 0xff) + agcm;
+
+        return 0;
+}
+
+struct cnr {
+        u8 cn_reg;
+        u8 cn_val;
+};
+
+static const struct cnr cnr_tab[] = {
+        {  35,  2 },
+        {  40,  3 },
+        {  50,  4 },
+        {  60,  5 },
+        {  70,  6 },
+        {  80,  7 },
+        {  92,  8 },
+        { 103,  9 },
+        { 115, 10 },
+        { 138, 12 },
+        { 162, 15 },
+        { 180, 18 },
+        { 185, 19 },
+        { 189, 20 },
+        { 195, 22 },
+        { 199, 24 },
+        { 201, 25 },
+        { 202, 26 },
+        { 203, 27 },
+        { 205, 28 },
+        { 208, 30 }
+};
+
+static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+        struct mb86a16_state *state = fe->demodulator_priv;
+        int i = 0;
+        int low_tide = 2, high_tide = 30, q_level;
+        u8  cn;
+
+        *snr = 0;
+        if (mb86a16_read(state, 0x26, &cn) != 2) {
+                dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+                return -EREMOTEIO;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
+                if (cn < cnr_tab[i].cn_reg) {
+                        *snr = cnr_tab[i].cn_val;
+                        break;
+                }
+        }
+        q_level = (*snr * 100) / (high_tide - low_tide);
+        dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
+        *snr = (0xffff - 0xff) + *snr;
+
+        return 0;
+}
+
+static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+        u8 dist;
+        struct mb86a16_state *state = fe->demodulator_priv;
+
+        if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) {
+                dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
+                return -EREMOTEIO;
+        }
+        *ucblocks = dist;
+
+        return 0;
+}
+
+static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
+{
+        return DVBFE_ALGO_CUSTOM;
+}
+
+static struct dvb_frontend_ops mb86a16_ops = {
+        .info = {
+                .name                   = "Fujitsu MB86A16 DVB-S",
+                .type                   = FE_QPSK,
+                .frequency_min          = 950000,
+                .frequency_max          = 2150000,
+                .frequency_stepsize     = 3000,
+                .frequency_tolerance    = 0,
+                .symbol_rate_min        = 1000000,
+                .symbol_rate_max        = 45000000,
+                .symbol_rate_tolerance  = 500,
+                .caps                   = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
+                                          FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
+                                          FE_CAN_FEC_7_8 | FE_CAN_QPSK    |
+                                          FE_CAN_FEC_AUTO
+        },
+        .release                        = mb86a16_release,
+
+        .get_frontend_algo              = mb86a16_frontend_algo,
+        .search                         = mb86a16_search,
+        .read_status                    = mb86a16_read_status,
+        .init                           = mb86a16_init,
+        .sleep                          = mb86a16_sleep,
+        .read_status                    = mb86a16_read_status,
+
+        .read_ber                       = mb86a16_read_ber,
+        .read_signal_strength           = mb86a16_read_signal_strength,
+        .read_snr                       = mb86a16_read_snr,
+        .read_ucblocks                  = mb86a16_read_ucblocks,
+
+        .diseqc_send_master_cmd         = mb86a16_send_diseqc_msg,
+        .diseqc_send_burst              = mb86a16_send_diseqc_burst,
+        .set_tone                       = mb86a16_set_tone,
+};
+
+struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
+                                    struct i2c_adapter *i2c_adap)
+{
+        u8 dev_id = 0;
+        struct mb86a16_state *state = NULL;
+
+        state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL);
+        if (state == NULL)
+                goto error;
+
+        state->config = config;
+        state->i2c_adap = i2c_adap;
+
+        mb86a16_read(state, 0x7f, &dev_id);
+        if (dev_id != 0xfe)
+                goto error;
+
+        memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops));
+        state->frontend.demodulator_priv = state;
+        state->frontend.ops.set_voltage = state->config->set_voltage;
+
+        return &state->frontend;
+error:
+        kfree(state);
+        return NULL;
+}
+EXPORT_SYMBOL(mb86a16_attach);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Manu Abraham");
diff --git a/drivers/media/dvb/frontends/mb86a16.h b/drivers/media/dvb/frontends/mb86a16.h
new file mode 100644
index 000000000000..6ea8c376394f
--- /dev/null
+++ b/drivers/media/dvb/frontends/mb86a16.h
@@ -0,0 +1,52 @@
+/*
+        Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
+
+        Copyright (C) Manu Abraham (abraham.manu@gmail.com)
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __MB86A16_H
+#define __MB86A16_H
+
+#include <linux/dvb/frontend.h>
+#include "dvb_frontend.h"
+
+
+struct mb86a16_config {
+        u8 demod_address;
+
+        int (*set_voltage)(struct dvb_frontend *fe, fe_sec_voltage_t voltage);
+};
+
+
+
+#if defined(CONFIG_DVB_MB86A16) || (defined(CONFIG_DVB_MB86A16_MODULE) && defined(MODULE))
+
+extern struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
+                                           struct i2c_adapter *i2c_adap);
+
+#else
+
+static inline struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
+                                           struct i2c_adapter *i2c_adap)
+{
+        printk(KERN_WARNING "%s: Driver disabled by Kconfig\n", __func__);
+        return NULL;
+}
+
+#endif /* CONFIG_DVB_MB86A16 */
+
+#endif /* __MB86A16_H */
diff --git a/drivers/media/dvb/frontends/mb86a16_priv.h b/drivers/media/dvb/frontends/mb86a16_priv.h
new file mode 100644
index 000000000000..360a35acfe84
--- /dev/null
+++ b/drivers/media/dvb/frontends/mb86a16_priv.h
@@ -0,0 +1,151 @@
+/*
+        Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
+
+        Copyright (C) Manu Abraham (abraham.manu@gmail.com)
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __MB86A16_PRIV_H
+#define __MB86A16_PRIV_H
+
+#define MB86A16_TSOUT           0x00
+#define MB86A16_TSOUT_HIZSEL    (0x01 << 5)
+#define MB86A16_TSOUT_HIZCNTI   (0x01 << 4)
+#define MB86A16_TSOUT_MODE      (0x01 << 3)
+#define MB86A16_TSOUT_ORDER     (0x01 << 2)
+#define MB86A16_TSOUT_ERROR     (0x01 << 1)
+#define Mb86A16_TSOUT_EDGE      (0x01 << 0)
+
+#define MB86A16_FEC             0x01
+#define MB86A16_FEC_FSYNC       (0x01 << 5)
+#define MB86A16_FEC_PCKB8       (0x01 << 4)
+#define MB86A16_FEC_DVDS        (0x01 << 3)
+#define MB86A16_FEC_EREN        (0x01 << 2)
+#define Mb86A16_FEC_RSEN        (0x01 << 1)
+#define MB86A16_FEC_DIEN        (0x01 << 0)
+
+#define MB86A16_AGC             0x02
+#define MB86A16_AGC_AGMD        (0x01 << 6)
+#define MB86A16_AGC_AGCW        (0x0f << 2)
+#define MB86A16_AGC_AGCP        (0x01 << 1)
+#define MB86A16_AGC_AGCR        (0x01 << 0)
+
+#define MB86A16_SRATE1          0x03
+#define MB86A16_SRATE1_DECI     (0x07 << 2)
+#define MB86A16_SRATE1_CSEL     (0x01 << 1)
+#define MB86A16_SRATE1_RSEL     (0x01 << 0)
+
+#define MB86A16_SRATE2          0x04
+#define MB86A16_SRATE2_STOFSL   (0xff << 0)
+
+#define MB86A16_SRATE3          0x05
+#define MB86A16_SRATE2_STOFSH   (0xff << 0)
+
+#define MB86A16_VITERBI         0x06
+#define MB86A16_FRAMESYNC       0x07
+#define MB86A16_CRLFILTCOEF1    0x08
+#define MB86A16_CRLFILTCOEF2    0x09
+#define MB86A16_STRFILTCOEF1    0x0a
+#define MB86A16_STRFILTCOEF2    0x0b
+#define MB86A16_RESET           0x0c
+#define MB86A16_STATUS          0x0d
+#define MB86A16_AFCML           0x0e
+#define MB86A16_AFCMH           0x0f
+#define MB86A16_BERMON          0x10
+#define MB86A16_BERTAB          0x11
+#define MB86A16_BERLSB          0x12
+#define MB86A16_BERMID          0x13
+#define MB86A16_BERMSB          0x14
+#define MB86A16_AGCM            0x15
+
+#define MB86A16_DCC1            0x16
+#define MB86A16_DCC1_DISTA      (0x01 << 7)
+#define MB86A16_DCC1_PRTY       (0x01 << 6)
+#define MB86A16_DCC1_CTOE       (0x01 << 5)
+#define MB86A16_DCC1_TBEN       (0x01 << 4)
+#define MB86A16_DCC1_TBO        (0x01 << 3)
+#define MB86A16_DCC1_NUM        (0x07 << 0)
+
+#define MB86A16_DCC2            0x17
+#define MB86A16_DCC2_DCBST      (0x01 << 0)
+
+#define MB86A16_DCC3            0x18
+#define MB86A16_DCC3_CODE0      (0xff << 0)
+
+#define MB86A16_DCC4            0x19
+#define MB86A16_DCC4_CODE1      (0xff << 0)
+
+#define MB86A16_DCC5            0x1a
+#define MB86A16_DCC5_CODE2      (0xff << 0)
+
+#define MB86A16_DCC6            0x1b
+#define MB86A16_DCC6_CODE3      (0xff << 0)
+
+#define MB86A16_DCC7            0x1c
+#define MB86A16_DCC7_CODE4      (0xff << 0)
+
+#define MB86A16_DCC8            0x1d
+#define MB86A16_DCC8_CODE5      (0xff << 0)
+
+#define MB86A16_DCCOUT          0x1e
+#define MB86A16_DCCOUT_DISEN    (0x01 << 0)
+
+#define MB86A16_TONEOUT1        0x1f
+#define MB86A16_TONE_TDIVL      (0xff << 0)
+
+#define MB86A16_TONEOUT2        0x20
+#define MB86A16_TONE_TMD        (0x03 << 2)
+#define MB86A16_TONE_TDIVH      (0x03 << 0)
+
+#define MB86A16_FREQ1           0x21
+#define MB86A16_FREQ2           0x22
+#define MB86A16_FREQ3           0x23
+#define MB86A16_FREQ4           0x24
+#define MB86A16_FREQSET         0x25
+#define MB86A16_CNM             0x26
+#define MB86A16_PORT0           0x27
+#define MB86A16_PORT1           0x28
+#define MB86A16_DRCFILT         0x29
+#define MB86A16_AFC             0x2a
+#define MB86A16_AFCEXL          0x2b
+#define MB86A16_AFCEXH          0x2c
+#define MB86A16_DAGC            0x2d
+#define MB86A16_SEQMODE         0x32
+#define MB86A16_S0S1T           0x33
+#define MB86A16_S2S3T           0x34
+#define MB86A16_S4S5T           0x35
+#define MB86A16_CNTMR           0x36
+#define MB86A16_SIG1            0x37
+#define MB86A16_SIG2            0x38
+#define MB86A16_VIMAG           0x39
+#define MB86A16_VISET1          0x3a
+#define MB86A16_VISET2          0x3b
+#define MB86A16_VISET3          0x3c
+#define MB86A16_FAGCS1          0x3d
+#define MB86A16_FAGCS2          0x3e
+#define MB86A16_FAGCS3          0x3f
+#define MB86A16_FAGCS4          0x40
+#define MB86A16_FAGCS5          0x41
+#define MB86A16_FAGCS6          0x42
+#define MB86A16_CRM             0x43
+#define MB86A16_STRM            0x44
+#define MB86A16_DAGCML          0x45
+#define MB86A16_DAGCMH          0x46
+#define MB86A16_QPSKTST         0x49
+#define MB86A16_DISTMON         0x52
+#define MB86A16_VERSION         0x7f
+
+#endif /* __MB86A16_PRIV_H */
diff --git a/drivers/media/dvb/frontends/s5h1409.c b/drivers/media/dvb/frontends/s5h1409.c
index fb3011518427..0e2f61a8978f 100644
--- a/drivers/media/dvb/frontends/s5h1409.c
+++ b/drivers/media/dvb/frontends/s5h1409.c
@@ -44,7 +44,15 @@ struct s5h1409_state {
         int if_freq;
 
         u32 is_qam_locked;
-        u32 qam_state;
+
+        /* QAM tuning state goes through the following state transitions */
+#define QAM_STATE_UNTUNED 0
+#define QAM_STATE_TUNING_STARTED 1
+#define QAM_STATE_INTERLEAVE_SET 2
+#define QAM_STATE_QAM_OPTIMIZED_L1 3
+#define QAM_STATE_QAM_OPTIMIZED_L2 4
+#define QAM_STATE_QAM_OPTIMIZED_L3 5
+        u8  qam_state;
 };
 
 static int debug;
@@ -347,7 +355,7 @@ static int s5h1409_softreset(struct dvb_frontend *fe)
         s5h1409_writereg(state, 0xf5, 0);
         s5h1409_writereg(state, 0xf5, 1);
         state->is_qam_locked = 0;
-        state->qam_state = 0;
+        state->qam_state = QAM_STATE_UNTUNED;
         return 0;
 }
 
@@ -474,6 +482,59 @@ static void s5h1409_set_qam_amhum_mode(struct dvb_frontend *fe)
         struct s5h1409_state *state = fe->demodulator_priv;
         u16 reg;
 
+        if (state->qam_state < QAM_STATE_INTERLEAVE_SET) {
+                /* We should not perform amhum optimization until
+                   the interleave mode has been configured */
+                return;
+        }
+
+        if (state->qam_state == QAM_STATE_QAM_OPTIMIZED_L3) {
+                /* We've already reached the maximum optimization level, so
+                   dont bother banging on the status registers */
+                return;
+        }
+
+        /* QAM EQ lock check */
+        reg = s5h1409_readreg(state, 0xf0);
+
+        if ((reg >> 13) & 0x1) {
+                reg &= 0xff;
+
+                s5h1409_writereg(state, 0x96, 0x000c);
+                if (reg < 0x68) {
+                        if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L3) {
+                                dprintk("%s() setting QAM state to OPT_L3\n",
+                                        __func__);
+                                s5h1409_writereg(state, 0x93, 0x3130);
+                                s5h1409_writereg(state, 0x9e, 0x2836);
+                                state->qam_state = QAM_STATE_QAM_OPTIMIZED_L3;
+                        }
+                } else {
+                        if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L2) {
+                                dprintk("%s() setting QAM state to OPT_L2\n",
+                                        __func__);
+                                s5h1409_writereg(state, 0x93, 0x3332);
+                                s5h1409_writereg(state, 0x9e, 0x2c37);
+                                state->qam_state = QAM_STATE_QAM_OPTIMIZED_L2;
+                        }
+                }
+
+        } else {
+                if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L1) {
+                        dprintk("%s() setting QAM state to OPT_L1\n", __func__);
+                        s5h1409_writereg(state, 0x96, 0x0008);
+                        s5h1409_writereg(state, 0x93, 0x3332);
+                        s5h1409_writereg(state, 0x9e, 0x2c37);
+                        state->qam_state = QAM_STATE_QAM_OPTIMIZED_L1;
+                }
+        }
+}
+
+static void s5h1409_set_qam_amhum_mode_legacy(struct dvb_frontend *fe)
+{
+        struct s5h1409_state *state = fe->demodulator_priv;
+        u16 reg;
+
         if (state->is_qam_locked)
                 return;
 
@@ -506,6 +567,44 @@ static void s5h1409_set_qam_interleave_mode(struct dvb_frontend *fe)
         struct s5h1409_state *state = fe->demodulator_priv;
         u16 reg, reg1, reg2;
 
+        if (state->qam_state >= QAM_STATE_INTERLEAVE_SET) {
+                /* We've done the optimization already */
+                return;
+        }
+
+        reg = s5h1409_readreg(state, 0xf1);
+
+        /* Master lock */
+        if ((reg >> 15) & 0x1) {
+                if (state->qam_state == QAM_STATE_UNTUNED ||
+                    state->qam_state == QAM_STATE_TUNING_STARTED) {
+                        dprintk("%s() setting QAM state to INTERLEAVE_SET\n",
+                                __func__);
+                        reg1 = s5h1409_readreg(state, 0xb2);
+                        reg2 = s5h1409_readreg(state, 0xad);
+
+                        s5h1409_writereg(state, 0x96, 0x0020);
+                        s5h1409_writereg(state, 0xad,
+                                (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
+                        state->qam_state = QAM_STATE_INTERLEAVE_SET;
+                }
+        } else {
+                if (state->qam_state == QAM_STATE_UNTUNED) {
+                        dprintk("%s() setting QAM state to TUNING_STARTED\n",
+                                __func__);
+                        s5h1409_writereg(state, 0x96, 0x08);
+                        s5h1409_writereg(state, 0xab,
+                                s5h1409_readreg(state, 0xab) | 0x1001);
+                        state->qam_state = QAM_STATE_TUNING_STARTED;
+                }
+        }
+}
+
+static void s5h1409_set_qam_interleave_mode_legacy(struct dvb_frontend *fe)
+{
+        struct s5h1409_state *state = fe->demodulator_priv;
+        u16 reg, reg1, reg2;
+
         reg = s5h1409_readreg(state, 0xf1);
 
         /* Master lock */
@@ -553,16 +652,24 @@ static int s5h1409_set_frontend(struct dvb_frontend *fe,
                         fe->ops.i2c_gate_ctrl(fe, 0);
         }
 
-        /* Optimize the demod for QAM */
-        if (p->u.vsb.modulation != VSB_8) {
-                s5h1409_set_qam_amhum_mode(fe);
-                s5h1409_set_qam_interleave_mode(fe);
-        }
-
         /* Issue a reset to the demod so it knows to resync against the
            newly tuned frequency */
         s5h1409_softreset(fe);
 
+        /* Optimize the demod for QAM */
+        if (state->current_modulation != VSB_8) {
+                /* This almost certainly applies to all boards, but for now
+                   only do it for the HVR-1600.  Once the other boards are
+                   tested, the "legacy" versions can just go away */
+                if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
+                        s5h1409_set_qam_interleave_mode(fe);
+                        s5h1409_set_qam_amhum_mode(fe);
+                } else {
+                        s5h1409_set_qam_amhum_mode_legacy(fe);
+                        s5h1409_set_qam_interleave_mode_legacy(fe);
+                }
+        }
+
         return 0;
 }
 
@@ -614,6 +721,21 @@ static int s5h1409_init(struct dvb_frontend *fe)
         /* The datasheet says that after initialisation, VSB is default */
         state->current_modulation = VSB_8;
 
+        /* Optimize for the HVR-1600 if appropriate.  Note that some of these
+           may get folded into the generic case after testing with other
+           devices */
+        if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
+                /* VSB AGC REF */
+                s5h1409_writereg(state, 0x09, 0x0050);
+
+                /* Unknown but Windows driver does it... */
+                s5h1409_writereg(state, 0x21, 0x0001);
+                s5h1409_writereg(state, 0x50, 0x030e);
+
+                /* QAM AGC REF */
+                s5h1409_writereg(state, 0x82, 0x0800);
+        }
+
         if (state->config->output_mode == S5H1409_SERIAL_OUTPUT)
                 s5h1409_writereg(state, 0xab,
                         s5h1409_readreg(state, 0xab) | 0x100); /* Serial */
@@ -641,6 +763,17 @@ static int s5h1409_read_status(struct dvb_frontend *fe, fe_status_t *status)
 
         *status = 0;
 
+        /* Optimize the demod for QAM */
+        if (state->current_modulation != VSB_8) {
+                /* This almost certainly applies to all boards, but for now
+                   only do it for the HVR-1600.  Once the other boards are
+                   tested, the "legacy" versions can just go away */
+                if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
+                        s5h1409_set_qam_interleave_mode(fe);
+                        s5h1409_set_qam_amhum_mode(fe);
+                }
+        }
+
         /* Get the demodulator status */
         reg = s5h1409_readreg(state, 0xf1);
         if (reg & 0x1000)
diff --git a/drivers/media/dvb/frontends/s5h1409.h b/drivers/media/dvb/frontends/s5h1409.h
index 070d9743e330..91f2ebd1a534 100644
--- a/drivers/media/dvb/frontends/s5h1409.h
+++ b/drivers/media/dvb/frontends/s5h1409.h
@@ -57,6 +57,13 @@ struct s5h1409_config {
 #define S5H1409_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK    2
 #define S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK 3
         u16 mpeg_timing;
+
+        /* HVR-1600 optimizations (to better work with MXL5005s)
+           Note: some of these are likely to be folded into the generic driver
+           after being regression tested with other boards */
+#define S5H1409_HVR1600_NOOPTIMIZE 0
+#define S5H1409_HVR1600_OPTIMIZE   1
+        u8 hvr1600_opt;
 };
 
 #if defined(CONFIG_DVB_S5H1409) || (defined(CONFIG_DVB_S5H1409_MODULE) \
diff --git a/drivers/media/dvb/frontends/s921_module.c b/drivers/media/dvb/frontends/s921_module.c
index 3156b64cfc96..0eefff61cc50 100644
--- a/drivers/media/dvb/frontends/s921_module.c
+++ b/drivers/media/dvb/frontends/s921_module.c
@@ -9,6 +9,7 @@
 
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/delay.h>
 #include "dvb_frontend.h"
 #include "s921_module.h"
diff --git a/drivers/media/dvb/frontends/si21xx.c b/drivers/media/dvb/frontends/si21xx.c
index 9552a22ccffb..d21a327db629 100644
--- a/drivers/media/dvb/frontends/si21xx.c
+++ b/drivers/media/dvb/frontends/si21xx.c
@@ -97,8 +97,6 @@
 #define LNB_SUPPLY_CTRL_REG_4           0xce
 #define LNB_SUPPLY_STATUS_REG           0xcf
 
-#define FALSE   0
-#define TRUE    1
 #define FAIL    -1
 #define PASS    0
 
@@ -718,7 +716,7 @@ static int si21xx_set_frontend(struct dvb_frontend *fe,
         int fine_tune_freq;
         unsigned char sample_rate = 0;
         /* boolean */
-        unsigned int inband_interferer_ind;
+        bool inband_interferer_ind;
 
         /* INTERMEDIATE VALUES */
         int icoarse_tune_freq; /* MHz */
@@ -728,15 +726,8 @@ static int si21xx_set_frontend(struct dvb_frontend *fe,
         unsigned int x1;
         unsigned int x2;
         int i;
-        unsigned int inband_interferer_div2[ALLOWABLE_FS_COUNT] = {
-                        FALSE, FALSE, FALSE, FALSE, FALSE,
-                        FALSE, FALSE, FALSE, FALSE, FALSE
-        };
-        unsigned int inband_interferer_div4[ALLOWABLE_FS_COUNT] = {
-                        FALSE, FALSE, FALSE, FALSE, FALSE,
-                        FALSE, FALSE, FALSE, FALSE, FALSE
-        };
-
+        bool inband_interferer_div2[ALLOWABLE_FS_COUNT];
+        bool inband_interferer_div4[ALLOWABLE_FS_COUNT];
         int status;
 
         /* allowable sample rates for ADC in MHz */
@@ -762,7 +753,7 @@ static int si21xx_set_frontend(struct dvb_frontend *fe,
         }
 
         for (i = 0; i < ALLOWABLE_FS_COUNT; ++i)
-                inband_interferer_div2[i] = inband_interferer_div4[i] = FALSE;
+                inband_interferer_div2[i] = inband_interferer_div4[i] = false;
 
         if_limit_high = -700000;
         if_limit_low = -100000;
@@ -798,7 +789,7 @@ static int si21xx_set_frontend(struct dvb_frontend *fe,
 
                 if (((band_low < x1) && (x1 < band_high)) ||
                                         ((band_low < x2) && (x2 < band_high)))
-                                        inband_interferer_div4[i] = TRUE;
+                                        inband_interferer_div4[i] = true;
 
         }
 
@@ -811,25 +802,28 @@ static int si21xx_set_frontend(struct dvb_frontend *fe,
 
                 if (((band_low < x1) && (x1 < band_high)) ||
                                         ((band_low < x2) && (x2 < band_high)))
-                                        inband_interferer_div2[i] = TRUE;
+                                        inband_interferer_div2[i] = true;
         }
 
-        inband_interferer_ind = TRUE;
-        for (i = 0; i < ALLOWABLE_FS_COUNT; ++i)
-                inband_interferer_ind &= inband_interferer_div2[i] |
-                                                inband_interferer_div4[i];
+        inband_interferer_ind = true;
+        for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
+                if (inband_interferer_div2[i] || inband_interferer_div4[i]) {
+                        inband_interferer_ind = false;
+                        break;
+                }
+        }
 
         if (inband_interferer_ind) {
                 for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
-                        if (inband_interferer_div2[i] == FALSE) {
+                        if (!inband_interferer_div2[i]) {
                                 sample_rate = (u8) afs[i];
                                 break;
                         }
                 }
         } else {
                 for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
-                        if ((inband_interferer_div2[i] |
-                                        inband_interferer_div4[i]) == FALSE) {
+                        if ((inband_interferer_div2[i] ||
+                             !inband_interferer_div4[i])) {
                                 sample_rate = (u8) afs[i];
                                 break;
                         }
diff --git a/drivers/media/dvb/frontends/stb0899_drv.c b/drivers/media/dvb/frontends/stb0899_drv.c
index a04c782fff8d..8e38fcee564e 100644
--- a/drivers/media/dvb/frontends/stb0899_drv.c
+++ b/drivers/media/dvb/frontends/stb0899_drv.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/string.h>
 
 #include <linux/dvb/frontend.h>
@@ -1571,7 +1572,7 @@ static enum dvbfe_search stb0899_search(struct dvb_frontend *fe, struct dvb_fron
  * stb0899_track
  * periodically check the signal level against a specified
  * threshold level and perform derotator centering.
- * called once we have a lock from a succesful search
+ * called once we have a lock from a successful search
  * event.
  *
  * Will be called periodically called to maintain the
diff --git a/drivers/media/dvb/frontends/stb6000.c b/drivers/media/dvb/frontends/stb6000.c
index 0e2cb0df1441..ed699647050e 100644
--- a/drivers/media/dvb/frontends/stb6000.c
+++ b/drivers/media/dvb/frontends/stb6000.c
@@ -20,6 +20,7 @@
 
   */
 
+#include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/dvb/frontend.h>
 #include <asm/types.h>
diff --git a/drivers/media/dvb/frontends/stb6100.c b/drivers/media/dvb/frontends/stb6100.c
index 60ee18a94f43..f73c13323e90 100644
--- a/drivers/media/dvb/frontends/stb6100.c
+++ b/drivers/media/dvb/frontends/stb6100.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/string.h>
 
 #include "dvb_frontend.h"
diff --git a/drivers/media/dvb/frontends/stb6100_proc.h b/drivers/media/dvb/frontends/stb6100_proc.h
new file mode 100644
index 000000000000..112163a48622
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb6100_proc.h
@@ -0,0 +1,138 @@
+/*
+        STB6100 Silicon Tuner wrapper
+        Copyright (C)2009 Igor M. Liplianin (liplianin@me.by)
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+static int stb6100_get_freq(struct dvb_frontend *fe, u32 *frequency)
+{
+        struct dvb_frontend_ops *frontend_ops = NULL;
+        struct dvb_tuner_ops    *tuner_ops = NULL;
+        struct tuner_state      state;
+        int err = 0;
+
+        if (&fe->ops)
+                frontend_ops = &fe->ops;
+        if (&frontend_ops->tuner_ops)
+                tuner_ops = &frontend_ops->tuner_ops;
+        if (tuner_ops->get_state) {
+                if (frontend_ops->i2c_gate_ctrl)
+                        frontend_ops->i2c_gate_ctrl(fe, 1);
+
+                err = tuner_ops->get_state(fe, DVBFE_TUNER_FREQUENCY, &state);
+                if (err < 0) {
+                        printk(KERN_ERR "%s: Invalid parameter\n", __func__);
+                        return err;
+                }
+
+                if (frontend_ops->i2c_gate_ctrl)
+                        frontend_ops->i2c_gate_ctrl(fe, 0);
+
+                *frequency = state.frequency;
+        }
+
+        return 0;
+}
+
+static int stb6100_set_freq(struct dvb_frontend *fe, u32 frequency)
+{
+        struct dvb_frontend_ops *frontend_ops = NULL;
+        struct dvb_tuner_ops    *tuner_ops = NULL;
+        struct tuner_state      state;
+        int err = 0;
+
+        state.frequency = frequency;
+        if (&fe->ops)
+                frontend_ops = &fe->ops;
+        if (&frontend_ops->tuner_ops)
+                tuner_ops = &frontend_ops->tuner_ops;
+        if (tuner_ops->set_state) {
+                if (frontend_ops->i2c_gate_ctrl)
+                        frontend_ops->i2c_gate_ctrl(fe, 1);
+
+                err = tuner_ops->set_state(fe, DVBFE_TUNER_FREQUENCY, &state);
+                if (err < 0) {
+                        printk(KERN_ERR "%s: Invalid parameter\n", __func__);
+                        return err;
+                }
+
+                if (frontend_ops->i2c_gate_ctrl)
+                        frontend_ops->i2c_gate_ctrl(fe, 0);
+
+        }
+
+        return 0;
+}
+
+static int stb6100_get_bandw(struct dvb_frontend *fe, u32 *bandwidth)
+{
+        struct dvb_frontend_ops *frontend_ops = NULL;
+        struct dvb_tuner_ops    *tuner_ops = NULL;
+        struct tuner_state      state;
+        int err = 0;
+
+        if (&fe->ops)
+                frontend_ops = &fe->ops;
+        if (&frontend_ops->tuner_ops)
+                tuner_ops = &frontend_ops->tuner_ops;
+        if (tuner_ops->get_state) {
+                if (frontend_ops->i2c_gate_ctrl)
+                        frontend_ops->i2c_gate_ctrl(fe, 1);
+
+                err = tuner_ops->get_state(fe, DVBFE_TUNER_BANDWIDTH, &state);
+                if (err < 0) {
+                        printk(KERN_ERR "%s: Invalid parameter\n", __func__);
+                        return err;
+                }
+
+                if (frontend_ops->i2c_gate_ctrl)
+                        frontend_ops->i2c_gate_ctrl(fe, 0);
+
+                *bandwidth = state.bandwidth;
+        }
+
+        return 0;
+}
+
+static int stb6100_set_bandw(struct dvb_frontend *fe, u32 bandwidth)
+{
+        struct dvb_frontend_ops *frontend_ops = NULL;
+        struct dvb_tuner_ops    *tuner_ops = NULL;
+        struct tuner_state      state;
+        int err = 0;
+
+        state.bandwidth = bandwidth;
+        if (&fe->ops)
+                frontend_ops = &fe->ops;
+        if (&frontend_ops->tuner_ops)
+                tuner_ops = &frontend_ops->tuner_ops;
+        if (tuner_ops->set_state) {
+                if (frontend_ops->i2c_gate_ctrl)
+                        frontend_ops->i2c_gate_ctrl(fe, 1);
+
+                err = tuner_ops->set_state(fe, DVBFE_TUNER_BANDWIDTH, &state);
+                if (err < 0) {
+                        printk(KERN_ERR "%s: Invalid parameter\n", __func__);
+                        return err;
+                }
+
+                if (frontend_ops->i2c_gate_ctrl)
+                        frontend_ops->i2c_gate_ctrl(fe, 0);
+
+        }
+
+        return 0;
+}
diff --git a/drivers/media/dvb/frontends/stv0900.h b/drivers/media/dvb/frontends/stv0900.h
index bf4e9b633044..e3e35d1ce838 100644
--- a/drivers/media/dvb/frontends/stv0900.h
+++ b/drivers/media/dvb/frontends/stv0900.h
@@ -36,6 +36,7 @@ struct stv0900_reg {
 
 struct stv0900_config {
         u8 demod_address;
+        u8 demod_mode;
         u32 xtal;
         u8 clkmode;/* 0 for CLKI,  2 for XTALI */
 
@@ -48,6 +49,10 @@ struct stv0900_config {
         u8 tun2_maddress;
         u8 tun1_adc;/* 1 for stv6110, 2 for stb6100 */
         u8 tun2_adc;
+        u8 tun1_type;/* for now 3 for stb6100 auto, else - software */
+        u8 tun2_type;
+        /* Set device param to start dma */
+        int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured);
 };
 
 #if defined(CONFIG_DVB_STV0900) || (defined(CONFIG_DVB_STV0900_MODULE) \
diff --git a/drivers/media/dvb/frontends/stv0900_core.c b/drivers/media/dvb/frontends/stv0900_core.c
index 3bde3324a032..01f8f1f802fd 100644
--- a/drivers/media/dvb/frontends/stv0900_core.c
+++ b/drivers/media/dvb/frontends/stv0900_core.c
@@ -34,7 +34,7 @@
 #include "stv0900_priv.h"
 #include "stv0900_init.h"
 
-static int stvdebug = 1;
+int stvdebug = 1;
 module_param_named(debug, stvdebug, int, 0644);
 
 /* internal params node */
@@ -105,7 +105,8 @@ static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
                 while (new_node->next_inode != NULL)
                         new_node = new_node->next_inode;
 
-                new_node->next_inode = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
+                new_node->next_inode = kmalloc(sizeof(struct stv0900_inode),
+                                                                GFP_KERNEL);
                 if (new_node->next_inode != NULL)
                         new_node = new_node->next_inode;
                 else
@@ -128,13 +129,13 @@ s32 ge2comp(s32 a, s32 width)
                 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
 }
 
-void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
+void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr,
                                                                 u8 reg_data)
 {
         u8 data[3];
         int ret;
         struct i2c_msg i2cmsg = {
-                .addr  = i_params->i2c_addr,
+                .addr  = intp->i2c_addr,
                 .flags = 0,
                 .len   = 3,
                 .buf   = data,
@@ -144,39 +145,39 @@ void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
         data[1] = LSB(reg_addr);
         data[2] = reg_data;
 
-        ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1);
+        ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1);
         if (ret != 1)
-                dprintk(KERN_ERR "%s: i2c error %d\n", __func__, ret);
+                dprintk("%s: i2c error %d\n", __func__, ret);
 }
 
-u8 stv0900_read_reg(struct stv0900_internal *i_params, u16 reg)
+u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg)
 {
         int ret;
         u8 b0[] = { MSB(reg), LSB(reg) };
         u8 buf = 0;
         struct i2c_msg msg[] = {
                 {
-                        .addr   = i_params->i2c_addr,
+                        .addr   = intp->i2c_addr,
                         .flags  = 0,
                         .buf = b0,
                         .len = 2,
                 }, {
-                        .addr   = i_params->i2c_addr,
+                        .addr   = intp->i2c_addr,
                         .flags  = I2C_M_RD,
                         .buf = &buf,
                         .len = 1,
                 },
         };
 
-        ret = i2c_transfer(i_params->i2c_adap, msg, 2);
+        ret = i2c_transfer(intp->i2c_adap, msg, 2);
         if (ret != 2)
-                dprintk(KERN_ERR "%s: i2c error %d, reg[0x%02x]\n",
+                dprintk("%s: i2c error %d, reg[0x%02x]\n",
                                 __func__, ret, reg);
 
         return buf;
 }
 
-void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
+static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
 {
         u8 position = 0, i = 0;
 
@@ -190,169 +191,165 @@ void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
         (*pos) = (i - 1);
 }
 
-void stv0900_write_bits(struct stv0900_internal *i_params, u32 label, u8 val)
+void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val)
 {
         u8 reg, mask, pos;
 
-        reg = stv0900_read_reg(i_params, (label >> 16) & 0xffff);
+        reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
         extract_mask_pos(label, &mask, &pos);
 
         val = mask & (val << pos);
 
         reg = (reg & (~mask)) | val;
-        stv0900_write_reg(i_params, (label >> 16) & 0xffff, reg);
+        stv0900_write_reg(intp, (label >> 16) & 0xffff, reg);
 
 }
 
-u8 stv0900_get_bits(struct stv0900_internal *i_params, u32 label)
+u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label)
 {
         u8 val = 0xff;
         u8 mask, pos;
 
         extract_mask_pos(label, &mask, &pos);
 
-        val = stv0900_read_reg(i_params, label >> 16);
+        val = stv0900_read_reg(intp, label >> 16);
         val = (val & mask) >> pos;
 
         return val;
 }
 
-enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *i_params)
+static enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp)
 {
         s32 i;
-        enum fe_stv0900_error error;
-
-        if (i_params != NULL) {
-                i_params->chip_id = stv0900_read_reg(i_params, R0900_MID);
-                if (i_params->errs == STV0900_NO_ERROR) {
-                        /*Startup sequence*/
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5c);
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5c);
-                        stv0900_write_reg(i_params, R0900_P1_TNRCFG, 0x6c);
-                        stv0900_write_reg(i_params, R0900_P2_TNRCFG, 0x6f);
-                        stv0900_write_reg(i_params, R0900_P1_I2CRPT, 0x20);
-                        stv0900_write_reg(i_params, R0900_P2_I2CRPT, 0x20);
-                        stv0900_write_reg(i_params, R0900_NCOARSE, 0x13);
-                        msleep(3);
-                        stv0900_write_reg(i_params, R0900_I2CCFG, 0x08);
-
-                        switch (i_params->clkmode) {
-                        case 0:
-                        case 2:
-                                stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20
-                                                | i_params->clkmode);
-                                break;
-                        default:
-                                /* preserve SELOSCI bit */
-                                i = 0x02 & stv0900_read_reg(i_params, R0900_SYNTCTRL);
-                                stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20 | i);
-                                break;
-                        }
 
-                        msleep(3);
-                        for (i = 0; i < 182; i++)
-                                stv0900_write_reg(i_params, STV0900_InitVal[i][0], STV0900_InitVal[i][1]);
+        if (intp == NULL)
+                return STV0900_INVALID_HANDLE;
 
-                        if (stv0900_read_reg(i_params, R0900_MID) >= 0x20) {
-                                stv0900_write_reg(i_params, R0900_TSGENERAL, 0x0c);
-                                for (i = 0; i < 32; i++)
-                                        stv0900_write_reg(i_params, STV0900_Cut20_AddOnVal[i][0], STV0900_Cut20_AddOnVal[i][1]);
-                        }
+        intp->chip_id = stv0900_read_reg(intp, R0900_MID);
 
-                        stv0900_write_reg(i_params, R0900_P1_FSPYCFG, 0x6c);
-                        stv0900_write_reg(i_params, R0900_P2_FSPYCFG, 0x6c);
-                        stv0900_write_reg(i_params, R0900_TSTRES0, 0x80);
-                        stv0900_write_reg(i_params, R0900_TSTRES0, 0x00);
-                }
-                error = i_params->errs;
-        } else
-                error = STV0900_INVALID_HANDLE;
+        if (intp->errs != STV0900_NO_ERROR)
+                return intp->errs;
 
-        return error;
+        /*Startup sequence*/
+        stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c);
+        stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c);
+        msleep(3);
+        stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c);
+        stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f);
+        stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20);
+        stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20);
+        stv0900_write_reg(intp, R0900_NCOARSE, 0x13);
+        msleep(3);
+        stv0900_write_reg(intp, R0900_I2CCFG, 0x08);
+
+        switch (intp->clkmode) {
+        case 0:
+        case 2:
+                stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20
+                                | intp->clkmode);
+                break;
+        default:
+                /* preserve SELOSCI bit */
+                i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
+                stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i);
+                break;
+        }
+
+        msleep(3);
+        for (i = 0; i < 181; i++)
+                stv0900_write_reg(intp, STV0900_InitVal[i][0],
+                                STV0900_InitVal[i][1]);
+
+        if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
+                stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c);
+                for (i = 0; i < 32; i++)
+                        stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0],
+                                        STV0900_Cut20_AddOnVal[i][1]);
+        }
 
+        stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c);
+        stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c);
+
+        stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01);
+        stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21);
+
+        stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20);
+        stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20);
+
+        stv0900_write_reg(intp, R0900_TSTRES0, 0x80);
+        stv0900_write_reg(intp, R0900_TSTRES0, 0x00);
+
+        return STV0900_NO_ERROR;
 }
 
-u32 stv0900_get_mclk_freq(struct stv0900_internal *i_params, u32 ext_clk)
+static u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk)
 {
         u32 mclk = 90000000, div = 0, ad_div = 0;
 
-        div = stv0900_get_bits(i_params, F0900_M_DIV);
-        ad_div = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
+        div = stv0900_get_bits(intp, F0900_M_DIV);
+        ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
 
         mclk = (div + 1) * ext_clk / ad_div;
 
-        dprintk(KERN_INFO "%s: Calculated Mclk = %d\n", __func__, mclk);
+        dprintk("%s: Calculated Mclk = %d\n", __func__, mclk);
 
         return mclk;
 }
 
-enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *i_params, u32 mclk)
+static enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk)
 {
-        enum fe_stv0900_error error = STV0900_NO_ERROR;
         u32 m_div, clk_sel;
 
-        dprintk(KERN_INFO "%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
-                        i_params->quartz);
+        dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
+                        intp->quartz);
 
-        if (i_params == NULL)
-                error = STV0900_INVALID_HANDLE;
-        else {
-                if (i_params->errs)
-                        error = STV0900_I2C_ERROR;
-                else {
-                        clk_sel = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
-                        m_div = ((clk_sel * mclk) / i_params->quartz) - 1;
-                        stv0900_write_bits(i_params, F0900_M_DIV, m_div);
-                        i_params->mclk = stv0900_get_mclk_freq(i_params,
-                                                        i_params->quartz);
-
-                        /*Set the DiseqC frequency to 22KHz */
-                        /*
-                                Formula:
-                                DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
-                                DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
-                        */
-                        m_div = i_params->mclk / 704000;
-                        stv0900_write_reg(i_params, R0900_P1_F22TX, m_div);
-                        stv0900_write_reg(i_params, R0900_P1_F22RX, m_div);
-
-                        stv0900_write_reg(i_params, R0900_P2_F22TX, m_div);
-                        stv0900_write_reg(i_params, R0900_P2_F22RX, m_div);
-
-                        if ((i_params->errs))
-                                error = STV0900_I2C_ERROR;
-                }
-        }
+        if (intp == NULL)
+                return STV0900_INVALID_HANDLE;
 
-        return error;
+        if (intp->errs)
+                return STV0900_I2C_ERROR;
+
+        clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
+        m_div = ((clk_sel * mclk) / intp->quartz) - 1;
+        stv0900_write_bits(intp, F0900_M_DIV, m_div);
+        intp->mclk = stv0900_get_mclk_freq(intp,
+                                        intp->quartz);
+
+        /*Set the DiseqC frequency to 22KHz */
+        /*
+                Formula:
+                DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
+                DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
+        */
+        m_div = intp->mclk / 704000;
+        stv0900_write_reg(intp, R0900_P1_F22TX, m_div);
+        stv0900_write_reg(intp, R0900_P1_F22RX, m_div);
+
+        stv0900_write_reg(intp, R0900_P2_F22TX, m_div);
+        stv0900_write_reg(intp, R0900_P2_F22RX, m_div);
+
+        if ((intp->errs))
+                return STV0900_I2C_ERROR;
+
+        return STV0900_NO_ERROR;
 }
 
-u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
+static u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr,
                                         enum fe_stv0900_demod_num demod)
 {
         u32 lsb, msb, hsb, err_val;
-        s32 err1field_hsb, err1field_msb, err1field_lsb;
-        s32 err2field_hsb, err2field_msb, err2field_lsb;
-
-        dmd_reg(err1field_hsb, F0900_P1_ERR_CNT12, F0900_P2_ERR_CNT12);
-        dmd_reg(err1field_msb, F0900_P1_ERR_CNT11, F0900_P2_ERR_CNT11);
-        dmd_reg(err1field_lsb, F0900_P1_ERR_CNT10, F0900_P2_ERR_CNT10);
-
-        dmd_reg(err2field_hsb, F0900_P1_ERR_CNT22, F0900_P2_ERR_CNT22);
-        dmd_reg(err2field_msb, F0900_P1_ERR_CNT21, F0900_P2_ERR_CNT21);
-        dmd_reg(err2field_lsb, F0900_P1_ERR_CNT20, F0900_P2_ERR_CNT20);
 
         switch (cntr) {
         case 0:
         default:
-                hsb = stv0900_get_bits(i_params, err1field_hsb);
-                msb = stv0900_get_bits(i_params, err1field_msb);
-                lsb = stv0900_get_bits(i_params, err1field_lsb);
+                hsb = stv0900_get_bits(intp, ERR_CNT12);
+                msb = stv0900_get_bits(intp, ERR_CNT11);
+                lsb = stv0900_get_bits(intp, ERR_CNT10);
                 break;
         case 1:
-                hsb = stv0900_get_bits(i_params, err2field_hsb);
-                msb = stv0900_get_bits(i_params, err2field_msb);
-                lsb = stv0900_get_bits(i_params, err2field_lsb);
+                hsb = stv0900_get_bits(intp, ERR_CNT22);
+                msb = stv0900_get_bits(intp, ERR_CNT21);
+                lsb = stv0900_get_bits(intp, ERR_CNT20);
                 break;
         }
 
@@ -364,26 +361,22 @@ u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
 static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
 
-        u32 fi2c;
-
-        dmd_reg(fi2c, F0900_P1_I2CT_ON, F0900_P2_I2CT_ON);
-
-        stv0900_write_bits(i_params, fi2c, enable);
+        stv0900_write_bits(intp, I2CT_ON, enable);
 
         return 0;
 }
 
-static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
+static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp,
                                         enum fe_stv0900_clock_type path1_ts,
                                         enum fe_stv0900_clock_type path2_ts)
 {
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
-        if (i_params->chip_id >= 0x20) {
+        if (intp->chip_id >= 0x20) {
                 switch (path1_ts) {
                 case STV0900_PARALLEL_PUNCT_CLOCK:
                 case STV0900_DVBCI_CLOCK:
@@ -391,20 +384,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
                         case STV0900_SERIAL_PUNCT_CLOCK:
                         case STV0900_SERIAL_CONT_CLOCK:
                         default:
-                                stv0900_write_reg(i_params, R0900_TSGENERAL,
+                                stv0900_write_reg(intp, R0900_TSGENERAL,
                                                         0x00);
                                 break;
                         case STV0900_PARALLEL_PUNCT_CLOCK:
                         case STV0900_DVBCI_CLOCK:
-                                stv0900_write_reg(i_params, R0900_TSGENERAL,
+                                stv0900_write_reg(intp, R0900_TSGENERAL,
                                                         0x06);
-                                stv0900_write_bits(i_params,
+                                stv0900_write_bits(intp,
                                                 F0900_P1_TSFIFO_MANSPEED, 3);
-                                stv0900_write_bits(i_params,
+                                stv0900_write_bits(intp,
                                                 F0900_P2_TSFIFO_MANSPEED, 0);
-                                stv0900_write_reg(i_params,
+                                stv0900_write_reg(intp,
                                                 R0900_P1_TSSPEED, 0x14);
-                                stv0900_write_reg(i_params,
+                                stv0900_write_reg(intp,
                                                 R0900_P2_TSSPEED, 0x28);
                                 break;
                         }
@@ -416,14 +409,14 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
                         case STV0900_SERIAL_PUNCT_CLOCK:
                         case STV0900_SERIAL_CONT_CLOCK:
                         default:
-                                stv0900_write_reg(i_params,
+                                stv0900_write_reg(intp,
                                                 R0900_TSGENERAL, 0x0C);
                                 break;
                         case STV0900_PARALLEL_PUNCT_CLOCK:
                         case STV0900_DVBCI_CLOCK:
-                                stv0900_write_reg(i_params,
+                                stv0900_write_reg(intp,
                                                 R0900_TSGENERAL, 0x0A);
-                                dprintk(KERN_INFO "%s: 0x0a\n", __func__);
+                                dprintk("%s: 0x0a\n", __func__);
                                 break;
                         }
                         break;
@@ -436,20 +429,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
                         case STV0900_SERIAL_PUNCT_CLOCK:
                         case STV0900_SERIAL_CONT_CLOCK:
                         default:
-                                stv0900_write_reg(i_params, R0900_TSGENERAL1X,
+                                stv0900_write_reg(intp, R0900_TSGENERAL1X,
                                                         0x10);
                                 break;
                         case STV0900_PARALLEL_PUNCT_CLOCK:
                         case STV0900_DVBCI_CLOCK:
-                                stv0900_write_reg(i_params, R0900_TSGENERAL1X,
+                                stv0900_write_reg(intp, R0900_TSGENERAL1X,
                                                         0x16);
-                                stv0900_write_bits(i_params,
+                                stv0900_write_bits(intp,
                                                 F0900_P1_TSFIFO_MANSPEED, 3);
-                                stv0900_write_bits(i_params,
+                                stv0900_write_bits(intp,
                                                 F0900_P2_TSFIFO_MANSPEED, 0);
-                                stv0900_write_reg(i_params, R0900_P1_TSSPEED,
+                                stv0900_write_reg(intp, R0900_P1_TSSPEED,
                                                         0x14);
-                                stv0900_write_reg(i_params, R0900_P2_TSSPEED,
+                                stv0900_write_reg(intp, R0900_P2_TSSPEED,
                                                         0x28);
                                 break;
                         }
@@ -462,14 +455,14 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
                         case STV0900_SERIAL_PUNCT_CLOCK:
                         case STV0900_SERIAL_CONT_CLOCK:
                         default:
-                                stv0900_write_reg(i_params, R0900_TSGENERAL1X,
+                                stv0900_write_reg(intp, R0900_TSGENERAL1X,
                                                         0x14);
                                 break;
                         case STV0900_PARALLEL_PUNCT_CLOCK:
                         case STV0900_DVBCI_CLOCK:
-                                stv0900_write_reg(i_params, R0900_TSGENERAL1X,
+                                stv0900_write_reg(intp, R0900_TSGENERAL1X,
                                                         0x12);
-                                dprintk(KERN_INFO "%s: 0x12\n", __func__);
+                                dprintk("%s: 0x12\n", __func__);
                                 break;
                         }
 
@@ -479,20 +472,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
 
         switch (path1_ts) {
         case STV0900_PARALLEL_PUNCT_CLOCK:
-                stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
-                stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
+                stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
+                stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
                 break;
         case STV0900_DVBCI_CLOCK:
-                stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
-                stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
+                stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
+                stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
                 break;
         case STV0900_SERIAL_PUNCT_CLOCK:
-                stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
-                stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
+                stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
+                stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
                 break;
         case STV0900_SERIAL_CONT_CLOCK:
-                stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
-                stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
+                stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
+                stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
                 break;
         default:
                 break;
@@ -500,29 +493,29 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
 
         switch (path2_ts) {
         case STV0900_PARALLEL_PUNCT_CLOCK:
-                stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
-                stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
+                stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
+                stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
                 break;
         case STV0900_DVBCI_CLOCK:
-                stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
-                stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
+                stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
+                stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
                 break;
         case STV0900_SERIAL_PUNCT_CLOCK:
-                stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
-                stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
+                stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
+                stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
                 break;
         case STV0900_SERIAL_CONT_CLOCK:
-                stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
-                stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
+                stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
+                stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
                 break;
         default:
                 break;
         }
 
-        stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1);
-        stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 0);
-        stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1);
-        stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 0);
+        stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
+        stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
+        stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
+        stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
 }
 
 void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
@@ -574,7 +567,47 @@ void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
         }
 }
 
-static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
+u32 stv0900_get_freq_auto(struct stv0900_internal *intp, int demod)
+{
+        u32 freq, round;
+        /*      Formulat :
+        Tuner_Frequency(MHz)    = Regs / 64
+        Tuner_granularity(MHz)  = Regs / 2048
+        real_Tuner_Frequency    = Tuner_Frequency(MHz) - Tuner_granularity(MHz)
+        */
+        freq = (stv0900_get_bits(intp, TUN_RFFREQ2) << 10) +
+                (stv0900_get_bits(intp, TUN_RFFREQ1) << 2) +
+                stv0900_get_bits(intp, TUN_RFFREQ0);
+
+        freq = (freq * 1000) / 64;
+
+        round = (stv0900_get_bits(intp, TUN_RFRESTE1) >> 2) +
+                stv0900_get_bits(intp, TUN_RFRESTE0);
+
+        round = (round * 1000) / 2048;
+
+        return freq + round;
+}
+
+void stv0900_set_tuner_auto(struct stv0900_internal *intp, u32 Frequency,
+                                                u32 Bandwidth, int demod)
+{
+        u32 tunerFrequency;
+        /* Formulat:
+        Tuner_frequency_reg= Frequency(MHz)*64
+        */
+        tunerFrequency = (Frequency * 64) / 1000;
+
+        stv0900_write_bits(intp, TUN_RFFREQ2, (tunerFrequency >> 10));
+        stv0900_write_bits(intp, TUN_RFFREQ1, (tunerFrequency >> 2) & 0xff);
+        stv0900_write_bits(intp, TUN_RFFREQ0, (tunerFrequency & 0x03));
+        /* Low Pass Filter = BW /2 (MHz)*/
+        stv0900_write_bits(intp, TUN_BW, Bandwidth / 2000000);
+        /* Tuner Write trig */
+        stv0900_write_reg(intp, TNRLD, 1);
+}
+
+static s32 stv0900_get_rf_level(struct stv0900_internal *intp,
                                 const struct stv0900_table *lookup,
                                 enum fe_stv0900_demod_num demod)
 {
@@ -584,45 +617,41 @@ static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
                 i,
                 rf_lvl = 0;
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
-        if ((lookup != NULL) && lookup->size) {
-                switch (demod) {
-                case STV0900_DEMOD_1:
-                default:
-                        agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE1),
-                                                stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE0));
-                        break;
-                case STV0900_DEMOD_2:
-                        agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE1),
-                                                stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE0));
-                        break;
-                }
+        if ((lookup == NULL) || (lookup->size <= 0))
+                return 0;
 
-                imin = 0;
-                imax = lookup->size - 1;
-                if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[imax].regval)) {
-                        while ((imax - imin) > 1) {
-                                i = (imax + imin) >> 1;
+        agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
+                                stv0900_get_bits(intp, AGCIQ_VALUE0));
 
-                                if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[i].regval))
-                                        imax = i;
-                                else
-                                        imin = i;
-                        }
+        imin = 0;
+        imax = lookup->size - 1;
+        if (INRANGE(lookup->table[imin].regval, agc_gain,
+                                        lookup->table[imax].regval)) {
+                while ((imax - imin) > 1) {
+                        i = (imax + imin) >> 1;
 
-                        rf_lvl = (((s32)agc_gain - lookup->table[imin].regval)
-                                        * (lookup->table[imax].realval - lookup->table[imin].realval)
-                                        / (lookup->table[imax].regval - lookup->table[imin].regval))
-                                        + lookup->table[imin].realval;
-                } else if (agc_gain > lookup->table[0].regval)
-                        rf_lvl = 5;
-                else if (agc_gain < lookup->table[lookup->size-1].regval)
-                        rf_lvl = -100;
+                        if (INRANGE(lookup->table[imin].regval,
+                                        agc_gain,
+                                        lookup->table[i].regval))
+                                imax = i;
+                        else
+                                imin = i;
+                }
 
-        }
+                rf_lvl = (s32)agc_gain - lookup->table[imin].regval;
+                rf_lvl *= (lookup->table[imax].realval -
+                                lookup->table[imin].realval);
+                rf_lvl /= (lookup->table[imax].regval -
+                                lookup->table[imin].regval);
+                rf_lvl += lookup->table[imin].realval;
+        } else if (agc_gain > lookup->table[0].regval)
+                rf_lvl = 5;
+        else if (agc_gain < lookup->table[lookup->size-1].regval)
+                rf_lvl = -100;
 
-        dprintk(KERN_INFO "%s: RFLevel = %d\n", __func__, rf_lvl);
+        dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
 
         return rf_lvl;
 }
@@ -634,50 +663,51 @@ static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
         s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
                                                                 state->demod);
 
-        *strength = (rflevel + 100) * (16383 / 105);
+        rflevel = (rflevel + 100) * (65535 / 70);
+        if (rflevel < 0)
+                rflevel = 0;
+
+        if (rflevel > 65535)
+                rflevel = 65535;
+
+        *strength = rflevel;
 
         return 0;
 }
 
-
 static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
                                         const struct stv0900_table *lookup)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
 
-        s32 c_n = -100,
-                regval, imin, imax,
+        s32     c_n = -100,
+                regval,
+                imin,
+                imax,
                 i,
-                lock_flag_field,
                 noise_field1,
                 noise_field0;
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
-        dmd_reg(lock_flag_field, F0900_P1_LOCK_DEFINITIF,
-                                        F0900_P2_LOCK_DEFINITIF);
         if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
-                dmd_reg(noise_field1, F0900_P1_NOSPLHT_NORMED1,
-                                        F0900_P2_NOSPLHT_NORMED1);
-                dmd_reg(noise_field0, F0900_P1_NOSPLHT_NORMED0,
-                                        F0900_P2_NOSPLHT_NORMED0);
+                noise_field1 = NOSPLHT_NORMED1;
+                noise_field0 = NOSPLHT_NORMED0;
         } else {
-                dmd_reg(noise_field1, F0900_P1_NOSDATAT_NORMED1,
-                                        F0900_P2_NOSDATAT_NORMED1);
-                dmd_reg(noise_field0, F0900_P1_NOSDATAT_NORMED0,
-                                        F0900_P2_NOSDATAT_NORMED0);
+                noise_field1 = NOSDATAT_NORMED1;
+                noise_field0 = NOSDATAT_NORMED0;
         }
 
-        if (stv0900_get_bits(i_params, lock_flag_field)) {
+        if (stv0900_get_bits(intp, LOCK_DEFINITIF)) {
                 if ((lookup != NULL) && lookup->size) {
                         regval = 0;
                         msleep(5);
                         for (i = 0; i < 16; i++) {
-                                regval += MAKEWORD(stv0900_get_bits(i_params,
+                                regval += MAKEWORD(stv0900_get_bits(intp,
                                                                 noise_field1),
-                                                stv0900_get_bits(i_params,
+                                                stv0900_get_bits(intp,
                                                                 noise_field0));
                                 msleep(1);
                         }
@@ -715,10 +745,9 @@ static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
 static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
         u8 err_val1, err_val0;
-        s32 err_field1, err_field0;
         u32 header_err_val = 0;
 
         *ucblocks = 0x0;
@@ -726,24 +755,14 @@ static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
                 /* DVB-S2 delineator errors count */
 
                 /* retreiving number for errnous headers */
-                dmd_reg(err_field0, R0900_P1_BBFCRCKO0,
-                                        R0900_P2_BBFCRCKO0);
-                dmd_reg(err_field1, R0900_P1_BBFCRCKO1,
-                                        R0900_P2_BBFCRCKO1);
-
-                err_val1 = stv0900_read_reg(i_params, err_field1);
-                err_val0 = stv0900_read_reg(i_params, err_field0);
-                header_err_val = (err_val1<<8) | err_val0;
+                err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
+                err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
+                header_err_val = (err_val1 << 8) | err_val0;
 
                 /* retreiving number for errnous packets */
-                dmd_reg(err_field0, R0900_P1_UPCRCKO0,
-                                        R0900_P2_UPCRCKO0);
-                dmd_reg(err_field1, R0900_P1_UPCRCKO1,
-                                        R0900_P2_UPCRCKO1);
-
-                err_val1 = stv0900_read_reg(i_params, err_field1);
-                err_val0 = stv0900_read_reg(i_params, err_field0);
-                *ucblocks = (err_val1<<8) | err_val0;
+                err_val1 = stv0900_read_reg(intp, UPCRCKO1);
+                err_val0 = stv0900_read_reg(intp, UPCRCKO0);
+                *ucblocks = (err_val1 << 8) | err_val0;
                 *ucblocks += header_err_val;
         }
 
@@ -752,33 +771,27 @@ static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
 
 static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
 {
-        *snr = stv0900_carr_get_quality(fe,
+        s32 snrlcl = stv0900_carr_get_quality(fe,
                         (const struct stv0900_table *)&stv0900_s2_cn);
-        *snr += 30;
-        *snr *= (16383 / 1030);
+        snrlcl = (snrlcl + 30) * 384;
+        if (snrlcl < 0)
+                snrlcl = 0;
+
+        if (snrlcl > 65535)
+                snrlcl = 65535;
+
+        *snr = snrlcl;
 
         return 0;
 }
 
-static u32 stv0900_get_ber(struct stv0900_internal *i_params,
+static u32 stv0900_get_ber(struct stv0900_internal *intp,
                                 enum fe_stv0900_demod_num demod)
 {
         u32 ber = 10000000, i;
-        s32 dmd_state_reg;
         s32 demod_state;
-        s32 vstatus_reg;
-        s32 prvit_field;
-        s32 pdel_status_reg;
-        s32 pdel_lock_field;
 
-        dmd_reg(dmd_state_reg, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
-        dmd_reg(vstatus_reg, R0900_P1_VSTATUSVIT, R0900_P2_VSTATUSVIT);
-        dmd_reg(prvit_field, F0900_P1_PRFVIT, F0900_P2_PRFVIT);
-        dmd_reg(pdel_status_reg, R0900_P1_PDELSTATUS1, R0900_P2_PDELSTATUS1);
-        dmd_reg(pdel_lock_field, F0900_P1_PKTDELIN_LOCK,
-                                F0900_P2_PKTDELIN_LOCK);
-
-        demod_state = stv0900_get_bits(i_params, dmd_state_reg);
+        demod_state = stv0900_get_bits(intp, HEADER_MODE);
 
         switch (demod_state) {
         case STV0900_SEARCH:
@@ -790,11 +803,11 @@ static u32 stv0900_get_ber(struct stv0900_internal *i_params,
                 ber = 0;
                 for (i = 0; i < 5; i++) {
                         msleep(5);
-                        ber += stv0900_get_err_count(i_params, 0, demod);
+                        ber += stv0900_get_err_count(intp, 0, demod);
                 }
 
                 ber /= 5;
-                if (stv0900_get_bits(i_params, prvit_field)) {
+                if (stv0900_get_bits(intp, PRFVIT)) {
                         ber *= 9766;
                         ber = ber >> 13;
                 }
@@ -804,11 +817,11 @@ static u32 stv0900_get_ber(struct stv0900_internal *i_params,
                 ber = 0;
                 for (i = 0; i < 5; i++) {
                         msleep(5);
-                        ber += stv0900_get_err_count(i_params, 0, demod);
+                        ber += stv0900_get_err_count(intp, 0, demod);
                 }
 
                 ber /= 5;
-                if (stv0900_get_bits(i_params, pdel_lock_field)) {
+                if (stv0900_get_bits(intp, PKTDELIN_LOCK)) {
                         ber *= 9766;
                         ber = ber >> 13;
                 }
@@ -829,20 +842,16 @@ static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
         return 0;
 }
 
-int stv0900_get_demod_lock(struct stv0900_internal *i_params,
+int stv0900_get_demod_lock(struct stv0900_internal *intp,
                         enum fe_stv0900_demod_num demod, s32 time_out)
 {
         s32 timer = 0,
-                lock = 0,
-                header_field,
-                lock_field;
+                lock = 0;
 
         enum fe_stv0900_search_state    dmd_state;
 
-        dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
-        dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
         while ((timer < time_out) && (lock == 0)) {
-                dmd_state = stv0900_get_bits(i_params, header_field);
+                dmd_state = stv0900_get_bits(intp, HEADER_MODE);
                 dprintk("Demod State = %d\n", dmd_state);
                 switch (dmd_state) {
                 case STV0900_SEARCH:
@@ -852,7 +861,7 @@ int stv0900_get_demod_lock(struct stv0900_internal *i_params,
                         break;
                 case STV0900_DVBS2_FOUND:
                 case STV0900_DVBS_FOUND:
-                        lock = stv0900_get_bits(i_params, lock_field);
+                        lock = stv0900_get_bits(intp, LOCK_DEFINITIF);
                         break;
                 }
 
@@ -870,56 +879,40 @@ int stv0900_get_demod_lock(struct stv0900_internal *i_params,
         return lock;
 }
 
-void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
+void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp,
                                 enum fe_stv0900_demod_num demod)
 {
         s32 regflist,
         i;
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
-        dmd_reg(regflist, R0900_P1_MODCODLST0, R0900_P2_MODCODLST0);
+        regflist = MODCODLST0;
 
         for (i = 0; i < 16; i++)
-                stv0900_write_reg(i_params, regflist + i, 0xff);
+                stv0900_write_reg(intp, regflist + i, 0xff);
 }
 
-void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
+void stv0900_activate_s2_modcod(struct stv0900_internal *intp,
                                 enum fe_stv0900_demod_num demod)
 {
         u32 matype,
-        mod_code,
-        fmod,
-        reg_index,
-        field_index;
+                mod_code,
+                fmod,
+                reg_index,
+                field_index;
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
-        if (i_params->chip_id <= 0x11) {
+        if (intp->chip_id <= 0x11) {
                 msleep(5);
 
-                switch (demod) {
-                case STV0900_DEMOD_1:
-                default:
-                        mod_code = stv0900_read_reg(i_params,
-                                                        R0900_P1_PLHMODCOD);
-                        matype = mod_code & 0x3;
-                        mod_code = (mod_code & 0x7f) >> 2;
-
-                        reg_index = R0900_P1_MODCODLSTF - mod_code / 2;
-                        field_index = mod_code % 2;
-                        break;
-                case STV0900_DEMOD_2:
-                        mod_code = stv0900_read_reg(i_params,
-                                                        R0900_P2_PLHMODCOD);
-                        matype = mod_code & 0x3;
-                        mod_code = (mod_code & 0x7f) >> 2;
-
-                        reg_index = R0900_P2_MODCODLSTF - mod_code / 2;
-                        field_index = mod_code % 2;
-                        break;
-                }
+                mod_code = stv0900_read_reg(intp, PLHMODCOD);
+                matype = mod_code & 0x3;
+                mod_code = (mod_code & 0x7f) >> 2;
 
+                reg_index = MODCODLSTF - mod_code / 2;
+                field_index = mod_code % 2;
 
                 switch (matype) {
                 case 0:
@@ -938,70 +931,41 @@ void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
                 }
 
                 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
-                                                        && (matype <= 1)) {
+                                                && (matype <= 1)) {
                         if (field_index == 0)
-                                stv0900_write_reg(i_params, reg_index,
+                                stv0900_write_reg(intp, reg_index,
                                                         0xf0 | fmod);
                         else
-                                stv0900_write_reg(i_params, reg_index,
+                                stv0900_write_reg(intp, reg_index,
                                                         (fmod << 4) | 0xf);
                 }
-        } else if (i_params->chip_id >= 0x12) {
-                switch (demod) {
-                case STV0900_DEMOD_1:
-                default:
-                        for (reg_index = 0; reg_index < 7; reg_index++)
-                                stv0900_write_reg(i_params, R0900_P1_MODCODLST0 + reg_index, 0xff);
 
-                        stv0900_write_reg(i_params, R0900_P1_MODCODLSTE, 0xff);
-                        stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0xcf);
-                        for (reg_index = 0; reg_index < 8; reg_index++)
-                                stv0900_write_reg(i_params, R0900_P1_MODCODLST7 + reg_index, 0xcc);
+        } else if (intp->chip_id >= 0x12) {
+                for (reg_index = 0; reg_index < 7; reg_index++)
+                        stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff);
 
-                        break;
-                case STV0900_DEMOD_2:
-                        for (reg_index = 0; reg_index < 7; reg_index++)
-                                stv0900_write_reg(i_params, R0900_P2_MODCODLST0 + reg_index, 0xff);
+                stv0900_write_reg(intp, MODCODLSTE, 0xff);
+                stv0900_write_reg(intp, MODCODLSTF, 0xcf);
+                for (reg_index = 0; reg_index < 8; reg_index++)
+                        stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc);
 
-                        stv0900_write_reg(i_params, R0900_P2_MODCODLSTE, 0xff);
-                        stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0xcf);
-                        for (reg_index = 0; reg_index < 8; reg_index++)
-                                stv0900_write_reg(i_params, R0900_P2_MODCODLST7 + reg_index, 0xcc);
-
-                        break;
-                }
 
         }
 }
 
-void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params,
+void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp,
                                         enum fe_stv0900_demod_num demod)
 {
         u32 reg_index;
 
-        dprintk(KERN_INFO "%s\n", __func__);
-
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                stv0900_write_reg(i_params, R0900_P1_MODCODLST0, 0xff);
-                stv0900_write_reg(i_params, R0900_P1_MODCODLST1, 0xf0);
-                stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0x0f);
-                for (reg_index = 0; reg_index < 13; reg_index++)
-                        stv0900_write_reg(i_params,
-                                        R0900_P1_MODCODLST2 + reg_index, 0);
+        dprintk("%s\n", __func__);
 
-                break;
-        case STV0900_DEMOD_2:
-                stv0900_write_reg(i_params, R0900_P2_MODCODLST0, 0xff);
-                stv0900_write_reg(i_params, R0900_P2_MODCODLST1, 0xf0);
-                stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0x0f);
-                for (reg_index = 0; reg_index < 13; reg_index++)
-                        stv0900_write_reg(i_params,
-                                        R0900_P2_MODCODLST2 + reg_index, 0);
+        stv0900_write_reg(intp, MODCODLST0, 0xff);
+        stv0900_write_reg(intp, MODCODLST1, 0xf0);
+        stv0900_write_reg(intp, MODCODLSTF, 0x0f);
+        for (reg_index = 0; reg_index < 13; reg_index++)
+                stv0900_write_reg(intp, MODCODLST2 + reg_index, 0);
 
-                break;
-        }
 }
 
 static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
@@ -1012,7 +976,7 @@ static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
 static int stb0900_set_property(struct dvb_frontend *fe,
                                 struct dtv_property *tvp)
 {
-        dprintk(KERN_INFO "%s(..)\n", __func__);
+        dprintk("%s(..)\n", __func__);
 
         return 0;
 }
@@ -1020,166 +984,123 @@ static int stb0900_set_property(struct dvb_frontend *fe,
 static int stb0900_get_property(struct dvb_frontend *fe,
                                 struct dtv_property *tvp)
 {
-        dprintk(KERN_INFO "%s(..)\n", __func__);
+        dprintk("%s(..)\n", __func__);
 
         return 0;
 }
 
-void stv0900_start_search(struct stv0900_internal *i_params,
+void stv0900_start_search(struct stv0900_internal *intp,
                                 enum fe_stv0900_demod_num demod)
 {
-
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1f);
-
-                if (i_params->chip_id == 0x10)
-                        stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xaa);
-
-                if (i_params->chip_id < 0x20)
-                        stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
-
-                if (i_params->dmd1_symbol_rate <= 5000000) {
-                        stv0900_write_reg(i_params, R0900_P1_CARCFG, 0x44);
-                        stv0900_write_reg(i_params, R0900_P1_CFRUP1, 0x0f);
-                        stv0900_write_reg(i_params, R0900_P1_CFRUP0, 0xff);
-                        stv0900_write_reg(i_params, R0900_P1_CFRLOW1, 0xf0);
-                        stv0900_write_reg(i_params, R0900_P1_CFRLOW0, 0x00);
-                        stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
+        u32 freq;
+        s16 freq_s16 ;
+
+        stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
+        if (intp->chip_id == 0x10)
+                stv0900_write_reg(intp, CORRELEXP, 0xaa);
+
+        if (intp->chip_id < 0x20)
+                stv0900_write_reg(intp, CARHDR, 0x55);
+
+        if (intp->chip_id <= 0x20) {
+                if (intp->symbol_rate[0] <= 5000000) {
+                        stv0900_write_reg(intp, CARCFG, 0x44);
+                        stv0900_write_reg(intp, CFRUP1, 0x0f);
+                        stv0900_write_reg(intp, CFRUP0, 0xff);
+                        stv0900_write_reg(intp, CFRLOW1, 0xf0);
+                        stv0900_write_reg(intp, CFRLOW0, 0x00);
+                        stv0900_write_reg(intp, RTCS2, 0x68);
                 } else {
-                        stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xc4);
-                        stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
+                        stv0900_write_reg(intp, CARCFG, 0xc4);
+                        stv0900_write_reg(intp, RTCS2, 0x44);
                 }
 
-                stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
-                stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
-
-                if (i_params->chip_id >= 0x20) {
-                        stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
-                        stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
-
-                        if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
-                                stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
-                                stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
-                        }
-                }
-
-                stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
-                stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xe0);
-                stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xc0);
-                stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
-                stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
-                stv0900_write_bits(i_params, F0900_P1_S1S2_SEQUENTIAL, 0);
-                stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
-                if (i_params->chip_id >= 0x20) {
-                        if (i_params->dmd1_symbol_rate < 2000000) {
-                                stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x39);
-                                stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x40);
-                        }
-
-                        if (i_params->dmd1_symbol_rate < 10000000) {
-                                stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4c);
-                                stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
-                        } else {
-                                stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4b);
-                                stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
-                        }
+        } else { /*cut 3.0 above*/
+                if (intp->symbol_rate[demod] <= 5000000)
+                        stv0900_write_reg(intp, RTCS2, 0x68);
+                else
+                        stv0900_write_reg(intp, RTCS2, 0x44);
 
+                stv0900_write_reg(intp, CARCFG, 0x46);
+                if (intp->srch_algo[demod] == STV0900_WARM_START) {
+                        freq = 1000 << 16;
+                        freq /= (intp->mclk / 1000);
+                        freq_s16 = (s16)freq;
                 } else {
-                        if (i_params->dmd1_symbol_rate < 10000000)
-                                stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xef);
+                        freq = (intp->srch_range[demod] / 2000);
+                        if (intp->symbol_rate[demod] <= 5000000)
+                                freq += 80;
                         else
-                                stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
-                }
+                                freq += 600;
 
-                switch (i_params->dmd1_srch_algo) {
-                case STV0900_WARM_START:
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
-                        break;
-                case STV0900_COLD_START:
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
-                        break;
-                default:
-                        break;
+                        freq = freq << 16;
+                        freq /= (intp->mclk / 1000);
+                        freq_s16 = (s16)freq;
                 }
 
-                break;
-        case STV0900_DEMOD_2:
-                stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1f);
-                if (i_params->chip_id == 0x10)
-                        stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xaa);
-
-                if (i_params->chip_id < 0x20)
-                        stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
-
-                if (i_params->dmd2_symbol_rate <= 5000000) {
-                        stv0900_write_reg(i_params, R0900_P2_CARCFG, 0x44);
-                        stv0900_write_reg(i_params, R0900_P2_CFRUP1, 0x0f);
-                        stv0900_write_reg(i_params, R0900_P2_CFRUP0, 0xff);
-                        stv0900_write_reg(i_params, R0900_P2_CFRLOW1, 0xf0);
-                        stv0900_write_reg(i_params, R0900_P2_CFRLOW0, 0x00);
-                        stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
-                } else {
-                        stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xc4);
-                        stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
-                }
+                stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16));
+                stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16));
+                freq_s16 *= (-1);
+                stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16));
+                stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16));
+        }
 
-                stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0);
-                stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0);
+        stv0900_write_reg(intp, CFRINIT1, 0);
+        stv0900_write_reg(intp, CFRINIT0, 0);
 
-                if (i_params->chip_id >= 0x20) {
-                        stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41);
-                        stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
-                        if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
-                                stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
-                                stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
-                        }
-                }
+        if (intp->chip_id >= 0x20) {
+                stv0900_write_reg(intp, EQUALCFG, 0x41);
+                stv0900_write_reg(intp, FFECFG, 0x41);
 
-                stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00);
-                stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xe0);
-                stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xc0);
-                stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
-                stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
-                stv0900_write_bits(i_params, F0900_P2_S1S2_SEQUENTIAL, 0);
-                stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
-                if (i_params->chip_id >= 0x20) {
-                        if (i_params->dmd2_symbol_rate < 2000000) {
-                                stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x39);
-                                stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x40);
-                        }
-
-                        if (i_params->dmd2_symbol_rate < 10000000) {
-                                stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4c);
-                                stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
-                        } else {
-                                stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4b);
-                                stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
-                        }
+                if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
+                        (intp->srch_standard[demod] == STV0900_SEARCH_DSS) ||
+                        (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) {
+                        stv0900_write_reg(intp, VITSCALE,
+                                                                0x82);
+                        stv0900_write_reg(intp, VAVSRVIT, 0x0);
+                }
+        }
 
+        stv0900_write_reg(intp, SFRSTEP, 0x00);
+        stv0900_write_reg(intp, TMGTHRISE, 0xe0);
+        stv0900_write_reg(intp, TMGTHFALL, 0xc0);
+        stv0900_write_bits(intp, SCAN_ENABLE, 0);
+        stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
+        stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0);
+        stv0900_write_reg(intp, RTC, 0x88);
+        if (intp->chip_id >= 0x20) {
+                if (intp->symbol_rate[demod] < 2000000) {
+                        if (intp->chip_id <= 0x20)
+                                stv0900_write_reg(intp, CARFREQ, 0x39);
+                        else  /*cut 3.0*/
+                                stv0900_write_reg(intp, CARFREQ, 0x89);
+
+                        stv0900_write_reg(intp, CARHDR, 0x40);
+                } else if (intp->symbol_rate[demod] < 10000000) {
+                        stv0900_write_reg(intp, CARFREQ, 0x4c);
+                        stv0900_write_reg(intp, CARHDR, 0x20);
                 } else {
-                        if (i_params->dmd2_symbol_rate < 10000000)
-                                stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xef);
-                        else
-                                stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
+                        stv0900_write_reg(intp, CARFREQ, 0x4b);
+                        stv0900_write_reg(intp, CARHDR, 0x20);
                 }
 
-                switch (i_params->dmd2_srch_algo) {
-                case STV0900_WARM_START:
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
-                        break;
-                case STV0900_COLD_START:
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
-                        break;
-                default:
-                        break;
-                }
+        } else {
+                if (intp->symbol_rate[demod] < 10000000)
+                        stv0900_write_reg(intp, CARFREQ, 0xef);
+                else
+                        stv0900_write_reg(intp, CARFREQ, 0xed);
+        }
 
+        switch (intp->srch_algo[demod]) {
+        case STV0900_WARM_START:
+                stv0900_write_reg(intp, DMDISTATE, 0x1f);
+                stv0900_write_reg(intp, DMDISTATE, 0x18);
+                break;
+        case STV0900_COLD_START:
+                stv0900_write_reg(intp, DMDISTATE, 0x1f);
+                stv0900_write_reg(intp, DMDISTATE, 0x15);
+                break;
+        default:
                 break;
         }
 }
@@ -1188,33 +1109,40 @@ u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
                                                         s32 pilot, u8 chip_id)
 {
         u8 aclc_value = 0x29;
-        s32     i;
-        const struct stv0900_car_loop_optim *car_loop_s2;
-
-        dprintk(KERN_INFO "%s\n", __func__);
-
-        if (chip_id <= 0x12)
-                car_loop_s2 = FE_STV0900_S2CarLoop;
-        else if (chip_id == 0x20)
-                car_loop_s2 = FE_STV0900_S2CarLoopCut20;
-        else
-                car_loop_s2 = FE_STV0900_S2CarLoop;
+        s32 i;
+        const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2;
+
+        dprintk("%s\n", __func__);
+
+        if (chip_id <= 0x12) {
+                cls2 = FE_STV0900_S2CarLoop;
+                cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
+                cllas2 = FE_STV0900_S2APSKCarLoopCut30;
+        } else if (chip_id == 0x20) {
+                cls2 = FE_STV0900_S2CarLoopCut20;
+                cllqs2 = FE_STV0900_S2LowQPCarLoopCut20;
+                cllas2 = FE_STV0900_S2APSKCarLoopCut20;
+        } else {
+                cls2 = FE_STV0900_S2CarLoopCut30;
+                cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
+                cllas2 = FE_STV0900_S2APSKCarLoopCut30;
+        }
 
         if (modcode < STV0900_QPSK_12) {
                 i = 0;
-                while ((i < 3) && (modcode != FE_STV0900_S2LowQPCarLoopCut20[i].modcode))
+                while ((i < 3) && (modcode != cllqs2[i].modcode))
                         i++;
 
                 if (i >= 3)
                         i = 2;
         } else {
                 i = 0;
-                while ((i < 14) && (modcode != car_loop_s2[i].modcode))
+                while ((i < 14) && (modcode != cls2[i].modcode))
                         i++;
 
                 if (i >= 14) {
                         i = 0;
-                        while ((i < 11) && (modcode != FE_STV0900_S2APSKCarLoopCut20[i].modcode))
+                        while ((i < 11) && (modcode != cllas2[i].modcode))
                                 i++;
 
                         if (i >= 11)
@@ -1225,76 +1153,82 @@ u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
         if (modcode <= STV0900_QPSK_25) {
                 if (pilot) {
                         if (srate <= 3000000)
-                                aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_2;
+                                aclc_value = cllqs2[i].car_loop_pilots_on_2;
                         else if (srate <= 7000000)
-                                aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_5;
+                                aclc_value = cllqs2[i].car_loop_pilots_on_5;
                         else if (srate <= 15000000)
-                                aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_10;
+                                aclc_value = cllqs2[i].car_loop_pilots_on_10;
                         else if (srate <= 25000000)
-                                aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_20;
+                                aclc_value = cllqs2[i].car_loop_pilots_on_20;
                         else
-                                aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_30;
+                                aclc_value = cllqs2[i].car_loop_pilots_on_30;
                 } else {
                         if (srate <= 3000000)
-                                aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_2;
+                                aclc_value = cllqs2[i].car_loop_pilots_off_2;
                         else if (srate <= 7000000)
-                                aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_5;
+                                aclc_value = cllqs2[i].car_loop_pilots_off_5;
                         else if (srate <= 15000000)
-                                aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_10;
+                                aclc_value = cllqs2[i].car_loop_pilots_off_10;
                         else if (srate <= 25000000)
-                                aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_20;
+                                aclc_value = cllqs2[i].car_loop_pilots_off_20;
                         else
-                                aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_30;
+                                aclc_value = cllqs2[i].car_loop_pilots_off_30;
                 }
 
         } else if (modcode <= STV0900_8PSK_910) {
                 if (pilot) {
                         if (srate <= 3000000)
-                                aclc_value = car_loop_s2[i].car_loop_pilots_on_2;
+                                aclc_value = cls2[i].car_loop_pilots_on_2;
                         else if (srate <= 7000000)
-                                aclc_value = car_loop_s2[i].car_loop_pilots_on_5;
+                                aclc_value = cls2[i].car_loop_pilots_on_5;
                         else if (srate <= 15000000)
-                                aclc_value = car_loop_s2[i].car_loop_pilots_on_10;
+                                aclc_value = cls2[i].car_loop_pilots_on_10;
                         else if (srate <= 25000000)
-                                aclc_value = car_loop_s2[i].car_loop_pilots_on_20;
+                                aclc_value = cls2[i].car_loop_pilots_on_20;
                         else
-                                aclc_value = car_loop_s2[i].car_loop_pilots_on_30;
+                                aclc_value = cls2[i].car_loop_pilots_on_30;
                 } else {
                         if (srate <= 3000000)
-                                aclc_value = car_loop_s2[i].car_loop_pilots_off_2;
+                                aclc_value = cls2[i].car_loop_pilots_off_2;
                         else if (srate <= 7000000)
-                                aclc_value = car_loop_s2[i].car_loop_pilots_off_5;
+                                aclc_value = cls2[i].car_loop_pilots_off_5;
                         else if (srate <= 15000000)
-                                aclc_value = car_loop_s2[i].car_loop_pilots_off_10;
+                                aclc_value = cls2[i].car_loop_pilots_off_10;
                         else if (srate <= 25000000)
-                                aclc_value = car_loop_s2[i].car_loop_pilots_off_20;
+                                aclc_value = cls2[i].car_loop_pilots_off_20;
                         else
-                                aclc_value = car_loop_s2[i].car_loop_pilots_off_30;
+                                aclc_value = cls2[i].car_loop_pilots_off_30;
                 }
 
         } else {
                 if (srate <= 3000000)
-                        aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_2;
+                        aclc_value = cllas2[i].car_loop_pilots_on_2;
                 else if (srate <= 7000000)
-                        aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_5;
+                        aclc_value = cllas2[i].car_loop_pilots_on_5;
                 else if (srate <= 15000000)
-                        aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_10;
+                        aclc_value = cllas2[i].car_loop_pilots_on_10;
                 else if (srate <= 25000000)
-                        aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_20;
+                        aclc_value = cllas2[i].car_loop_pilots_on_20;
                 else
-                        aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_30;
+                        aclc_value = cllas2[i].car_loop_pilots_on_30;
         }
 
         return aclc_value;
 }
 
-u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modulation, u8 chip_id)
+u8 stv0900_get_optim_short_carr_loop(s32 srate,
+                                enum fe_stv0900_modulation modulation,
+                                u8 chip_id)
 {
+        const struct stv0900_short_frames_car_loop_optim *s2scl;
+        const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30;
         s32 mod_index = 0;
-
         u8 aclc_value = 0x0b;
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
+
+        s2scl = FE_STV0900_S2ShortCarLoop;
+        s2sclc30 = FE_STV0900_S2ShortCarLoopCut30;
 
         switch (modulation) {
         case STV0900_QPSK:
@@ -1312,75 +1246,116 @@ u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modul
                 break;
         }
 
-        switch (chip_id) {
-        case 0x20:
+        if (chip_id >= 0x30) {
                 if (srate <= 3000000)
-                        aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_2;
+                        aclc_value = s2sclc30[mod_index].car_loop_2;
                 else if (srate <= 7000000)
-                        aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_5;
+                        aclc_value = s2sclc30[mod_index].car_loop_5;
                 else if (srate <= 15000000)
-                        aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_10;
+                        aclc_value = s2sclc30[mod_index].car_loop_10;
                 else if (srate <= 25000000)
-                        aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_20;
+                        aclc_value = s2sclc30[mod_index].car_loop_20;
                 else
-                        aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_30;
+                        aclc_value = s2sclc30[mod_index].car_loop_30;
 
-                break;
-        case 0x12:
-        default:
+        } else if (chip_id >= 0x20) {
                 if (srate <= 3000000)
-                        aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_2;
+                        aclc_value = s2scl[mod_index].car_loop_cut20_2;
                 else if (srate <= 7000000)
-                        aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_5;
+                        aclc_value = s2scl[mod_index].car_loop_cut20_5;
                 else if (srate <= 15000000)
-                        aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_10;
+                        aclc_value = s2scl[mod_index].car_loop_cut20_10;
                 else if (srate <= 25000000)
-                        aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_20;
+                        aclc_value = s2scl[mod_index].car_loop_cut20_20;
                 else
-                        aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_30;
+                        aclc_value = s2scl[mod_index].car_loop_cut20_30;
+
+        } else {
+                if (srate <= 3000000)
+                        aclc_value = s2scl[mod_index].car_loop_cut12_2;
+                else if (srate <= 7000000)
+                        aclc_value = s2scl[mod_index].car_loop_cut12_5;
+                else if (srate <= 15000000)
+                        aclc_value = s2scl[mod_index].car_loop_cut12_10;
+                else if (srate <= 25000000)
+                        aclc_value = s2scl[mod_index].car_loop_cut12_20;
+                else
+                        aclc_value = s2scl[mod_index].car_loop_cut12_30;
 
-                break;
         }
 
         return aclc_value;
 }
 
-static enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *i_params,
+static
+enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp,
                                         enum fe_stv0900_demod_mode LDPC_Mode,
                                         enum fe_stv0900_demod_num demod)
 {
         enum fe_stv0900_error error = STV0900_NO_ERROR;
+        s32 reg_ind;
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
         switch (LDPC_Mode) {
         case STV0900_DUAL:
         default:
-                if ((i_params->demod_mode != STV0900_DUAL)
-                        || (stv0900_get_bits(i_params, F0900_DDEMOD) != 1)) {
-                        stv0900_write_reg(i_params, R0900_GENCFG, 0x1d);
-
-                        i_params->demod_mode = STV0900_DUAL;
-
-                        stv0900_write_bits(i_params, F0900_FRESFEC, 1);
-                        stv0900_write_bits(i_params, F0900_FRESFEC, 0);
+                if ((intp->demod_mode != STV0900_DUAL)
+                        || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) {
+                        stv0900_write_reg(intp, R0900_GENCFG, 0x1d);
+
+                        intp->demod_mode = STV0900_DUAL;
+
+                        stv0900_write_bits(intp, F0900_FRESFEC, 1);
+                        stv0900_write_bits(intp, F0900_FRESFEC, 0);
+
+                        for (reg_ind = 0; reg_ind < 7; reg_ind++)
+                                stv0900_write_reg(intp,
+                                                R0900_P1_MODCODLST0 + reg_ind,
+                                                0xff);
+                        for (reg_ind = 0; reg_ind < 8; reg_ind++)
+                                stv0900_write_reg(intp,
+                                                R0900_P1_MODCODLST7 + reg_ind,
+                                                0xcc);
+
+                        stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff);
+                        stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf);
+
+                        for (reg_ind = 0; reg_ind < 7; reg_ind++)
+                                stv0900_write_reg(intp,
+                                                R0900_P2_MODCODLST0 + reg_ind,
+                                                0xff);
+                        for (reg_ind = 0; reg_ind < 8; reg_ind++)
+                                stv0900_write_reg(intp,
+                                                R0900_P2_MODCODLST7 + reg_ind,
+                                                0xcc);
+
+                        stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff);
+                        stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf);
                 }
 
                 break;
         case STV0900_SINGLE:
-                if (demod == STV0900_DEMOD_2)
-                        stv0900_write_reg(i_params, R0900_GENCFG, 0x06);
-                else
-                        stv0900_write_reg(i_params, R0900_GENCFG, 0x04);
+                if (demod == STV0900_DEMOD_2) {
+                        stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1);
+                        stv0900_activate_s2_modcod_single(intp,
+                                                        STV0900_DEMOD_2);
+                        stv0900_write_reg(intp, R0900_GENCFG, 0x06);
+                } else {
+                        stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2);
+                        stv0900_activate_s2_modcod_single(intp,
+                                                        STV0900_DEMOD_1);
+                        stv0900_write_reg(intp, R0900_GENCFG, 0x04);
+                }
 
-                i_params->demod_mode = STV0900_SINGLE;
+                intp->demod_mode = STV0900_SINGLE;
 
-                stv0900_write_bits(i_params, F0900_FRESFEC, 1);
-                stv0900_write_bits(i_params, F0900_FRESFEC, 0);
-                stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
-                stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
-                stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
-                stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
+                stv0900_write_bits(intp, F0900_FRESFEC, 1);
+                stv0900_write_bits(intp, F0900_FRESFEC, 0);
+                stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1);
+                stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0);
+                stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1);
+                stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0);
                 break;
         }
 
@@ -1393,131 +1368,178 @@ static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
         struct stv0900_state *state = fe->demodulator_priv;
         enum fe_stv0900_error error = STV0900_NO_ERROR;
         enum fe_stv0900_error demodError = STV0900_NO_ERROR;
+        struct stv0900_internal *intp = NULL;
         int selosci, i;
 
         struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
                                                 state->config->demod_address);
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
-        if (temp_int != NULL) {
+        if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) {
                 state->internal = temp_int->internal;
                 (state->internal->dmds_used)++;
-                dprintk(KERN_INFO "%s: Find Internal Structure!\n", __func__);
+                dprintk("%s: Find Internal Structure!\n", __func__);
                 return STV0900_NO_ERROR;
         } else {
-                state->internal = kmalloc(sizeof(struct stv0900_internal), GFP_KERNEL);
+                state->internal = kmalloc(sizeof(struct stv0900_internal),
+                                                                GFP_KERNEL);
+                if (state->internal == NULL)
+                        return STV0900_INVALID_HANDLE;
                 temp_int = append_internal(state->internal);
+                if (temp_int == NULL) {
+                        kfree(state->internal);
+                        state->internal = NULL;
+                        return STV0900_INVALID_HANDLE;
+                }
                 state->internal->dmds_used = 1;
                 state->internal->i2c_adap = state->i2c_adap;
                 state->internal->i2c_addr = state->config->demod_address;
                 state->internal->clkmode = state->config->clkmode;
                 state->internal->errs = STV0900_NO_ERROR;
-                dprintk(KERN_INFO "%s: Create New Internal Structure!\n", __func__);
+                dprintk("%s: Create New Internal Structure!\n", __func__);
         }
 
-        if (state->internal != NULL) {
-                demodError = stv0900_initialize(state->internal);
-                if (demodError == STV0900_NO_ERROR) {
-                                error = STV0900_NO_ERROR;
-                } else {
-                        if (demodError == STV0900_INVALID_HANDLE)
-                                error = STV0900_INVALID_HANDLE;
-                        else
-                                error = STV0900_I2C_ERROR;
-                }
+        if (state->internal == NULL) {
+                error = STV0900_INVALID_HANDLE;
+                return error;
+        }
 
-                if (state->internal != NULL) {
-                        if (error == STV0900_NO_ERROR) {
-                                state->internal->demod_mode = p_init->demod_mode;
-
-                                stv0900_st_dvbs2_single(state->internal, state->internal->demod_mode, STV0900_DEMOD_1);
-
-                                state->internal->chip_id = stv0900_read_reg(state->internal, R0900_MID);
-                                state->internal->rolloff = p_init->rolloff;
-                                state->internal->quartz = p_init->dmd_ref_clk;
-
-                                stv0900_write_bits(state->internal, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
-                                stv0900_write_bits(state->internal, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
-
-                                state->internal->ts_config = p_init->ts_config;
-                                if (state->internal->ts_config == NULL)
-                                        stv0900_set_ts_parallel_serial(state->internal,
-                                                        p_init->path1_ts_clock,
-                                                        p_init->path2_ts_clock);
-                                else {
-                                        for (i = 0; state->internal->ts_config[i].addr != 0xffff; i++)
-                                                stv0900_write_reg(state->internal,
-                                                                state->internal->ts_config[i].addr,
-                                                                state->internal->ts_config[i].val);
-
-                                        stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 1);
-                                        stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 0);
-                                        stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 1);
-                                        stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 0);
-                                }
+        demodError = stv0900_initialize(state->internal);
+        if (demodError == STV0900_NO_ERROR) {
+                        error = STV0900_NO_ERROR;
+        } else {
+                if (demodError == STV0900_INVALID_HANDLE)
+                        error = STV0900_INVALID_HANDLE;
+                else
+                        error = STV0900_I2C_ERROR;
 
-                                stv0900_write_bits(state->internal, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
-                                switch (p_init->tuner1_adc) {
-                                case 1:
-                                        stv0900_write_reg(state->internal, R0900_TSTTNR1, 0x26);
-                                        break;
-                                default:
-                                        break;
-                                }
+                return error;
+        }
 
-                                stv0900_write_bits(state->internal, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
-                                switch (p_init->tuner2_adc) {
-                                case 1:
-                                        stv0900_write_reg(state->internal, R0900_TSTTNR3, 0x26);
-                                        break;
-                                default:
-                                        break;
-                                }
+        intp = state->internal;
 
-                                stv0900_write_bits(state->internal, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inversion);
-                                stv0900_write_bits(state->internal, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inversion);
-                                stv0900_set_mclk(state->internal, 135000000);
-                                msleep(3);
-
-                                switch (state->internal->clkmode) {
-                                case 0:
-                                case 2:
-                                        stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | state->internal->clkmode);
-                                        break;
-                                default:
-                                        selosci = 0x02 & stv0900_read_reg(state->internal, R0900_SYNTCTRL);
-                                        stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | selosci);
-                                        break;
-                                }
-                                msleep(3);
+        intp->demod_mode = p_init->demod_mode;
+        stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1);
+        intp->chip_id = stv0900_read_reg(intp, R0900_MID);
+        intp->rolloff = p_init->rolloff;
+        intp->quartz = p_init->dmd_ref_clk;
 
-                                state->internal->mclk = stv0900_get_mclk_freq(state->internal, state->internal->quartz);
-                                if (state->internal->errs)
-                                        error = STV0900_I2C_ERROR;
-                        }
-                } else {
-                        error = STV0900_INVALID_HANDLE;
-                }
+        stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
+        stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
+
+        intp->ts_config = p_init->ts_config;
+        if (intp->ts_config == NULL)
+                stv0900_set_ts_parallel_serial(intp,
+                                p_init->path1_ts_clock,
+                                p_init->path2_ts_clock);
+        else {
+                for (i = 0; intp->ts_config[i].addr != 0xffff; i++)
+                        stv0900_write_reg(intp,
+                                        intp->ts_config[i].addr,
+                                        intp->ts_config[i].val);
+
+                stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
+                stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
+                stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
+                stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
         }
 
+        intp->tuner_type[0] = p_init->tuner1_type;
+        intp->tuner_type[1] = p_init->tuner2_type;
+        /* tuner init */
+        switch (p_init->tuner1_type) {
+        case 3: /*FE_AUTO_STB6100:*/
+                stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x3c);
+                stv0900_write_reg(intp, R0900_P1_TNRCFG2, 0x86);
+                stv0900_write_reg(intp, R0900_P1_TNRCFG3, 0x18);
+                stv0900_write_reg(intp, R0900_P1_TNRXTAL, 27); /* 27MHz */
+                stv0900_write_reg(intp, R0900_P1_TNRSTEPS, 0x05);
+                stv0900_write_reg(intp, R0900_P1_TNRGAIN, 0x17);
+                stv0900_write_reg(intp, R0900_P1_TNRADJ, 0x1f);
+                stv0900_write_reg(intp, R0900_P1_TNRCTL2, 0x0);
+                stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 3);
+                break;
+        /* case FE_SW_TUNER: */
+        default:
+                stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 6);
+                break;
+        }
+
+        stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
+        switch (p_init->tuner1_adc) {
+        case 1:
+                stv0900_write_reg(intp, R0900_TSTTNR1, 0x26);
+                break;
+        default:
+                break;
+        }
+
+        stv0900_write_reg(intp, R0900_P1_TNRLD, 1); /* hw tuner */
+
+        /* tuner init */
+        switch (p_init->tuner2_type) {
+        case 3: /*FE_AUTO_STB6100:*/
+                stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x3c);
+                stv0900_write_reg(intp, R0900_P2_TNRCFG2, 0x86);
+                stv0900_write_reg(intp, R0900_P2_TNRCFG3, 0x18);
+                stv0900_write_reg(intp, R0900_P2_TNRXTAL, 27); /* 27MHz */
+                stv0900_write_reg(intp, R0900_P2_TNRSTEPS, 0x05);
+                stv0900_write_reg(intp, R0900_P2_TNRGAIN, 0x17);
+                stv0900_write_reg(intp, R0900_P2_TNRADJ, 0x1f);
+                stv0900_write_reg(intp, R0900_P2_TNRCTL2, 0x0);
+                stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 3);
+                break;
+        /* case FE_SW_TUNER: */
+        default:
+                stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 6);
+                break;
+        }
+
+        stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
+        switch (p_init->tuner2_adc) {
+        case 1:
+                stv0900_write_reg(intp, R0900_TSTTNR3, 0x26);
+                break;
+        default:
+                break;
+        }
+
+        stv0900_write_reg(intp, R0900_P2_TNRLD, 1); /* hw tuner */
+
+        stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv);
+        stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv);
+        stv0900_set_mclk(intp, 135000000);
+        msleep(3);
+
+        switch (intp->clkmode) {
+        case 0:
+        case 2:
+                stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode);
+                break;
+        default:
+                selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
+                stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci);
+                break;
+        }
+        msleep(3);
+
+        intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz);
+        if (intp->errs)
+                error = STV0900_I2C_ERROR;
+
         return error;
 }
 
-static int stv0900_status(struct stv0900_internal *i_params,
+static int stv0900_status(struct stv0900_internal *intp,
                                         enum fe_stv0900_demod_num demod)
 {
         enum fe_stv0900_search_state demod_state;
-        s32 mode_field, delin_field, lock_field, fifo_field, lockedvit_field;
         int locked = FALSE;
+        u8 tsbitrate0_val, tsbitrate1_val;
+        s32 bitrate;
 
-        dmd_reg(mode_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
-        dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
-        dmd_reg(delin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
-        dmd_reg(fifo_field, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
-        dmd_reg(lockedvit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
-
-        demod_state = stv0900_get_bits(i_params, mode_field);
+        demod_state = stv0900_get_bits(intp, HEADER_MODE);
         switch (demod_state) {
         case STV0900_SEARCH:
         case STV0900_PLH_DETECTED:
@@ -1525,17 +1547,30 @@ static int stv0900_status(struct stv0900_internal *i_params,
                 locked = FALSE;
                 break;
         case STV0900_DVBS2_FOUND:
-                locked = stv0900_get_bits(i_params, lock_field) &&
-                                stv0900_get_bits(i_params, delin_field) &&
-                                stv0900_get_bits(i_params, fifo_field);
+                locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
+                                stv0900_get_bits(intp, PKTDELIN_LOCK) &&
+                                stv0900_get_bits(intp, TSFIFO_LINEOK);
                 break;
         case STV0900_DVBS_FOUND:
-                locked = stv0900_get_bits(i_params, lock_field) &&
-                                stv0900_get_bits(i_params, lockedvit_field) &&
-                                stv0900_get_bits(i_params, fifo_field);
+                locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
+                                stv0900_get_bits(intp, LOCKEDVIT) &&
+                                stv0900_get_bits(intp, TSFIFO_LINEOK);
                 break;
         }
 
+        dprintk("%s: locked = %d\n", __func__, locked);
+
+        if (stvdebug) {
+                /* Print TS bitrate */
+                tsbitrate0_val = stv0900_read_reg(intp, TSBITRATE0);
+                tsbitrate1_val = stv0900_read_reg(intp, TSBITRATE1);
+                /* Formula Bit rate = Mclk * px_tsfifo_bitrate / 16384 */
+                bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000)
+                        * (tsbitrate1_val << 8 | tsbitrate0_val);
+                bitrate /= 16384;
+                dprintk("TS bitrate = %d Mbit/sec \n", bitrate);
+        };
+
         return locked;
 }
 
@@ -1543,7 +1578,8 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
                                         struct dvb_frontend_parameters *params)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
+        enum fe_stv0900_demod_num demod = state->demod;
         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 
         struct stv0900_search_params p_search;
@@ -1551,10 +1587,16 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
 
         enum fe_stv0900_error error = STV0900_NO_ERROR;
 
-        dprintk(KERN_INFO "%s: ", __func__);
+        dprintk("%s: ", __func__);
+
+        if (!(INRANGE(100000, c->symbol_rate, 70000000)))
+                return DVBFE_ALGO_SEARCH_FAILED;
+
+        if (state->config->set_ts_params)
+                state->config->set_ts_params(fe, 0);
 
         p_result.locked = FALSE;
-        p_search.path = state->demod;
+        p_search.path = demod;
         p_search.frequency = c->frequency;
         p_search.symbol_rate = c->symbol_rate;
         p_search.search_range = 10000000;
@@ -1563,103 +1605,47 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
         p_search.iq_inversion = STV0900_IQ_AUTO;
         p_search.search_algo = STV0900_BLIND_SEARCH;
 
-        if ((INRANGE(100000, p_search.symbol_rate, 70000000)) &&
-                        (INRANGE(100000, p_search.search_range, 50000000))) {
-                switch (p_search.path) {
-                case STV0900_DEMOD_1:
-                default:
-                        i_params->dmd1_srch_standard = p_search.standard;
-                        i_params->dmd1_symbol_rate = p_search.symbol_rate;
-                        i_params->dmd1_srch_range = p_search.search_range;
-                        i_params->tuner1_freq = p_search.frequency;
-                        i_params->dmd1_srch_algo = p_search.search_algo;
-                        i_params->dmd1_srch_iq_inv = p_search.iq_inversion;
-                        i_params->dmd1_fec = p_search.fec;
+        intp->srch_standard[demod] = p_search.standard;
+        intp->symbol_rate[demod] = p_search.symbol_rate;
+        intp->srch_range[demod] = p_search.search_range;
+        intp->freq[demod] = p_search.frequency;
+        intp->srch_algo[demod] = p_search.search_algo;
+        intp->srch_iq_inv[demod] = p_search.iq_inversion;
+        intp->fec[demod] = p_search.fec;
+        if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
+                                (intp->errs == STV0900_NO_ERROR)) {
+                p_result.locked = intp->result[demod].locked;
+                p_result.standard = intp->result[demod].standard;
+                p_result.frequency = intp->result[demod].frequency;
+                p_result.symbol_rate = intp->result[demod].symbol_rate;
+                p_result.fec = intp->result[demod].fec;
+                p_result.modcode = intp->result[demod].modcode;
+                p_result.pilot = intp->result[demod].pilot;
+                p_result.frame_len = intp->result[demod].frame_len;
+                p_result.spectrum = intp->result[demod].spectrum;
+                p_result.rolloff = intp->result[demod].rolloff;
+                p_result.modulation = intp->result[demod].modulation;
+        } else {
+                p_result.locked = FALSE;
+                switch (intp->err[demod]) {
+                case STV0900_I2C_ERROR:
+                        error = STV0900_I2C_ERROR;
                         break;
-
-                case STV0900_DEMOD_2:
-                        i_params->dmd2_srch_stndrd = p_search.standard;
-                        i_params->dmd2_symbol_rate = p_search.symbol_rate;
-                        i_params->dmd2_srch_range = p_search.search_range;
-                        i_params->tuner2_freq = p_search.frequency;
-                        i_params->dmd2_srch_algo = p_search.search_algo;
-                        i_params->dmd2_srch_iq_inv = p_search.iq_inversion;
-                        i_params->dmd2_fec = p_search.fec;
+                case STV0900_NO_ERROR:
+                default:
+                        error = STV0900_SEARCH_FAILED;
                         break;
                 }
-
-                if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
-                                        (i_params->errs == STV0900_NO_ERROR)) {
-                        switch (p_search.path) {
-                        case STV0900_DEMOD_1:
-                        default:
-                                p_result.locked = i_params->dmd1_rslts.locked;
-                                p_result.standard = i_params->dmd1_rslts.standard;
-                                p_result.frequency = i_params->dmd1_rslts.frequency;
-                                p_result.symbol_rate = i_params->dmd1_rslts.symbol_rate;
-                                p_result.fec = i_params->dmd1_rslts.fec;
-                                p_result.modcode = i_params->dmd1_rslts.modcode;
-                                p_result.pilot = i_params->dmd1_rslts.pilot;
-                                p_result.frame_length = i_params->dmd1_rslts.frame_length;
-                                p_result.spectrum = i_params->dmd1_rslts.spectrum;
-                                p_result.rolloff = i_params->dmd1_rslts.rolloff;
-                                p_result.modulation = i_params->dmd1_rslts.modulation;
-                                break;
-                        case STV0900_DEMOD_2:
-                                p_result.locked = i_params->dmd2_rslts.locked;
-                                p_result.standard = i_params->dmd2_rslts.standard;
-                                p_result.frequency = i_params->dmd2_rslts.frequency;
-                                p_result.symbol_rate = i_params->dmd2_rslts.symbol_rate;
-                                p_result.fec = i_params->dmd2_rslts.fec;
-                                p_result.modcode = i_params->dmd2_rslts.modcode;
-                                p_result.pilot = i_params->dmd2_rslts.pilot;
-                                p_result.frame_length = i_params->dmd2_rslts.frame_length;
-                                p_result.spectrum = i_params->dmd2_rslts.spectrum;
-                                p_result.rolloff = i_params->dmd2_rslts.rolloff;
-                                p_result.modulation = i_params->dmd2_rslts.modulation;
-                                break;
-                        }
-
-                } else {
-                        p_result.locked = FALSE;
-                        switch (p_search.path) {
-                        case STV0900_DEMOD_1:
-                                switch (i_params->dmd1_err) {
-                                case STV0900_I2C_ERROR:
-                                        error = STV0900_I2C_ERROR;
-                                        break;
-                                case STV0900_NO_ERROR:
-                                default:
-                                        error = STV0900_SEARCH_FAILED;
-                                        break;
-                                }
-                                break;
-                        case STV0900_DEMOD_2:
-                                switch (i_params->dmd2_err) {
-                                case STV0900_I2C_ERROR:
-                                        error = STV0900_I2C_ERROR;
-                                        break;
-                                case STV0900_NO_ERROR:
-                                default:
-                                        error = STV0900_SEARCH_FAILED;
-                                        break;
-                                }
-                                break;
-                        }
-                }
-
-        } else
-                error = STV0900_BAD_PARAMETER;
+        }
 
         if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
-                dprintk(KERN_INFO "Search Success\n");
+                dprintk("Search Success\n");
                 return DVBFE_ALGO_SEARCH_SUCCESS;
         } else {
-                dprintk(KERN_INFO "Search Fail\n");
+                dprintk("Search Fail\n");
                 return DVBFE_ALGO_SEARCH_FAILED;
         }
 
-        return DVBFE_ALGO_SEARCH_ERROR;
 }
 
 static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
@@ -1690,16 +1676,13 @@ static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
 {
 
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
-        s32 rst_field;
-
-        dmd_reg(rst_field, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
 
         if (stop_ts == TRUE)
-                stv0900_write_bits(i_params, rst_field, 1);
+                stv0900_write_bits(intp, RST_HWARE, 1);
         else
-                stv0900_write_bits(i_params, rst_field, 0);
+                stv0900_write_bits(intp, RST_HWARE, 0);
 
         return 0;
 }
@@ -1707,23 +1690,19 @@ static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
 static int stv0900_diseqc_init(struct dvb_frontend *fe)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
-        s32 mode_field, reset_field;
 
-        dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
-        dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
-
-        stv0900_write_bits(i_params, mode_field, state->config->diseqc_mode);
-        stv0900_write_bits(i_params, reset_field, 1);
-        stv0900_write_bits(i_params, reset_field, 0);
+        stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode);
+        stv0900_write_bits(intp, DISEQC_RESET, 1);
+        stv0900_write_bits(intp, DISEQC_RESET, 0);
 
         return 0;
 }
 
 static int stv0900_init(struct dvb_frontend *fe)
 {
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
         stv0900_stop_ts(fe, 1);
         stv0900_diseqc_init(fe);
@@ -1731,48 +1710,24 @@ static int stv0900_init(struct dvb_frontend *fe)
         return 0;
 }
 
-static int stv0900_diseqc_send(struct stv0900_internal *i_params , u8 *Data,
+static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data,
                                 u32 NbData, enum fe_stv0900_demod_num demod)
 {
         s32 i = 0;
 
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 1);
-                while (i < NbData) {
-                        while (stv0900_get_bits(i_params, F0900_P1_FIFO_FULL))
-                                ;/* checkpatch complains */
-                        stv0900_write_reg(i_params, R0900_P1_DISTXDATA, Data[i]);
-                        i++;
-                }
-
-                stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 0);
-                i = 0;
-                while ((stv0900_get_bits(i_params, F0900_P1_TX_IDLE) != 1) && (i < 10)) {
-                        msleep(10);
-                        i++;
-                }
-
-                break;
-        case STV0900_DEMOD_2:
-                stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 1);
-
-                while (i < NbData) {
-                        while (stv0900_get_bits(i_params, F0900_P2_FIFO_FULL))
-                                ;/* checkpatch complains */
-                        stv0900_write_reg(i_params, R0900_P2_DISTXDATA, Data[i]);
-                        i++;
-                }
-
-                stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 0);
-                i = 0;
-                while ((stv0900_get_bits(i_params, F0900_P2_TX_IDLE) != 1) && (i < 10)) {
-                        msleep(10);
-                        i++;
-                }
+        stv0900_write_bits(intp, DIS_PRECHARGE, 1);
+        while (i < NbData) {
+                while (stv0900_get_bits(intp, FIFO_FULL))
+                        ;/* checkpatch complains */
+                stv0900_write_reg(intp, DISTXDATA, data[i]);
+                i++;
+        }
 
-                break;
+        stv0900_write_bits(intp, DIS_PRECHARGE, 0);
+        i = 0;
+        while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) {
+                msleep(10);
+                i++;
         }
 
         return 0;
@@ -1792,22 +1747,21 @@ static int stv0900_send_master_cmd(struct dvb_frontend *fe,
 static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
-        s32 mode_field;
-        u32 diseqc_fifo;
+        u8 data;
 
-        dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
-        dmd_reg(diseqc_fifo, R0900_P1_DISTXDATA, R0900_P2_DISTXDATA);
 
         switch (burst) {
         case SEC_MINI_A:
-                stv0900_write_bits(i_params, mode_field, 3);/* Unmodulated */
-                stv0900_write_reg(i_params, diseqc_fifo, 0x00);
+                stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */
+                data = 0x00;
+                stv0900_diseqc_send(intp, &data, 1, state->demod);
                 break;
         case SEC_MINI_B:
-                stv0900_write_bits(i_params, mode_field, 2);/* Modulated */
-                stv0900_write_reg(i_params, diseqc_fifo, 0xff);
+                stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */
+                data = 0xff;
+                stv0900_diseqc_send(intp, &data, 1, state->demod);
                 break;
         }
 
@@ -1818,68 +1772,54 @@ static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
                                 struct dvb_diseqc_slave_reply *reply)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
+        enum fe_stv0900_demod_num demod = state->demod;
         s32 i = 0;
 
-        switch (state->demod) {
-        case STV0900_DEMOD_1:
-        default:
-                reply->msg_len = 0;
-
-                while ((stv0900_get_bits(i_params, F0900_P1_RX_END) != 1) && (i < 10)) {
-                        msleep(10);
-                        i++;
-                }
-
-                if (stv0900_get_bits(i_params, F0900_P1_RX_END)) {
-                        reply->msg_len = stv0900_get_bits(i_params, F0900_P1_FIFO_BYTENBR);
-
-                        for (i = 0; i < reply->msg_len; i++)
-                                reply->msg[i] = stv0900_read_reg(i_params, R0900_P1_DISRXDATA);
-                }
-                break;
-        case STV0900_DEMOD_2:
-                reply->msg_len = 0;
+        reply->msg_len = 0;
 
-                while ((stv0900_get_bits(i_params, F0900_P2_RX_END) != 1) && (i < 10)) {
-                        msleep(10);
-                        i++;
-                }
+        while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) {
+                msleep(10);
+                i++;
+        }
 
-                if (stv0900_get_bits(i_params, F0900_P2_RX_END)) {
-                        reply->msg_len = stv0900_get_bits(i_params, F0900_P2_FIFO_BYTENBR);
+        if (stv0900_get_bits(intp, RX_END)) {
+                reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR);
 
-                        for (i = 0; i < reply->msg_len; i++)
-                                reply->msg[i] = stv0900_read_reg(i_params, R0900_P2_DISRXDATA);
-                }
-                break;
+                for (i = 0; i < reply->msg_len; i++)
+                        reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
         }
 
         return 0;
 }
 
-static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
+static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
-        s32 mode_field, reset_field;
-
-        dprintk(KERN_INFO "%s: %s\n", __func__, ((tone == 0) ? "Off" : "On"));
 
-        dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
-        dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
+        dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
 
-        if (tone) {
-                /*Set the DiseqC mode to 22Khz continues tone*/
-                stv0900_write_bits(i_params, mode_field, 0);
-                stv0900_write_bits(i_params, reset_field, 1);
+        switch (toneoff) {
+        case SEC_TONE_ON:
+                /*Set the DiseqC mode to 22Khz _continues_ tone*/
+                stv0900_write_bits(intp, DISTX_MODE, 0);
+                stv0900_write_bits(intp, DISEQC_RESET, 1);
                 /*release DiseqC reset to enable the 22KHz tone*/
-                stv0900_write_bits(i_params, reset_field, 0);
-        } else {
-                stv0900_write_bits(i_params, mode_field, 0);
+                stv0900_write_bits(intp, DISEQC_RESET, 0);
+                break;
+        case SEC_TONE_OFF:
+                /*return diseqc mode to config->diseqc_mode.
+                Usually it's without _continues_ tone */
+                stv0900_write_bits(intp, DISTX_MODE,
+                                state->config->diseqc_mode);
                 /*maintain the DiseqC reset to disable the 22KHz tone*/
-                stv0900_write_bits(i_params, reset_field, 1);
+                stv0900_write_bits(intp, DISEQC_RESET, 1);
+                stv0900_write_bits(intp, DISEQC_RESET, 0);
+                break;
+        default:
+                return -EINVAL;
         }
 
         return 0;
@@ -1889,11 +1829,11 @@ static void stv0900_release(struct dvb_frontend *fe)
 {
         struct stv0900_state *state = fe->demodulator_priv;
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
         if ((--(state->internal->dmds_used)) <= 0) {
 
-                dprintk(KERN_INFO "%s: Actually removing\n", __func__);
+                dprintk("%s: Actually removing\n", __func__);
 
                 remove_inode(state->internal);
                 kfree(state->internal);
@@ -1963,17 +1903,19 @@ struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
         case 0:
         case 1:
                 init_params.dmd_ref_clk         = config->xtal;
-                init_params.demod_mode          = STV0900_DUAL;
+                init_params.demod_mode          = config->demod_mode;
                 init_params.rolloff             = STV0900_35;
                 init_params.path1_ts_clock      = config->path1_mode;
                 init_params.tun1_maddress       = config->tun1_maddress;
-                init_params.tun1_iq_inversion   = STV0900_IQ_NORMAL;
+                init_params.tun1_iq_inv         = STV0900_IQ_NORMAL;
                 init_params.tuner1_adc          = config->tun1_adc;
+                init_params.tuner1_type         = config->tun1_type;
                 init_params.path2_ts_clock      = config->path2_mode;
                 init_params.ts_config           = config->ts_config_regs;
                 init_params.tun2_maddress       = config->tun2_maddress;
                 init_params.tuner2_adc          = config->tun2_adc;
-                init_params.tun2_iq_inversion   = STV0900_IQ_SWAPPED;
+                init_params.tuner2_type         = config->tun2_type;
+                init_params.tun2_iq_inv         = STV0900_IQ_SWAPPED;
 
                 err_stv0900 = stv0900_init_internal(&state->frontend,
                                                         &init_params);
diff --git a/drivers/media/dvb/frontends/stv0900_init.h b/drivers/media/dvb/frontends/stv0900_init.h
index ff388b47a4e3..b684df9995d8 100644
--- a/drivers/media/dvb/frontends/stv0900_init.h
+++ b/drivers/media/dvb/frontends/stv0900_init.h
@@ -141,85 +141,228 @@ struct stv0900_short_frames_car_loop_optim {
 
 };
 
+struct stv0900_short_frames_car_loop_optim_vs_mod {
+        enum fe_stv0900_modulation modulation;
+        u8 car_loop_2;    /* SR<3msps      */
+        u8 car_loop_5;    /* 3<SR<=7msps   */
+        u8 car_loop_10;   /* 7<SR<=15msps  */
+        u8 car_loop_20;   /* 10<SR<=25msps */
+        u8 car_loop_30;   /* 10<SR<=45msps */
+};
+
 /* Cut 1.x Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */
-static const struct stv0900_car_loop_optim      FE_STV0900_S2CarLoop[14] = {
-        /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon  10MPoff 20MPon  20MPoff 30MPon  30MPoff */
-        { STV0900_QPSK_12,      0x1C,   0x0D,   0x1B,   0x2C,   0x3A,   0x1C,   0x2A,   0x3B,   0x2A,   0x1B },
-        { STV0900_QPSK_35,      0x2C,   0x0D,   0x2B,   0x2C,   0x3A,   0x0C,   0x3A,   0x2B,   0x2A,   0x0B },
-        { STV0900_QPSK_23,      0x2C,   0x0D,   0x2B,   0x2C,   0x0B,   0x0C,   0x3A,   0x1B,   0x2A,   0x3A },
-        { STV0900_QPSK_34,      0x3C,   0x0D,   0x3B,   0x1C,   0x0B,   0x3B,   0x3A,   0x0B,   0x2A,   0x3A },
-        { STV0900_QPSK_45,      0x3C,   0x0D,   0x3B,   0x1C,   0x0B,   0x3B,   0x3A,   0x0B,   0x2A,   0x3A },
-        { STV0900_QPSK_56,      0x0D,   0x0D,   0x3B,   0x1C,   0x0B,   0x3B,   0x3A,   0x0B,   0x2A,   0x3A },
-        { STV0900_QPSK_89,      0x0D,   0x0D,   0x3B,   0x1C,   0x1B,   0x3B,   0x3A,   0x0B,   0x2A,   0x3A },
-        { STV0900_QPSK_910,     0x1D,   0x0D,   0x3B,   0x1C,   0x1B,   0x3B,   0x3A,   0x0B,   0x2A,   0x3A },
-        { STV0900_8PSK_35,      0x29,   0x3B,   0x09,   0x2B,   0x38,   0x0B,   0x18,   0x1A,   0x08,   0x0A },
-        { STV0900_8PSK_23,      0x0A,   0x3B,   0x29,   0x2B,   0x19,   0x0B,   0x38,   0x1A,   0x18,   0x0A },
-        { STV0900_8PSK_34,      0x3A,   0x3B,   0x2A,   0x2B,   0x39,   0x0B,   0x19,   0x1A,   0x38,   0x0A },
-        { STV0900_8PSK_56,      0x1B,   0x3B,   0x0B,   0x2B,   0x1A,   0x0B,   0x39,   0x1A,   0x19,   0x0A },
-        { STV0900_8PSK_89,      0x3B,   0x3B,   0x0B,   0x2B,   0x2A,   0x0B,   0x39,   0x1A,   0x29,   0x39 },
-        { STV0900_8PSK_910,     0x3B,   0x3B,   0x0B,   0x2B,   0x2A,   0x0B,   0x39,   0x1A,   0x29,   0x39 }
+static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoop[14] = {
+        /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
+                                10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+        { STV0900_QPSK_12,      0x1C,   0x0D,   0x1B,   0x2C,   0x3A,
+                                0x1C,   0x2A,   0x3B,   0x2A,   0x1B },
+        { STV0900_QPSK_35,      0x2C,   0x0D,   0x2B,   0x2C,   0x3A,
+                                0x0C,   0x3A,   0x2B,   0x2A,   0x0B },
+        { STV0900_QPSK_23,      0x2C,   0x0D,   0x2B,   0x2C,   0x0B,
+                                0x0C,   0x3A,   0x1B,   0x2A,   0x3A },
+        { STV0900_QPSK_34,      0x3C,   0x0D,   0x3B,   0x1C,   0x0B,
+                                0x3B,   0x3A,   0x0B,   0x2A,   0x3A },
+        { STV0900_QPSK_45,      0x3C,   0x0D,   0x3B,   0x1C,   0x0B,
+                                0x3B,   0x3A,   0x0B,   0x2A,   0x3A },
+        { STV0900_QPSK_56,      0x0D,   0x0D,   0x3B,   0x1C,   0x0B,
+                                0x3B,   0x3A,   0x0B,   0x2A,   0x3A },
+        { STV0900_QPSK_89,      0x0D,   0x0D,   0x3B,   0x1C,   0x1B,
+                                0x3B,   0x3A,   0x0B,   0x2A,   0x3A },
+        { STV0900_QPSK_910,     0x1D,   0x0D,   0x3B,   0x1C,   0x1B,
+                                0x3B,   0x3A,   0x0B,   0x2A,   0x3A },
+        { STV0900_8PSK_35,      0x29,   0x3B,   0x09,   0x2B,   0x38,
+                                0x0B,   0x18,   0x1A,   0x08,   0x0A },
+        { STV0900_8PSK_23,      0x0A,   0x3B,   0x29,   0x2B,   0x19,
+                                0x0B,   0x38,   0x1A,   0x18,   0x0A },
+        { STV0900_8PSK_34,      0x3A,   0x3B,   0x2A,   0x2B,   0x39,
+                                0x0B,   0x19,   0x1A,   0x38,   0x0A },
+        { STV0900_8PSK_56,      0x1B,   0x3B,   0x0B,   0x2B,   0x1A,
+                                0x0B,   0x39,   0x1A,   0x19,   0x0A },
+        { STV0900_8PSK_89,      0x3B,   0x3B,   0x0B,   0x2B,   0x2A,
+                                0x0B,   0x39,   0x1A,   0x29,   0x39 },
+        { STV0900_8PSK_910,     0x3B,   0x3B,   0x0B,   0x2B,   0x2A,
+                                0x0B,   0x39,   0x1A,   0x29,   0x39 }
 };
 
 
 /* Cut 2.0 Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */
-static const struct stv0900_car_loop_optim      FE_STV0900_S2CarLoopCut20[14]   = {
-        /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon  10MPoff 20MPon  20MPoff 30MPon  30MPoff */
-        { STV0900_QPSK_12,      0x1F,   0x3F,   0x1E,   0x3F,   0x3D,   0x1F,   0x3D,   0x3E,   0x3D,   0x1E },
-        { STV0900_QPSK_35,      0x2F,   0x3F,   0x2E,   0x2F,   0x3D,   0x0F,   0x0E,   0x2E,   0x3D,   0x0E },
-        { STV0900_QPSK_23,      0x2F,   0x3F,   0x2E,   0x2F,   0x0E,   0x0F,   0x0E,   0x1E,   0x3D,   0x3D },
-        { STV0900_QPSK_34,      0x3F,   0x3F,   0x3E,   0x1F,   0x0E,   0x3E,   0x0E,   0x1E,   0x3D,   0x3D },
-        { STV0900_QPSK_45,      0x3F,   0x3F,   0x3E,   0x1F,   0x0E,   0x3E,   0x0E,   0x1E,   0x3D,   0x3D },
-        { STV0900_QPSK_56,      0x3F,   0x3F,   0x3E,   0x1F,   0x0E,   0x3E,   0x0E,   0x1E,   0x3D,   0x3D },
-        { STV0900_QPSK_89,      0x3F,   0x3F,   0x3E,   0x1F,   0x1E,   0x3E,   0x0E,   0x1E,   0x3D,   0x3D },
-        { STV0900_QPSK_910,     0x3F,   0x3F,   0x3E,   0x1F,   0x1E,   0x3E,   0x0E,   0x1E,   0x3D,   0x3D },
-        { STV0900_8PSK_35,      0x3c,   0x0c,   0x1c,   0x3b,   0x0c,   0x3b,   0x2b,   0x2b,   0x1b,   0x2b },
-        { STV0900_8PSK_23,      0x1d,   0x0c,   0x3c,   0x0c,   0x2c,   0x3b,   0x0c,   0x2b,   0x2b,   0x2b },
-        { STV0900_8PSK_34,      0x0e,   0x1c,   0x3d,   0x0c,   0x0d,   0x3b,   0x2c,   0x3b,   0x0c,   0x2b },
-        { STV0900_8PSK_56,      0x2e,   0x3e,   0x1e,   0x2e,   0x2d,   0x1e,   0x3c,   0x2d,   0x2c,   0x1d },
-        { STV0900_8PSK_89,      0x3e,   0x3e,   0x1e,   0x2e,   0x3d,   0x1e,   0x0d,   0x2d,   0x3c,   0x1d },
-        { STV0900_8PSK_910,     0x3e,   0x3e,   0x1e,   0x2e,   0x3d,   0x1e,   0x1d,   0x2d,   0x0d,   0x1d }
+static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = {
+        /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon
+                                10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+        { STV0900_QPSK_12,      0x1F,   0x3F,   0x1E,   0x3F,   0x3D,
+                                0x1F,   0x3D,   0x3E,   0x3D,   0x1E },
+        { STV0900_QPSK_35,      0x2F,   0x3F,   0x2E,   0x2F,   0x3D,
+                                0x0F,   0x0E,   0x2E,   0x3D,   0x0E },
+        { STV0900_QPSK_23,      0x2F,   0x3F,   0x2E,   0x2F,   0x0E,
+                                0x0F,   0x0E,   0x1E,   0x3D,   0x3D },
+        { STV0900_QPSK_34,      0x3F,   0x3F,   0x3E,   0x1F,   0x0E,
+                                0x3E,   0x0E,   0x1E,   0x3D,   0x3D },
+        { STV0900_QPSK_45,      0x3F,   0x3F,   0x3E,   0x1F,   0x0E,
+                                0x3E,   0x0E,   0x1E,   0x3D,   0x3D },
+        { STV0900_QPSK_56,      0x3F,   0x3F,   0x3E,   0x1F,   0x0E,
+                                0x3E,   0x0E,   0x1E,   0x3D,   0x3D },
+        { STV0900_QPSK_89,      0x3F,   0x3F,   0x3E,   0x1F,   0x1E,
+                                0x3E,   0x0E,   0x1E,   0x3D,   0x3D },
+        { STV0900_QPSK_910,     0x3F,   0x3F,   0x3E,   0x1F,   0x1E,
+                                0x3E,   0x0E,   0x1E,   0x3D,   0x3D },
+        { STV0900_8PSK_35,      0x3c,   0x0c,   0x1c,   0x3b,   0x0c,
+                                0x3b,   0x2b,   0x2b,   0x1b,   0x2b },
+        { STV0900_8PSK_23,      0x1d,   0x0c,   0x3c,   0x0c,   0x2c,
+                                0x3b,   0x0c,   0x2b,   0x2b,   0x2b },
+        { STV0900_8PSK_34,      0x0e,   0x1c,   0x3d,   0x0c,   0x0d,
+                                0x3b,   0x2c,   0x3b,   0x0c,   0x2b },
+        { STV0900_8PSK_56,      0x2e,   0x3e,   0x1e,   0x2e,   0x2d,
+                                0x1e,   0x3c,   0x2d,   0x2c,   0x1d },
+        { STV0900_8PSK_89,      0x3e,   0x3e,   0x1e,   0x2e,   0x3d,
+                                0x1e,   0x0d,   0x2d,   0x3c,   0x1d },
+        { STV0900_8PSK_910,     0x3e,   0x3e,   0x1e,   0x2e,   0x3d,
+                                0x1e,   0x1d,   0x2d,   0x0d,   0x1d },
 };
 
 
 
 /* Cut 2.0 Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame */
 static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut20[11] = {
-        /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon  10MPoff 20MPon  20MPoff 30MPon  30MPoff */
-        { STV0900_16APSK_23,    0x0C,   0x0C,   0x0C,   0x0C,   0x1D,   0x0C,   0x3C,   0x0C,   0x2C,   0x0C },
-        { STV0900_16APSK_34,    0x0C,   0x0C,   0x0C,   0x0C,   0x0E,   0x0C,   0x2D,   0x0C,   0x1D,   0x0C },
-        { STV0900_16APSK_45,    0x0C,   0x0C,   0x0C,   0x0C,   0x1E,   0x0C,   0x3D,   0x0C,   0x2D,   0x0C },
-        { STV0900_16APSK_56,    0x0C,   0x0C,   0x0C,   0x0C,   0x1E,   0x0C,   0x3D,   0x0C,   0x2D,   0x0C },
-        { STV0900_16APSK_89,    0x0C,   0x0C,   0x0C,   0x0C,   0x2E,   0x0C,   0x0E,   0x0C,   0x3D,   0x0C },
-        { STV0900_16APSK_910,   0x0C,   0x0C,   0x0C,   0x0C,   0x2E,   0x0C,   0x0E,   0x0C,   0x3D,   0x0C },
-        { STV0900_32APSK_34,    0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C },
-        { STV0900_32APSK_45,    0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C },
-        { STV0900_32APSK_56,    0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C },
-        { STV0900_32APSK_89,    0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C },
-        { STV0900_32APSK_910,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C }
+        /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon
+                                10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+        { STV0900_16APSK_23,    0x0C,   0x0C,   0x0C,   0x0C,   0x1D,
+                                0x0C,   0x3C,   0x0C,   0x2C,   0x0C },
+        { STV0900_16APSK_34,    0x0C,   0x0C,   0x0C,   0x0C,   0x0E,
+                                0x0C,   0x2D,   0x0C,   0x1D,   0x0C },
+        { STV0900_16APSK_45,    0x0C,   0x0C,   0x0C,   0x0C,   0x1E,
+                                0x0C,   0x3D,   0x0C,   0x2D,   0x0C },
+        { STV0900_16APSK_56,    0x0C,   0x0C,   0x0C,   0x0C,   0x1E,
+                                0x0C,   0x3D,   0x0C,   0x2D,   0x0C },
+        { STV0900_16APSK_89,    0x0C,   0x0C,   0x0C,   0x0C,   0x2E,
+                                0x0C,   0x0E,   0x0C,   0x3D,   0x0C },
+        { STV0900_16APSK_910,   0x0C,   0x0C,   0x0C,   0x0C,   0x2E,
+                                0x0C,   0x0E,   0x0C,   0x3D,   0x0C },
+        { STV0900_32APSK_34,    0x0C,   0x0C,   0x0C,   0x0C,   0x0C,
+                                0x0C,   0x0C,   0x0C,   0x0C,   0x0C },
+        { STV0900_32APSK_45,    0x0C,   0x0C,   0x0C,   0x0C,   0x0C,
+                                0x0C,   0x0C,   0x0C,   0x0C,   0x0C },
+        { STV0900_32APSK_56,    0x0C,   0x0C,   0x0C,   0x0C,   0x0C,
+                                0x0C,   0x0C,   0x0C,   0x0C,   0x0C },
+        { STV0900_32APSK_89,    0x0C,   0x0C,   0x0C,   0x0C,   0x0C,
+                                0x0C,   0x0C,   0x0C,   0x0C,   0x0C },
+        { STV0900_32APSK_910,   0x0C,   0x0C,   0x0C,   0x0C,   0x0C,
+                                0x0C,   0x0C,   0x0C,   0x0C,   0x0C },
 };
 
 
 /* Cut 2.0 Tracking carrier loop carrier QPSK 1/4 to QPSK 2/5 long Frame */
 static const struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut20[3] = {
-        /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon  10MPoff 20MPon  20MPoff 30MPon  30MPoff */
-        { STV0900_QPSK_14,      0x0F,   0x3F,   0x0E,   0x3F,   0x2D,   0x2F,   0x2D,   0x1F,   0x3D,   0x3E },
-        { STV0900_QPSK_13,      0x0F,   0x3F,   0x0E,   0x3F,   0x2D,   0x2F,   0x3D,   0x0F,   0x3D,   0x2E },
-        { STV0900_QPSK_25,      0x1F,   0x3F,   0x1E,   0x3F,   0x3D,   0x1F,   0x3D,   0x3E,   0x3D,   0x2E }
+        /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon
+                                10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+        { STV0900_QPSK_14,      0x0F,   0x3F,   0x0E,   0x3F,   0x2D,
+                                0x2F,   0x2D,   0x1F,   0x3D,   0x3E },
+        { STV0900_QPSK_13,      0x0F,   0x3F,   0x0E,   0x3F,   0x2D,
+                                0x2F,   0x3D,   0x0F,   0x3D,   0x2E },
+        { STV0900_QPSK_25,      0x1F,   0x3F,   0x1E,   0x3F,   0x3D,
+                                0x1F,   0x3D,   0x3E,   0x3D,   0x2E }
 };
 
 
 /* Cut 2.0 Tracking carrier loop carrier  short Frame, cut 1.2 and 2.0 */
-static const struct stv0900_short_frames_car_loop_optim FE_STV0900_S2ShortCarLoop[4]    = {
-        /*Mod   2M_cut1.2 2M_cut2.0 5M_cut1.2 5M_cut2.0 10M_cut1.2 10M_cut2.0 20M_cut1.2 20M_cut2.0 30M_cut1.2 30M_cut2.0 */
-        { STV0900_QPSK,         0x3C,   0x2F,   0x2B,   0x2E,   0x0B,   0x0E,   0x3A,   0x0E,   0x2A,   0x3D },
-        { STV0900_8PSK,         0x0B,   0x3E,   0x2A,   0x0E,   0x0A,   0x2D,   0x19,   0x0D,   0x09,   0x3C },
-        { STV0900_16APSK,       0x1B,   0x1E,   0x1B,   0x1E,   0x1B,   0x1E,   0x3A,   0x3D,   0x2A,   0x2D },
-        { STV0900_32APSK,       0x1B,   0x1E,   0x1B,   0x1E,   0x1B,   0x1E,   0x3A,   0x3D,   0x2A,   0x2D }
+static const
+struct stv0900_short_frames_car_loop_optim FE_STV0900_S2ShortCarLoop[4] = {
+        /*Mod           2Mcut1.2 2Mcut2.0 5Mcut1.2 5Mcut2.0 10Mcut1.2
+                        10Mcut2.0 20Mcut1.2 20M_cut2.0 30Mcut1.2 30Mcut2.0*/
+        { STV0900_QPSK,         0x3C,   0x2F,   0x2B,   0x2E,   0x0B,
+                                0x0E,   0x3A,   0x0E,   0x2A,   0x3D },
+        { STV0900_8PSK,         0x0B,   0x3E,   0x2A,   0x0E,   0x0A,
+                                0x2D,   0x19,   0x0D,   0x09,   0x3C },
+        { STV0900_16APSK,       0x1B,   0x1E,   0x1B,   0x1E,   0x1B,
+                                0x1E,   0x3A,   0x3D,   0x2A,   0x2D },
+        { STV0900_32APSK,       0x1B,   0x1E,   0x1B,   0x1E,   0x1B,
+                                0x1E,   0x3A,   0x3D,   0x2A,   0x2D }
+};
+
+static  const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut30[14] = {
+        /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
+                                10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+        { STV0900_QPSK_12,      0x3C,   0x2C,   0x0C,   0x2C,   0x1B,
+                                0x2C,   0x1B,   0x1C,   0x0B,   0x3B },
+        { STV0900_QPSK_35,      0x0D,   0x0D,   0x0C,   0x0D,   0x1B,
+                                0x3C,   0x1B,   0x1C,   0x0B,   0x3B },
+        { STV0900_QPSK_23,      0x1D,   0x0D,   0x0C,   0x1D,   0x2B,
+                                0x3C,   0x1B,   0x1C,   0x0B,   0x3B },
+        { STV0900_QPSK_34,      0x1D,   0x1D,   0x0C,   0x1D,   0x2B,
+                                0x3C,   0x1B,   0x1C,   0x0B,   0x3B },
+        { STV0900_QPSK_45,      0x2D,   0x1D,   0x1C,   0x1D,   0x2B,
+                                0x3C,   0x2B,   0x0C,   0x1B,   0x3B },
+        { STV0900_QPSK_56,      0x2D,   0x1D,   0x1C,   0x1D,   0x2B,
+                                0x3C,   0x2B,   0x0C,   0x1B,   0x3B },
+        { STV0900_QPSK_89,      0x3D,   0x2D,   0x1C,   0x1D,   0x3B,
+                                0x3C,   0x2B,   0x0C,   0x1B,   0x3B },
+        { STV0900_QPSK_910,     0x3D,   0x2D,   0x1C,   0x1D,   0x3B,
+                                0x3C,   0x2B,   0x0C,   0x1B,   0x3B },
+        { STV0900_8PSK_35,      0x39,   0x19,   0x39,   0x19,   0x19,
+                                0x19,   0x19,   0x19,   0x09,   0x19 },
+        { STV0900_8PSK_23,      0x2A,   0x39,   0x1A,   0x0A,   0x39,
+                                0x0A,   0x29,   0x39,   0x29,   0x0A },
+        { STV0900_8PSK_34,      0x0B,   0x3A,   0x0B,   0x0B,   0x3A,
+                                0x1B,   0x1A,   0x0B,   0x1A,   0x3A },
+        { STV0900_8PSK_56,      0x0C,   0x1B,   0x3B,   0x2B,   0x1B,
+                                0x3B,   0x3A,   0x3B,   0x3A,   0x1B },
+        { STV0900_8PSK_89,      0x2C,   0x2C,   0x2C,   0x1C,   0x2B,
+                                0x0C,   0x0B,   0x3B,   0x0B,   0x1B },
+        { STV0900_8PSK_910,     0x2C,   0x3C,   0x2C,   0x1C,   0x3B,
+                                0x1C,   0x0B,   0x3B,   0x0B,   0x1B }
+};
+
+static  const
+struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut30[11] = {
+        /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
+                                10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+        { STV0900_16APSK_23,    0x0A,   0x0A,   0x0A,   0x0A,   0x1A,
+                                0x0A,   0x3A,   0x0A,   0x2A,   0x0A },
+        { STV0900_16APSK_34,    0x0A,   0x0A,   0x0A,   0x0A,   0x0B,
+                                0x0A,   0x3B,   0x0A,   0x1B,   0x0A },
+        { STV0900_16APSK_45,    0x0A,   0x0A,   0x0A,   0x0A,   0x1B,
+                                0x0A,   0x3B,   0x0A,   0x2B,   0x0A },
+        { STV0900_16APSK_56,    0x0A,   0x0A,   0x0A,   0x0A,   0x1B,
+                                0x0A,   0x3B,   0x0A,   0x2B,   0x0A },
+        { STV0900_16APSK_89,    0x0A,   0x0A,   0x0A,   0x0A,   0x2B,
+                                0x0A,   0x0C,   0x0A,   0x3B,   0x0A },
+        { STV0900_16APSK_910,   0x0A,   0x0A,   0x0A,   0x0A,   0x2B,
+                                0x0A,   0x0C,   0x0A,   0x3B,   0x0A },
+        { STV0900_32APSK_34,    0x0A,   0x0A,   0x0A,   0x0A,   0x0A,
+                                0x0A,   0x0A,   0x0A,   0x0A,   0x0A },
+        { STV0900_32APSK_45,    0x0A,   0x0A,   0x0A,   0x0A,   0x0A,
+                                0x0A,   0x0A,   0x0A,   0x0A,   0x0A },
+        { STV0900_32APSK_56,    0x0A,   0x0A,   0x0A,   0x0A,   0x0A,
+                                0x0A,   0x0A,   0x0A,   0x0A,   0x0A },
+        { STV0900_32APSK_89,    0x0A,   0x0A,   0x0A,   0x0A,   0x0A,
+                                0x0A,   0x0A,   0x0A,   0x0A,   0x0A },
+        { STV0900_32APSK_910,   0x0A,   0x0A,   0x0A,   0x0A,   0x0A,
+                                0x0A,   0x0A,   0x0A,   0x0A,   0x0A }
+};
+
+static  const
+struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut30[3] = {
+        /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
+                                10MPoff 20MPon  20MPoff 30MPon  30MPoff*/
+        { STV0900_QPSK_14,      0x0C,   0x3C,   0x0B,   0x3C,   0x2A,
+                                0x2C,   0x2A,   0x1C,   0x3A,   0x3B },
+        { STV0900_QPSK_13,      0x0C,   0x3C,   0x0B,   0x3C,   0x2A,
+                                0x2C,   0x3A,   0x0C,   0x3A,   0x2B },
+        { STV0900_QPSK_25,      0x1C,   0x3C,   0x1B,   0x3C,   0x3A,
+                                0x1C,   0x3A,   0x3B,   0x3A,   0x2B }
+};
+
+static  const struct stv0900_short_frames_car_loop_optim_vs_mod
+FE_STV0900_S2ShortCarLoopCut30[4] = {
+        /*Mod           2Mcut3.0 5Mcut3.0 10Mcut3.0 20Mcut3.0 30Mcut3.0*/
+        { STV0900_QPSK,         0x2C,   0x2B,   0x0B,   0x0B,   0x3A },
+        { STV0900_8PSK,         0x3B,   0x0B,   0x2A,   0x0A,   0x39 },
+        { STV0900_16APSK,       0x1B,   0x1B,   0x1B,   0x3A,   0x2A },
+        { STV0900_32APSK,       0x1B,   0x1B,   0x1B,   0x3A,   0x2A },
+
 };
 
-static const u16 STV0900_InitVal[182][2] = {
+static const u16 STV0900_InitVal[181][2] = {
         { R0900_OUTCFG          , 0x00  },
-        { R0900_MODECFG         , 0xff  },
         { R0900_AGCRF1CFG       , 0x11  },
         { R0900_AGCRF2CFG       , 0x13  },
         { R0900_TSGENERAL1X     , 0x14  },
@@ -381,7 +524,7 @@ static const u16 STV0900_InitVal[182][2] = {
         { R0900_GAINLLR_NF15    , 0x1A  },
         { R0900_GAINLLR_NF16    , 0x1F  },
         { R0900_GAINLLR_NF17    , 0x21  },
-        { R0900_RCCFGH          , 0x20  },
+        { R0900_RCCFG2          , 0x20  },
         { R0900_P1_FECM         , 0x01  }, /*disable DSS modes*/
         { R0900_P2_FECM         , 0x01  }, /*disable DSS modes*/
         { R0900_P1_PRVIT        , 0x2F  }, /*disable puncture rate 6/7*/
diff --git a/drivers/media/dvb/frontends/stv0900_priv.h b/drivers/media/dvb/frontends/stv0900_priv.h
index 5ed7a145c7d3..b62b0f0a4fef 100644
--- a/drivers/media/dvb/frontends/stv0900_priv.h
+++ b/drivers/media/dvb/frontends/stv0900_priv.h
@@ -46,22 +46,6 @@
 #define FALSE (!TRUE)
 #endif
 
-#define dmd_reg(a, b, c) \
-        do { \
-                a = 0; \
-                switch (demod) { \
-                case STV0900_DEMOD_1: \
-                default: \
-                        a = b; \
-                        break; \
-                case STV0900_DEMOD_2: \
-                        a = c; \
-                        break; \
-                } \
-        } while (0)
-
-static int stvdebug;
-
 #define dprintk(args...) \
         do { \
                 if (stvdebug) \
@@ -70,6 +54,8 @@ static int stvdebug;
 
 #define STV0900_MAXLOOKUPSIZE 500
 #define STV0900_BLIND_SEARCH_AGC2_TH 700
+#define STV0900_BLIND_SEARCH_AGC2_TH_CUT30 1400
+#define IQPOWER_THRESHOLD  30
 
 /* One point of the lookup table */
 struct stv000_lookpoint {
@@ -261,16 +247,18 @@ struct stv0900_init_params{
 
         u8      tun1_maddress;
         int     tuner1_adc;
+        int     tuner1_type;
 
         /* IQ from the tuner1 to the demod */
-        enum stv0900_iq_inversion       tun1_iq_inversion;
+        enum stv0900_iq_inversion       tun1_iq_inv;
         enum fe_stv0900_clock_type      path2_ts_clock;
 
         u8      tun2_maddress;
         int     tuner2_adc;
+        int     tuner2_type;
 
         /* IQ from the tuner2 to the demod */
-        enum stv0900_iq_inversion       tun2_iq_inversion;
+        enum stv0900_iq_inversion       tun2_iq_inv;
         struct stv0900_reg              *ts_config;
 };
 
@@ -300,7 +288,7 @@ struct stv0900_signal_info {
         enum fe_stv0900_modcode                 modcode;
         enum fe_stv0900_modulation              modulation;
         enum fe_stv0900_pilot                   pilot;
-        enum fe_stv0900_frame_length            frame_length;
+        enum fe_stv0900_frame_length            frame_len;
         enum stv0900_iq_inversion               spectrum;
         enum fe_stv0900_rolloff                 rolloff;
 
@@ -318,47 +306,27 @@ struct stv0900_internal{
         /* Demodulator use for single demod or for dual demod) */
         enum fe_stv0900_demod_mode      demod_mode;
 
-        /*Demod 1*/
-        s32     tuner1_freq;
-        s32     tuner1_bw;
-        s32     dmd1_symbol_rate;
-        s32     dmd1_srch_range;
+        /*Demods */
+        s32     freq[2];
+        s32     bw[2];
+        s32     symbol_rate[2];
+        s32     srch_range[2];
+        /* for software/auto tuner */
+        int     tuner_type[2];
 
         /* algorithm for search Blind, Cold or Warm*/
-        enum fe_stv0900_search_algo     dmd1_srch_algo;
+        enum fe_stv0900_search_algo     srch_algo[2];
         /* search standard: Auto, DVBS1/DSS only or DVBS2 only*/
-        enum fe_stv0900_search_standard dmd1_srch_standard;
+        enum fe_stv0900_search_standard srch_standard[2];
         /* inversion search : auto, auto norma first, normal or inverted */
-        enum fe_stv0900_search_iq       dmd1_srch_iq_inv;
-        enum fe_stv0900_modcode         dmd1_modcode;
-        enum fe_stv0900_modulation      dmd1_modulation;
-        enum fe_stv0900_fec             dmd1_fec;
-
-        struct stv0900_signal_info      dmd1_rslts;
-        enum fe_stv0900_signal_type     dmd1_state;
-
-        enum fe_stv0900_error           dmd1_err;
+        enum fe_stv0900_search_iq       srch_iq_inv[2];
+        enum fe_stv0900_modcode         modcode[2];
+        enum fe_stv0900_modulation      modulation[2];
+        enum fe_stv0900_fec             fec[2];
 
-        /*Demod 2*/
-        s32     tuner2_freq;
-        s32     tuner2_bw;
-        s32     dmd2_symbol_rate;
-        s32     dmd2_srch_range;
+        struct stv0900_signal_info      result[2];
+        enum fe_stv0900_error           err[2];
 
-        enum fe_stv0900_search_algo     dmd2_srch_algo;
-        enum fe_stv0900_search_standard dmd2_srch_stndrd;
-        /* inversion search : auto, auto normal first, normal or inverted */
-        enum fe_stv0900_search_iq       dmd2_srch_iq_inv;
-        enum fe_stv0900_modcode         dmd2_modcode;
-        enum fe_stv0900_modulation      dmd2_modulation;
-        enum fe_stv0900_fec             dmd2_fec;
-
-        /* results of the search*/
-        struct stv0900_signal_info      dmd2_rslts;
-        /* current state of the search algorithm */
-        enum fe_stv0900_signal_type     dmd2_state;
-
-        enum fe_stv0900_error           dmd2_err;
 
         struct i2c_adapter      *i2c_adap;
         u8                      i2c_addr;
@@ -379,6 +347,8 @@ struct stv0900_state {
         int demod;
 };
 
+extern int stvdebug;
+
 extern s32 ge2comp(s32 a, s32 width);
 
 extern void stv0900_write_reg(struct stv0900_internal *i_params,
@@ -418,13 +388,21 @@ extern u8 stv0900_get_optim_short_carr_loop(s32 srate,
 extern void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
                                 enum fe_stv0900_demod_num demod);
 
-extern void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
+extern void stv0900_activate_s2_modcod(struct stv0900_internal *i_params,
                                 enum fe_stv0900_demod_num demod);
 
-extern void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params,
+extern void stv0900_activate_s2_modcod_single(struct stv0900_internal *i_params,
                                 enum fe_stv0900_demod_num demod);
 
-extern enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
+extern enum
+fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
                                 enum fe_stv0900_demod_num demod);
 
+extern u32
+stv0900_get_freq_auto(struct stv0900_internal *intp, int demod);
+
+extern void
+stv0900_set_tuner_auto(struct stv0900_internal *intp, u32 Frequency,
+                                                u32 Bandwidth, int demod);
+
 #endif
diff --git a/drivers/media/dvb/frontends/stv0900_reg.h b/drivers/media/dvb/frontends/stv0900_reg.h
index 264f9cf9a17e..731afe93a823 100644
--- a/drivers/media/dvb/frontends/stv0900_reg.h
+++ b/drivers/media/dvb/frontends/stv0900_reg.h
@@ -14,7 +14,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  *
  * GNU General Public License for more details.
  *
@@ -26,3762 +26,3956 @@
 #ifndef STV0900_REG_H
 #define STV0900_REG_H
 
+extern s32 shiftx(s32 x, int demod, s32 shift);
+
+#define REGx(x) shiftx(x, demod, 0x200)
+#define FLDx(x) shiftx(x, demod, 0x2000000)
+
 /*MID*/
-#define R0900_MID  0xf100
-#define F0900_MCHIP_IDENT  0xf10000f0
-#define F0900_MRELEASE  0xf100000f
+#define R0900_MID 0xf100
+#define F0900_MCHIP_IDENT 0xf10000f0
+#define F0900_MRELEASE 0xf100000f
 
 /*DACR1*/
-#define R0900_DACR1  0xf113
-#define F0900_DAC_MODE  0xf11300e0
-#define F0900_DAC_VALUE1  0xf113000f
+#define R0900_DACR1 0xf113
+#define F0900_DAC_MODE 0xf11300e0
+#define F0900_DAC_VALUE1 0xf113000f
 
 /*DACR2*/
-#define R0900_DACR2  0xf114
-#define F0900_DAC_VALUE0  0xf11400ff
+#define R0900_DACR2 0xf114
+#define F0900_DAC_VALUE0 0xf11400ff
 
 /*OUTCFG*/
-#define R0900_OUTCFG  0xf11c
-#define F0900_INV_DATA6  0xf11c0080
-#define F0900_OUTSERRS1_HZ  0xf11c0040
-#define F0900_OUTSERRS2_HZ  0xf11c0020
-#define F0900_OUTSERRS3_HZ  0xf11c0010
-#define F0900_OUTPARRS3_HZ  0xf11c0008
-#define F0900_OUTHZ3_CONTROL  0xf11c0007
-
-/*MODECFG*/
-#define R0900_MODECFG  0xf11d
-#define F0900_FECSPY_SEL_2  0xf11d0020
-#define F0900_HWARE_SEL_2  0xf11d0010
-#define F0900_PKTDEL_SEL_2  0xf11d0008
-#define F0900_DISEQC_SEL_2  0xf11d0004
-#define F0900_VIT_SEL_2  0xf11d0002
-#define F0900_DEMOD_SEL_2  0xf11d0001
+#define R0900_OUTCFG 0xf11c
+#define F0900_OUTSERRS1_HZ 0xf11c0040
+#define F0900_OUTSERRS2_HZ 0xf11c0020
+#define F0900_OUTSERRS3_HZ 0xf11c0010
+#define F0900_OUTPARRS3_HZ 0xf11c0008
 
 /*IRQSTATUS3*/
-#define R0900_IRQSTATUS3  0xf120
-#define F0900_SPLL_LOCK  0xf1200020
-#define F0900_SSTREAM_LCK_3  0xf1200010
-#define F0900_SSTREAM_LCK_2  0xf1200008
-#define F0900_SSTREAM_LCK_1  0xf1200004
-#define F0900_SDVBS1_PRF_2  0xf1200002
-#define F0900_SDVBS1_PRF_1  0xf1200001
+#define R0900_IRQSTATUS3 0xf120
+#define F0900_SPLL_LOCK 0xf1200020
+#define F0900_SSTREAM_LCK_3 0xf1200010
+#define F0900_SSTREAM_LCK_2 0xf1200008
+#define F0900_SSTREAM_LCK_1 0xf1200004
+#define F0900_SDVBS1_PRF_2 0xf1200002
+#define F0900_SDVBS1_PRF_1 0xf1200001
 
 /*IRQSTATUS2*/
-#define R0900_IRQSTATUS2  0xf121
-#define F0900_SSPY_ENDSIM_3  0xf1210080
-#define F0900_SSPY_ENDSIM_2  0xf1210040
-#define F0900_SSPY_ENDSIM_1  0xf1210020
-#define F0900_SPKTDEL_ERROR_2  0xf1210010
-#define F0900_SPKTDEL_LOCKB_2  0xf1210008
-#define F0900_SPKTDEL_LOCK_2  0xf1210004
-#define F0900_SPKTDEL_ERROR_1  0xf1210002
-#define F0900_SPKTDEL_LOCKB_1  0xf1210001
+#define R0900_IRQSTATUS2 0xf121
+#define F0900_SSPY_ENDSIM_3 0xf1210080
+#define F0900_SSPY_ENDSIM_2 0xf1210040
+#define F0900_SSPY_ENDSIM_1 0xf1210020
+#define F0900_SPKTDEL_ERROR_2 0xf1210010
+#define F0900_SPKTDEL_LOCKB_2 0xf1210008
+#define F0900_SPKTDEL_LOCK_2 0xf1210004
+#define F0900_SPKTDEL_ERROR_1 0xf1210002
+#define F0900_SPKTDEL_LOCKB_1 0xf1210001
 
 /*IRQSTATUS1*/
-#define R0900_IRQSTATUS1  0xf122
-#define F0900_SPKTDEL_LOCK_1  0xf1220080
-#define F0900_SEXTPINB2  0xf1220040
-#define F0900_SEXTPIN2  0xf1220020
-#define F0900_SEXTPINB1  0xf1220010
-#define F0900_SEXTPIN1  0xf1220008
-#define F0900_SDEMOD_LOCKB_2  0xf1220004
-#define F0900_SDEMOD_LOCK_2  0xf1220002
-#define F0900_SDEMOD_IRQ_2  0xf1220001
+#define R0900_IRQSTATUS1 0xf122
+#define F0900_SPKTDEL_LOCK_1 0xf1220080
+#define F0900_SDEMOD_LOCKB_2 0xf1220004
+#define F0900_SDEMOD_LOCK_2 0xf1220002
+#define F0900_SDEMOD_IRQ_2 0xf1220001
 
 /*IRQSTATUS0*/
-#define R0900_IRQSTATUS0  0xf123
-#define F0900_SDEMOD_LOCKB_1  0xf1230080
-#define F0900_SDEMOD_LOCK_1  0xf1230040
-#define F0900_SDEMOD_IRQ_1  0xf1230020
-#define F0900_SBCH_ERRFLAG  0xf1230010
-#define F0900_SDISEQC2RX_IRQ  0xf1230008
-#define F0900_SDISEQC2TX_IRQ  0xf1230004
-#define F0900_SDISEQC1RX_IRQ  0xf1230002
-#define F0900_SDISEQC1TX_IRQ  0xf1230001
+#define R0900_IRQSTATUS0 0xf123
+#define F0900_SDEMOD_LOCKB_1 0xf1230080
+#define F0900_SDEMOD_LOCK_1 0xf1230040
+#define F0900_SDEMOD_IRQ_1 0xf1230020
+#define F0900_SBCH_ERRFLAG 0xf1230010
+#define F0900_SDISEQC2RX_IRQ 0xf1230008
+#define F0900_SDISEQC2TX_IRQ 0xf1230004
+#define F0900_SDISEQC1RX_IRQ 0xf1230002
+#define F0900_SDISEQC1TX_IRQ 0xf1230001
 
 /*IRQMASK3*/
-#define R0900_IRQMASK3  0xf124
-#define F0900_MPLL_LOCK  0xf1240020
-#define F0900_MSTREAM_LCK_3  0xf1240010
-#define F0900_MSTREAM_LCK_2  0xf1240008
-#define F0900_MSTREAM_LCK_1  0xf1240004
-#define F0900_MDVBS1_PRF_2  0xf1240002
-#define F0900_MDVBS1_PRF_1  0xf1240001
+#define R0900_IRQMASK3 0xf124
+#define F0900_MPLL_LOCK 0xf1240020
+#define F0900_MSTREAM_LCK_3 0xf1240010
+#define F0900_MSTREAM_LCK_2 0xf1240008
+#define F0900_MSTREAM_LCK_1 0xf1240004
+#define F0900_MDVBS1_PRF_2 0xf1240002
+#define F0900_MDVBS1_PRF_1 0xf1240001
 
 /*IRQMASK2*/
-#define R0900_IRQMASK2  0xf125
-#define F0900_MSPY_ENDSIM_3  0xf1250080
-#define F0900_MSPY_ENDSIM_2  0xf1250040
-#define F0900_MSPY_ENDSIM_1  0xf1250020
-#define F0900_MPKTDEL_ERROR_2  0xf1250010
-#define F0900_MPKTDEL_LOCKB_2  0xf1250008
-#define F0900_MPKTDEL_LOCK_2  0xf1250004
-#define F0900_MPKTDEL_ERROR_1  0xf1250002
-#define F0900_MPKTDEL_LOCKB_1  0xf1250001
+#define R0900_IRQMASK2 0xf125
+#define F0900_MSPY_ENDSIM_3 0xf1250080
+#define F0900_MSPY_ENDSIM_2 0xf1250040
+#define F0900_MSPY_ENDSIM_1 0xf1250020
+#define F0900_MPKTDEL_ERROR_2 0xf1250010
+#define F0900_MPKTDEL_LOCKB_2 0xf1250008
+#define F0900_MPKTDEL_LOCK_2 0xf1250004
+#define F0900_MPKTDEL_ERROR_1 0xf1250002
+#define F0900_MPKTDEL_LOCKB_1 0xf1250001
 
 /*IRQMASK1*/
-#define R0900_IRQMASK1  0xf126
-#define F0900_MPKTDEL_LOCK_1  0xf1260080
-#define F0900_MEXTPINB2  0xf1260040
-#define F0900_MEXTPIN2  0xf1260020
-#define F0900_MEXTPINB1  0xf1260010
-#define F0900_MEXTPIN1  0xf1260008
-#define F0900_MDEMOD_LOCKB_2  0xf1260004
-#define F0900_MDEMOD_LOCK_2  0xf1260002
-#define F0900_MDEMOD_IRQ_2  0xf1260001
+#define R0900_IRQMASK1 0xf126
+#define F0900_MPKTDEL_LOCK_1 0xf1260080
+#define F0900_MEXTPINB2 0xf1260040
+#define F0900_MEXTPIN2 0xf1260020
+#define F0900_MEXTPINB1 0xf1260010
+#define F0900_MEXTPIN1 0xf1260008
+#define F0900_MDEMOD_LOCKB_2 0xf1260004
+#define F0900_MDEMOD_LOCK_2 0xf1260002
+#define F0900_MDEMOD_IRQ_2 0xf1260001
 
 /*IRQMASK0*/
-#define R0900_IRQMASK0  0xf127
-#define F0900_MDEMOD_LOCKB_1  0xf1270080
-#define F0900_MDEMOD_LOCK_1  0xf1270040
-#define F0900_MDEMOD_IRQ_1  0xf1270020
-#define F0900_MBCH_ERRFLAG  0xf1270010
-#define F0900_MDISEQC2RX_IRQ  0xf1270008
-#define F0900_MDISEQC2TX_IRQ  0xf1270004
-#define F0900_MDISEQC1RX_IRQ  0xf1270002
-#define F0900_MDISEQC1TX_IRQ  0xf1270001
+#define R0900_IRQMASK0 0xf127
+#define F0900_MDEMOD_LOCKB_1 0xf1270080
+#define F0900_MDEMOD_LOCK_1 0xf1270040
+#define F0900_MDEMOD_IRQ_1 0xf1270020
+#define F0900_MBCH_ERRFLAG 0xf1270010
+#define F0900_MDISEQC2RX_IRQ 0xf1270008
+#define F0900_MDISEQC2TX_IRQ 0xf1270004
+#define F0900_MDISEQC1RX_IRQ 0xf1270002
+#define F0900_MDISEQC1TX_IRQ 0xf1270001
 
 /*I2CCFG*/
-#define R0900_I2CCFG  0xf129
-#define F0900_I2C2_FASTMODE  0xf1290080
-#define F0900_STATUS_WR2  0xf1290040
-#define F0900_I2C2ADDR_INC  0xf1290030
-#define F0900_I2C_FASTMODE  0xf1290008
-#define F0900_STATUS_WR  0xf1290004
-#define F0900_I2CADDR_INC  0xf1290003
+#define R0900_I2CCFG 0xf129
+#define F0900_I2C_FASTMODE 0xf1290008
+#define F0900_I2CADDR_INC 0xf1290003
 
 /*P1_I2CRPT*/
-#define R0900_P1_I2CRPT  0xf12a
-#define F0900_P1_I2CT_ON  0xf12a0080
-#define F0900_P1_ENARPT_LEVEL  0xf12a0070
-#define F0900_P1_SCLT_DELAY  0xf12a0008
-#define F0900_P1_STOP_ENABLE  0xf12a0004
-#define F0900_P1_STOP_SDAT2SDA  0xf12a0002
+#define R0900_P1_I2CRPT 0xf12a
+#define I2CRPT shiftx(R0900_P1_I2CRPT, demod, -1)
+#define F0900_P1_I2CT_ON 0xf12a0080
+#define I2CT_ON shiftx(F0900_P1_I2CT_ON, demod, -0x10000)
+#define F0900_P1_ENARPT_LEVEL 0xf12a0070
+#define F0900_P1_SCLT_DELAY 0xf12a0008
+#define F0900_P1_STOP_ENABLE 0xf12a0004
+#define F0900_P1_STOP_SDAT2SDA 0xf12a0002
 
 /*P2_I2CRPT*/
-#define R0900_P2_I2CRPT  0xf12b
-#define F0900_P2_I2CT_ON  0xf12b0080
-#define F0900_P2_ENARPT_LEVEL  0xf12b0070
-#define F0900_P2_SCLT_DELAY  0xf12b0008
-#define F0900_P2_STOP_ENABLE  0xf12b0004
-#define F0900_P2_STOP_SDAT2SDA  0xf12b0002
+#define R0900_P2_I2CRPT 0xf12b
+#define F0900_P2_I2CT_ON 0xf12b0080
+#define F0900_P2_ENARPT_LEVEL 0xf12b0070
+#define F0900_P2_SCLT_DELAY 0xf12b0008
+#define F0900_P2_STOP_ENABLE 0xf12b0004
+#define F0900_P2_STOP_SDAT2SDA 0xf12b0002
+
+/*IOPVALUE6*/
+#define R0900_IOPVALUE6 0xf138
+#define F0900_VSCL 0xf1380004
+#define F0900_VSDA 0xf1380002
+#define F0900_VDATA3_0 0xf1380001
+
+/*IOPVALUE5*/
+#define R0900_IOPVALUE5 0xf139
+#define F0900_VDATA3_1 0xf1390080
+#define F0900_VDATA3_2 0xf1390040
+#define F0900_VDATA3_3 0xf1390020
+#define F0900_VDATA3_4 0xf1390010
+#define F0900_VDATA3_5 0xf1390008
+#define F0900_VDATA3_6 0xf1390004
+#define F0900_VDATA3_7 0xf1390002
+#define F0900_VCLKOUT3 0xf1390001
+
+/*IOPVALUE4*/
+#define R0900_IOPVALUE4 0xf13a
+#define F0900_VSTROUT3 0xf13a0080
+#define F0900_VDPN3 0xf13a0040
+#define F0900_VERROR3 0xf13a0020
+#define F0900_VDATA2_7 0xf13a0010
+#define F0900_VCLKOUT2 0xf13a0008
+#define F0900_VSTROUT2 0xf13a0004
+#define F0900_VDPN2 0xf13a0002
+#define F0900_VERROR2 0xf13a0001
+
+/*IOPVALUE3*/
+#define R0900_IOPVALUE3 0xf13b
+#define F0900_VDATA1_7 0xf13b0080
+#define F0900_VCLKOUT1 0xf13b0040
+#define F0900_VSTROUT1 0xf13b0020
+#define F0900_VDPN1 0xf13b0010
+#define F0900_VERROR1 0xf13b0008
+#define F0900_VCLKOUT27 0xf13b0004
+#define F0900_VDISEQCOUT2 0xf13b0002
+#define F0900_VSCLT2 0xf13b0001
+
+/*IOPVALUE2*/
+#define R0900_IOPVALUE2 0xf13c
+#define F0900_VSDAT2 0xf13c0080
+#define F0900_VAGCRF2 0xf13c0040
+#define F0900_VDISEQCOUT1 0xf13c0020
+#define F0900_VSCLT1 0xf13c0010
+#define F0900_VSDAT1 0xf13c0008
+#define F0900_VAGCRF1 0xf13c0004
+#define F0900_VDIRCLK 0xf13c0002
+#define F0900_VSTDBY 0xf13c0001
+
+/*IOPVALUE1*/
+#define R0900_IOPVALUE1 0xf13d
+#define F0900_VCS1 0xf13d0080
+#define F0900_VCS0 0xf13d0040
+#define F0900_VGPIO13 0xf13d0020
+#define F0900_VGPIO12 0xf13d0010
+#define F0900_VGPIO11 0xf13d0008
+#define F0900_VGPIO10 0xf13d0004
+#define F0900_VGPIO9 0xf13d0002
+#define F0900_VGPIO8 0xf13d0001
+
+/*IOPVALUE0*/
+#define R0900_IOPVALUE0 0xf13e
+#define F0900_VGPIO7 0xf13e0080
+#define F0900_VGPIO6 0xf13e0040
+#define F0900_VGPIO5 0xf13e0020
+#define F0900_VGPIO4 0xf13e0010
+#define F0900_VGPIO3 0xf13e0008
+#define F0900_VGPIO2 0xf13e0004
+#define F0900_VGPIO1 0xf13e0002
+#define F0900_VCLKI2 0xf13e0001
 
 /*CLKI2CFG*/
-#define R0900_CLKI2CFG  0xf140
-#define F0900_CLKI2_OPD  0xf1400080
-#define F0900_CLKI2_CONFIG  0xf140007e
-#define F0900_CLKI2_XOR  0xf1400001
+#define R0900_CLKI2CFG 0xf140
+#define F0900_CLKI2_OPD 0xf1400080
+#define F0900_CLKI2_CONFIG 0xf140007e
+#define F0900_CLKI2_XOR 0xf1400001
 
 /*GPIO1CFG*/
-#define R0900_GPIO1CFG  0xf141
-#define F0900_GPIO1_OPD  0xf1410080
-#define F0900_GPIO1_CONFIG  0xf141007e
-#define F0900_GPIO1_XOR  0xf1410001
+#define R0900_GPIO1CFG 0xf141
+#define F0900_GPIO1_OPD 0xf1410080
+#define F0900_GPIO1_CONFIG 0xf141007e
+#define F0900_GPIO1_XOR 0xf1410001
 
 /*GPIO2CFG*/
-#define R0900_GPIO2CFG  0xf142
-#define F0900_GPIO2_OPD  0xf1420080
-#define F0900_GPIO2_CONFIG  0xf142007e
-#define F0900_GPIO2_XOR  0xf1420001
+#define R0900_GPIO2CFG 0xf142
+#define F0900_GPIO2_OPD 0xf1420080
+#define F0900_GPIO2_CONFIG 0xf142007e
+#define F0900_GPIO2_XOR 0xf1420001
 
 /*GPIO3CFG*/
-#define R0900_GPIO3CFG  0xf143
-#define F0900_GPIO3_OPD  0xf1430080
-#define F0900_GPIO3_CONFIG  0xf143007e
-#define F0900_GPIO3_XOR  0xf1430001
+#define R0900_GPIO3CFG 0xf143
+#define F0900_GPIO3_OPD 0xf1430080
+#define F0900_GPIO3_CONFIG 0xf143007e
+#define F0900_GPIO3_XOR 0xf1430001
 
 /*GPIO4CFG*/
-#define R0900_GPIO4CFG  0xf144
-#define F0900_GPIO4_OPD  0xf1440080
-#define F0900_GPIO4_CONFIG  0xf144007e
-#define F0900_GPIO4_XOR  0xf1440001
+#define R0900_GPIO4CFG 0xf144
+#define F0900_GPIO4_OPD 0xf1440080
+#define F0900_GPIO4_CONFIG 0xf144007e
+#define F0900_GPIO4_XOR 0xf1440001
 
 /*GPIO5CFG*/
-#define R0900_GPIO5CFG  0xf145
-#define F0900_GPIO5_OPD  0xf1450080
-#define F0900_GPIO5_CONFIG  0xf145007e
-#define F0900_GPIO5_XOR  0xf1450001
+#define R0900_GPIO5CFG 0xf145
+#define F0900_GPIO5_OPD 0xf1450080
+#define F0900_GPIO5_CONFIG 0xf145007e
+#define F0900_GPIO5_XOR 0xf1450001
 
 /*GPIO6CFG*/
-#define R0900_GPIO6CFG  0xf146
-#define F0900_GPIO6_OPD  0xf1460080
-#define F0900_GPIO6_CONFIG  0xf146007e
-#define F0900_GPIO6_XOR  0xf1460001
+#define R0900_GPIO6CFG 0xf146
+#define F0900_GPIO6_OPD 0xf1460080
+#define F0900_GPIO6_CONFIG 0xf146007e
+#define F0900_GPIO6_XOR 0xf1460001
 
 /*GPIO7CFG*/
-#define R0900_GPIO7CFG  0xf147
-#define F0900_GPIO7_OPD  0xf1470080
-#define F0900_GPIO7_CONFIG  0xf147007e
-#define F0900_GPIO7_XOR  0xf1470001
+#define R0900_GPIO7CFG 0xf147
+#define F0900_GPIO7_OPD 0xf1470080
+#define F0900_GPIO7_CONFIG 0xf147007e
+#define F0900_GPIO7_XOR 0xf1470001
 
 /*GPIO8CFG*/
-#define R0900_GPIO8CFG  0xf148
-#define F0900_GPIO8_OPD  0xf1480080
-#define F0900_GPIO8_CONFIG  0xf148007e
-#define F0900_GPIO8_XOR  0xf1480001
+#define R0900_GPIO8CFG 0xf148
+#define F0900_GPIO8_OPD 0xf1480080
+#define F0900_GPIO8_CONFIG 0xf148007e
+#define F0900_GPIO8_XOR 0xf1480001
 
 /*GPIO9CFG*/
-#define R0900_GPIO9CFG  0xf149
-#define F0900_GPIO9_OPD  0xf1490080
-#define F0900_GPIO9_CONFIG  0xf149007e
-#define F0900_GPIO9_XOR  0xf1490001
+#define R0900_GPIO9CFG 0xf149
+#define F0900_GPIO9_OPD 0xf1490080
+#define F0900_GPIO9_CONFIG 0xf149007e
+#define F0900_GPIO9_XOR 0xf1490001
 
 /*GPIO10CFG*/
-#define R0900_GPIO10CFG  0xf14a
-#define F0900_GPIO10_OPD  0xf14a0080
-#define F0900_GPIO10_CONFIG  0xf14a007e
-#define F0900_GPIO10_XOR  0xf14a0001
+#define R0900_GPIO10CFG 0xf14a
+#define F0900_GPIO10_OPD 0xf14a0080
+#define F0900_GPIO10_CONFIG 0xf14a007e
+#define F0900_GPIO10_XOR 0xf14a0001
 
 /*GPIO11CFG*/
-#define R0900_GPIO11CFG  0xf14b
-#define F0900_GPIO11_OPD  0xf14b0080
-#define F0900_GPIO11_CONFIG  0xf14b007e
-#define F0900_GPIO11_XOR  0xf14b0001
+#define R0900_GPIO11CFG 0xf14b
+#define F0900_GPIO11_OPD 0xf14b0080
+#define F0900_GPIO11_CONFIG 0xf14b007e
+#define F0900_GPIO11_XOR 0xf14b0001
 
 /*GPIO12CFG*/
-#define R0900_GPIO12CFG  0xf14c
-#define F0900_GPIO12_OPD  0xf14c0080
-#define F0900_GPIO12_CONFIG  0xf14c007e
-#define F0900_GPIO12_XOR  0xf14c0001
+#define R0900_GPIO12CFG 0xf14c
+#define F0900_GPIO12_OPD 0xf14c0080
+#define F0900_GPIO12_CONFIG 0xf14c007e
+#define F0900_GPIO12_XOR 0xf14c0001
 
 /*GPIO13CFG*/
-#define R0900_GPIO13CFG  0xf14d
-#define F0900_GPIO13_OPD  0xf14d0080
-#define F0900_GPIO13_CONFIG  0xf14d007e
-#define F0900_GPIO13_XOR  0xf14d0001
+#define R0900_GPIO13CFG 0xf14d
+#define F0900_GPIO13_OPD 0xf14d0080
+#define F0900_GPIO13_CONFIG 0xf14d007e
+#define F0900_GPIO13_XOR 0xf14d0001
 
 /*CS0CFG*/
-#define R0900_CS0CFG  0xf14e
-#define F0900_CS0_OPD  0xf14e0080
-#define F0900_CS0_CONFIG  0xf14e007e
-#define F0900_CS0_XOR  0xf14e0001
+#define R0900_CS0CFG 0xf14e
+#define F0900_CS0_OPD 0xf14e0080
+#define F0900_CS0_CONFIG 0xf14e007e
+#define F0900_CS0_XOR 0xf14e0001
 
 /*CS1CFG*/
-#define R0900_CS1CFG  0xf14f
-#define F0900_CS1_OPD  0xf14f0080
-#define F0900_CS1_CONFIG  0xf14f007e
-#define F0900_CS1_XOR  0xf14f0001
+#define R0900_CS1CFG 0xf14f
+#define F0900_CS1_OPD 0xf14f0080
+#define F0900_CS1_CONFIG 0xf14f007e
+#define F0900_CS1_XOR 0xf14f0001
 
 /*STDBYCFG*/
-#define R0900_STDBYCFG  0xf150
-#define F0900_STDBY_OPD  0xf1500080
-#define F0900_STDBY_CONFIG  0xf150007e
-#define F0900_STBDY_XOR  0xf1500001
+#define R0900_STDBYCFG 0xf150
+#define F0900_STDBY_OPD 0xf1500080
+#define F0900_STDBY_CONFIG 0xf150007e
+#define F0900_STBDY_XOR 0xf1500001
 
 /*DIRCLKCFG*/
-#define R0900_DIRCLKCFG  0xf151
-#define F0900_DIRCLK_OPD  0xf1510080
-#define F0900_DIRCLK_CONFIG  0xf151007e
-#define F0900_DIRCLK_XOR  0xf1510001
+#define R0900_DIRCLKCFG 0xf151
+#define F0900_DIRCLK_OPD 0xf1510080
+#define F0900_DIRCLK_CONFIG 0xf151007e
+#define F0900_DIRCLK_XOR 0xf1510001
 
 /*AGCRF1CFG*/
-#define R0900_AGCRF1CFG  0xf152
-#define F0900_AGCRF1_OPD  0xf1520080
-#define F0900_AGCRF1_CONFIG  0xf152007e
-#define F0900_AGCRF1_XOR  0xf1520001
+#define R0900_AGCRF1CFG 0xf152
+#define F0900_AGCRF1_OPD 0xf1520080
+#define F0900_AGCRF1_CONFIG 0xf152007e
+#define F0900_AGCRF1_XOR 0xf1520001
 
 /*SDAT1CFG*/
-#define R0900_SDAT1CFG  0xf153
-#define F0900_SDAT1_OPD  0xf1530080
-#define F0900_SDAT1_CONFIG  0xf153007e
-#define F0900_SDAT1_XOR  0xf1530001
+#define R0900_SDAT1CFG 0xf153
+#define F0900_SDAT1_OPD 0xf1530080
+#define F0900_SDAT1_CONFIG 0xf153007e
+#define F0900_SDAT1_XOR 0xf1530001
 
 /*SCLT1CFG*/
-#define R0900_SCLT1CFG  0xf154
-#define F0900_SCLT1_OPD  0xf1540080
-#define F0900_SCLT1_CONFIG  0xf154007e
-#define F0900_SCLT1_XOR  0xf1540001
+#define R0900_SCLT1CFG 0xf154
+#define F0900_SCLT1_OPD 0xf1540080
+#define F0900_SCLT1_CONFIG 0xf154007e
+#define F0900_SCLT1_XOR 0xf1540001
 
 /*DISEQCO1CFG*/
-#define R0900_DISEQCO1CFG  0xf155
-#define F0900_DISEQCO1_OPD  0xf1550080
-#define F0900_DISEQCO1_CONFIG  0xf155007e
-#define F0900_DISEQC1_XOR  0xf1550001
+#define R0900_DISEQCO1CFG 0xf155
+#define F0900_DISEQCO1_OPD 0xf1550080
+#define F0900_DISEQCO1_CONFIG 0xf155007e
+#define F0900_DISEQC1_XOR 0xf1550001
 
 /*AGCRF2CFG*/
-#define R0900_AGCRF2CFG  0xf156
-#define F0900_AGCRF2_OPD  0xf1560080
-#define F0900_AGCRF2_CONFIG  0xf156007e
-#define F0900_AGCRF2_XOR  0xf1560001
+#define R0900_AGCRF2CFG 0xf156
+#define F0900_AGCRF2_OPD 0xf1560080
+#define F0900_AGCRF2_CONFIG 0xf156007e
+#define F0900_AGCRF2_XOR 0xf1560001
 
 /*SDAT2CFG*/
-#define R0900_SDAT2CFG  0xf157
-#define F0900_SDAT2_OPD  0xf1570080
-#define F0900_SDAT2_CONFIG  0xf157007e
-#define F0900_SDAT2_XOR  0xf1570001
+#define R0900_SDAT2CFG 0xf157
+#define F0900_SDAT2_OPD 0xf1570080
+#define F0900_SDAT2_CONFIG 0xf157007e
+#define F0900_SDAT2_XOR 0xf1570001
 
 /*SCLT2CFG*/
-#define R0900_SCLT2CFG  0xf158
-#define F0900_SCLT2_OPD  0xf1580080
-#define F0900_SCLT2_CONFIG  0xf158007e
-#define F0900_SCLT2_XOR  0xf1580001
+#define R0900_SCLT2CFG 0xf158
+#define F0900_SCLT2_OPD 0xf1580080
+#define F0900_SCLT2_CONFIG 0xf158007e
+#define F0900_SCLT2_XOR 0xf1580001
 
 /*DISEQCO2CFG*/
-#define R0900_DISEQCO2CFG  0xf159
-#define F0900_DISEQCO2_OPD  0xf1590080
-#define F0900_DISEQCO2_CONFIG  0xf159007e
-#define F0900_DISEQC2_XOR  0xf1590001
+#define R0900_DISEQCO2CFG 0xf159
+#define F0900_DISEQCO2_OPD 0xf1590080
+#define F0900_DISEQCO2_CONFIG 0xf159007e
+#define F0900_DISEQC2_XOR 0xf1590001
 
 /*CLKOUT27CFG*/
-#define R0900_CLKOUT27CFG  0xf15a
-#define F0900_CLKOUT27_OPD  0xf15a0080
-#define F0900_CLKOUT27_CONFIG  0xf15a007e
-#define F0900_CLKOUT27_XOR  0xf15a0001
+#define R0900_CLKOUT27CFG 0xf15a
+#define F0900_CLKOUT27_OPD 0xf15a0080
+#define F0900_CLKOUT27_CONFIG 0xf15a007e
+#define F0900_CLKOUT27_XOR 0xf15a0001
 
 /*ERROR1CFG*/
-#define R0900_ERROR1CFG  0xf15b
-#define F0900_ERROR1_OPD  0xf15b0080
-#define F0900_ERROR1_CONFIG  0xf15b007e
-#define F0900_ERROR1_XOR  0xf15b0001
+#define R0900_ERROR1CFG 0xf15b
+#define F0900_ERROR1_OPD 0xf15b0080
+#define F0900_ERROR1_CONFIG 0xf15b007e
+#define F0900_ERROR1_XOR 0xf15b0001
 
 /*DPN1CFG*/
-#define R0900_DPN1CFG  0xf15c
-#define F0900_DPN1_OPD  0xf15c0080
-#define F0900_DPN1_CONFIG  0xf15c007e
-#define F0900_DPN1_XOR  0xf15c0001
+#define R0900_DPN1CFG 0xf15c
+#define F0900_DPN1_OPD 0xf15c0080
+#define F0900_DPN1_CONFIG 0xf15c007e
+#define F0900_DPN1_XOR 0xf15c0001
 
 /*STROUT1CFG*/
-#define R0900_STROUT1CFG  0xf15d
-#define F0900_STROUT1_OPD  0xf15d0080
-#define F0900_STROUT1_CONFIG  0xf15d007e
-#define F0900_STROUT1_XOR  0xf15d0001
+#define R0900_STROUT1CFG 0xf15d
+#define F0900_STROUT1_OPD 0xf15d0080
+#define F0900_STROUT1_CONFIG 0xf15d007e
+#define F0900_STROUT1_XOR 0xf15d0001
 
 /*CLKOUT1CFG*/
-#define R0900_CLKOUT1CFG  0xf15e
-#define F0900_CLKOUT1_OPD  0xf15e0080
-#define F0900_CLKOUT1_CONFIG  0xf15e007e
-#define F0900_CLKOUT1_XOR  0xf15e0001
+#define R0900_CLKOUT1CFG 0xf15e
+#define F0900_CLKOUT1_OPD 0xf15e0080
+#define F0900_CLKOUT1_CONFIG 0xf15e007e
+#define F0900_CLKOUT1_XOR 0xf15e0001
 
 /*DATA71CFG*/
-#define R0900_DATA71CFG  0xf15f
-#define F0900_DATA71_OPD  0xf15f0080
-#define F0900_DATA71_CONFIG  0xf15f007e
-#define F0900_DATA71_XOR  0xf15f0001
+#define R0900_DATA71CFG 0xf15f
+#define F0900_DATA71_OPD 0xf15f0080
+#define F0900_DATA71_CONFIG 0xf15f007e
+#define F0900_DATA71_XOR 0xf15f0001
 
 /*ERROR2CFG*/
-#define R0900_ERROR2CFG  0xf160
-#define F0900_ERROR2_OPD  0xf1600080
-#define F0900_ERROR2_CONFIG  0xf160007e
-#define F0900_ERROR2_XOR  0xf1600001
+#define R0900_ERROR2CFG 0xf160
+#define F0900_ERROR2_OPD 0xf1600080
+#define F0900_ERROR2_CONFIG 0xf160007e
+#define F0900_ERROR2_XOR 0xf1600001
 
 /*DPN2CFG*/
-#define R0900_DPN2CFG  0xf161
-#define F0900_DPN2_OPD  0xf1610080
-#define F0900_DPN2_CONFIG  0xf161007e
-#define F0900_DPN2_XOR  0xf1610001
+#define R0900_DPN2CFG 0xf161
+#define F0900_DPN2_OPD 0xf1610080
+#define F0900_DPN2_CONFIG 0xf161007e
+#define F0900_DPN2_XOR 0xf1610001
 
 /*STROUT2CFG*/
-#define R0900_STROUT2CFG  0xf162
-#define F0900_STROUT2_OPD  0xf1620080
-#define F0900_STROUT2_CONFIG  0xf162007e
-#define F0900_STROUT2_XOR  0xf1620001
+#define R0900_STROUT2CFG 0xf162
+#define F0900_STROUT2_OPD 0xf1620080
+#define F0900_STROUT2_CONFIG 0xf162007e
+#define F0900_STROUT2_XOR 0xf1620001
 
 /*CLKOUT2CFG*/
-#define R0900_CLKOUT2CFG  0xf163
-#define F0900_CLKOUT2_OPD  0xf1630080
-#define F0900_CLKOUT2_CONFIG  0xf163007e
-#define F0900_CLKOUT2_XOR  0xf1630001
+#define R0900_CLKOUT2CFG 0xf163
+#define F0900_CLKOUT2_OPD 0xf1630080
+#define F0900_CLKOUT2_CONFIG 0xf163007e
+#define F0900_CLKOUT2_XOR 0xf1630001
 
 /*DATA72CFG*/
-#define R0900_DATA72CFG  0xf164
-#define F0900_DATA72_OPD  0xf1640080
-#define F0900_DATA72_CONFIG  0xf164007e
-#define F0900_DATA72_XOR  0xf1640001
+#define R0900_DATA72CFG 0xf164
+#define F0900_DATA72_OPD 0xf1640080
+#define F0900_DATA72_CONFIG 0xf164007e
+#define F0900_DATA72_XOR 0xf1640001
 
 /*ERROR3CFG*/
-#define R0900_ERROR3CFG  0xf165
-#define F0900_ERROR3_OPD  0xf1650080
-#define F0900_ERROR3_CONFIG  0xf165007e
-#define F0900_ERROR3_XOR  0xf1650001
+#define R0900_ERROR3CFG 0xf165
+#define F0900_ERROR3_OPD 0xf1650080
+#define F0900_ERROR3_CONFIG 0xf165007e
+#define F0900_ERROR3_XOR 0xf1650001
 
 /*DPN3CFG*/
-#define R0900_DPN3CFG  0xf166
-#define F0900_DPN3_OPD  0xf1660080
-#define F0900_DPN3_CONFIG  0xf166007e
-#define F0900_DPN3_XOR  0xf1660001
+#define R0900_DPN3CFG 0xf166
+#define F0900_DPN3_OPD 0xf1660080
+#define F0900_DPN3_CONFIG 0xf166007e
+#define F0900_DPN3_XOR 0xf1660001
 
 /*STROUT3CFG*/
-#define R0900_STROUT3CFG  0xf167
-#define F0900_STROUT3_OPD  0xf1670080
-#define F0900_STROUT3_CONFIG  0xf167007e
-#define F0900_STROUT3_XOR  0xf1670001
+#define R0900_STROUT3CFG 0xf167
+#define F0900_STROUT3_OPD 0xf1670080
+#define F0900_STROUT3_CONFIG 0xf167007e
+#define F0900_STROUT3_XOR 0xf1670001
 
 /*CLKOUT3CFG*/
-#define R0900_CLKOUT3CFG  0xf168
-#define F0900_CLKOUT3_OPD  0xf1680080
-#define F0900_CLKOUT3_CONFIG  0xf168007e
-#define F0900_CLKOUT3_XOR  0xf1680001
+#define R0900_CLKOUT3CFG 0xf168
+#define F0900_CLKOUT3_OPD 0xf1680080
+#define F0900_CLKOUT3_CONFIG 0xf168007e
+#define F0900_CLKOUT3_XOR 0xf1680001
 
 /*DATA73CFG*/
-#define R0900_DATA73CFG  0xf169
-#define F0900_DATA73_OPD  0xf1690080
-#define F0900_DATA73_CONFIG  0xf169007e
-#define F0900_DATA73_XOR  0xf1690001
+#define R0900_DATA73CFG 0xf169
+#define F0900_DATA73_OPD 0xf1690080
+#define F0900_DATA73_CONFIG 0xf169007e
+#define F0900_DATA73_XOR 0xf1690001
+
+/*STRSTATUS1*/
+#define R0900_STRSTATUS1 0xf16a
+#define F0900_STRSTATUS_SEL2 0xf16a00f0
+#define F0900_STRSTATUS_SEL1 0xf16a000f
+
+/*STRSTATUS2*/
+#define R0900_STRSTATUS2 0xf16b
+#define F0900_STRSTATUS_SEL4 0xf16b00f0
+#define F0900_STRSTATUS_SEL3 0xf16b000f
+
+/*STRSTATUS3*/
+#define R0900_STRSTATUS3 0xf16c
+#define F0900_STRSTATUS_SEL6 0xf16c00f0
+#define F0900_STRSTATUS_SEL5 0xf16c000f
 
 /*FSKTFC2*/
-#define R0900_FSKTFC2  0xf170
-#define F0900_FSKT_KMOD  0xf17000fc
-#define F0900_FSKT_CAR2  0xf1700003
+#define R0900_FSKTFC2 0xf170
+#define F0900_FSKT_KMOD 0xf17000fc
+#define F0900_FSKT_CAR2 0xf1700003
 
 /*FSKTFC1*/
-#define R0900_FSKTFC1  0xf171
-#define F0900_FSKT_CAR1  0xf17100ff
+#define R0900_FSKTFC1 0xf171
+#define F0900_FSKT_CAR1 0xf17100ff
 
 /*FSKTFC0*/
-#define R0900_FSKTFC0  0xf172
-#define F0900_FSKT_CAR0  0xf17200ff
+#define R0900_FSKTFC0 0xf172
+#define F0900_FSKT_CAR0 0xf17200ff
 
 /*FSKTDELTAF1*/
-#define R0900_FSKTDELTAF1  0xf173
-#define F0900_FSKT_DELTAF1  0xf173000f
+#define R0900_FSKTDELTAF1 0xf173
+#define F0900_FSKT_DELTAF1 0xf173000f
 
 /*FSKTDELTAF0*/
-#define R0900_FSKTDELTAF0  0xf174
-#define F0900_FSKT_DELTAF0  0xf17400ff
+#define R0900_FSKTDELTAF0 0xf174
+#define F0900_FSKT_DELTAF0 0xf17400ff
 
 /*FSKTCTRL*/
-#define R0900_FSKTCTRL  0xf175
-#define F0900_FSKT_EN_SGN  0xf1750040
-#define F0900_FSKT_MOD_SGN  0xf1750020
-#define F0900_FSKT_MOD_EN  0xf175001c
-#define F0900_FSKT_DACMODE  0xf1750003
+#define R0900_FSKTCTRL 0xf175
+#define F0900_FSKT_EN_SGN 0xf1750040
+#define F0900_FSKT_MOD_SGN 0xf1750020
+#define F0900_FSKT_MOD_EN 0xf175001c
+#define F0900_FSKT_DACMODE 0xf1750003
 
 /*FSKRFC2*/
-#define R0900_FSKRFC2  0xf176
-#define F0900_FSKR_DETSGN  0xf1760040
-#define F0900_FSKR_OUTSGN  0xf1760020
-#define F0900_FSKR_KAGC  0xf176001c
-#define F0900_FSKR_CAR2  0xf1760003
+#define R0900_FSKRFC2 0xf176
+#define F0900_FSKR_DETSGN 0xf1760040
+#define F0900_FSKR_OUTSGN 0xf1760020
+#define F0900_FSKR_KAGC 0xf176001c
+#define F0900_FSKR_CAR2 0xf1760003
 
 /*FSKRFC1*/
-#define R0900_FSKRFC1  0xf177
-#define F0900_FSKR_CAR1  0xf17700ff
+#define R0900_FSKRFC1 0xf177
+#define F0900_FSKR_CAR1 0xf17700ff
 
 /*FSKRFC0*/
-#define R0900_FSKRFC0  0xf178
-#define F0900_FSKR_CAR0  0xf17800ff
+#define R0900_FSKRFC0 0xf178
+#define F0900_FSKR_CAR0 0xf17800ff
 
 /*FSKRK1*/
-#define R0900_FSKRK1  0xf179
-#define F0900_FSKR_K1_EXP  0xf17900e0
-#define F0900_FSKR_K1_MANT  0xf179001f
+#define R0900_FSKRK1 0xf179
+#define F0900_FSKR_K1_EXP 0xf17900e0
+#define F0900_FSKR_K1_MANT 0xf179001f
 
 /*FSKRK2*/
-#define R0900_FSKRK2  0xf17a
-#define F0900_FSKR_K2_EXP  0xf17a00e0
-#define F0900_FSKR_K2_MANT  0xf17a001f
+#define R0900_FSKRK2 0xf17a
+#define F0900_FSKR_K2_EXP 0xf17a00e0
+#define F0900_FSKR_K2_MANT 0xf17a001f
 
 /*FSKRAGCR*/
-#define R0900_FSKRAGCR  0xf17b
-#define F0900_FSKR_OUTCTL  0xf17b00c0
-#define F0900_FSKR_AGC_REF  0xf17b003f
+#define R0900_FSKRAGCR 0xf17b
+#define F0900_FSKR_OUTCTL 0xf17b00c0
+#define F0900_FSKR_AGC_REF 0xf17b003f
 
 /*FSKRAGC*/
-#define R0900_FSKRAGC  0xf17c
-#define F0900_FSKR_AGC_ACCU  0xf17c00ff
+#define R0900_FSKRAGC 0xf17c
+#define F0900_FSKR_AGC_ACCU 0xf17c00ff
 
 /*FSKRALPHA*/
-#define R0900_FSKRALPHA  0xf17d
-#define F0900_FSKR_ALPHA_EXP  0xf17d001c
-#define F0900_FSKR_ALPHA_M  0xf17d0003
+#define R0900_FSKRALPHA 0xf17d
+#define F0900_FSKR_ALPHA_EXP 0xf17d001c
+#define F0900_FSKR_ALPHA_M 0xf17d0003
 
 /*FSKRPLTH1*/
-#define R0900_FSKRPLTH1  0xf17e
-#define F0900_FSKR_BETA  0xf17e00f0
-#define F0900_FSKR_PLL_TRESH1  0xf17e000f
+#define R0900_FSKRPLTH1 0xf17e
+#define F0900_FSKR_BETA 0xf17e00f0
+#define F0900_FSKR_PLL_TRESH1 0xf17e000f
 
 /*FSKRPLTH0*/
-#define R0900_FSKRPLTH0  0xf17f
-#define F0900_FSKR_PLL_TRESH0  0xf17f00ff
+#define R0900_FSKRPLTH0 0xf17f
+#define F0900_FSKR_PLL_TRESH0 0xf17f00ff
 
 /*FSKRDF1*/
-#define R0900_FSKRDF1  0xf180
-#define F0900_FSKR_OUT  0xf1800080
-#define F0900_FSKR_DELTAF1  0xf180001f
+#define R0900_FSKRDF1 0xf180
+#define F0900_FSKR_OUT 0xf1800080
+#define F0900_FSKR_DELTAF1 0xf180001f
 
 /*FSKRDF0*/
-#define R0900_FSKRDF0  0xf181
-#define F0900_FSKR_DELTAF0  0xf18100ff
+#define R0900_FSKRDF0 0xf181
+#define F0900_FSKR_DELTAF0 0xf18100ff
 
 /*FSKRSTEPP*/
-#define R0900_FSKRSTEPP  0xf182
-#define F0900_FSKR_STEP_PLUS  0xf18200ff
+#define R0900_FSKRSTEPP 0xf182
+#define F0900_FSKR_STEP_PLUS 0xf18200ff
 
 /*FSKRSTEPM*/
-#define R0900_FSKRSTEPM  0xf183
-#define F0900_FSKR_STEP_MINUS  0xf18300ff
+#define R0900_FSKRSTEPM 0xf183
+#define F0900_FSKR_STEP_MINUS 0xf18300ff
 
 /*FSKRDET1*/
-#define R0900_FSKRDET1  0xf184
-#define F0900_FSKR_DETECT  0xf1840080
-#define F0900_FSKR_CARDET_ACCU1  0xf184000f
+#define R0900_FSKRDET1 0xf184
+#define F0900_FSKR_DETECT 0xf1840080
+#define F0900_FSKR_CARDET_ACCU1 0xf184000f
 
 /*FSKRDET0*/
-#define R0900_FSKRDET0  0xf185
-#define F0900_FSKR_CARDET_ACCU0  0xf18500ff
+#define R0900_FSKRDET0 0xf185
+#define F0900_FSKR_CARDET_ACCU0 0xf18500ff
 
 /*FSKRDTH1*/
-#define R0900_FSKRDTH1  0xf186
-#define F0900_FSKR_CARLOSS_THRESH1  0xf18600f0
-#define F0900_FSKR_CARDET_THRESH1  0xf186000f
+#define R0900_FSKRDTH1 0xf186
+#define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0
+#define F0900_FSKR_CARDET_THRESH1 0xf186000f
 
 /*FSKRDTH0*/
-#define R0900_FSKRDTH0  0xf187
-#define F0900_FSKR_CARDET_THRESH0  0xf18700ff
+#define R0900_FSKRDTH0 0xf187
+#define F0900_FSKR_CARDET_THRESH0 0xf18700ff
 
 /*FSKRLOSS*/
-#define R0900_FSKRLOSS  0xf188
-#define F0900_FSKR_CARLOSS_THRESH0  0xf18800ff
+#define R0900_FSKRLOSS 0xf188
+#define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff
 
 /*P2_DISTXCTL*/
-#define R0900_P2_DISTXCTL  0xf190
-#define F0900_P2_TIM_OFF  0xf1900080
-#define F0900_P2_DISEQC_RESET  0xf1900040
-#define F0900_P2_TIM_CMD  0xf1900030
-#define F0900_P2_DIS_PRECHARGE  0xf1900008
-#define F0900_P2_DISTX_MODE  0xf1900007
+#define R0900_P2_DISTXCTL 0xf190
+#define F0900_P2_TIM_OFF 0xf1900080
+#define F0900_P2_DISEQC_RESET 0xf1900040
+#define F0900_P2_TIM_CMD 0xf1900030
+#define F0900_P2_DIS_PRECHARGE 0xf1900008
+#define F0900_P2_DISTX_MODE 0xf1900007
 
 /*P2_DISRXCTL*/
-#define R0900_P2_DISRXCTL  0xf191
-#define F0900_P2_RECEIVER_ON  0xf1910080
-#define F0900_P2_IGNO_SHORT22K  0xf1910040
-#define F0900_P2_ONECHIP_TRX  0xf1910020
-#define F0900_P2_EXT_ENVELOP  0xf1910010
-#define F0900_P2_PIN_SELECT  0xf191000c
-#define F0900_P2_IRQ_RXEND  0xf1910002
-#define F0900_P2_IRQ_4NBYTES  0xf1910001
+#define R0900_P2_DISRXCTL 0xf191
+#define F0900_P2_RECEIVER_ON 0xf1910080
+#define F0900_P2_IGNO_SHORT22K 0xf1910040
+#define F0900_P2_ONECHIP_TRX 0xf1910020
+#define F0900_P2_EXT_ENVELOP 0xf1910010
+#define F0900_P2_PIN_SELECT0 0xf191000c
+#define F0900_P2_IRQ_RXEND 0xf1910002
+#define F0900_P2_IRQ_4NBYTES 0xf1910001
 
 /*P2_DISRX_ST0*/
-#define R0900_P2_DISRX_ST0  0xf194
-#define F0900_P2_RX_END  0xf1940080
-#define F0900_P2_RX_ACTIVE  0xf1940040
-#define F0900_P2_SHORT_22KHZ  0xf1940020
-#define F0900_P2_CONT_TONE  0xf1940010
-#define F0900_P2_FIFO_4BREADY  0xf1940008
-#define F0900_P2_FIFO_EMPTY  0xf1940004
-#define F0900_P2_ABORT_DISRX  0xf1940001
+#define R0900_P2_DISRX_ST0 0xf194
+#define F0900_P2_RX_END 0xf1940080
+#define F0900_P2_RX_ACTIVE 0xf1940040
+#define F0900_P2_SHORT_22KHZ 0xf1940020
+#define F0900_P2_CONT_TONE 0xf1940010
+#define F0900_P2_FIFO_4BREADY 0xf1940008
+#define F0900_P2_FIFO_EMPTY 0xf1940004
+#define F0900_P2_ABORT_DISRX 0xf1940001
 
 /*P2_DISRX_ST1*/
-#define R0900_P2_DISRX_ST1  0xf195
-#define F0900_P2_RX_FAIL  0xf1950080
-#define F0900_P2_FIFO_PARITYFAIL  0xf1950040
-#define F0900_P2_RX_NONBYTE  0xf1950020
-#define F0900_P2_FIFO_OVERFLOW  0xf1950010
-#define F0900_P2_FIFO_BYTENBR  0xf195000f
+#define R0900_P2_DISRX_ST1 0xf195
+#define F0900_P2_RX_FAIL 0xf1950080
+#define F0900_P2_FIFO_PARITYFAIL 0xf1950040
+#define F0900_P2_RX_NONBYTE 0xf1950020
+#define F0900_P2_FIFO_OVERFLOW 0xf1950010
+#define F0900_P2_FIFO_BYTENBR 0xf195000f
 
 /*P2_DISRXDATA*/
-#define R0900_P2_DISRXDATA  0xf196
-#define F0900_P2_DISRX_DATA  0xf19600ff
+#define R0900_P2_DISRXDATA 0xf196
+#define F0900_P2_DISRX_DATA 0xf19600ff
 
 /*P2_DISTXDATA*/
-#define R0900_P2_DISTXDATA  0xf197
-#define F0900_P2_DISEQC_FIFO  0xf19700ff
+#define R0900_P2_DISTXDATA 0xf197
+#define F0900_P2_DISEQC_FIFO 0xf19700ff
 
 /*P2_DISTXSTATUS*/
-#define R0900_P2_DISTXSTATUS  0xf198
-#define F0900_P2_TX_FAIL  0xf1980080
-#define F0900_P2_FIFO_FULL  0xf1980040
-#define F0900_P2_TX_IDLE  0xf1980020
-#define F0900_P2_GAP_BURST  0xf1980010
-#define F0900_P2_TXFIFO_BYTES  0xf198000f
+#define R0900_P2_DISTXSTATUS 0xf198
+#define F0900_P2_TX_FAIL 0xf1980080
+#define F0900_P2_FIFO_FULL 0xf1980040
+#define F0900_P2_TX_IDLE 0xf1980020
+#define F0900_P2_GAP_BURST 0xf1980010
+#define F0900_P2_TXFIFO_BYTES 0xf198000f
 
 /*P2_F22TX*/
-#define R0900_P2_F22TX  0xf199
-#define F0900_P2_F22_REG  0xf19900ff
+#define R0900_P2_F22TX 0xf199
+#define F0900_P2_F22_REG 0xf19900ff
 
 /*P2_F22RX*/
-#define R0900_P2_F22RX  0xf19a
-#define F0900_P2_F22RX_REG  0xf19a00ff
+#define R0900_P2_F22RX 0xf19a
+#define F0900_P2_F22RX_REG 0xf19a00ff
 
 /*P2_ACRPRESC*/
-#define R0900_P2_ACRPRESC  0xf19c
-#define F0900_P2_ACR_CODFRDY  0xf19c0008
-#define F0900_P2_ACR_PRESC  0xf19c0007
+#define R0900_P2_ACRPRESC 0xf19c
+#define F0900_P2_ACR_PRESC 0xf19c0007
 
 /*P2_ACRDIV*/
-#define R0900_P2_ACRDIV  0xf19d
-#define F0900_P2_ACR_DIV  0xf19d00ff
+#define R0900_P2_ACRDIV 0xf19d
+#define F0900_P2_ACR_DIV 0xf19d00ff
 
 /*P1_DISTXCTL*/
-#define R0900_P1_DISTXCTL  0xf1a0
-#define F0900_P1_TIM_OFF  0xf1a00080
-#define F0900_P1_DISEQC_RESET  0xf1a00040
-#define F0900_P1_TIM_CMD  0xf1a00030
-#define F0900_P1_DIS_PRECHARGE  0xf1a00008
-#define F0900_P1_DISTX_MODE  0xf1a00007
+#define R0900_P1_DISTXCTL 0xf1a0
+#define DISTXCTL shiftx(R0900_P1_DISTXCTL, demod, 0x10)
+#define F0900_P1_TIM_OFF 0xf1a00080
+#define F0900_P1_DISEQC_RESET 0xf1a00040
+#define DISEQC_RESET shiftx(F0900_P1_DISEQC_RESET, demod, 0x100000)
+#define F0900_P1_TIM_CMD 0xf1a00030
+#define F0900_P1_DIS_PRECHARGE 0xf1a00008
+#define DIS_PRECHARGE shiftx(F0900_P1_DIS_PRECHARGE, demod, 0x100000)
+#define F0900_P1_DISTX_MODE 0xf1a00007
+#define DISTX_MODE shiftx(F0900_P1_DISTX_MODE, demod, 0x100000)
 
 /*P1_DISRXCTL*/
-#define R0900_P1_DISRXCTL  0xf1a1
-#define F0900_P1_RECEIVER_ON  0xf1a10080
-#define F0900_P1_IGNO_SHORT22K  0xf1a10040
-#define F0900_P1_ONECHIP_TRX  0xf1a10020
-#define F0900_P1_EXT_ENVELOP  0xf1a10010
-#define F0900_P1_PIN_SELECT  0xf1a1000c
-#define F0900_P1_IRQ_RXEND  0xf1a10002
-#define F0900_P1_IRQ_4NBYTES  0xf1a10001
+#define R0900_P1_DISRXCTL 0xf1a1
+#define DISRXCTL shiftx(R0900_P1_DISRXCTL, demod, 0x10)
+#define F0900_P1_RECEIVER_ON 0xf1a10080
+#define F0900_P1_IGNO_SHORT22K 0xf1a10040
+#define F0900_P1_ONECHIP_TRX 0xf1a10020
+#define F0900_P1_EXT_ENVELOP 0xf1a10010
+#define F0900_P1_PIN_SELECT0 0xf1a1000c
+#define F0900_P1_IRQ_RXEND 0xf1a10002
+#define F0900_P1_IRQ_4NBYTES 0xf1a10001
 
 /*P1_DISRX_ST0*/
-#define R0900_P1_DISRX_ST0  0xf1a4
-#define F0900_P1_RX_END  0xf1a40080
-#define F0900_P1_RX_ACTIVE  0xf1a40040
-#define F0900_P1_SHORT_22KHZ  0xf1a40020
-#define F0900_P1_CONT_TONE  0xf1a40010
-#define F0900_P1_FIFO_4BREADY  0xf1a40008
-#define F0900_P1_FIFO_EMPTY  0xf1a40004
-#define F0900_P1_ABORT_DISRX  0xf1a40001
+#define R0900_P1_DISRX_ST0 0xf1a4
+#define DISRX_ST0 shiftx(R0900_P1_DISRX_ST0, demod, 0x10)
+#define F0900_P1_RX_END 0xf1a40080
+#define RX_END shiftx(F0900_P1_RX_END, demod, 0x100000)
+#define F0900_P1_RX_ACTIVE 0xf1a40040
+#define F0900_P1_SHORT_22KHZ 0xf1a40020
+#define F0900_P1_CONT_TONE 0xf1a40010
+#define F0900_P1_FIFO_4BREADY 0xf1a40008
+#define F0900_P1_FIFO_EMPTY 0xf1a40004
+#define F0900_P1_ABORT_DISRX 0xf1a40001
 
 /*P1_DISRX_ST1*/
-#define R0900_P1_DISRX_ST1  0xf1a5
-#define F0900_P1_RX_FAIL  0xf1a50080
-#define F0900_P1_FIFO_PARITYFAIL  0xf1a50040
-#define F0900_P1_RX_NONBYTE  0xf1a50020
-#define F0900_P1_FIFO_OVERFLOW  0xf1a50010
-#define F0900_P1_FIFO_BYTENBR  0xf1a5000f
+#define R0900_P1_DISRX_ST1 0xf1a5
+#define DISRX_ST1 shiftx(R0900_P1_DISRX_ST1, demod, 0x10)
+#define F0900_P1_RX_FAIL 0xf1a50080
+#define F0900_P1_FIFO_PARITYFAIL 0xf1a50040
+#define F0900_P1_RX_NONBYTE 0xf1a50020
+#define F0900_P1_FIFO_OVERFLOW 0xf1a50010
+#define F0900_P1_FIFO_BYTENBR 0xf1a5000f
+#define FIFO_BYTENBR shiftx(F0900_P1_FIFO_BYTENBR, demod, 0x100000)
 
 /*P1_DISRXDATA*/
-#define R0900_P1_DISRXDATA  0xf1a6
-#define F0900_P1_DISRX_DATA  0xf1a600ff
+#define R0900_P1_DISRXDATA 0xf1a6
+#define DISRXDATA shiftx(R0900_P1_DISRXDATA, demod, 0x10)
+#define F0900_P1_DISRX_DATA 0xf1a600ff
 
 /*P1_DISTXDATA*/
-#define R0900_P1_DISTXDATA  0xf1a7
-#define F0900_P1_DISEQC_FIFO  0xf1a700ff
+#define R0900_P1_DISTXDATA 0xf1a7
+#define DISTXDATA shiftx(R0900_P1_DISTXDATA, demod, 0x10)
+#define F0900_P1_DISEQC_FIFO 0xf1a700ff
 
 /*P1_DISTXSTATUS*/
-#define R0900_P1_DISTXSTATUS  0xf1a8
-#define F0900_P1_TX_FAIL  0xf1a80080
-#define F0900_P1_FIFO_FULL  0xf1a80040
-#define F0900_P1_TX_IDLE  0xf1a80020
-#define F0900_P1_GAP_BURST  0xf1a80010
-#define F0900_P1_TXFIFO_BYTES  0xf1a8000f
+#define R0900_P1_DISTXSTATUS 0xf1a8
+#define F0900_P1_TX_FAIL 0xf1a80080
+#define F0900_P1_FIFO_FULL 0xf1a80040
+#define FIFO_FULL shiftx(F0900_P1_FIFO_FULL, demod, 0x100000)
+#define F0900_P1_TX_IDLE 0xf1a80020
+#define TX_IDLE shiftx(F0900_P1_TX_IDLE, demod, 0x100000)
+#define F0900_P1_GAP_BURST 0xf1a80010
+#define F0900_P1_TXFIFO_BYTES 0xf1a8000f
 
 /*P1_F22TX*/
-#define R0900_P1_F22TX  0xf1a9
-#define F0900_P1_F22_REG  0xf1a900ff
+#define R0900_P1_F22TX 0xf1a9
+#define F22TX shiftx(R0900_P1_F22TX, demod, 0x10)
+#define F0900_P1_F22_REG 0xf1a900ff
 
 /*P1_F22RX*/
-#define R0900_P1_F22RX  0xf1aa
-#define F0900_P1_F22RX_REG  0xf1aa00ff
+#define R0900_P1_F22RX 0xf1aa
+#define F22RX shiftx(R0900_P1_F22RX, demod, 0x10)
+#define F0900_P1_F22RX_REG 0xf1aa00ff
 
 /*P1_ACRPRESC*/
-#define R0900_P1_ACRPRESC  0xf1ac
-#define F0900_P1_ACR_CODFRDY  0xf1ac0008
-#define F0900_P1_ACR_PRESC  0xf1ac0007
+#define R0900_P1_ACRPRESC 0xf1ac
+#define ACRPRESC shiftx(R0900_P1_ACRPRESC, demod, 0x10)
+#define F0900_P1_ACR_PRESC 0xf1ac0007
 
 /*P1_ACRDIV*/
-#define R0900_P1_ACRDIV  0xf1ad
-#define F0900_P1_ACR_DIV  0xf1ad00ff
+#define R0900_P1_ACRDIV 0xf1ad
+#define ACRDIV shiftx(R0900_P1_ACRDIV, demod, 0x10)
+#define F0900_P1_ACR_DIV 0xf1ad00ff
 
 /*NCOARSE*/
-#define R0900_NCOARSE  0xf1b3
-#define F0900_M_DIV  0xf1b300ff
+#define R0900_NCOARSE 0xf1b3
+#define F0900_M_DIV 0xf1b300ff
 
 /*SYNTCTRL*/
-#define R0900_SYNTCTRL  0xf1b6
-#define F0900_STANDBY  0xf1b60080
-#define F0900_BYPASSPLLCORE  0xf1b60040
-#define F0900_SELX1RATIO  0xf1b60020
-#define F0900_I2C_TUD  0xf1b60010
-#define F0900_STOP_PLL  0xf1b60008
-#define F0900_BYPASSPLLFSK  0xf1b60004
-#define F0900_SELOSCI  0xf1b60002
-#define F0900_BYPASSPLLADC  0xf1b60001
+#define R0900_SYNTCTRL 0xf1b6
+#define F0900_STANDBY 0xf1b60080
+#define F0900_BYPASSPLLCORE 0xf1b60040
+#define F0900_SELX1RATIO 0xf1b60020
+#define F0900_STOP_PLL 0xf1b60008
+#define F0900_BYPASSPLLFSK 0xf1b60004
+#define F0900_SELOSCI 0xf1b60002
+#define F0900_BYPASSPLLADC 0xf1b60001
 
 /*FILTCTRL*/
-#define R0900_FILTCTRL  0xf1b7
-#define F0900_INV_CLK135  0xf1b70080
-#define F0900_PERM_BYPDIS  0xf1b70040
-#define F0900_SEL_FSKCKDIV  0xf1b70004
-#define F0900_INV_CLKFSK  0xf1b70002
-#define F0900_BYPASS_APPLI  0xf1b70001
+#define R0900_FILTCTRL 0xf1b7
+#define F0900_INV_CLK135 0xf1b70080
+#define F0900_SEL_FSKCKDIV 0xf1b70004
+#define F0900_INV_CLKFSK 0xf1b70002
+#define F0900_BYPASS_APPLI 0xf1b70001
 
 /*PLLSTAT*/
-#define R0900_PLLSTAT  0xf1b8
-#define F0900_ACM_SEL  0xf1b80080
-#define F0900_DTV_SEL  0xf1b80040
-#define F0900_PLLLOCK  0xf1b80001
+#define R0900_PLLSTAT 0xf1b8
+#define F0900_PLLLOCK 0xf1b80001
 
 /*STOPCLK1*/
-#define R0900_STOPCLK1  0xf1c2
-#define F0900_STOP_CLKPKDT2  0xf1c20040
-#define F0900_STOP_CLKPKDT1  0xf1c20020
-#define F0900_STOP_CLKFEC  0xf1c20010
-#define F0900_STOP_CLKADCI2  0xf1c20008
-#define F0900_INV_CLKADCI2  0xf1c20004
-#define F0900_STOP_CLKADCI1  0xf1c20002
-#define F0900_INV_CLKADCI1  0xf1c20001
+#define R0900_STOPCLK1 0xf1c2
+#define F0900_STOP_CLKPKDT2 0xf1c20040
+#define F0900_STOP_CLKPKDT1 0xf1c20020
+#define F0900_STOP_CLKFEC 0xf1c20010
+#define F0900_STOP_CLKADCI2 0xf1c20008
+#define F0900_INV_CLKADCI2 0xf1c20004
+#define F0900_STOP_CLKADCI1 0xf1c20002
+#define F0900_INV_CLKADCI1 0xf1c20001
 
 /*STOPCLK2*/
-#define R0900_STOPCLK2  0xf1c3
-#define F0900_STOP_CLKSAMP2  0xf1c30010
-#define F0900_STOP_CLKSAMP1  0xf1c30008
-#define F0900_STOP_CLKVIT2  0xf1c30004
-#define F0900_STOP_CLKVIT1  0xf1c30002
-#define F0900_STOP_CLKTS  0xf1c30001
+#define R0900_STOPCLK2 0xf1c3
+#define F0900_STOP_CLKSAMP2 0xf1c30010
+#define F0900_STOP_CLKSAMP1 0xf1c30008
+#define F0900_STOP_CLKVIT2 0xf1c30004
+#define F0900_STOP_CLKVIT1 0xf1c30002
+#define STOP_CLKVIT shiftx(F0900_STOP_CLKVIT1, demod, -2)
+#define F0900_STOP_CLKTS 0xf1c30001
 
 /*TSTTNR0*/
-#define R0900_TSTTNR0  0xf1df
-#define F0900_SEL_FSK  0xf1df0080
-#define F0900_FSK_PON  0xf1df0004
-#define F0900_FSK_OPENLOOP  0xf1df0002
+#define R0900_TSTTNR0 0xf1df
+#define F0900_SEL_FSK 0xf1df0080
+#define F0900_FSK_PON 0xf1df0004
 
 /*TSTTNR1*/
-#define R0900_TSTTNR1  0xf1e0
-#define F0900_BYPASS_ADC1  0xf1e00080
-#define F0900_INVADC1_CKOUT  0xf1e00040
-#define F0900_SELIQSRC1  0xf1e00030
-#define F0900_ADC1_PON  0xf1e00002
-#define F0900_ADC1_INMODE  0xf1e00001
+#define R0900_TSTTNR1 0xf1e0
+#define F0900_ADC1_PON 0xf1e00002
+#define F0900_ADC1_INMODE 0xf1e00001
 
 /*TSTTNR2*/
-#define R0900_TSTTNR2  0xf1e1
-#define F0900_DISEQC1_PON  0xf1e10020
-#define F0900_DISEQC1_TEST  0xf1e1001f
+#define R0900_TSTTNR2 0xf1e1
+#define F0900_DISEQC1_PON 0xf1e10020
 
 /*TSTTNR3*/
-#define R0900_TSTTNR3  0xf1e2
-#define F0900_BYPASS_ADC2  0xf1e20080
-#define F0900_INVADC2_CKOUT  0xf1e20040
-#define F0900_SELIQSRC2  0xf1e20030
-#define F0900_ADC2_PON  0xf1e20002
-#define F0900_ADC2_INMODE  0xf1e20001
+#define R0900_TSTTNR3 0xf1e2
+#define F0900_ADC2_PON 0xf1e20002
+#define F0900_ADC2_INMODE 0xf1e20001
 
 /*TSTTNR4*/
-#define R0900_TSTTNR4  0xf1e3
-#define F0900_DISEQC2_PON  0xf1e30020
-#define F0900_DISEQC2_TEST  0xf1e3001f
+#define R0900_TSTTNR4 0xf1e3
+#define F0900_DISEQC2_PON 0xf1e30020
 
 /*P2_IQCONST*/
-#define R0900_P2_IQCONST  0xf200
-#define F0900_P2_CONSTEL_SELECT  0xf2000060
-#define F0900_P2_IQSYMB_SEL  0xf200001f
+#define R0900_P2_IQCONST 0xf200
+#define F0900_P2_CONSTEL_SELECT 0xf2000060
+#define F0900_P2_IQSYMB_SEL 0xf200001f
 
 /*P2_NOSCFG*/
-#define R0900_P2_NOSCFG  0xf201
-#define F0900_P2_DUMMYPL_NOSDATA  0xf2010020
-#define F0900_P2_NOSPLH_BETA  0xf2010018
-#define F0900_P2_NOSDATA_BETA  0xf2010007
+#define R0900_P2_NOSCFG 0xf201
+#define F0900_P2_DUMMYPL_NOSDATA 0xf2010020
+#define F0900_P2_NOSPLH_BETA 0xf2010018
+#define F0900_P2_NOSDATA_BETA 0xf2010007
 
 /*P2_ISYMB*/
-#define R0900_P2_ISYMB  0xf202
-#define F0900_P2_I_SYMBOL  0xf20201ff
+#define R0900_P2_ISYMB 0xf202
+#define F0900_P2_I_SYMBOL 0xf20201ff
 
 /*P2_QSYMB*/
-#define R0900_P2_QSYMB  0xf203
-#define F0900_P2_Q_SYMBOL  0xf20301ff
+#define R0900_P2_QSYMB 0xf203
+#define F0900_P2_Q_SYMBOL 0xf20301ff
 
 /*P2_AGC1CFG*/
-#define R0900_P2_AGC1CFG  0xf204
-#define F0900_P2_DC_FROZEN  0xf2040080
-#define F0900_P2_DC_CORRECT  0xf2040040
-#define F0900_P2_AMM_FROZEN  0xf2040020
-#define F0900_P2_AMM_CORRECT  0xf2040010
-#define F0900_P2_QUAD_FROZEN  0xf2040008
-#define F0900_P2_QUAD_CORRECT  0xf2040004
-#define F0900_P2_DCCOMP_SLOW  0xf2040002
-#define F0900_P2_IQMISM_SLOW  0xf2040001
+#define R0900_P2_AGC1CFG 0xf204
+#define F0900_P2_DC_FROZEN 0xf2040080
+#define F0900_P2_DC_CORRECT 0xf2040040
+#define F0900_P2_AMM_FROZEN 0xf2040020
+#define F0900_P2_AMM_CORRECT 0xf2040010
+#define F0900_P2_QUAD_FROZEN 0xf2040008
+#define F0900_P2_QUAD_CORRECT 0xf2040004
 
 /*P2_AGC1CN*/
-#define R0900_P2_AGC1CN  0xf206
-#define F0900_P2_AGC1_LOCKED  0xf2060080
-#define F0900_P2_AGC1_OVERFLOW  0xf2060040
-#define F0900_P2_AGC1_NOSLOWLK  0xf2060020
-#define F0900_P2_AGC1_MINPOWER  0xf2060010
-#define F0900_P2_AGCOUT_FAST  0xf2060008
-#define F0900_P2_AGCIQ_BETA  0xf2060007
+#define R0900_P2_AGC1CN 0xf206
+#define F0900_P2_AGC1_LOCKED 0xf2060080
+#define F0900_P2_AGC1_MINPOWER 0xf2060010
+#define F0900_P2_AGCOUT_FAST 0xf2060008
+#define F0900_P2_AGCIQ_BETA 0xf2060007
 
 /*P2_AGC1REF*/
-#define R0900_P2_AGC1REF  0xf207
-#define F0900_P2_AGCIQ_REF  0xf20700ff
+#define R0900_P2_AGC1REF 0xf207
+#define F0900_P2_AGCIQ_REF 0xf20700ff
 
 /*P2_IDCCOMP*/
-#define R0900_P2_IDCCOMP  0xf208
-#define F0900_P2_IAVERAGE_ADJ  0xf20801ff
+#define R0900_P2_IDCCOMP 0xf208
+#define F0900_P2_IAVERAGE_ADJ 0xf20801ff
 
 /*P2_QDCCOMP*/
-#define R0900_P2_QDCCOMP  0xf209
-#define F0900_P2_QAVERAGE_ADJ  0xf20901ff
+#define R0900_P2_QDCCOMP 0xf209
+#define F0900_P2_QAVERAGE_ADJ 0xf20901ff
 
 /*P2_POWERI*/
-#define R0900_P2_POWERI  0xf20a
-#define F0900_P2_POWER_I  0xf20a00ff
+#define R0900_P2_POWERI 0xf20a
+#define F0900_P2_POWER_I 0xf20a00ff
 
 /*P2_POWERQ*/
-#define R0900_P2_POWERQ  0xf20b
-#define F0900_P2_POWER_Q  0xf20b00ff
+#define R0900_P2_POWERQ 0xf20b
+#define F0900_P2_POWER_Q 0xf20b00ff
 
 /*P2_AGC1AMM*/
-#define R0900_P2_AGC1AMM  0xf20c
-#define F0900_P2_AMM_VALUE  0xf20c00ff
+#define R0900_P2_AGC1AMM 0xf20c
+#define F0900_P2_AMM_VALUE 0xf20c00ff
 
 /*P2_AGC1QUAD*/
-#define R0900_P2_AGC1QUAD  0xf20d
-#define F0900_P2_QUAD_VALUE  0xf20d01ff
+#define R0900_P2_AGC1QUAD 0xf20d
+#define F0900_P2_QUAD_VALUE 0xf20d01ff
 
 /*P2_AGCIQIN1*/
-#define R0900_P2_AGCIQIN1  0xf20e
-#define F0900_P2_AGCIQ_VALUE1  0xf20e00ff
+#define R0900_P2_AGCIQIN1 0xf20e
+#define F0900_P2_AGCIQ_VALUE1 0xf20e00ff
 
 /*P2_AGCIQIN0*/
-#define R0900_P2_AGCIQIN0  0xf20f
-#define F0900_P2_AGCIQ_VALUE0  0xf20f00ff
+#define R0900_P2_AGCIQIN0 0xf20f
+#define F0900_P2_AGCIQ_VALUE0 0xf20f00ff
 
 /*P2_DEMOD*/
-#define R0900_P2_DEMOD  0xf210
-#define F0900_P2_DEMOD_STOP  0xf2100040
-#define F0900_P2_SPECINV_CONTROL  0xf2100030
-#define F0900_P2_FORCE_ENASAMP  0xf2100008
-#define F0900_P2_MANUAL_ROLLOFF  0xf2100004
-#define F0900_P2_ROLLOFF_CONTROL  0xf2100003
+#define R0900_P2_DEMOD 0xf210
+#define F0900_P2_MANUALS2_ROLLOFF 0xf2100080
+#define F0900_P2_SPECINV_CONTROL 0xf2100030
+#define F0900_P2_FORCE_ENASAMP 0xf2100008
+#define F0900_P2_MANUALSX_ROLLOFF 0xf2100004
+#define F0900_P2_ROLLOFF_CONTROL 0xf2100003
 
 /*P2_DMDMODCOD*/
-#define R0900_P2_DMDMODCOD  0xf211
-#define F0900_P2_MANUAL_MODCOD  0xf2110080
-#define F0900_P2_DEMOD_MODCOD  0xf211007c
-#define F0900_P2_DEMOD_TYPE  0xf2110003
+#define R0900_P2_DMDMODCOD 0xf211
+#define F0900_P2_MANUAL_MODCOD 0xf2110080
+#define F0900_P2_DEMOD_MODCOD 0xf211007c
+#define F0900_P2_DEMOD_TYPE 0xf2110003
 
 /*P2_DSTATUS*/
-#define R0900_P2_DSTATUS  0xf212
-#define F0900_P2_CAR_LOCK  0xf2120080
-#define F0900_P2_TMGLOCK_QUALITY  0xf2120060
-#define F0900_P2_SDVBS1_ENABLE  0xf2120010
-#define F0900_P2_LOCK_DEFINITIF  0xf2120008
-#define F0900_P2_TIMING_IS_LOCKED  0xf2120004
-#define F0900_P2_COARSE_TMGLOCK  0xf2120002
-#define F0900_P2_COARSE_CARLOCK  0xf2120001
+#define R0900_P2_DSTATUS 0xf212
+#define F0900_P2_CAR_LOCK 0xf2120080
+#define F0900_P2_TMGLOCK_QUALITY 0xf2120060
+#define F0900_P2_LOCK_DEFINITIF 0xf2120008
+#define F0900_P2_OVADC_DETECT 0xf2120001
 
 /*P2_DSTATUS2*/
-#define R0900_P2_DSTATUS2  0xf213
-#define F0900_P2_DEMOD_DELOCK  0xf2130080
-#define F0900_P2_DEMOD_TIMEOUT  0xf2130040
-#define F0900_P2_MODCODRQ_SYNCTAG  0xf2130020
-#define F0900_P2_POLYPH_SATEVENT  0xf2130010
-#define F0900_P2_AGC1_NOSIGNALACK  0xf2130008
-#define F0900_P2_AGC2_OVERFLOW  0xf2130004
-#define F0900_P2_CFR_OVERFLOW  0xf2130002
-#define F0900_P2_GAMMA_OVERUNDER  0xf2130001
+#define R0900_P2_DSTATUS2 0xf213
+#define F0900_P2_DEMOD_DELOCK 0xf2130080
+#define F0900_P2_AGC1_NOSIGNALACK 0xf2130008
+#define F0900_P2_AGC2_OVERFLOW 0xf2130004
+#define F0900_P2_CFR_OVERFLOW 0xf2130002
+#define F0900_P2_GAMMA_OVERUNDER 0xf2130001
 
 /*P2_DMDCFGMD*/
-#define R0900_P2_DMDCFGMD  0xf214
-#define F0900_P2_DVBS2_ENABLE  0xf2140080
-#define F0900_P2_DVBS1_ENABLE  0xf2140040
-#define F0900_P2_CFR_AUTOSCAN  0xf2140020
-#define F0900_P2_SCAN_ENABLE  0xf2140010
-#define F0900_P2_TUN_AUTOSCAN  0xf2140008
-#define F0900_P2_NOFORCE_RELOCK  0xf2140004
-#define F0900_P2_TUN_RNG  0xf2140003
+#define R0900_P2_DMDCFGMD 0xf214
+#define F0900_P2_DVBS2_ENABLE 0xf2140080
+#define F0900_P2_DVBS1_ENABLE 0xf2140040
+#define F0900_P2_SCAN_ENABLE 0xf2140010
+#define F0900_P2_CFR_AUTOSCAN 0xf2140008
+#define F0900_P2_TUN_RNG 0xf2140003
 
 /*P2_DMDCFG2*/
-#define R0900_P2_DMDCFG2  0xf215
-#define F0900_P2_AGC1_WAITLOCK  0xf2150080
-#define F0900_P2_S1S2_SEQUENTIAL  0xf2150040
-#define F0900_P2_OVERFLOW_TIMEOUT  0xf2150020
-#define F0900_P2_SCANFAIL_TIMEOUT  0xf2150010
-#define F0900_P2_DMDTOUT_BACK  0xf2150008
-#define F0900_P2_CARLOCK_S1ENABLE  0xf2150004
-#define F0900_P2_COARSE_LK3MODE  0xf2150002
-#define F0900_P2_COARSE_LK2MODE  0xf2150001
+#define R0900_P2_DMDCFG2 0xf215
+#define F0900_P2_S1S2_SEQUENTIAL 0xf2150040
+#define F0900_P2_INFINITE_RELOCK 0xf2150010
 
 /*P2_DMDISTATE*/
-#define R0900_P2_DMDISTATE  0xf216
-#define F0900_P2_I2C_NORESETDMODE  0xf2160080
-#define F0900_P2_FORCE_ETAPED  0xf2160040
-#define F0900_P2_SDMDRST_DIRCLK  0xf2160020
-#define F0900_P2_I2C_DEMOD_MODE  0xf216001f
+#define R0900_P2_DMDISTATE 0xf216
+#define F0900_P2_I2C_DEMOD_MODE 0xf216001f
 
 /*P2_DMDT0M*/
-#define R0900_P2_DMDT0M  0xf217
-#define F0900_P2_DMDT0_MIN  0xf21700ff
+#define R0900_P2_DMDT0M 0xf217
+#define F0900_P2_DMDT0_MIN 0xf21700ff
 
 /*P2_DMDSTATE*/
-#define R0900_P2_DMDSTATE  0xf21b
-#define F0900_P2_DEMOD_LOCKED  0xf21b0080
-#define F0900_P2_HEADER_MODE  0xf21b0060
-#define F0900_P2_DEMOD_MODE  0xf21b001f
+#define R0900_P2_DMDSTATE 0xf21b
+#define F0900_P2_HEADER_MODE 0xf21b0060
 
 /*P2_DMDFLYW*/
-#define R0900_P2_DMDFLYW  0xf21c
-#define F0900_P2_I2C_IRQVAL  0xf21c00f0
-#define F0900_P2_FLYWHEEL_CPT  0xf21c000f
+#define R0900_P2_DMDFLYW 0xf21c
+#define F0900_P2_I2C_IRQVAL 0xf21c00f0
+#define F0900_P2_FLYWHEEL_CPT 0xf21c000f
 
 /*P2_DSTATUS3*/
-#define R0900_P2_DSTATUS3  0xf21d
-#define F0900_P2_CFR_ZIGZAG  0xf21d0080
-#define F0900_P2_DEMOD_CFGMODE  0xf21d0060
-#define F0900_P2_GAMMA_LOWBAUDRATE  0xf21d0010
-#define F0900_P2_RELOCK_MODE  0xf21d0008
-#define F0900_P2_DEMOD_FAIL  0xf21d0004
-#define F0900_P2_ETAPE1A_DVBXMEM  0xf21d0003
+#define R0900_P2_DSTATUS3 0xf21d
+#define F0900_P2_DEMOD_CFGMODE 0xf21d0060
 
 /*P2_DMDCFG3*/
-#define R0900_P2_DMDCFG3  0xf21e
-#define F0900_P2_DVBS1_TMGWAIT  0xf21e0080
-#define F0900_P2_NO_BWCENTERING  0xf21e0040
-#define F0900_P2_INV_SEQSRCH  0xf21e0020
-#define F0900_P2_DIS_SFRUPLOW_TRK  0xf21e0010
-#define F0900_P2_NOSTOP_FIFOFULL  0xf21e0008
-#define F0900_P2_LOCKTIME_MODE  0xf21e0007
+#define R0900_P2_DMDCFG3 0xf21e
+#define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008
 
 /*P2_DMDCFG4*/
-#define R0900_P2_DMDCFG4  0xf21f
-#define F0900_P2_TUNER_NRELAUNCH  0xf21f0008
-#define F0900_P2_DIS_CLKENABLE  0xf21f0004
-#define F0900_P2_DIS_HDRDIVLOCK  0xf21f0002
-#define F0900_P2_NO_TNRWBINIT  0xf21f0001
+#define R0900_P2_DMDCFG4 0xf21f
+#define F0900_P2_TUNER_NRELAUNCH 0xf21f0008
 
 /*P2_CORRELMANT*/
-#define R0900_P2_CORRELMANT  0xf220
-#define F0900_P2_CORREL_MANT  0xf22000ff
+#define R0900_P2_CORRELMANT 0xf220
+#define F0900_P2_CORREL_MANT 0xf22000ff
 
 /*P2_CORRELABS*/
-#define R0900_P2_CORRELABS  0xf221
-#define F0900_P2_CORREL_ABS  0xf22100ff
+#define R0900_P2_CORRELABS 0xf221
+#define F0900_P2_CORREL_ABS 0xf22100ff
 
 /*P2_CORRELEXP*/
-#define R0900_P2_CORRELEXP  0xf222
-#define F0900_P2_CORREL_ABSEXP  0xf22200f0
-#define F0900_P2_CORREL_EXP  0xf222000f
+#define R0900_P2_CORRELEXP 0xf222
+#define F0900_P2_CORREL_ABSEXP 0xf22200f0
+#define F0900_P2_CORREL_EXP 0xf222000f
 
 /*P2_PLHMODCOD*/
-#define R0900_P2_PLHMODCOD  0xf224
-#define F0900_P2_SPECINV_DEMOD  0xf2240080
-#define F0900_P2_PLH_MODCOD  0xf224007c
-#define F0900_P2_PLH_TYPE  0xf2240003
-
-/*P2_AGCK32*/
-#define R0900_P2_AGCK32  0xf22b
-#define F0900_P2_R3ADJOFF_32APSK  0xf22b0080
-#define F0900_P2_R2ADJOFF_32APSK  0xf22b0040
-#define F0900_P2_R1ADJOFF_32APSK  0xf22b0020
-#define F0900_P2_RADJ_32APSK  0xf22b001f
+#define R0900_P2_PLHMODCOD 0xf224
+#define F0900_P2_SPECINV_DEMOD 0xf2240080
+#define F0900_P2_PLH_MODCOD 0xf224007c
+#define F0900_P2_PLH_TYPE 0xf2240003
+
+/*P2_DMDREG*/
+#define R0900_P2_DMDREG 0xf225
+#define F0900_P2_DECIM_PLFRAMES 0xf2250001
 
 /*P2_AGC2O*/
-#define R0900_P2_AGC2O  0xf22c
-#define F0900_P2_AGC2REF_ADJUSTING  0xf22c0080
-#define F0900_P2_AGC2_COARSEFAST  0xf22c0040
-#define F0900_P2_AGC2_LKSQRT  0xf22c0020
-#define F0900_P2_AGC2_LKMODE  0xf22c0010
-#define F0900_P2_AGC2_LKEQUA  0xf22c0008
-#define F0900_P2_AGC2_COEF  0xf22c0007
+#define R0900_P2_AGC2O 0xf22c
+#define F0900_P2_AGC2_COEF 0xf22c0007
 
 /*P2_AGC2REF*/
-#define R0900_P2_AGC2REF  0xf22d
-#define F0900_P2_AGC2_REF  0xf22d00ff
+#define R0900_P2_AGC2REF 0xf22d
+#define F0900_P2_AGC2_REF 0xf22d00ff
 
 /*P2_AGC1ADJ*/
-#define R0900_P2_AGC1ADJ  0xf22e
-#define F0900_P2_AGC1ADJ_MANUAL  0xf22e0080
-#define F0900_P2_AGC1_ADJUSTED  0xf22e017f
+#define R0900_P2_AGC1ADJ 0xf22e
+#define F0900_P2_AGC1_ADJUSTED 0xf22e007f
 
 /*P2_AGC2I1*/
-#define R0900_P2_AGC2I1  0xf236
-#define F0900_P2_AGC2_INTEGRATOR1  0xf23600ff
+#define R0900_P2_AGC2I1 0xf236
+#define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff
 
 /*P2_AGC2I0*/
-#define R0900_P2_AGC2I0  0xf237
-#define F0900_P2_AGC2_INTEGRATOR0  0xf23700ff
+#define R0900_P2_AGC2I0 0xf237
+#define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff
 
 /*P2_CARCFG*/
-#define R0900_P2_CARCFG  0xf238
-#define F0900_P2_CFRUPLOW_AUTO  0xf2380080
-#define F0900_P2_CFRUPLOW_TEST  0xf2380040
-#define F0900_P2_EN_CAR2CENTER  0xf2380020
-#define F0900_P2_CARHDR_NODIV8  0xf2380010
-#define F0900_P2_I2C_ROTA  0xf2380008
-#define F0900_P2_ROTAON  0xf2380004
-#define F0900_P2_PH_DET_ALGO  0xf2380003
+#define R0900_P2_CARCFG 0xf238
+#define F0900_P2_CFRUPLOW_AUTO 0xf2380080
+#define F0900_P2_CFRUPLOW_TEST 0xf2380040
+#define F0900_P2_ROTAON 0xf2380004
+#define F0900_P2_PH_DET_ALGO 0xf2380003
 
 /*P2_ACLC*/
-#define R0900_P2_ACLC  0xf239
-#define F0900_P2_STOP_S2ALPHA  0xf23900c0
-#define F0900_P2_CAR_ALPHA_MANT  0xf2390030
-#define F0900_P2_CAR_ALPHA_EXP  0xf239000f
+#define R0900_P2_ACLC 0xf239
+#define F0900_P2_CAR_ALPHA_MANT 0xf2390030
+#define F0900_P2_CAR_ALPHA_EXP 0xf239000f
 
 /*P2_BCLC*/
-#define R0900_P2_BCLC  0xf23a
-#define F0900_P2_STOP_S2BETA  0xf23a00c0
-#define F0900_P2_CAR_BETA_MANT  0xf23a0030
-#define F0900_P2_CAR_BETA_EXP  0xf23a000f
+#define R0900_P2_BCLC 0xf23a
+#define F0900_P2_CAR_BETA_MANT 0xf23a0030
+#define F0900_P2_CAR_BETA_EXP 0xf23a000f
 
 /*P2_CARFREQ*/
-#define R0900_P2_CARFREQ  0xf23d
-#define F0900_P2_KC_COARSE_EXP  0xf23d00f0
-#define F0900_P2_BETA_FREQ  0xf23d000f
+#define R0900_P2_CARFREQ 0xf23d
+#define F0900_P2_KC_COARSE_EXP 0xf23d00f0
+#define F0900_P2_BETA_FREQ 0xf23d000f
 
 /*P2_CARHDR*/
-#define R0900_P2_CARHDR  0xf23e
-#define F0900_P2_K_FREQ_HDR  0xf23e00ff
+#define R0900_P2_CARHDR 0xf23e
+#define F0900_P2_K_FREQ_HDR 0xf23e00ff
 
 /*P2_LDT*/
-#define R0900_P2_LDT  0xf23f
-#define F0900_P2_CARLOCK_THRES  0xf23f01ff
+#define R0900_P2_LDT 0xf23f
+#define F0900_P2_CARLOCK_THRES 0xf23f01ff
 
 /*P2_LDT2*/
-#define R0900_P2_LDT2  0xf240
-#define F0900_P2_CARLOCK_THRES2  0xf24001ff
+#define R0900_P2_LDT2 0xf240
+#define F0900_P2_CARLOCK_THRES2 0xf24001ff
 
 /*P2_CFRICFG*/
-#define R0900_P2_CFRICFG  0xf241
-#define F0900_P2_CFRINIT_UNVALRNG  0xf2410080
-#define F0900_P2_CFRINIT_LUNVALCPT  0xf2410040
-#define F0900_P2_CFRINIT_ABORTDBL  0xf2410020
-#define F0900_P2_CFRINIT_ABORTPRED  0xf2410010
-#define F0900_P2_CFRINIT_UNVALSKIP  0xf2410008
-#define F0900_P2_CFRINIT_CSTINC  0xf2410004
-#define F0900_P2_NEG_CFRSTEP  0xf2410001
+#define R0900_P2_CFRICFG 0xf241
+#define F0900_P2_NEG_CFRSTEP 0xf2410001
 
 /*P2_CFRUP1*/
-#define R0900_P2_CFRUP1  0xf242
-#define F0900_P2_CFR_UP1  0xf24201ff
+#define R0900_P2_CFRUP1 0xf242
+#define F0900_P2_CFR_UP1 0xf24201ff
 
 /*P2_CFRUP0*/
-#define R0900_P2_CFRUP0  0xf243
-#define F0900_P2_CFR_UP0  0xf24300ff
+#define R0900_P2_CFRUP0 0xf243
+#define F0900_P2_CFR_UP0 0xf24300ff
 
 /*P2_CFRLOW1*/
-#define R0900_P2_CFRLOW1  0xf246
-#define F0900_P2_CFR_LOW1  0xf24601ff
+#define R0900_P2_CFRLOW1 0xf246
+#define F0900_P2_CFR_LOW1 0xf24601ff
 
 /*P2_CFRLOW0*/
-#define R0900_P2_CFRLOW0  0xf247
-#define F0900_P2_CFR_LOW0  0xf24700ff
+#define R0900_P2_CFRLOW0 0xf247
+#define F0900_P2_CFR_LOW0 0xf24700ff
 
 /*P2_CFRINIT1*/
-#define R0900_P2_CFRINIT1  0xf248
-#define F0900_P2_CFR_INIT1  0xf24801ff
+#define R0900_P2_CFRINIT1 0xf248
+#define F0900_P2_CFR_INIT1 0xf24801ff
 
 /*P2_CFRINIT0*/
-#define R0900_P2_CFRINIT0  0xf249
-#define F0900_P2_CFR_INIT0  0xf24900ff
+#define R0900_P2_CFRINIT0 0xf249
+#define F0900_P2_CFR_INIT0 0xf24900ff
 
 /*P2_CFRINC1*/
-#define R0900_P2_CFRINC1  0xf24a
-#define F0900_P2_MANUAL_CFRINC  0xf24a0080
-#define F0900_P2_CFR_INC1  0xf24a017f
+#define R0900_P2_CFRINC1 0xf24a
+#define F0900_P2_MANUAL_CFRINC 0xf24a0080
+#define F0900_P2_CFR_INC1 0xf24a003f
 
 /*P2_CFRINC0*/
-#define R0900_P2_CFRINC0  0xf24b
-#define F0900_P2_CFR_INC0  0xf24b00f0
+#define R0900_P2_CFRINC0 0xf24b
+#define F0900_P2_CFR_INC0 0xf24b00f8
 
 /*P2_CFR2*/
-#define R0900_P2_CFR2  0xf24c
-#define F0900_P2_CAR_FREQ2  0xf24c01ff
+#define R0900_P2_CFR2 0xf24c
+#define F0900_P2_CAR_FREQ2 0xf24c01ff
 
 /*P2_CFR1*/
-#define R0900_P2_CFR1  0xf24d
-#define F0900_P2_CAR_FREQ1  0xf24d00ff
+#define R0900_P2_CFR1 0xf24d
+#define F0900_P2_CAR_FREQ1 0xf24d00ff
 
 /*P2_CFR0*/
-#define R0900_P2_CFR0  0xf24e
-#define F0900_P2_CAR_FREQ0  0xf24e00ff
+#define R0900_P2_CFR0 0xf24e
+#define F0900_P2_CAR_FREQ0 0xf24e00ff
 
 /*P2_LDI*/
-#define R0900_P2_LDI  0xf24f
-#define F0900_P2_LOCK_DET_INTEGR  0xf24f01ff
+#define R0900_P2_LDI 0xf24f
+#define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff
 
 /*P2_TMGCFG*/
-#define R0900_P2_TMGCFG  0xf250
-#define F0900_P2_TMGLOCK_BETA  0xf25000c0
-#define F0900_P2_NOTMG_GROUPDELAY  0xf2500020
-#define F0900_P2_DO_TIMING_CORR  0xf2500010
-#define F0900_P2_MANUAL_SCAN  0xf250000c
-#define F0900_P2_TMG_MINFREQ  0xf2500003
+#define R0900_P2_TMGCFG 0xf250
+#define F0900_P2_TMGLOCK_BETA 0xf25000c0
+#define F0900_P2_DO_TIMING_CORR 0xf2500010
+#define F0900_P2_TMG_MINFREQ 0xf2500003
 
 /*P2_RTC*/
-#define R0900_P2_RTC  0xf251
-#define F0900_P2_TMGALPHA_EXP  0xf25100f0
-#define F0900_P2_TMGBETA_EXP  0xf251000f
+#define R0900_P2_RTC 0xf251
+#define F0900_P2_TMGALPHA_EXP 0xf25100f0
+#define F0900_P2_TMGBETA_EXP 0xf251000f
 
 /*P2_RTCS2*/
-#define R0900_P2_RTCS2  0xf252
-#define F0900_P2_TMGALPHAS2_EXP  0xf25200f0
-#define F0900_P2_TMGBETAS2_EXP  0xf252000f
+#define R0900_P2_RTCS2 0xf252
+#define F0900_P2_TMGALPHAS2_EXP 0xf25200f0
+#define F0900_P2_TMGBETAS2_EXP 0xf252000f
 
 /*P2_TMGTHRISE*/
-#define R0900_P2_TMGTHRISE  0xf253
-#define F0900_P2_TMGLOCK_THRISE  0xf25300ff
+#define R0900_P2_TMGTHRISE 0xf253
+#define F0900_P2_TMGLOCK_THRISE 0xf25300ff
 
 /*P2_TMGTHFALL*/
-#define R0900_P2_TMGTHFALL  0xf254
-#define F0900_P2_TMGLOCK_THFALL  0xf25400ff
+#define R0900_P2_TMGTHFALL 0xf254
+#define F0900_P2_TMGLOCK_THFALL 0xf25400ff
 
 /*P2_SFRUPRATIO*/
-#define R0900_P2_SFRUPRATIO  0xf255
-#define F0900_P2_SFR_UPRATIO  0xf25500ff
+#define R0900_P2_SFRUPRATIO 0xf255
+#define F0900_P2_SFR_UPRATIO 0xf25500ff
 
 /*P2_SFRLOWRATIO*/
-#define R0900_P2_SFRLOWRATIO  0xf256
-#define F0900_P2_SFR_LOWRATIO  0xf25600ff
+#define R0900_P2_SFRLOWRATIO 0xf256
+#define F0900_P2_SFR_LOWRATIO 0xf25600ff
 
 /*P2_KREFTMG*/
-#define R0900_P2_KREFTMG  0xf258
-#define F0900_P2_KREF_TMG  0xf25800ff
+#define R0900_P2_KREFTMG 0xf258
+#define F0900_P2_KREF_TMG 0xf25800ff
 
 /*P2_SFRSTEP*/
-#define R0900_P2_SFRSTEP  0xf259
-#define F0900_P2_SFR_SCANSTEP  0xf25900f0
-#define F0900_P2_SFR_CENTERSTEP  0xf259000f
+#define R0900_P2_SFRSTEP 0xf259
+#define F0900_P2_SFR_SCANSTEP 0xf25900f0
+#define F0900_P2_SFR_CENTERSTEP 0xf259000f
 
 /*P2_TMGCFG2*/
-#define R0900_P2_TMGCFG2  0xf25a
-#define F0900_P2_DIS_AUTOSAMP  0xf25a0008
-#define F0900_P2_SCANINIT_QUART  0xf25a0004
-#define F0900_P2_NOTMG_DVBS1DERAT  0xf25a0002
-#define F0900_P2_SFRRATIO_FINE  0xf25a0001
+#define R0900_P2_TMGCFG2 0xf25a
+#define F0900_P2_SFRRATIO_FINE 0xf25a0001
+
+/*P2_KREFTMG2*/
+#define R0900_P2_KREFTMG2 0xf25b
+#define F0900_P2_KREF_TMG2 0xf25b00ff
 
 /*P2_SFRINIT1*/
-#define R0900_P2_SFRINIT1  0xf25e
-#define F0900_P2_SFR_INIT1  0xf25e00ff
+#define R0900_P2_SFRINIT1 0xf25e
+#define F0900_P2_SFR_INIT1 0xf25e007f
 
 /*P2_SFRINIT0*/
-#define R0900_P2_SFRINIT0  0xf25f
-#define F0900_P2_SFR_INIT0  0xf25f00ff
+#define R0900_P2_SFRINIT0 0xf25f
+#define F0900_P2_SFR_INIT0 0xf25f00ff
 
 /*P2_SFRUP1*/
-#define R0900_P2_SFRUP1  0xf260
-#define F0900_P2_AUTO_GUP  0xf2600080
-#define F0900_P2_SYMB_FREQ_UP1  0xf260007f
+#define R0900_P2_SFRUP1 0xf260
+#define F0900_P2_AUTO_GUP 0xf2600080
+#define F0900_P2_SYMB_FREQ_UP1 0xf260007f
 
 /*P2_SFRUP0*/
-#define R0900_P2_SFRUP0  0xf261
-#define F0900_P2_SYMB_FREQ_UP0  0xf26100ff
+#define R0900_P2_SFRUP0 0xf261
+#define F0900_P2_SYMB_FREQ_UP0 0xf26100ff
 
 /*P2_SFRLOW1*/
-#define R0900_P2_SFRLOW1  0xf262
-#define F0900_P2_AUTO_GLOW  0xf2620080
-#define F0900_P2_SYMB_FREQ_LOW1  0xf262007f
+#define R0900_P2_SFRLOW1 0xf262
+#define F0900_P2_AUTO_GLOW 0xf2620080
+#define F0900_P2_SYMB_FREQ_LOW1 0xf262007f
 
 /*P2_SFRLOW0*/
-#define R0900_P2_SFRLOW0  0xf263
-#define F0900_P2_SYMB_FREQ_LOW0  0xf26300ff
+#define R0900_P2_SFRLOW0 0xf263
+#define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff
 
 /*P2_SFR3*/
-#define R0900_P2_SFR3  0xf264
-#define F0900_P2_SYMB_FREQ3  0xf26400ff
+#define R0900_P2_SFR3 0xf264
+#define F0900_P2_SYMB_FREQ3 0xf26400ff
 
 /*P2_SFR2*/
-#define R0900_P2_SFR2  0xf265
-#define F0900_P2_SYMB_FREQ2  0xf26500ff
+#define R0900_P2_SFR2 0xf265
+#define F0900_P2_SYMB_FREQ2 0xf26500ff
 
 /*P2_SFR1*/
-#define R0900_P2_SFR1  0xf266
-#define F0900_P2_SYMB_FREQ1  0xf26600ff
+#define R0900_P2_SFR1 0xf266
+#define F0900_P2_SYMB_FREQ1 0xf26600ff
 
 /*P2_SFR0*/
-#define R0900_P2_SFR0  0xf267
-#define F0900_P2_SYMB_FREQ0  0xf26700ff
+#define R0900_P2_SFR0 0xf267
+#define F0900_P2_SYMB_FREQ0 0xf26700ff
 
 /*P2_TMGREG2*/
-#define R0900_P2_TMGREG2  0xf268
-#define F0900_P2_TMGREG2  0xf26800ff
+#define R0900_P2_TMGREG2 0xf268
+#define F0900_P2_TMGREG2 0xf26800ff
 
 /*P2_TMGREG1*/
-#define R0900_P2_TMGREG1  0xf269
-#define F0900_P2_TMGREG1  0xf26900ff
+#define R0900_P2_TMGREG1 0xf269
+#define F0900_P2_TMGREG1 0xf26900ff
 
 /*P2_TMGREG0*/
-#define R0900_P2_TMGREG0  0xf26a
-#define F0900_P2_TMGREG0  0xf26a00ff
+#define R0900_P2_TMGREG0 0xf26a
+#define F0900_P2_TMGREG0 0xf26a00ff
 
 /*P2_TMGLOCK1*/
-#define R0900_P2_TMGLOCK1  0xf26b
-#define F0900_P2_TMGLOCK_LEVEL1  0xf26b01ff
+#define R0900_P2_TMGLOCK1 0xf26b
+#define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff
 
 /*P2_TMGLOCK0*/
-#define R0900_P2_TMGLOCK0  0xf26c
-#define F0900_P2_TMGLOCK_LEVEL0  0xf26c00ff
+#define R0900_P2_TMGLOCK0 0xf26c
+#define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff
 
 /*P2_TMGOBS*/
-#define R0900_P2_TMGOBS  0xf26d
-#define F0900_P2_ROLLOFF_STATUS  0xf26d00c0
-#define F0900_P2_SCAN_SIGN  0xf26d0030
-#define F0900_P2_TMG_SCANNING  0xf26d0008
-#define F0900_P2_CHCENTERING_MODE  0xf26d0004
-#define F0900_P2_TMG_SCANFAIL  0xf26d0002
+#define R0900_P2_TMGOBS 0xf26d
+#define F0900_P2_ROLLOFF_STATUS 0xf26d00c0
 
 /*P2_EQUALCFG*/
-#define R0900_P2_EQUALCFG  0xf26f
-#define F0900_P2_NOTMG_NEGALWAIT  0xf26f0080
-#define F0900_P2_EQUAL_ON  0xf26f0040
-#define F0900_P2_SEL_EQUALCOR  0xf26f0038
-#define F0900_P2_MU_EQUALDFE  0xf26f0007
+#define R0900_P2_EQUALCFG 0xf26f
+#define F0900_P2_EQUAL_ON 0xf26f0040
+#define F0900_P2_MU_EQUALDFE 0xf26f0007
 
 /*P2_EQUAI1*/
-#define R0900_P2_EQUAI1  0xf270
-#define F0900_P2_EQUA_ACCI1  0xf27001ff
+#define R0900_P2_EQUAI1 0xf270
+#define F0900_P2_EQUA_ACCI1 0xf27001ff
 
 /*P2_EQUAQ1*/
-#define R0900_P2_EQUAQ1  0xf271
-#define F0900_P2_EQUA_ACCQ1  0xf27101ff
+#define R0900_P2_EQUAQ1 0xf271
+#define F0900_P2_EQUA_ACCQ1 0xf27101ff
 
 /*P2_EQUAI2*/
-#define R0900_P2_EQUAI2  0xf272
-#define F0900_P2_EQUA_ACCI2  0xf27201ff
+#define R0900_P2_EQUAI2 0xf272
+#define F0900_P2_EQUA_ACCI2 0xf27201ff
 
 /*P2_EQUAQ2*/
-#define R0900_P2_EQUAQ2  0xf273
-#define F0900_P2_EQUA_ACCQ2  0xf27301ff
+#define R0900_P2_EQUAQ2 0xf273
+#define F0900_P2_EQUA_ACCQ2 0xf27301ff
 
 /*P2_EQUAI3*/
-#define R0900_P2_EQUAI3  0xf274
-#define F0900_P2_EQUA_ACCI3  0xf27401ff
+#define R0900_P2_EQUAI3 0xf274
+#define F0900_P2_EQUA_ACCI3 0xf27401ff
 
 /*P2_EQUAQ3*/
-#define R0900_P2_EQUAQ3  0xf275
-#define F0900_P2_EQUA_ACCQ3  0xf27501ff
+#define R0900_P2_EQUAQ3 0xf275
+#define F0900_P2_EQUA_ACCQ3 0xf27501ff
 
 /*P2_EQUAI4*/
-#define R0900_P2_EQUAI4  0xf276
-#define F0900_P2_EQUA_ACCI4  0xf27601ff
+#define R0900_P2_EQUAI4 0xf276
+#define F0900_P2_EQUA_ACCI4 0xf27601ff
 
 /*P2_EQUAQ4*/
-#define R0900_P2_EQUAQ4  0xf277
-#define F0900_P2_EQUA_ACCQ4  0xf27701ff
+#define R0900_P2_EQUAQ4 0xf277
+#define F0900_P2_EQUA_ACCQ4 0xf27701ff
 
 /*P2_EQUAI5*/
-#define R0900_P2_EQUAI5  0xf278
-#define F0900_P2_EQUA_ACCI5  0xf27801ff
+#define R0900_P2_EQUAI5 0xf278
+#define F0900_P2_EQUA_ACCI5 0xf27801ff
 
 /*P2_EQUAQ5*/
-#define R0900_P2_EQUAQ5  0xf279
-#define F0900_P2_EQUA_ACCQ5  0xf27901ff
+#define R0900_P2_EQUAQ5 0xf279
+#define F0900_P2_EQUA_ACCQ5 0xf27901ff
 
 /*P2_EQUAI6*/
-#define R0900_P2_EQUAI6  0xf27a
-#define F0900_P2_EQUA_ACCI6  0xf27a01ff
+#define R0900_P2_EQUAI6 0xf27a
+#define F0900_P2_EQUA_ACCI6 0xf27a01ff
 
 /*P2_EQUAQ6*/
-#define R0900_P2_EQUAQ6  0xf27b
-#define F0900_P2_EQUA_ACCQ6  0xf27b01ff
+#define R0900_P2_EQUAQ6 0xf27b
+#define F0900_P2_EQUA_ACCQ6 0xf27b01ff
 
 /*P2_EQUAI7*/
-#define R0900_P2_EQUAI7  0xf27c
-#define F0900_P2_EQUA_ACCI7  0xf27c01ff
+#define R0900_P2_EQUAI7 0xf27c
+#define F0900_P2_EQUA_ACCI7 0xf27c01ff
 
 /*P2_EQUAQ7*/
-#define R0900_P2_EQUAQ7  0xf27d
-#define F0900_P2_EQUA_ACCQ7  0xf27d01ff
+#define R0900_P2_EQUAQ7 0xf27d
+#define F0900_P2_EQUA_ACCQ7 0xf27d01ff
 
 /*P2_EQUAI8*/
-#define R0900_P2_EQUAI8  0xf27e
-#define F0900_P2_EQUA_ACCI8  0xf27e01ff
+#define R0900_P2_EQUAI8 0xf27e
+#define F0900_P2_EQUA_ACCI8 0xf27e01ff
 
 /*P2_EQUAQ8*/
-#define R0900_P2_EQUAQ8  0xf27f
-#define F0900_P2_EQUA_ACCQ8  0xf27f01ff
+#define R0900_P2_EQUAQ8 0xf27f
+#define F0900_P2_EQUA_ACCQ8 0xf27f01ff
 
 /*P2_NNOSDATAT1*/
-#define R0900_P2_NNOSDATAT1  0xf280
-#define F0900_P2_NOSDATAT_NORMED1  0xf28000ff
+#define R0900_P2_NNOSDATAT1 0xf280
+#define F0900_P2_NOSDATAT_NORMED1 0xf28000ff
 
 /*P2_NNOSDATAT0*/
-#define R0900_P2_NNOSDATAT0  0xf281
-#define F0900_P2_NOSDATAT_NORMED0  0xf28100ff
+#define R0900_P2_NNOSDATAT0 0xf281
+#define F0900_P2_NOSDATAT_NORMED0 0xf28100ff
 
 /*P2_NNOSDATA1*/
-#define R0900_P2_NNOSDATA1  0xf282
-#define F0900_P2_NOSDATA_NORMED1  0xf28200ff
+#define R0900_P2_NNOSDATA1 0xf282
+#define F0900_P2_NOSDATA_NORMED1 0xf28200ff
 
 /*P2_NNOSDATA0*/
-#define R0900_P2_NNOSDATA0  0xf283
-#define F0900_P2_NOSDATA_NORMED0  0xf28300ff
+#define R0900_P2_NNOSDATA0 0xf283
+#define F0900_P2_NOSDATA_NORMED0 0xf28300ff
 
 /*P2_NNOSPLHT1*/
-#define R0900_P2_NNOSPLHT1  0xf284
-#define F0900_P2_NOSPLHT_NORMED1  0xf28400ff
+#define R0900_P2_NNOSPLHT1 0xf284
+#define F0900_P2_NOSPLHT_NORMED1 0xf28400ff
 
 /*P2_NNOSPLHT0*/
-#define R0900_P2_NNOSPLHT0  0xf285
-#define F0900_P2_NOSPLHT_NORMED0  0xf28500ff
+#define R0900_P2_NNOSPLHT0 0xf285
+#define F0900_P2_NOSPLHT_NORMED0 0xf28500ff
 
 /*P2_NNOSPLH1*/
-#define R0900_P2_NNOSPLH1  0xf286
-#define F0900_P2_NOSPLH_NORMED1  0xf28600ff
+#define R0900_P2_NNOSPLH1 0xf286
+#define F0900_P2_NOSPLH_NORMED1 0xf28600ff
 
 /*P2_NNOSPLH0*/
-#define R0900_P2_NNOSPLH0  0xf287
-#define F0900_P2_NOSPLH_NORMED0  0xf28700ff
+#define R0900_P2_NNOSPLH0 0xf287
+#define F0900_P2_NOSPLH_NORMED0 0xf28700ff
 
 /*P2_NOSDATAT1*/
-#define R0900_P2_NOSDATAT1  0xf288
-#define F0900_P2_NOSDATAT_UNNORMED1  0xf28800ff
+#define R0900_P2_NOSDATAT1 0xf288
+#define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff
 
 /*P2_NOSDATAT0*/
-#define R0900_P2_NOSDATAT0  0xf289
-#define F0900_P2_NOSDATAT_UNNORMED0  0xf28900ff
+#define R0900_P2_NOSDATAT0 0xf289
+#define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff
 
 /*P2_NOSDATA1*/
-#define R0900_P2_NOSDATA1  0xf28a
-#define F0900_P2_NOSDATA_UNNORMED1  0xf28a00ff
+#define R0900_P2_NOSDATA1 0xf28a
+#define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff
 
 /*P2_NOSDATA0*/
-#define R0900_P2_NOSDATA0  0xf28b
-#define F0900_P2_NOSDATA_UNNORMED0  0xf28b00ff
+#define R0900_P2_NOSDATA0 0xf28b
+#define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff
 
 /*P2_NOSPLHT1*/
-#define R0900_P2_NOSPLHT1  0xf28c
-#define F0900_P2_NOSPLHT_UNNORMED1  0xf28c00ff
+#define R0900_P2_NOSPLHT1 0xf28c
+#define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff
 
 /*P2_NOSPLHT0*/
-#define R0900_P2_NOSPLHT0  0xf28d
-#define F0900_P2_NOSPLHT_UNNORMED0  0xf28d00ff
+#define R0900_P2_NOSPLHT0 0xf28d
+#define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff
 
 /*P2_NOSPLH1*/
-#define R0900_P2_NOSPLH1  0xf28e
-#define F0900_P2_NOSPLH_UNNORMED1  0xf28e00ff
+#define R0900_P2_NOSPLH1 0xf28e
+#define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff
 
 /*P2_NOSPLH0*/
-#define R0900_P2_NOSPLH0  0xf28f
-#define F0900_P2_NOSPLH_UNNORMED0  0xf28f00ff
+#define R0900_P2_NOSPLH0 0xf28f
+#define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff
 
 /*P2_CAR2CFG*/
-#define R0900_P2_CAR2CFG  0xf290
-#define F0900_P2_DESCRAMB_OFF  0xf2900080
-#define F0900_P2_PN4_SELECT  0xf2900040
-#define F0900_P2_CFR2_STOPDVBS1  0xf2900020
-#define F0900_P2_STOP_CFR2UPDATE  0xf2900010
-#define F0900_P2_STOP_NCO2UPDATE  0xf2900008
-#define F0900_P2_ROTA2ON  0xf2900004
-#define F0900_P2_PH_DET_ALGO2  0xf2900003
-
-/*P2_ACLC2*/
-#define R0900_P2_ACLC2  0xf291
-#define F0900_P2_CAR2_PUNCT_ADERAT  0xf2910040
-#define F0900_P2_CAR2_ALPHA_MANT  0xf2910030
-#define F0900_P2_CAR2_ALPHA_EXP  0xf291000f
-
-/*P2_BCLC2*/
-#define R0900_P2_BCLC2  0xf292
-#define F0900_P2_DVBS2_NIP  0xf2920080
-#define F0900_P2_CAR2_PUNCT_BDERAT  0xf2920040
-#define F0900_P2_CAR2_BETA_MANT  0xf2920030
-#define F0900_P2_CAR2_BETA_EXP  0xf292000f
+#define R0900_P2_CAR2CFG 0xf290
+#define F0900_P2_CARRIER3_DISABLE 0xf2900040
+#define F0900_P2_ROTA2ON 0xf2900004
+#define F0900_P2_PH_DET_ALGO2 0xf2900003
+
+/*P2_CFR2CFR1*/
+#define R0900_P2_CFR2CFR1 0xf291
+#define F0900_P2_CFR2TOCFR1_DVBS1 0xf29100c0
+#define F0900_P2_EN_S2CAR2CENTER 0xf2910020
+#define F0900_P2_DIS_BCHERRCFR2 0xf2910010
+#define F0900_P2_CFR2TOCFR1_BETA 0xf2910007
 
 /*P2_CFR22*/
-#define R0900_P2_CFR22  0xf293
-#define F0900_P2_CAR2_FREQ2  0xf29301ff
+#define R0900_P2_CFR22 0xf293
+#define F0900_P2_CAR2_FREQ2 0xf29301ff
 
 /*P2_CFR21*/
-#define R0900_P2_CFR21  0xf294
-#define F0900_P2_CAR2_FREQ1  0xf29400ff
+#define R0900_P2_CFR21 0xf294
+#define F0900_P2_CAR2_FREQ1 0xf29400ff
 
 /*P2_CFR20*/
-#define R0900_P2_CFR20  0xf295
-#define F0900_P2_CAR2_FREQ0  0xf29500ff
+#define R0900_P2_CFR20 0xf295
+#define F0900_P2_CAR2_FREQ0 0xf29500ff
 
 /*P2_ACLC2S2Q*/
-#define R0900_P2_ACLC2S2Q  0xf297
-#define F0900_P2_ENAB_SPSKSYMB  0xf2970080
-#define F0900_P2_CAR2S2_QADERAT  0xf2970040
-#define F0900_P2_CAR2S2_Q_ALPH_M  0xf2970030
-#define F0900_P2_CAR2S2_Q_ALPH_E  0xf297000f
+#define R0900_P2_ACLC2S2Q 0xf297
+#define F0900_P2_ENAB_SPSKSYMB 0xf2970080
+#define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030
+#define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f
 
 /*P2_ACLC2S28*/
-#define R0900_P2_ACLC2S28  0xf298
-#define F0900_P2_OLDI3Q_MODE  0xf2980080
-#define F0900_P2_CAR2S2_8ADERAT  0xf2980040
-#define F0900_P2_CAR2S2_8_ALPH_M  0xf2980030
-#define F0900_P2_CAR2S2_8_ALPH_E  0xf298000f
+#define R0900_P2_ACLC2S28 0xf298
+#define F0900_P2_OLDI3Q_MODE 0xf2980080
+#define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030
+#define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f
 
 /*P2_ACLC2S216A*/
-#define R0900_P2_ACLC2S216A  0xf299
-#define F0900_P2_CAR2S2_16ADERAT  0xf2990040
-#define F0900_P2_CAR2S2_16A_ALPH_M  0xf2990030
-#define F0900_P2_CAR2S2_16A_ALPH_E  0xf299000f
+#define R0900_P2_ACLC2S216A 0xf299
+#define F0900_P2_DIS_C3STOPA2 0xf2990080
+#define F0900_P2_CAR2S2_16ADERAT 0xf2990040
+#define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030
+#define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f
 
 /*P2_ACLC2S232A*/
-#define R0900_P2_ACLC2S232A  0xf29a
-#define F0900_P2_CAR2S2_32ADERAT  0xf29a0040
-#define F0900_P2_CAR2S2_32A_ALPH_M  0xf29a0030
-#define F0900_P2_CAR2S2_32A_ALPH_E  0xf29a000f
+#define R0900_P2_ACLC2S232A 0xf29a
+#define F0900_P2_CAR2S2_32ADERAT 0xf29a0040
+#define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030
+#define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f
 
 /*P2_BCLC2S2Q*/
-#define R0900_P2_BCLC2S2Q  0xf29c
-#define F0900_P2_DVBS2S2Q_NIP  0xf29c0080
-#define F0900_P2_CAR2S2_QBDERAT  0xf29c0040
-#define F0900_P2_CAR2S2_Q_BETA_M  0xf29c0030
-#define F0900_P2_CAR2S2_Q_BETA_E  0xf29c000f
+#define R0900_P2_BCLC2S2Q 0xf29c
+#define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030
+#define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f
 
 /*P2_BCLC2S28*/
-#define R0900_P2_BCLC2S28  0xf29d
-#define F0900_P2_DVBS2S28_NIP  0xf29d0080
-#define F0900_P2_CAR2S2_8BDERAT  0xf29d0040
-#define F0900_P2_CAR2S2_8_BETA_M  0xf29d0030
-#define F0900_P2_CAR2S2_8_BETA_E  0xf29d000f
+#define R0900_P2_BCLC2S28 0xf29d
+#define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030
+#define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f
 
 /*P2_BCLC2S216A*/
-#define R0900_P2_BCLC2S216A  0xf29e
-#define F0900_P2_DVBS2S216A_NIP  0xf29e0080
-#define F0900_P2_CAR2S2_16BDERAT  0xf29e0040
-#define F0900_P2_CAR2S2_16A_BETA_M  0xf29e0030
-#define F0900_P2_CAR2S2_16A_BETA_E  0xf29e000f
+#define R0900_P2_BCLC2S216A 0xf29e
 
 /*P2_BCLC2S232A*/
-#define R0900_P2_BCLC2S232A  0xf29f
-#define F0900_P2_DVBS2S232A_NIP  0xf29f0080
-#define F0900_P2_CAR2S2_32BDERAT  0xf29f0040
-#define F0900_P2_CAR2S2_32A_BETA_M  0xf29f0030
-#define F0900_P2_CAR2S2_32A_BETA_E  0xf29f000f
+#define R0900_P2_BCLC2S232A 0xf29f
 
 /*P2_PLROOT2*/
-#define R0900_P2_PLROOT2  0xf2ac
-#define F0900_P2_SHORTFR_DISABLE  0xf2ac0080
-#define F0900_P2_LONGFR_DISABLE  0xf2ac0040
-#define F0900_P2_DUMMYPL_DISABLE  0xf2ac0020
-#define F0900_P2_SHORTFR_AVOID  0xf2ac0010
-#define F0900_P2_PLSCRAMB_MODE  0xf2ac000c
-#define F0900_P2_PLSCRAMB_ROOT2  0xf2ac0003
+#define R0900_P2_PLROOT2 0xf2ac
+#define F0900_P2_PLSCRAMB_MODE 0xf2ac000c
+#define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003
 
 /*P2_PLROOT1*/
-#define R0900_P2_PLROOT1  0xf2ad
-#define F0900_P2_PLSCRAMB_ROOT1  0xf2ad00ff
+#define R0900_P2_PLROOT1 0xf2ad
+#define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff
 
 /*P2_PLROOT0*/
-#define R0900_P2_PLROOT0  0xf2ae
-#define F0900_P2_PLSCRAMB_ROOT0  0xf2ae00ff
+#define R0900_P2_PLROOT0 0xf2ae
+#define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff
 
 /*P2_MODCODLST0*/
-#define R0900_P2_MODCODLST0  0xf2b0
-#define F0900_P2_EN_TOKEN31  0xf2b00080
-#define F0900_P2_SYNCTAG_SELECT  0xf2b00040
-#define F0900_P2_MODCODRQ_MODE  0xf2b00030
+#define R0900_P2_MODCODLST0 0xf2b0
 
 /*P2_MODCODLST1*/
-#define R0900_P2_MODCODLST1  0xf2b1
-#define F0900_P2_DIS_MODCOD29  0xf2b100f0
-#define F0900_P2_DIS_32PSK_9_10  0xf2b1000f
+#define R0900_P2_MODCODLST1 0xf2b1
+#define F0900_P2_DIS_MODCOD29 0xf2b100f0
+#define F0900_P2_DIS_32PSK_9_10 0xf2b1000f
 
 /*P2_MODCODLST2*/
-#define R0900_P2_MODCODLST2  0xf2b2
-#define F0900_P2_DIS_32PSK_8_9  0xf2b200f0
-#define F0900_P2_DIS_32PSK_5_6  0xf2b2000f
+#define R0900_P2_MODCODLST2 0xf2b2
+#define F0900_P2_DIS_32PSK_8_9 0xf2b200f0
+#define F0900_P2_DIS_32PSK_5_6 0xf2b2000f
 
 /*P2_MODCODLST3*/
-#define R0900_P2_MODCODLST3  0xf2b3
-#define F0900_P2_DIS_32PSK_4_5  0xf2b300f0
-#define F0900_P2_DIS_32PSK_3_4  0xf2b3000f
+#define R0900_P2_MODCODLST3 0xf2b3
+#define F0900_P2_DIS_32PSK_4_5 0xf2b300f0
+#define F0900_P2_DIS_32PSK_3_4 0xf2b3000f
 
 /*P2_MODCODLST4*/
-#define R0900_P2_MODCODLST4  0xf2b4
-#define F0900_P2_DIS_16PSK_9_10  0xf2b400f0
-#define F0900_P2_DIS_16PSK_8_9  0xf2b4000f
+#define R0900_P2_MODCODLST4 0xf2b4
+#define F0900_P2_DIS_16PSK_9_10 0xf2b400f0
+#define F0900_P2_DIS_16PSK_8_9 0xf2b4000f
 
 /*P2_MODCODLST5*/
-#define R0900_P2_MODCODLST5  0xf2b5
-#define F0900_P2_DIS_16PSK_5_6  0xf2b500f0
-#define F0900_P2_DIS_16PSK_4_5  0xf2b5000f
+#define R0900_P2_MODCODLST5 0xf2b5
+#define F0900_P2_DIS_16PSK_5_6 0xf2b500f0
+#define F0900_P2_DIS_16PSK_4_5 0xf2b5000f
 
 /*P2_MODCODLST6*/
-#define R0900_P2_MODCODLST6  0xf2b6
-#define F0900_P2_DIS_16PSK_3_4  0xf2b600f0
-#define F0900_P2_DIS_16PSK_2_3  0xf2b6000f
+#define R0900_P2_MODCODLST6 0xf2b6
+#define F0900_P2_DIS_16PSK_3_4 0xf2b600f0
+#define F0900_P2_DIS_16PSK_2_3 0xf2b6000f
 
 /*P2_MODCODLST7*/
-#define R0900_P2_MODCODLST7  0xf2b7
-#define F0900_P2_DIS_8P_9_10  0xf2b700f0
-#define F0900_P2_DIS_8P_8_9  0xf2b7000f
+#define R0900_P2_MODCODLST7 0xf2b7
+#define F0900_P2_DIS_8P_9_10 0xf2b700f0
+#define F0900_P2_DIS_8P_8_9 0xf2b7000f
 
 /*P2_MODCODLST8*/
-#define R0900_P2_MODCODLST8  0xf2b8
-#define F0900_P2_DIS_8P_5_6  0xf2b800f0
-#define F0900_P2_DIS_8P_3_4  0xf2b8000f
+#define R0900_P2_MODCODLST8 0xf2b8
+#define F0900_P2_DIS_8P_5_6 0xf2b800f0
+#define F0900_P2_DIS_8P_3_4 0xf2b8000f
 
 /*P2_MODCODLST9*/
-#define R0900_P2_MODCODLST9  0xf2b9
-#define F0900_P2_DIS_8P_2_3  0xf2b900f0
-#define F0900_P2_DIS_8P_3_5  0xf2b9000f
+#define R0900_P2_MODCODLST9 0xf2b9
+#define F0900_P2_DIS_8P_2_3 0xf2b900f0
+#define F0900_P2_DIS_8P_3_5 0xf2b9000f
 
 /*P2_MODCODLSTA*/
-#define R0900_P2_MODCODLSTA  0xf2ba
-#define F0900_P2_DIS_QP_9_10  0xf2ba00f0
-#define F0900_P2_DIS_QP_8_9  0xf2ba000f
+#define R0900_P2_MODCODLSTA 0xf2ba
+#define F0900_P2_DIS_QP_9_10 0xf2ba00f0
+#define F0900_P2_DIS_QP_8_9 0xf2ba000f
 
 /*P2_MODCODLSTB*/
-#define R0900_P2_MODCODLSTB  0xf2bb
-#define F0900_P2_DIS_QP_5_6  0xf2bb00f0
-#define F0900_P2_DIS_QP_4_5  0xf2bb000f
+#define R0900_P2_MODCODLSTB 0xf2bb
+#define F0900_P2_DIS_QP_5_6 0xf2bb00f0
+#define F0900_P2_DIS_QP_4_5 0xf2bb000f
 
 /*P2_MODCODLSTC*/
-#define R0900_P2_MODCODLSTC  0xf2bc
-#define F0900_P2_DIS_QP_3_4  0xf2bc00f0
-#define F0900_P2_DIS_QP_2_3  0xf2bc000f
+#define R0900_P2_MODCODLSTC 0xf2bc
+#define F0900_P2_DIS_QP_3_4 0xf2bc00f0
+#define F0900_P2_DIS_QP_2_3 0xf2bc000f
 
 /*P2_MODCODLSTD*/
-#define R0900_P2_MODCODLSTD  0xf2bd
-#define F0900_P2_DIS_QP_3_5  0xf2bd00f0
-#define F0900_P2_DIS_QP_1_2  0xf2bd000f
+#define R0900_P2_MODCODLSTD 0xf2bd
+#define F0900_P2_DIS_QP_3_5 0xf2bd00f0
+#define F0900_P2_DIS_QP_1_2 0xf2bd000f
 
 /*P2_MODCODLSTE*/
-#define R0900_P2_MODCODLSTE  0xf2be
-#define F0900_P2_DIS_QP_2_5  0xf2be00f0
-#define F0900_P2_DIS_QP_1_3  0xf2be000f
+#define R0900_P2_MODCODLSTE 0xf2be
+#define F0900_P2_DIS_QP_2_5 0xf2be00f0
+#define F0900_P2_DIS_QP_1_3 0xf2be000f
 
 /*P2_MODCODLSTF*/
-#define R0900_P2_MODCODLSTF  0xf2bf
-#define F0900_P2_DIS_QP_1_4  0xf2bf00f0
-#define F0900_P2_DDEMOD_SET  0xf2bf0002
-#define F0900_P2_DDEMOD_MASK  0xf2bf0001
+#define R0900_P2_MODCODLSTF 0xf2bf
+#define F0900_P2_DIS_QP_1_4 0xf2bf00f0
+
+/*P2_GAUSSR0*/
+#define R0900_P2_GAUSSR0 0xf2c0
+#define F0900_P2_EN_CCIMODE 0xf2c00080
+#define F0900_P2_R0_GAUSSIEN 0xf2c0007f
+
+/*P2_CCIR0*/
+#define R0900_P2_CCIR0 0xf2c1
+#define F0900_P2_CCIDETECT_PLHONLY 0xf2c10080
+#define F0900_P2_R0_CCI 0xf2c1007f
+
+/*P2_CCIQUANT*/
+#define R0900_P2_CCIQUANT 0xf2c2
+#define F0900_P2_CCI_BETA 0xf2c200e0
+#define F0900_P2_CCI_QUANT 0xf2c2001f
+
+/*P2_CCITHRES*/
+#define R0900_P2_CCITHRES 0xf2c3
+#define F0900_P2_CCI_THRESHOLD 0xf2c300ff
+
+/*P2_CCIACC*/
+#define R0900_P2_CCIACC 0xf2c4
+#define F0900_P2_CCI_VALUE 0xf2c400ff
 
 /*P2_DMDRESCFG*/
-#define R0900_P2_DMDRESCFG  0xf2c6
-#define F0900_P2_DMDRES_RESET  0xf2c60080
-#define F0900_P2_DMDRES_NOISESQR  0xf2c60010
-#define F0900_P2_DMDRES_STRALL  0xf2c60008
-#define F0900_P2_DMDRES_NEWONLY  0xf2c60004
-#define F0900_P2_DMDRES_NOSTORE  0xf2c60002
-#define F0900_P2_DMDRES_AGC2MEM  0xf2c60001
+#define R0900_P2_DMDRESCFG 0xf2c6
+#define F0900_P2_DMDRES_RESET 0xf2c60080
+#define F0900_P2_DMDRES_STRALL 0xf2c60008
+#define F0900_P2_DMDRES_NEWONLY 0xf2c60004
+#define F0900_P2_DMDRES_NOSTORE 0xf2c60002
 
 /*P2_DMDRESADR*/
-#define R0900_P2_DMDRESADR  0xf2c7
-#define F0900_P2_SUSP_PREDCANAL  0xf2c70080
-#define F0900_P2_DMDRES_VALIDCFR  0xf2c70040
-#define F0900_P2_DMDRES_MEMFULL  0xf2c70030
-#define F0900_P2_DMDRES_RESNBR  0xf2c7000f
+#define R0900_P2_DMDRESADR 0xf2c7
+#define F0900_P2_DMDRES_VALIDCFR 0xf2c70040
+#define F0900_P2_DMDRES_MEMFULL 0xf2c70030
+#define F0900_P2_DMDRES_RESNBR 0xf2c7000f
 
 /*P2_DMDRESDATA7*/
-#define R0900_P2_DMDRESDATA7  0xf2c8
-#define F0900_P2_DMDRES_DATA7  0xf2c800ff
+#define R0900_P2_DMDRESDATA7 0xf2c8
+#define F0900_P2_DMDRES_DATA7 0xf2c800ff
 
 /*P2_DMDRESDATA6*/
-#define R0900_P2_DMDRESDATA6  0xf2c9
-#define F0900_P2_DMDRES_DATA6  0xf2c900ff
+#define R0900_P2_DMDRESDATA6 0xf2c9
+#define F0900_P2_DMDRES_DATA6 0xf2c900ff
 
 /*P2_DMDRESDATA5*/
-#define R0900_P2_DMDRESDATA5  0xf2ca
-#define F0900_P2_DMDRES_DATA5  0xf2ca00ff
+#define R0900_P2_DMDRESDATA5 0xf2ca
+#define F0900_P2_DMDRES_DATA5 0xf2ca00ff
 
 /*P2_DMDRESDATA4*/
-#define R0900_P2_DMDRESDATA4  0xf2cb
-#define F0900_P2_DMDRES_DATA4  0xf2cb00ff
+#define R0900_P2_DMDRESDATA4 0xf2cb
+#define F0900_P2_DMDRES_DATA4 0xf2cb00ff
 
 /*P2_DMDRESDATA3*/
-#define R0900_P2_DMDRESDATA3  0xf2cc
-#define F0900_P2_DMDRES_DATA3  0xf2cc00ff
+#define R0900_P2_DMDRESDATA3 0xf2cc
+#define F0900_P2_DMDRES_DATA3 0xf2cc00ff
 
 /*P2_DMDRESDATA2*/
-#define R0900_P2_DMDRESDATA2  0xf2cd
-#define F0900_P2_DMDRES_DATA2  0xf2cd00ff
+#define R0900_P2_DMDRESDATA2 0xf2cd
+#define F0900_P2_DMDRES_DATA2 0xf2cd00ff
 
 /*P2_DMDRESDATA1*/
-#define R0900_P2_DMDRESDATA1  0xf2ce
-#define F0900_P2_DMDRES_DATA1  0xf2ce00ff
+#define R0900_P2_DMDRESDATA1 0xf2ce
+#define F0900_P2_DMDRES_DATA1 0xf2ce00ff
 
 /*P2_DMDRESDATA0*/
-#define R0900_P2_DMDRESDATA0  0xf2cf
-#define F0900_P2_DMDRES_DATA0  0xf2cf00ff
+#define R0900_P2_DMDRESDATA0 0xf2cf
+#define F0900_P2_DMDRES_DATA0 0xf2cf00ff
 
 /*P2_FFEI1*/
-#define R0900_P2_FFEI1  0xf2d0
-#define F0900_P2_FFE_ACCI1  0xf2d001ff
+#define R0900_P2_FFEI1 0xf2d0
+#define F0900_P2_FFE_ACCI1 0xf2d001ff
 
 /*P2_FFEQ1*/
-#define R0900_P2_FFEQ1  0xf2d1
-#define F0900_P2_FFE_ACCQ1  0xf2d101ff
+#define R0900_P2_FFEQ1 0xf2d1
+#define F0900_P2_FFE_ACCQ1 0xf2d101ff
 
 /*P2_FFEI2*/
-#define R0900_P2_FFEI2  0xf2d2
-#define F0900_P2_FFE_ACCI2  0xf2d201ff
+#define R0900_P2_FFEI2 0xf2d2
+#define F0900_P2_FFE_ACCI2 0xf2d201ff
 
 /*P2_FFEQ2*/
-#define R0900_P2_FFEQ2  0xf2d3
-#define F0900_P2_FFE_ACCQ2  0xf2d301ff
+#define R0900_P2_FFEQ2 0xf2d3
+#define F0900_P2_FFE_ACCQ2 0xf2d301ff
 
 /*P2_FFEI3*/
-#define R0900_P2_FFEI3  0xf2d4
-#define F0900_P2_FFE_ACCI3  0xf2d401ff
+#define R0900_P2_FFEI3 0xf2d4
+#define F0900_P2_FFE_ACCI3 0xf2d401ff
 
 /*P2_FFEQ3*/
-#define R0900_P2_FFEQ3  0xf2d5
-#define F0900_P2_FFE_ACCQ3  0xf2d501ff
+#define R0900_P2_FFEQ3 0xf2d5
+#define F0900_P2_FFE_ACCQ3 0xf2d501ff
 
 /*P2_FFEI4*/
-#define R0900_P2_FFEI4  0xf2d6
-#define F0900_P2_FFE_ACCI4  0xf2d601ff
+#define R0900_P2_FFEI4 0xf2d6
+#define F0900_P2_FFE_ACCI4 0xf2d601ff
 
 /*P2_FFEQ4*/
-#define R0900_P2_FFEQ4  0xf2d7
-#define F0900_P2_FFE_ACCQ4  0xf2d701ff
+#define R0900_P2_FFEQ4 0xf2d7
+#define F0900_P2_FFE_ACCQ4 0xf2d701ff
 
 /*P2_FFECFG*/
-#define R0900_P2_FFECFG  0xf2d8
-#define F0900_P2_EQUALFFE_ON  0xf2d80040
-#define F0900_P2_EQUAL_USEDSYMB  0xf2d80030
-#define F0900_P2_MU_EQUALFFE  0xf2d80007
+#define R0900_P2_FFECFG 0xf2d8
+#define F0900_P2_EQUALFFE_ON 0xf2d80040
+#define F0900_P2_MU_EQUALFFE 0xf2d80007
 
 /*P2_TNRCFG*/
-#define R0900_P2_TNRCFG  0xf2e0
-#define F0900_P2_TUN_ACKFAIL  0xf2e00080
-#define F0900_P2_TUN_TYPE  0xf2e00070
-#define F0900_P2_TUN_SECSTOP  0xf2e00008
-#define F0900_P2_TUN_VCOSRCH  0xf2e00004
-#define F0900_P2_TUN_MADDRESS  0xf2e00003
+#define R0900_P2_TNRCFG 0xf2e0
+#define F0900_P2_TUN_ACKFAIL 0xf2e00080
+#define F0900_P2_TUN_TYPE 0xf2e00070
+#define F0900_P2_TUN_SECSTOP 0xf2e00008
+#define F0900_P2_TUN_VCOSRCH 0xf2e00004
+#define F0900_P2_TUN_MADDRESS 0xf2e00003
 
 /*P2_TNRCFG2*/
-#define R0900_P2_TNRCFG2  0xf2e1
-#define F0900_P2_TUN_IQSWAP  0xf2e10080
-#define F0900_P2_STB6110_STEP2MHZ  0xf2e10040
-#define F0900_P2_STB6120_DBLI2C  0xf2e10020
-#define F0900_P2_DIS_FCCK  0xf2e10010
-#define F0900_P2_DIS_LPEN  0xf2e10008
-#define F0900_P2_DIS_BWCALC  0xf2e10004
-#define F0900_P2_SHORT_WAITSTATES  0xf2e10002
-#define F0900_P2_DIS_2BWAGC1  0xf2e10001
+#define R0900_P2_TNRCFG2 0xf2e1
+#define F0900_P2_TUN_IQSWAP 0xf2e10080
+#define F0900_P2_DIS_BWCALC 0xf2e10004
+#define F0900_P2_SHORT_WAITSTATES 0xf2e10002
 
 /*P2_TNRXTAL*/
-#define R0900_P2_TNRXTAL  0xf2e4
-#define F0900_P2_TUN_MCLKDECIMAL  0xf2e400e0
-#define F0900_P2_TUN_XTALFREQ  0xf2e4001f
+#define R0900_P2_TNRXTAL 0xf2e4
+#define F0900_P2_TUN_XTALFREQ 0xf2e4001f
 
 /*P2_TNRSTEPS*/
-#define R0900_P2_TNRSTEPS  0xf2e7
-#define F0900_P2_TUNER_BW1P6  0xf2e70080
-#define F0900_P2_BWINC_OFFSET  0xf2e70070
-#define F0900_P2_SOFTSTEP_RNG  0xf2e70008
-#define F0900_P2_TUN_BWOFFSET  0xf2e70107
+#define R0900_P2_TNRSTEPS 0xf2e7
+#define F0900_P2_TUNER_BW0P125 0xf2e70080
+#define F0900_P2_BWINC_OFFSET 0xf2e70170
+#define F0900_P2_SOFTSTEP_RNG 0xf2e70008
+#define F0900_P2_TUN_BWOFFSET 0xf2e70007
 
 /*P2_TNRGAIN*/
-#define R0900_P2_TNRGAIN  0xf2e8
-#define F0900_P2_TUN_KDIVEN  0xf2e800c0
-#define F0900_P2_STB6X00_OCK  0xf2e80030
-#define F0900_P2_TUN_GAIN  0xf2e8000f
+#define R0900_P2_TNRGAIN 0xf2e8
+#define F0900_P2_TUN_KDIVEN 0xf2e800c0
+#define F0900_P2_STB6X00_OCK 0xf2e80030
+#define F0900_P2_TUN_GAIN 0xf2e8000f
 
 /*P2_TNRRF1*/
-#define R0900_P2_TNRRF1  0xf2e9
-#define F0900_P2_TUN_RFFREQ2  0xf2e900ff
+#define R0900_P2_TNRRF1 0xf2e9
+#define F0900_P2_TUN_RFFREQ2 0xf2e900ff
 
 /*P2_TNRRF0*/
-#define R0900_P2_TNRRF0  0xf2ea
-#define F0900_P2_TUN_RFFREQ1  0xf2ea00ff
+#define R0900_P2_TNRRF0 0xf2ea
+#define F0900_P2_TUN_RFFREQ1 0xf2ea00ff
 
 /*P2_TNRBW*/
-#define R0900_P2_TNRBW  0xf2eb
-#define F0900_P2_TUN_RFFREQ0  0xf2eb00c0
-#define F0900_P2_TUN_BW  0xf2eb003f
+#define R0900_P2_TNRBW 0xf2eb
+#define F0900_P2_TUN_RFFREQ0 0xf2eb00c0
+#define F0900_P2_TUN_BW 0xf2eb003f
 
 /*P2_TNRADJ*/
-#define R0900_P2_TNRADJ  0xf2ec
-#define F0900_P2_STB61X0_RCLK  0xf2ec0080
-#define F0900_P2_STB61X0_CALTIME  0xf2ec0040
-#define F0900_P2_STB6X00_DLB  0xf2ec0038
-#define F0900_P2_STB6000_FCL  0xf2ec0007
+#define R0900_P2_TNRADJ 0xf2ec
+#define F0900_P2_STB61X0_CALTIME 0xf2ec0040
 
 /*P2_TNRCTL2*/
-#define R0900_P2_TNRCTL2  0xf2ed
-#define F0900_P2_STB61X0_LCP1_RCCKOFF  0xf2ed0080
-#define F0900_P2_STB61X0_LCP0  0xf2ed0040
-#define F0900_P2_STB61X0_XTOUT_RFOUTS  0xf2ed0020
-#define F0900_P2_STB61X0_XTON_MCKDV  0xf2ed0010
-#define F0900_P2_STB61X0_CALOFF_DCOFF  0xf2ed0008
-#define F0900_P2_STB6110_LPT  0xf2ed0004
-#define F0900_P2_STB6110_RX  0xf2ed0002
-#define F0900_P2_STB6110_SYN  0xf2ed0001
+#define R0900_P2_TNRCTL2 0xf2ed
+#define F0900_P2_STB61X0_RCCKOFF 0xf2ed0080
+#define F0900_P2_STB61X0_ICP_SDOFF 0xf2ed0040
+#define F0900_P2_STB61X0_DCLOOPOFF 0xf2ed0020
+#define F0900_P2_STB61X0_REFOUTSEL 0xf2ed0010
+#define F0900_P2_STB61X0_CALOFF 0xf2ed0008
+#define F0900_P2_STB6XX0_LPT_BEN 0xf2ed0004
+#define F0900_P2_STB6XX0_RX_OSCP 0xf2ed0002
+#define F0900_P2_STB6XX0_SYN 0xf2ed0001
 
 /*P2_TNRCFG3*/
-#define R0900_P2_TNRCFG3  0xf2ee
-#define F0900_P2_STB6120_DISCTRL1  0xf2ee0080
-#define F0900_P2_STB6120_INVORDER  0xf2ee0040
-#define F0900_P2_STB6120_ENCTRL6  0xf2ee0020
-#define F0900_P2_TUN_PLLFREQ  0xf2ee001c
-#define F0900_P2_TUN_I2CFREQ_MODE  0xf2ee0003
+#define R0900_P2_TNRCFG3 0xf2ee
+#define F0900_P2_TUN_PLLFREQ 0xf2ee001c
+#define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003
 
 /*P2_TNRLAUNCH*/
-#define R0900_P2_TNRLAUNCH  0xf2f0
+#define R0900_P2_TNRLAUNCH 0xf2f0
 
 /*P2_TNRLD*/
-#define R0900_P2_TNRLD  0xf2f0
-#define F0900_P2_TUNLD_VCOING  0xf2f00080
-#define F0900_P2_TUN_REG1FAIL  0xf2f00040
-#define F0900_P2_TUN_REG2FAIL  0xf2f00020
-#define F0900_P2_TUN_REG3FAIL  0xf2f00010
-#define F0900_P2_TUN_REG4FAIL  0xf2f00008
-#define F0900_P2_TUN_REG5FAIL  0xf2f00004
-#define F0900_P2_TUN_BWING  0xf2f00002
-#define F0900_P2_TUN_LOCKED  0xf2f00001
+#define R0900_P2_TNRLD 0xf2f0
+#define F0900_P2_TUNLD_VCOING 0xf2f00080
+#define F0900_P2_TUN_REG1FAIL 0xf2f00040
+#define F0900_P2_TUN_REG2FAIL 0xf2f00020
+#define F0900_P2_TUN_REG3FAIL 0xf2f00010
+#define F0900_P2_TUN_REG4FAIL 0xf2f00008
+#define F0900_P2_TUN_REG5FAIL 0xf2f00004
+#define F0900_P2_TUN_BWING 0xf2f00002
+#define F0900_P2_TUN_LOCKED 0xf2f00001
 
 /*P2_TNROBSL*/
-#define R0900_P2_TNROBSL  0xf2f6
-#define F0900_P2_TUN_I2CABORTED  0xf2f60080
-#define F0900_P2_TUN_LPEN  0xf2f60040
-#define F0900_P2_TUN_FCCK  0xf2f60020
-#define F0900_P2_TUN_I2CLOCKED  0xf2f60010
-#define F0900_P2_TUN_PROGDONE  0xf2f6000c
-#define F0900_P2_TUN_RFRESTE1  0xf2f60003
+#define R0900_P2_TNROBSL 0xf2f6
+#define F0900_P2_TUN_I2CABORTED 0xf2f60080
+#define F0900_P2_TUN_LPEN 0xf2f60040
+#define F0900_P2_TUN_FCCK 0xf2f60020
+#define F0900_P2_TUN_I2CLOCKED 0xf2f60010
+#define F0900_P2_TUN_PROGDONE 0xf2f6000c
+#define F0900_P2_TUN_RFRESTE1 0xf2f60003
 
 /*P2_TNRRESTE*/
-#define R0900_P2_TNRRESTE  0xf2f7
-#define F0900_P2_TUN_RFRESTE0  0xf2f700ff
+#define R0900_P2_TNRRESTE 0xf2f7
+#define F0900_P2_TUN_RFRESTE0 0xf2f700ff
 
 /*P2_SMAPCOEF7*/
-#define R0900_P2_SMAPCOEF7  0xf300
-#define F0900_P2_DIS_QSCALE  0xf3000080
-#define F0900_P2_SMAPCOEF_Q_LLR12  0xf300017f
+#define R0900_P2_SMAPCOEF7 0xf300
+#define F0900_P2_DIS_QSCALE 0xf3000080
+#define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f
 
 /*P2_SMAPCOEF6*/
-#define R0900_P2_SMAPCOEF6  0xf301
-#define F0900_P2_DIS_NEWSCALE  0xf3010008
-#define F0900_P2_ADJ_8PSKLLR1  0xf3010004
-#define F0900_P2_OLD_8PSKLLR1  0xf3010002
-#define F0900_P2_DIS_AB8PSK  0xf3010001
+#define R0900_P2_SMAPCOEF6 0xf301
+#define F0900_P2_ADJ_8PSKLLR1 0xf3010004
+#define F0900_P2_OLD_8PSKLLR1 0xf3010002
+#define F0900_P2_DIS_AB8PSK 0xf3010001
 
 /*P2_SMAPCOEF5*/
-#define R0900_P2_SMAPCOEF5  0xf302
-#define F0900_P2_DIS_8SCALE  0xf3020080
-#define F0900_P2_SMAPCOEF_8P_LLR23  0xf302017f
+#define R0900_P2_SMAPCOEF5 0xf302
+#define F0900_P2_DIS_8SCALE 0xf3020080
+#define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f
+
+/*P2_NCO2MAX1*/
+#define R0900_P2_NCO2MAX1 0xf314
+#define F0900_P2_TETA2_MAXVABS1 0xf31400ff
+
+/*P2_NCO2MAX0*/
+#define R0900_P2_NCO2MAX0 0xf315
+#define F0900_P2_TETA2_MAXVABS0 0xf31500ff
+
+/*P2_NCO2FR1*/
+#define R0900_P2_NCO2FR1 0xf316
+#define F0900_P2_NCO2FINAL_ANGLE1 0xf31600ff
+
+/*P2_NCO2FR0*/
+#define R0900_P2_NCO2FR0 0xf317
+#define F0900_P2_NCO2FINAL_ANGLE0 0xf31700ff
+
+/*P2_CFR2AVRGE1*/
+#define R0900_P2_CFR2AVRGE1 0xf318
+#define F0900_P2_I2C_CFR2AVERAGE1 0xf31800ff
+
+/*P2_CFR2AVRGE0*/
+#define R0900_P2_CFR2AVRGE0 0xf319
+#define F0900_P2_I2C_CFR2AVERAGE0 0xf31900ff
 
 /*P2_DMDPLHSTAT*/
-#define R0900_P2_DMDPLHSTAT  0xf320
-#define F0900_P2_PLH_STATISTIC  0xf32000ff
+#define R0900_P2_DMDPLHSTAT 0xf320
+#define F0900_P2_PLH_STATISTIC 0xf32000ff
 
 /*P2_LOCKTIME3*/
-#define R0900_P2_LOCKTIME3  0xf322
-#define F0900_P2_DEMOD_LOCKTIME3  0xf32200ff
+#define R0900_P2_LOCKTIME3 0xf322
+#define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff
 
 /*P2_LOCKTIME2*/
-#define R0900_P2_LOCKTIME2  0xf323
-#define F0900_P2_DEMOD_LOCKTIME2  0xf32300ff
+#define R0900_P2_LOCKTIME2 0xf323
+#define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff
 
 /*P2_LOCKTIME1*/
-#define R0900_P2_LOCKTIME1  0xf324
-#define F0900_P2_DEMOD_LOCKTIME1  0xf32400ff
+#define R0900_P2_LOCKTIME1 0xf324
+#define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff
 
 /*P2_LOCKTIME0*/
-#define R0900_P2_LOCKTIME0  0xf325
-#define F0900_P2_DEMOD_LOCKTIME0  0xf32500ff
+#define R0900_P2_LOCKTIME0 0xf325
+#define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff
 
 /*P2_VITSCALE*/
-#define R0900_P2_VITSCALE  0xf332
-#define F0900_P2_NVTH_NOSRANGE  0xf3320080
-#define F0900_P2_VERROR_MAXMODE  0xf3320040
-#define F0900_P2_KDIV_MODE  0xf3320030
-#define F0900_P2_NSLOWSN_LOCKED  0xf3320008
-#define F0900_P2_DELOCK_PRFLOSS  0xf3320004
-#define F0900_P2_DIS_RSFLOCK  0xf3320002
+#define R0900_P2_VITSCALE 0xf332
+#define F0900_P2_NVTH_NOSRANGE 0xf3320080
+#define F0900_P2_VERROR_MAXMODE 0xf3320040
+#define F0900_P2_NSLOWSN_LOCKED 0xf3320008
+#define F0900_P2_DIS_RSFLOCK 0xf3320002
 
 /*P2_FECM*/
-#define R0900_P2_FECM  0xf333
-#define F0900_P2_DSS_DVB  0xf3330080
-#define F0900_P2_DEMOD_BYPASS  0xf3330040
-#define F0900_P2_CMP_SLOWMODE  0xf3330020
-#define F0900_P2_DSS_SRCH  0xf3330010
-#define F0900_P2_DIFF_MODEVIT  0xf3330004
-#define F0900_P2_SYNCVIT  0xf3330002
-#define F0900_P2_IQINV  0xf3330001
+#define R0900_P2_FECM 0xf333
+#define F0900_P2_DSS_DVB 0xf3330080
+#define F0900_P2_DSS_SRCH 0xf3330010
+#define F0900_P2_SYNCVIT 0xf3330002
+#define F0900_P2_IQINV 0xf3330001
 
 /*P2_VTH12*/
-#define R0900_P2_VTH12  0xf334
-#define F0900_P2_VTH12  0xf33400ff
+#define R0900_P2_VTH12 0xf334
+#define F0900_P2_VTH12 0xf33400ff
 
 /*P2_VTH23*/
-#define R0900_P2_VTH23  0xf335
-#define F0900_P2_VTH23  0xf33500ff
+#define R0900_P2_VTH23 0xf335
+#define F0900_P2_VTH23 0xf33500ff
 
 /*P2_VTH34*/
-#define R0900_P2_VTH34  0xf336
-#define F0900_P2_VTH34  0xf33600ff
+#define R0900_P2_VTH34 0xf336
+#define F0900_P2_VTH34 0xf33600ff
 
 /*P2_VTH56*/
-#define R0900_P2_VTH56  0xf337
-#define F0900_P2_VTH56  0xf33700ff
+#define R0900_P2_VTH56 0xf337
+#define F0900_P2_VTH56 0xf33700ff
 
 /*P2_VTH67*/
-#define R0900_P2_VTH67  0xf338
-#define F0900_P2_VTH67  0xf33800ff
+#define R0900_P2_VTH67 0xf338
+#define F0900_P2_VTH67 0xf33800ff
 
 /*P2_VTH78*/
-#define R0900_P2_VTH78  0xf339
-#define F0900_P2_VTH78  0xf33900ff
+#define R0900_P2_VTH78 0xf339
+#define F0900_P2_VTH78 0xf33900ff
 
 /*P2_VITCURPUN*/
-#define R0900_P2_VITCURPUN  0xf33a
-#define F0900_P2_VIT_MAPPING  0xf33a00e0
-#define F0900_P2_VIT_CURPUN  0xf33a001f
+#define R0900_P2_VITCURPUN 0xf33a
+#define F0900_P2_VIT_CURPUN 0xf33a001f
 
 /*P2_VERROR*/
-#define R0900_P2_VERROR  0xf33b
-#define F0900_P2_REGERR_VIT  0xf33b00ff
+#define R0900_P2_VERROR 0xf33b
+#define F0900_P2_REGERR_VIT 0xf33b00ff
 
 /*P2_PRVIT*/
-#define R0900_P2_PRVIT  0xf33c
-#define F0900_P2_DIS_VTHLOCK  0xf33c0040
-#define F0900_P2_E7_8VIT  0xf33c0020
-#define F0900_P2_E6_7VIT  0xf33c0010
-#define F0900_P2_E5_6VIT  0xf33c0008
-#define F0900_P2_E3_4VIT  0xf33c0004
-#define F0900_P2_E2_3VIT  0xf33c0002
-#define F0900_P2_E1_2VIT  0xf33c0001
+#define R0900_P2_PRVIT 0xf33c
+#define F0900_P2_DIS_VTHLOCK 0xf33c0040
+#define F0900_P2_E7_8VIT 0xf33c0020
+#define F0900_P2_E6_7VIT 0xf33c0010
+#define F0900_P2_E5_6VIT 0xf33c0008
+#define F0900_P2_E3_4VIT 0xf33c0004
+#define F0900_P2_E2_3VIT 0xf33c0002
+#define F0900_P2_E1_2VIT 0xf33c0001
 
 /*P2_VAVSRVIT*/
-#define R0900_P2_VAVSRVIT  0xf33d
-#define F0900_P2_AMVIT  0xf33d0080
-#define F0900_P2_FROZENVIT  0xf33d0040
-#define F0900_P2_SNVIT  0xf33d0030
-#define F0900_P2_TOVVIT  0xf33d000c
-#define F0900_P2_HYPVIT  0xf33d0003
+#define R0900_P2_VAVSRVIT 0xf33d
+#define F0900_P2_AMVIT 0xf33d0080
+#define F0900_P2_FROZENVIT 0xf33d0040
+#define F0900_P2_SNVIT 0xf33d0030
+#define F0900_P2_TOVVIT 0xf33d000c
+#define F0900_P2_HYPVIT 0xf33d0003
 
 /*P2_VSTATUSVIT*/
-#define R0900_P2_VSTATUSVIT  0xf33e
-#define F0900_P2_VITERBI_ON  0xf33e0080
-#define F0900_P2_END_LOOPVIT  0xf33e0040
-#define F0900_P2_VITERBI_DEPRF  0xf33e0020
-#define F0900_P2_PRFVIT  0xf33e0010
-#define F0900_P2_LOCKEDVIT  0xf33e0008
-#define F0900_P2_VITERBI_DELOCK  0xf33e0004
-#define F0900_P2_VIT_DEMODSEL  0xf33e0002
-#define F0900_P2_VITERBI_COMPOUT  0xf33e0001
+#define R0900_P2_VSTATUSVIT 0xf33e
+#define F0900_P2_PRFVIT 0xf33e0010
+#define F0900_P2_LOCKEDVIT 0xf33e0008
 
 /*P2_VTHINUSE*/
-#define R0900_P2_VTHINUSE  0xf33f
-#define F0900_P2_VIT_INUSE  0xf33f00ff
+#define R0900_P2_VTHINUSE 0xf33f
+#define F0900_P2_VIT_INUSE 0xf33f00ff
 
 /*P2_KDIV12*/
-#define R0900_P2_KDIV12  0xf340
-#define F0900_P2_KDIV12_MANUAL  0xf3400080
-#define F0900_P2_K_DIVIDER_12  0xf340007f
+#define R0900_P2_KDIV12 0xf340
+#define F0900_P2_K_DIVIDER_12 0xf340007f
 
 /*P2_KDIV23*/
-#define R0900_P2_KDIV23  0xf341
-#define F0900_P2_KDIV23_MANUAL  0xf3410080
-#define F0900_P2_K_DIVIDER_23  0xf341007f
+#define R0900_P2_KDIV23 0xf341
+#define F0900_P2_K_DIVIDER_23 0xf341007f
 
 /*P2_KDIV34*/
-#define R0900_P2_KDIV34  0xf342
-#define F0900_P2_KDIV34_MANUAL  0xf3420080
-#define F0900_P2_K_DIVIDER_34  0xf342007f
+#define R0900_P2_KDIV34 0xf342
+#define F0900_P2_K_DIVIDER_34 0xf342007f
 
 /*P2_KDIV56*/
-#define R0900_P2_KDIV56  0xf343
-#define F0900_P2_KDIV56_MANUAL  0xf3430080
-#define F0900_P2_K_DIVIDER_56  0xf343007f
+#define R0900_P2_KDIV56 0xf343
+#define F0900_P2_K_DIVIDER_56 0xf343007f
 
 /*P2_KDIV67*/
-#define R0900_P2_KDIV67  0xf344
-#define F0900_P2_KDIV67_MANUAL  0xf3440080
-#define F0900_P2_K_DIVIDER_67  0xf344007f
+#define R0900_P2_KDIV67 0xf344
+#define F0900_P2_K_DIVIDER_67 0xf344007f
 
 /*P2_KDIV78*/
-#define R0900_P2_KDIV78  0xf345
-#define F0900_P2_KDIV78_MANUAL  0xf3450080
-#define F0900_P2_K_DIVIDER_78  0xf345007f
+#define R0900_P2_KDIV78 0xf345
+#define F0900_P2_K_DIVIDER_78 0xf345007f
 
 /*P2_PDELCTRL1*/
-#define R0900_P2_PDELCTRL1  0xf350
-#define F0900_P2_INV_MISMASK  0xf3500080
-#define F0900_P2_FORCE_ACCEPTED  0xf3500040
-#define F0900_P2_FILTER_EN  0xf3500020
-#define F0900_P2_FORCE_PKTDELINUSE  0xf3500010
-#define F0900_P2_HYSTEN  0xf3500008
-#define F0900_P2_HYSTSWRST  0xf3500004
-#define F0900_P2_EN_MIS00  0xf3500002
-#define F0900_P2_ALGOSWRST  0xf3500001
+#define R0900_P2_PDELCTRL1 0xf350
+#define F0900_P2_INV_MISMASK 0xf3500080
+#define F0900_P2_FILTER_EN 0xf3500020
+#define F0900_P2_EN_MIS00 0xf3500002
+#define F0900_P2_ALGOSWRST 0xf3500001
 
 /*P2_PDELCTRL2*/
-#define R0900_P2_PDELCTRL2  0xf351
-#define F0900_P2_FORCE_CONTINUOUS  0xf3510080
-#define F0900_P2_RESET_UPKO_COUNT  0xf3510040
-#define F0900_P2_USER_PKTDELIN_NB  0xf3510020
-#define F0900_P2_FORCE_LOCKED  0xf3510010
-#define F0900_P2_DATA_UNBBSCRAM  0xf3510008
-#define F0900_P2_FORCE_LONGPKT  0xf3510004
-#define F0900_P2_FRAME_MODE  0xf3510002
+#define R0900_P2_PDELCTRL2 0xf351
+#define F0900_P2_RESET_UPKO_COUNT 0xf3510040
+#define F0900_P2_FRAME_MODE 0xf3510002
+#define F0900_P2_NOBCHERRFLG_USE 0xf3510001
 
 /*P2_HYSTTHRESH*/
-#define R0900_P2_HYSTTHRESH  0xf354
-#define F0900_P2_UNLCK_THRESH  0xf35400f0
-#define F0900_P2_DELIN_LCK_THRESH  0xf354000f
+#define R0900_P2_HYSTTHRESH 0xf354
+#define F0900_P2_UNLCK_THRESH 0xf35400f0
+#define F0900_P2_DELIN_LCK_THRESH 0xf354000f
 
 /*P2_ISIENTRY*/
-#define R0900_P2_ISIENTRY  0xf35e
-#define F0900_P2_ISI_ENTRY  0xf35e00ff
+#define R0900_P2_ISIENTRY 0xf35e
+#define F0900_P2_ISI_ENTRY 0xf35e00ff
 
 /*P2_ISIBITENA*/
-#define R0900_P2_ISIBITENA  0xf35f
-#define F0900_P2_ISI_BIT_EN  0xf35f00ff
+#define R0900_P2_ISIBITENA 0xf35f
+#define F0900_P2_ISI_BIT_EN 0xf35f00ff
 
 /*P2_MATSTR1*/
-#define R0900_P2_MATSTR1  0xf360
-#define F0900_P2_MATYPE_CURRENT1  0xf36000ff
+#define R0900_P2_MATSTR1 0xf360
+#define F0900_P2_MATYPE_CURRENT1 0xf36000ff
 
 /*P2_MATSTR0*/
-#define R0900_P2_MATSTR0  0xf361
-#define F0900_P2_MATYPE_CURRENT0  0xf36100ff
+#define R0900_P2_MATSTR0 0xf361
+#define F0900_P2_MATYPE_CURRENT0 0xf36100ff
 
 /*P2_UPLSTR1*/
-#define R0900_P2_UPLSTR1  0xf362
-#define F0900_P2_UPL_CURRENT1  0xf36200ff
+#define R0900_P2_UPLSTR1 0xf362
+#define F0900_P2_UPL_CURRENT1 0xf36200ff
 
 /*P2_UPLSTR0*/
-#define R0900_P2_UPLSTR0  0xf363
-#define F0900_P2_UPL_CURRENT0  0xf36300ff
+#define R0900_P2_UPLSTR0 0xf363
+#define F0900_P2_UPL_CURRENT0 0xf36300ff
 
 /*P2_DFLSTR1*/
-#define R0900_P2_DFLSTR1  0xf364
-#define F0900_P2_DFL_CURRENT1  0xf36400ff
+#define R0900_P2_DFLSTR1 0xf364
+#define F0900_P2_DFL_CURRENT1 0xf36400ff
 
 /*P2_DFLSTR0*/
-#define R0900_P2_DFLSTR0  0xf365
-#define F0900_P2_DFL_CURRENT0  0xf36500ff
+#define R0900_P2_DFLSTR0 0xf365
+#define F0900_P2_DFL_CURRENT0 0xf36500ff
 
 /*P2_SYNCSTR*/
-#define R0900_P2_SYNCSTR  0xf366
-#define F0900_P2_SYNC_CURRENT  0xf36600ff
+#define R0900_P2_SYNCSTR 0xf366
+#define F0900_P2_SYNC_CURRENT 0xf36600ff
 
 /*P2_SYNCDSTR1*/
-#define R0900_P2_SYNCDSTR1  0xf367
-#define F0900_P2_SYNCD_CURRENT1  0xf36700ff
+#define R0900_P2_SYNCDSTR1 0xf367
+#define F0900_P2_SYNCD_CURRENT1 0xf36700ff
 
 /*P2_SYNCDSTR0*/
-#define R0900_P2_SYNCDSTR0  0xf368
-#define F0900_P2_SYNCD_CURRENT0  0xf36800ff
+#define R0900_P2_SYNCDSTR0 0xf368
+#define F0900_P2_SYNCD_CURRENT0 0xf36800ff
 
 /*P2_PDELSTATUS1*/
-#define R0900_P2_PDELSTATUS1  0xf369
-#define F0900_P2_PKTDELIN_DELOCK  0xf3690080
-#define F0900_P2_SYNCDUPDFL_BADDFL  0xf3690040
-#define F0900_P2_CONTINUOUS_STREAM  0xf3690020
-#define F0900_P2_UNACCEPTED_STREAM  0xf3690010
-#define F0900_P2_BCH_ERROR_FLAG  0xf3690008
-#define F0900_P2_BBHCRCKO  0xf3690004
-#define F0900_P2_PKTDELIN_LOCK  0xf3690002
-#define F0900_P2_FIRST_LOCK  0xf3690001
+#define R0900_P2_PDELSTATUS1 0xf369
+#define F0900_P2_PKTDELIN_DELOCK 0xf3690080
+#define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040
+#define F0900_P2_CONTINUOUS_STREAM 0xf3690020
+#define F0900_P2_UNACCEPTED_STREAM 0xf3690010
+#define F0900_P2_BCH_ERROR_FLAG 0xf3690008
+#define F0900_P2_PKTDELIN_LOCK 0xf3690002
+#define F0900_P2_FIRST_LOCK 0xf3690001
 
 /*P2_PDELSTATUS2*/
-#define R0900_P2_PDELSTATUS2  0xf36a
-#define F0900_P2_PKTDEL_DEMODSEL  0xf36a0080
-#define F0900_P2_FRAME_MODCOD  0xf36a007c
-#define F0900_P2_FRAME_TYPE  0xf36a0003
+#define R0900_P2_PDELSTATUS2 0xf36a
+#define F0900_P2_FRAME_MODCOD 0xf36a007c
+#define F0900_P2_FRAME_TYPE 0xf36a0003
 
 /*P2_BBFCRCKO1*/
-#define R0900_P2_BBFCRCKO1  0xf36b
-#define F0900_P2_BBHCRC_KOCNT1  0xf36b00ff
+#define R0900_P2_BBFCRCKO1 0xf36b
+#define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff
 
 /*P2_BBFCRCKO0*/
-#define R0900_P2_BBFCRCKO0  0xf36c
-#define F0900_P2_BBHCRC_KOCNT0  0xf36c00ff
+#define R0900_P2_BBFCRCKO0 0xf36c
+#define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff
 
 /*P2_UPCRCKO1*/
-#define R0900_P2_UPCRCKO1  0xf36d
-#define F0900_P2_PKTCRC_KOCNT1  0xf36d00ff
+#define R0900_P2_UPCRCKO1 0xf36d
+#define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff
 
 /*P2_UPCRCKO0*/
-#define R0900_P2_UPCRCKO0  0xf36e
-#define F0900_P2_PKTCRC_KOCNT0  0xf36e00ff
+#define R0900_P2_UPCRCKO0 0xf36e
+#define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff
+
+/*P2_PDELCTRL3*/
+#define R0900_P2_PDELCTRL3 0xf36f
+#define F0900_P2_PKTDEL_CONTFAIL 0xf36f0080
+#define F0900_P2_NOFIFO_BCHERR 0xf36f0020
 
 /*P2_TSSTATEM*/
-#define R0900_P2_TSSTATEM  0xf370
-#define F0900_P2_TSDIL_ON  0xf3700080
-#define F0900_P2_TSSKIPRS_ON  0xf3700040
-#define F0900_P2_TSRS_ON  0xf3700020
-#define F0900_P2_TSDESCRAMB_ON  0xf3700010
-#define F0900_P2_TSFRAME_MODE  0xf3700008
-#define F0900_P2_TS_DISABLE  0xf3700004
-#define F0900_P2_TSACM_MODE  0xf3700002
-#define F0900_P2_TSOUT_NOSYNC  0xf3700001
+#define R0900_P2_TSSTATEM 0xf370
+#define F0900_P2_TSDIL_ON 0xf3700080
+#define F0900_P2_TSRS_ON 0xf3700020
+#define F0900_P2_TSDESCRAMB_ON 0xf3700010
+#define F0900_P2_TSFRAME_MODE 0xf3700008
+#define F0900_P2_TS_DISABLE 0xf3700004
+#define F0900_P2_TSOUT_NOSYNC 0xf3700001
 
 /*P2_TSCFGH*/
-#define R0900_P2_TSCFGH  0xf372
-#define F0900_P2_TSFIFO_DVBCI  0xf3720080
-#define F0900_P2_TSFIFO_SERIAL  0xf3720040
-#define F0900_P2_TSFIFO_TEIUPDATE  0xf3720020
-#define F0900_P2_TSFIFO_DUTY50  0xf3720010
-#define F0900_P2_TSFIFO_HSGNLOUT  0xf3720008
-#define F0900_P2_TSFIFO_ERRMODE  0xf3720006
-#define F0900_P2_RST_HWARE  0xf3720001
+#define R0900_P2_TSCFGH 0xf372
+#define F0900_P2_TSFIFO_DVBCI 0xf3720080
+#define F0900_P2_TSFIFO_SERIAL 0xf3720040
+#define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020
+#define F0900_P2_TSFIFO_DUTY50 0xf3720010
+#define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008
+#define F0900_P2_TSFIFO_ERRMODE 0xf3720006
+#define F0900_P2_RST_HWARE 0xf3720001
 
 /*P2_TSCFGM*/
-#define R0900_P2_TSCFGM  0xf373
-#define F0900_P2_TSFIFO_MANSPEED  0xf37300c0
-#define F0900_P2_TSFIFO_PERMDATA  0xf3730020
-#define F0900_P2_TSFIFO_NONEWSGNL  0xf3730010
-#define F0900_P2_TSFIFO_BITSPEED  0xf3730008
-#define F0900_P2_NPD_SPECDVBS2  0xf3730004
-#define F0900_P2_TSFIFO_STOPCKDIS  0xf3730002
-#define F0900_P2_TSFIFO_INVDATA  0xf3730001
+#define R0900_P2_TSCFGM 0xf373
+#define F0900_P2_TSFIFO_MANSPEED 0xf37300c0
+#define F0900_P2_TSFIFO_PERMDATA 0xf3730020
+#define F0900_P2_TSFIFO_DPUNACT 0xf3730002
+#define F0900_P2_TSFIFO_INVDATA 0xf3730001
 
 /*P2_TSCFGL*/
-#define R0900_P2_TSCFGL  0xf374
-#define F0900_P2_TSFIFO_BCLKDEL1CK  0xf37400c0
-#define F0900_P2_BCHERROR_MODE  0xf3740030
-#define F0900_P2_TSFIFO_NSGNL2DATA  0xf3740008
-#define F0900_P2_TSFIFO_EMBINDVB  0xf3740004
-#define F0900_P2_TSFIFO_DPUNACT  0xf3740002
-#define F0900_P2_TSFIFO_NPDOFF  0xf3740001
+#define R0900_P2_TSCFGL 0xf374
+#define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0
+#define F0900_P2_BCHERROR_MODE 0xf3740030
+#define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008
+#define F0900_P2_TSFIFO_EMBINDVB 0xf3740004
+#define F0900_P2_TSFIFO_BITSPEED 0xf3740003
 
 /*P2_TSINSDELH*/
-#define R0900_P2_TSINSDELH  0xf376
-#define F0900_P2_TSDEL_SYNCBYTE  0xf3760080
-#define F0900_P2_TSDEL_XXHEADER  0xf3760040
-#define F0900_P2_TSDEL_BBHEADER  0xf3760020
-#define F0900_P2_TSDEL_DATAFIELD  0xf3760010
-#define F0900_P2_TSINSDEL_ISCR  0xf3760008
-#define F0900_P2_TSINSDEL_NPD  0xf3760004
-#define F0900_P2_TSINSDEL_RSPARITY  0xf3760002
-#define F0900_P2_TSINSDEL_CRC8  0xf3760001
+#define R0900_P2_TSINSDELH 0xf376
+#define F0900_P2_TSDEL_SYNCBYTE 0xf3760080
+#define F0900_P2_TSDEL_XXHEADER 0xf3760040
+#define F0900_P2_TSDEL_BBHEADER 0xf3760020
+#define F0900_P2_TSDEL_DATAFIELD 0xf3760010
+#define F0900_P2_TSINSDEL_ISCR 0xf3760008
+#define F0900_P2_TSINSDEL_NPD 0xf3760004
+#define F0900_P2_TSINSDEL_RSPARITY 0xf3760002
+#define F0900_P2_TSINSDEL_CRC8 0xf3760001
+
+/*P2_TSDIVN*/
+#define R0900_P2_TSDIVN 0xf379
+#define F0900_P2_TSFIFO_SPEEDMODE 0xf37900c0
+
+/*P2_TSCFG4*/
+#define R0900_P2_TSCFG4 0xf37a
+#define F0900_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0
 
 /*P2_TSSPEED*/
-#define R0900_P2_TSSPEED  0xf380
-#define F0900_P2_TSFIFO_OUTSPEED  0xf38000ff
+#define R0900_P2_TSSPEED 0xf380
+#define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff
 
 /*P2_TSSTATUS*/
-#define R0900_P2_TSSTATUS  0xf381
-#define F0900_P2_TSFIFO_LINEOK  0xf3810080
-#define F0900_P2_TSFIFO_ERROR  0xf3810040
-#define F0900_P2_TSFIFO_DATA7  0xf3810020
-#define F0900_P2_TSFIFO_NOSYNC  0xf3810010
-#define F0900_P2_ISCR_INITIALIZED  0xf3810008
-#define F0900_P2_ISCR_UPDATED  0xf3810004
-#define F0900_P2_SOFFIFO_UNREGUL  0xf3810002
-#define F0900_P2_DIL_READY  0xf3810001
+#define R0900_P2_TSSTATUS 0xf381
+#define F0900_P2_TSFIFO_LINEOK 0xf3810080
+#define F0900_P2_TSFIFO_ERROR 0xf3810040
+#define F0900_P2_DIL_READY 0xf3810001
 
 /*P2_TSSTATUS2*/
-#define R0900_P2_TSSTATUS2  0xf382
-#define F0900_P2_TSFIFO_DEMODSEL  0xf3820080
-#define F0900_P2_TSFIFOSPEED_STORE  0xf3820040
-#define F0900_P2_DILXX_RESET  0xf3820020
-#define F0900_P2_TSSERIAL_IMPOS  0xf3820010
-#define F0900_P2_TSFIFO_LINENOK  0xf3820008
-#define F0900_P2_BITSPEED_EVENT  0xf3820004
-#define F0900_P2_SCRAMBDETECT  0xf3820002
-#define F0900_P2_ULDTV67_FALSELOCK  0xf3820001
+#define R0900_P2_TSSTATUS2 0xf382
+#define F0900_P2_TSFIFO_DEMODSEL 0xf3820080
+#define F0900_P2_TSFIFOSPEED_STORE 0xf3820040
+#define F0900_P2_DILXX_RESET 0xf3820020
+#define F0900_P2_TSSERIAL_IMPOS 0xf3820010
+#define F0900_P2_SCRAMBDETECT 0xf3820002
 
 /*P2_TSBITRATE1*/
-#define R0900_P2_TSBITRATE1  0xf383
-#define F0900_P2_TSFIFO_BITRATE1  0xf38300ff
+#define R0900_P2_TSBITRATE1 0xf383
+#define F0900_P2_TSFIFO_BITRATE1 0xf38300ff
 
 /*P2_TSBITRATE0*/
-#define R0900_P2_TSBITRATE0  0xf384
-#define F0900_P2_TSFIFO_BITRATE0  0xf38400ff
+#define R0900_P2_TSBITRATE0 0xf384
+#define F0900_P2_TSFIFO_BITRATE0 0xf38400ff
 
 /*P2_ERRCTRL1*/
-#define R0900_P2_ERRCTRL1  0xf398
-#define F0900_P2_ERR_SOURCE1  0xf39800f0
-#define F0900_P2_NUM_EVENT1  0xf3980007
+#define R0900_P2_ERRCTRL1 0xf398
+#define F0900_P2_ERR_SOURCE1 0xf39800f0
+#define F0900_P2_NUM_EVENT1 0xf3980007
 
 /*P2_ERRCNT12*/
-#define R0900_P2_ERRCNT12  0xf399
-#define F0900_P2_ERRCNT1_OLDVALUE  0xf3990080
-#define F0900_P2_ERR_CNT12  0xf399007f
+#define R0900_P2_ERRCNT12 0xf399
+#define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080
+#define F0900_P2_ERR_CNT12 0xf399007f
 
 /*P2_ERRCNT11*/
-#define R0900_P2_ERRCNT11  0xf39a
-#define F0900_P2_ERR_CNT11  0xf39a00ff
+#define R0900_P2_ERRCNT11 0xf39a
+#define F0900_P2_ERR_CNT11 0xf39a00ff
 
 /*P2_ERRCNT10*/
-#define R0900_P2_ERRCNT10  0xf39b
-#define F0900_P2_ERR_CNT10  0xf39b00ff
+#define R0900_P2_ERRCNT10 0xf39b
+#define F0900_P2_ERR_CNT10 0xf39b00ff
 
 /*P2_ERRCTRL2*/
-#define R0900_P2_ERRCTRL2  0xf39c
-#define F0900_P2_ERR_SOURCE2  0xf39c00f0
-#define F0900_P2_NUM_EVENT2  0xf39c0007
+#define R0900_P2_ERRCTRL2 0xf39c
+#define F0900_P2_ERR_SOURCE2 0xf39c00f0
+#define F0900_P2_NUM_EVENT2 0xf39c0007
 
 /*P2_ERRCNT22*/
-#define R0900_P2_ERRCNT22  0xf39d
-#define F0900_P2_ERRCNT2_OLDVALUE  0xf39d0080
-#define F0900_P2_ERR_CNT22  0xf39d007f
+#define R0900_P2_ERRCNT22 0xf39d
+#define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080
+#define F0900_P2_ERR_CNT22 0xf39d007f
 
 /*P2_ERRCNT21*/
-#define R0900_P2_ERRCNT21  0xf39e
-#define F0900_P2_ERR_CNT21  0xf39e00ff
+#define R0900_P2_ERRCNT21 0xf39e
+#define F0900_P2_ERR_CNT21 0xf39e00ff
 
 /*P2_ERRCNT20*/
-#define R0900_P2_ERRCNT20  0xf39f
-#define F0900_P2_ERR_CNT20  0xf39f00ff
+#define R0900_P2_ERRCNT20 0xf39f
+#define F0900_P2_ERR_CNT20 0xf39f00ff
 
 /*P2_FECSPY*/
-#define R0900_P2_FECSPY  0xf3a0
-#define F0900_P2_SPY_ENABLE  0xf3a00080
-#define F0900_P2_NO_SYNCBYTE  0xf3a00040
-#define F0900_P2_SERIAL_MODE  0xf3a00020
-#define F0900_P2_UNUSUAL_PACKET  0xf3a00010
-#define F0900_P2_BER_PACKMODE  0xf3a00008
-#define F0900_P2_BERMETER_LMODE  0xf3a00002
-#define F0900_P2_BERMETER_RESET  0xf3a00001
+#define R0900_P2_FECSPY 0xf3a0
+#define F0900_P2_SPY_ENABLE 0xf3a00080
+#define F0900_P2_NO_SYNCBYTE 0xf3a00040
+#define F0900_P2_SERIAL_MODE 0xf3a00020
+#define F0900_P2_UNUSUAL_PACKET 0xf3a00010
+#define F0900_P2_BERMETER_DATAMODE 0xf3a00008
+#define F0900_P2_BERMETER_LMODE 0xf3a00002
+#define F0900_P2_BERMETER_RESET 0xf3a00001
 
 /*P2_FSPYCFG*/
-#define R0900_P2_FSPYCFG  0xf3a1
-#define F0900_P2_FECSPY_INPUT  0xf3a100c0
-#define F0900_P2_RST_ON_ERROR  0xf3a10020
-#define F0900_P2_ONE_SHOT  0xf3a10010
-#define F0900_P2_I2C_MODE  0xf3a1000c
-#define F0900_P2_SPY_HYSTERESIS  0xf3a10003
+#define R0900_P2_FSPYCFG 0xf3a1
+#define F0900_P2_FECSPY_INPUT 0xf3a100c0
+#define F0900_P2_RST_ON_ERROR 0xf3a10020
+#define F0900_P2_ONE_SHOT 0xf3a10010
+#define F0900_P2_I2C_MODE 0xf3a1000c
+#define F0900_P2_SPY_HYSTERESIS 0xf3a10003
 
 /*P2_FSPYDATA*/
-#define R0900_P2_FSPYDATA  0xf3a2
-#define F0900_P2_SPY_STUFFING  0xf3a20080
-#define F0900_P2_NOERROR_PKTJITTER  0xf3a20040
-#define F0900_P2_SPY_CNULLPKT  0xf3a20020
-#define F0900_P2_SPY_OUTDATA_MODE  0xf3a2001f
+#define R0900_P2_FSPYDATA 0xf3a2
+#define F0900_P2_SPY_STUFFING 0xf3a20080
+#define F0900_P2_SPY_CNULLPKT 0xf3a20020
+#define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f
 
 /*P2_FSPYOUT*/
-#define R0900_P2_FSPYOUT  0xf3a3
-#define F0900_P2_FSPY_DIRECT  0xf3a30080
-#define F0900_P2_SPY_OUTDATA_BUS  0xf3a30038
-#define F0900_P2_STUFF_MODE  0xf3a30007
+#define R0900_P2_FSPYOUT 0xf3a3
+#define F0900_P2_FSPY_DIRECT 0xf3a30080
+#define F0900_P2_STUFF_MODE 0xf3a30007
 
 /*P2_FSTATUS*/
-#define R0900_P2_FSTATUS  0xf3a4
-#define F0900_P2_SPY_ENDSIM  0xf3a40080
-#define F0900_P2_VALID_SIM  0xf3a40040
-#define F0900_P2_FOUND_SIGNAL  0xf3a40020
-#define F0900_P2_DSS_SYNCBYTE  0xf3a40010
-#define F0900_P2_RESULT_STATE  0xf3a4000f
+#define R0900_P2_FSTATUS 0xf3a4
+#define F0900_P2_SPY_ENDSIM 0xf3a40080
+#define F0900_P2_VALID_SIM 0xf3a40040
+#define F0900_P2_FOUND_SIGNAL 0xf3a40020
+#define F0900_P2_DSS_SYNCBYTE 0xf3a40010
+#define F0900_P2_RESULT_STATE 0xf3a4000f
 
 /*P2_FBERCPT4*/
-#define R0900_P2_FBERCPT4  0xf3a8
-#define F0900_P2_FBERMETER_CPT4  0xf3a800ff
+#define R0900_P2_FBERCPT4 0xf3a8
+#define F0900_P2_FBERMETER_CPT4 0xf3a800ff
 
 /*P2_FBERCPT3*/
-#define R0900_P2_FBERCPT3  0xf3a9
-#define F0900_P2_FBERMETER_CPT3  0xf3a900ff
+#define R0900_P2_FBERCPT3 0xf3a9
+#define F0900_P2_FBERMETER_CPT3 0xf3a900ff
 
 /*P2_FBERCPT2*/
-#define R0900_P2_FBERCPT2  0xf3aa
-#define F0900_P2_FBERMETER_CPT2  0xf3aa00ff
+#define R0900_P2_FBERCPT2 0xf3aa
+#define F0900_P2_FBERMETER_CPT2 0xf3aa00ff
 
 /*P2_FBERCPT1*/
-#define R0900_P2_FBERCPT1  0xf3ab
-#define F0900_P2_FBERMETER_CPT1  0xf3ab00ff
+#define R0900_P2_FBERCPT1 0xf3ab
+#define F0900_P2_FBERMETER_CPT1 0xf3ab00ff
 
 /*P2_FBERCPT0*/
-#define R0900_P2_FBERCPT0  0xf3ac
-#define F0900_P2_FBERMETER_CPT0  0xf3ac00ff
+#define R0900_P2_FBERCPT0 0xf3ac
+#define F0900_P2_FBERMETER_CPT0 0xf3ac00ff
 
 /*P2_FBERERR2*/
-#define R0900_P2_FBERERR2  0xf3ad
-#define F0900_P2_FBERMETER_ERR2  0xf3ad00ff
+#define R0900_P2_FBERERR2 0xf3ad
+#define F0900_P2_FBERMETER_ERR2 0xf3ad00ff
 
 /*P2_FBERERR1*/
-#define R0900_P2_FBERERR1  0xf3ae
-#define F0900_P2_FBERMETER_ERR1  0xf3ae00ff
+#define R0900_P2_FBERERR1 0xf3ae
+#define F0900_P2_FBERMETER_ERR1 0xf3ae00ff
 
 /*P2_FBERERR0*/
-#define R0900_P2_FBERERR0  0xf3af
-#define F0900_P2_FBERMETER_ERR0  0xf3af00ff
+#define R0900_P2_FBERERR0 0xf3af
+#define F0900_P2_FBERMETER_ERR0 0xf3af00ff
 
 /*P2_FSPYBER*/
-#define R0900_P2_FSPYBER  0xf3b2
-#define F0900_P2_FSPYOBS_XORREAD  0xf3b20040
-#define F0900_P2_FSPYBER_OBSMODE  0xf3b20020
-#define F0900_P2_FSPYBER_SYNCBYTE  0xf3b20010
-#define F0900_P2_FSPYBER_UNSYNC  0xf3b20008
-#define F0900_P2_FSPYBER_CTIME  0xf3b20007
+#define R0900_P2_FSPYBER 0xf3b2
+#define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010
+#define F0900_P2_FSPYBER_UNSYNC 0xf3b20008
+#define F0900_P2_FSPYBER_CTIME 0xf3b20007
 
 /*P1_IQCONST*/
-#define R0900_P1_IQCONST  0xf400
-#define F0900_P1_CONSTEL_SELECT  0xf4000060
-#define F0900_P1_IQSYMB_SEL  0xf400001f
+#define R0900_P1_IQCONST 0xf400
+#define IQCONST REGx(R0900_P1_IQCONST)
+#define F0900_P1_CONSTEL_SELECT 0xf4000060
+#define F0900_P1_IQSYMB_SEL 0xf400001f
 
 /*P1_NOSCFG*/
-#define R0900_P1_NOSCFG  0xf401
-#define F0900_P1_DUMMYPL_NOSDATA  0xf4010020
-#define F0900_P1_NOSPLH_BETA  0xf4010018
-#define F0900_P1_NOSDATA_BETA  0xf4010007
+#define R0900_P1_NOSCFG 0xf401
+#define NOSCFG REGx(R0900_P1_NOSCFG)
+#define F0900_P1_DUMMYPL_NOSDATA 0xf4010020
+#define F0900_P1_NOSPLH_BETA 0xf4010018
+#define F0900_P1_NOSDATA_BETA 0xf4010007
 
 /*P1_ISYMB*/
-#define R0900_P1_ISYMB  0xf402
-#define F0900_P1_I_SYMBOL  0xf40201ff
+#define R0900_P1_ISYMB 0xf402
+#define ISYMB REGx(R0900_P1_ISYMB)
+#define F0900_P1_I_SYMBOL 0xf40201ff
 
 /*P1_QSYMB*/
-#define R0900_P1_QSYMB  0xf403
-#define F0900_P1_Q_SYMBOL  0xf40301ff
+#define R0900_P1_QSYMB 0xf403
+#define QSYMB REGx(R0900_P1_QSYMB)
+#define F0900_P1_Q_SYMBOL 0xf40301ff
 
 /*P1_AGC1CFG*/
-#define R0900_P1_AGC1CFG  0xf404
-#define F0900_P1_DC_FROZEN  0xf4040080
-#define F0900_P1_DC_CORRECT  0xf4040040
-#define F0900_P1_AMM_FROZEN  0xf4040020
-#define F0900_P1_AMM_CORRECT  0xf4040010
-#define F0900_P1_QUAD_FROZEN  0xf4040008
-#define F0900_P1_QUAD_CORRECT  0xf4040004
-#define F0900_P1_DCCOMP_SLOW  0xf4040002
-#define F0900_P1_IQMISM_SLOW  0xf4040001
+#define R0900_P1_AGC1CFG 0xf404
+#define AGC1CFG REGx(R0900_P1_AGC1CFG)
+#define F0900_P1_DC_FROZEN 0xf4040080
+#define F0900_P1_DC_CORRECT 0xf4040040
+#define F0900_P1_AMM_FROZEN 0xf4040020
+#define F0900_P1_AMM_CORRECT 0xf4040010
+#define F0900_P1_QUAD_FROZEN 0xf4040008
+#define F0900_P1_QUAD_CORRECT 0xf4040004
 
 /*P1_AGC1CN*/
-#define R0900_P1_AGC1CN  0xf406
-#define F0900_P1_AGC1_LOCKED  0xf4060080
-#define F0900_P1_AGC1_OVERFLOW  0xf4060040
-#define F0900_P1_AGC1_NOSLOWLK  0xf4060020
-#define F0900_P1_AGC1_MINPOWER  0xf4060010
-#define F0900_P1_AGCOUT_FAST  0xf4060008
-#define F0900_P1_AGCIQ_BETA  0xf4060007
+#define R0900_P1_AGC1CN 0xf406
+#define AGC1CN REGx(R0900_P1_AGC1CN)
+#define F0900_P1_AGC1_LOCKED 0xf4060080
+#define F0900_P1_AGC1_MINPOWER 0xf4060010
+#define F0900_P1_AGCOUT_FAST 0xf4060008
+#define F0900_P1_AGCIQ_BETA 0xf4060007
 
 /*P1_AGC1REF*/
-#define R0900_P1_AGC1REF  0xf407
-#define F0900_P1_AGCIQ_REF  0xf40700ff
+#define R0900_P1_AGC1REF 0xf407
+#define AGC1REF REGx(R0900_P1_AGC1REF)
+#define F0900_P1_AGCIQ_REF 0xf40700ff
 
 /*P1_IDCCOMP*/
-#define R0900_P1_IDCCOMP  0xf408
-#define F0900_P1_IAVERAGE_ADJ  0xf40801ff
+#define R0900_P1_IDCCOMP 0xf408
+#define IDCCOMP REGx(R0900_P1_IDCCOMP)
+#define F0900_P1_IAVERAGE_ADJ 0xf40801ff
 
 /*P1_QDCCOMP*/
-#define R0900_P1_QDCCOMP  0xf409
-#define F0900_P1_QAVERAGE_ADJ  0xf40901ff
+#define R0900_P1_QDCCOMP 0xf409
+#define QDCCOMP REGx(R0900_P1_QDCCOMP)
+#define F0900_P1_QAVERAGE_ADJ 0xf40901ff
 
 /*P1_POWERI*/
-#define R0900_P1_POWERI  0xf40a
-#define F0900_P1_POWER_I  0xf40a00ff
+#define R0900_P1_POWERI 0xf40a
+#define POWERI REGx(R0900_P1_POWERI)
+#define F0900_P1_POWER_I 0xf40a00ff
+#define POWER_I FLDx(F0900_P1_POWER_I)
 
 /*P1_POWERQ*/
-#define R0900_P1_POWERQ  0xf40b
-#define F0900_P1_POWER_Q  0xf40b00ff
+#define R0900_P1_POWERQ 0xf40b
+#define POWERQ REGx(R0900_P1_POWERQ)
+#define F0900_P1_POWER_Q 0xf40b00ff
+#define POWER_Q FLDx(F0900_P1_POWER_Q)
 
 /*P1_AGC1AMM*/
-#define R0900_P1_AGC1AMM  0xf40c
-#define F0900_P1_AMM_VALUE  0xf40c00ff
+#define R0900_P1_AGC1AMM 0xf40c
+#define AGC1AMM REGx(R0900_P1_AGC1AMM)
+#define F0900_P1_AMM_VALUE 0xf40c00ff
 
 /*P1_AGC1QUAD*/
-#define R0900_P1_AGC1QUAD  0xf40d
-#define F0900_P1_QUAD_VALUE  0xf40d01ff
+#define R0900_P1_AGC1QUAD 0xf40d
+#define AGC1QUAD REGx(R0900_P1_AGC1QUAD)
+#define F0900_P1_QUAD_VALUE 0xf40d01ff
 
 /*P1_AGCIQIN1*/
-#define R0900_P1_AGCIQIN1  0xf40e
-#define F0900_P1_AGCIQ_VALUE1  0xf40e00ff
+#define R0900_P1_AGCIQIN1 0xf40e
+#define AGCIQIN1 REGx(R0900_P1_AGCIQIN1)
+#define F0900_P1_AGCIQ_VALUE1 0xf40e00ff
+#define AGCIQ_VALUE1 FLDx(F0900_P1_AGCIQ_VALUE1)
 
 /*P1_AGCIQIN0*/
-#define R0900_P1_AGCIQIN0  0xf40f
-#define F0900_P1_AGCIQ_VALUE0  0xf40f00ff
+#define R0900_P1_AGCIQIN0 0xf40f
+#define AGCIQIN0 REGx(R0900_P1_AGCIQIN0)
+#define F0900_P1_AGCIQ_VALUE0 0xf40f00ff
+#define AGCIQ_VALUE0 FLDx(F0900_P1_AGCIQ_VALUE0)
 
 /*P1_DEMOD*/
-#define R0900_P1_DEMOD  0xf410
-#define F0900_P1_DEMOD_STOP  0xf4100040
-#define F0900_P1_SPECINV_CONTROL  0xf4100030
-#define F0900_P1_FORCE_ENASAMP  0xf4100008
-#define F0900_P1_MANUAL_ROLLOFF  0xf4100004
-#define F0900_P1_ROLLOFF_CONTROL  0xf4100003
+#define R0900_P1_DEMOD 0xf410
+#define DEMOD REGx(R0900_P1_DEMOD)
+#define F0900_P1_MANUALS2_ROLLOFF 0xf4100080
+#define MANUALS2_ROLLOFF FLDx(F0900_P1_MANUALS2_ROLLOFF)
+
+#define F0900_P1_SPECINV_CONTROL 0xf4100030
+#define SPECINV_CONTROL FLDx(F0900_P1_SPECINV_CONTROL)
+#define F0900_P1_FORCE_ENASAMP 0xf4100008
+#define F0900_P1_MANUALSX_ROLLOFF 0xf4100004
+#define MANUALSX_ROLLOFF FLDx(F0900_P1_MANUALSX_ROLLOFF)
+#define F0900_P1_ROLLOFF_CONTROL 0xf4100003
+#define ROLLOFF_CONTROL FLDx(F0900_P1_ROLLOFF_CONTROL)
 
 /*P1_DMDMODCOD*/
-#define R0900_P1_DMDMODCOD  0xf411
-#define F0900_P1_MANUAL_MODCOD  0xf4110080
-#define F0900_P1_DEMOD_MODCOD  0xf411007c
-#define F0900_P1_DEMOD_TYPE  0xf4110003
+#define R0900_P1_DMDMODCOD 0xf411
+#define DMDMODCOD REGx(R0900_P1_DMDMODCOD)
+#define F0900_P1_MANUAL_MODCOD 0xf4110080
+#define F0900_P1_DEMOD_MODCOD 0xf411007c
+#define DEMOD_MODCOD FLDx(F0900_P1_DEMOD_MODCOD)
+#define F0900_P1_DEMOD_TYPE 0xf4110003
+#define DEMOD_TYPE FLDx(F0900_P1_DEMOD_TYPE)
 
 /*P1_DSTATUS*/
-#define R0900_P1_DSTATUS  0xf412
-#define F0900_P1_CAR_LOCK  0xf4120080
-#define F0900_P1_TMGLOCK_QUALITY  0xf4120060
-#define F0900_P1_SDVBS1_ENABLE  0xf4120010
-#define F0900_P1_LOCK_DEFINITIF  0xf4120008
-#define F0900_P1_TIMING_IS_LOCKED  0xf4120004
-#define F0900_P1_COARSE_TMGLOCK  0xf4120002
-#define F0900_P1_COARSE_CARLOCK  0xf4120001
+#define R0900_P1_DSTATUS 0xf412
+#define DSTATUS REGx(R0900_P1_DSTATUS)
+#define F0900_P1_CAR_LOCK 0xf4120080
+#define F0900_P1_TMGLOCK_QUALITY 0xf4120060
+#define TMGLOCK_QUALITY FLDx(F0900_P1_TMGLOCK_QUALITY)
+#define F0900_P1_LOCK_DEFINITIF 0xf4120008
+#define LOCK_DEFINITIF FLDx(F0900_P1_LOCK_DEFINITIF)
+#define F0900_P1_OVADC_DETECT 0xf4120001
 
 /*P1_DSTATUS2*/
-#define R0900_P1_DSTATUS2  0xf413
-#define F0900_P1_DEMOD_DELOCK  0xf4130080
-#define F0900_P1_DEMOD_TIMEOUT  0xf4130040
-#define F0900_P1_MODCODRQ_SYNCTAG  0xf4130020
-#define F0900_P1_POLYPH_SATEVENT  0xf4130010
-#define F0900_P1_AGC1_NOSIGNALACK  0xf4130008
-#define F0900_P1_AGC2_OVERFLOW  0xf4130004
-#define F0900_P1_CFR_OVERFLOW  0xf4130002
-#define F0900_P1_GAMMA_OVERUNDER  0xf4130001
+#define R0900_P1_DSTATUS2 0xf413
+#define DSTATUS2 REGx(R0900_P1_DSTATUS2)
+#define F0900_P1_DEMOD_DELOCK 0xf4130080
+#define F0900_P1_AGC1_NOSIGNALACK 0xf4130008
+#define F0900_P1_AGC2_OVERFLOW 0xf4130004
+#define F0900_P1_CFR_OVERFLOW 0xf4130002
+#define F0900_P1_GAMMA_OVERUNDER 0xf4130001
 
 /*P1_DMDCFGMD*/
-#define R0900_P1_DMDCFGMD  0xf414
-#define F0900_P1_DVBS2_ENABLE  0xf4140080
-#define F0900_P1_DVBS1_ENABLE  0xf4140040
-#define F0900_P1_CFR_AUTOSCAN  0xf4140020
-#define F0900_P1_SCAN_ENABLE  0xf4140010
-#define F0900_P1_TUN_AUTOSCAN  0xf4140008
-#define F0900_P1_NOFORCE_RELOCK  0xf4140004
-#define F0900_P1_TUN_RNG  0xf4140003
+#define R0900_P1_DMDCFGMD 0xf414
+#define DMDCFGMD REGx(R0900_P1_DMDCFGMD)
+#define F0900_P1_DVBS2_ENABLE 0xf4140080
+#define DVBS2_ENABLE FLDx(F0900_P1_DVBS2_ENABLE)
+#define F0900_P1_DVBS1_ENABLE 0xf4140040
+#define DVBS1_ENABLE FLDx(F0900_P1_DVBS1_ENABLE)
+#define F0900_P1_SCAN_ENABLE 0xf4140010
+#define SCAN_ENABLE FLDx(F0900_P1_SCAN_ENABLE)
+#define F0900_P1_CFR_AUTOSCAN 0xf4140008
+#define CFR_AUTOSCAN FLDx(F0900_P1_CFR_AUTOSCAN)
+#define F0900_P1_TUN_RNG 0xf4140003
 
 /*P1_DMDCFG2*/
-#define R0900_P1_DMDCFG2  0xf415
-#define F0900_P1_AGC1_WAITLOCK  0xf4150080
-#define F0900_P1_S1S2_SEQUENTIAL  0xf4150040
-#define F0900_P1_OVERFLOW_TIMEOUT  0xf4150020
-#define F0900_P1_SCANFAIL_TIMEOUT  0xf4150010
-#define F0900_P1_DMDTOUT_BACK  0xf4150008
-#define F0900_P1_CARLOCK_S1ENABLE  0xf4150004
-#define F0900_P1_COARSE_LK3MODE  0xf4150002
-#define F0900_P1_COARSE_LK2MODE  0xf4150001
+#define R0900_P1_DMDCFG2 0xf415
+#define DMDCFG2 REGx(R0900_P1_DMDCFG2)
+#define F0900_P1_S1S2_SEQUENTIAL 0xf4150040
+#define S1S2_SEQUENTIAL FLDx(F0900_P1_S1S2_SEQUENTIAL)
+#define F0900_P1_INFINITE_RELOCK 0xf4150010
 
 /*P1_DMDISTATE*/
-#define R0900_P1_DMDISTATE  0xf416
-#define F0900_P1_I2C_NORESETDMODE  0xf4160080
-#define F0900_P1_FORCE_ETAPED  0xf4160040
-#define F0900_P1_SDMDRST_DIRCLK  0xf4160020
-#define F0900_P1_I2C_DEMOD_MODE  0xf416001f
+#define R0900_P1_DMDISTATE 0xf416
+#define DMDISTATE REGx(R0900_P1_DMDISTATE)
+#define F0900_P1_I2C_DEMOD_MODE 0xf416001f
+#define DEMOD_MODE FLDx(F0900_P1_I2C_DEMOD_MODE)
 
 /*P1_DMDT0M*/
-#define R0900_P1_DMDT0M  0xf417
-#define F0900_P1_DMDT0_MIN  0xf41700ff
+#define R0900_P1_DMDT0M 0xf417
+#define DMDT0M REGx(R0900_P1_DMDT0M)
+#define F0900_P1_DMDT0_MIN 0xf41700ff
 
 /*P1_DMDSTATE*/
-#define R0900_P1_DMDSTATE  0xf41b
-#define F0900_P1_DEMOD_LOCKED  0xf41b0080
-#define F0900_P1_HEADER_MODE  0xf41b0060
-#define F0900_P1_DEMOD_MODE  0xf41b001f
+#define R0900_P1_DMDSTATE 0xf41b
+#define DMDSTATE REGx(R0900_P1_DMDSTATE)
+#define F0900_P1_HEADER_MODE 0xf41b0060
+#define HEADER_MODE FLDx(F0900_P1_HEADER_MODE)
 
 /*P1_DMDFLYW*/
-#define R0900_P1_DMDFLYW  0xf41c
-#define F0900_P1_I2C_IRQVAL  0xf41c00f0
-#define F0900_P1_FLYWHEEL_CPT  0xf41c000f
+#define R0900_P1_DMDFLYW 0xf41c
+#define DMDFLYW REGx(R0900_P1_DMDFLYW)
+#define F0900_P1_I2C_IRQVAL 0xf41c00f0
+#define F0900_P1_FLYWHEEL_CPT 0xf41c000f
+#define FLYWHEEL_CPT FLDx(F0900_P1_FLYWHEEL_CPT)
 
 /*P1_DSTATUS3*/
-#define R0900_P1_DSTATUS3  0xf41d
-#define F0900_P1_CFR_ZIGZAG  0xf41d0080
-#define F0900_P1_DEMOD_CFGMODE  0xf41d0060
-#define F0900_P1_GAMMA_LOWBAUDRATE  0xf41d0010
-#define F0900_P1_RELOCK_MODE  0xf41d0008
-#define F0900_P1_DEMOD_FAIL  0xf41d0004
-#define F0900_P1_ETAPE1A_DVBXMEM  0xf41d0003
+#define R0900_P1_DSTATUS3 0xf41d
+#define DSTATUS3 REGx(R0900_P1_DSTATUS3)
+#define F0900_P1_DEMOD_CFGMODE 0xf41d0060
 
 /*P1_DMDCFG3*/
-#define R0900_P1_DMDCFG3  0xf41e
-#define F0900_P1_DVBS1_TMGWAIT  0xf41e0080
-#define F0900_P1_NO_BWCENTERING  0xf41e0040
-#define F0900_P1_INV_SEQSRCH  0xf41e0020
-#define F0900_P1_DIS_SFRUPLOW_TRK  0xf41e0010
-#define F0900_P1_NOSTOP_FIFOFULL  0xf41e0008
-#define F0900_P1_LOCKTIME_MODE  0xf41e0007
+#define R0900_P1_DMDCFG3 0xf41e
+#define DMDCFG3 REGx(R0900_P1_DMDCFG3)
+#define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008
 
 /*P1_DMDCFG4*/
-#define R0900_P1_DMDCFG4  0xf41f
-#define F0900_P1_TUNER_NRELAUNCH  0xf41f0008
-#define F0900_P1_DIS_CLKENABLE  0xf41f0004
-#define F0900_P1_DIS_HDRDIVLOCK  0xf41f0002
-#define F0900_P1_NO_TNRWBINIT  0xf41f0001
+#define R0900_P1_DMDCFG4 0xf41f
+#define DMDCFG4 REGx(R0900_P1_DMDCFG4)
+#define F0900_P1_TUNER_NRELAUNCH 0xf41f0008
 
 /*P1_CORRELMANT*/
-#define R0900_P1_CORRELMANT  0xf420
-#define F0900_P1_CORREL_MANT  0xf42000ff
+#define R0900_P1_CORRELMANT 0xf420
+#define CORRELMANT REGx(R0900_P1_CORRELMANT)
+#define F0900_P1_CORREL_MANT 0xf42000ff
 
 /*P1_CORRELABS*/
-#define R0900_P1_CORRELABS  0xf421
-#define F0900_P1_CORREL_ABS  0xf42100ff
+#define R0900_P1_CORRELABS 0xf421
+#define CORRELABS REGx(R0900_P1_CORRELABS)
+#define F0900_P1_CORREL_ABS 0xf42100ff
 
 /*P1_CORRELEXP*/
-#define R0900_P1_CORRELEXP  0xf422
-#define F0900_P1_CORREL_ABSEXP  0xf42200f0
-#define F0900_P1_CORREL_EXP  0xf422000f
+#define R0900_P1_CORRELEXP 0xf422
+#define CORRELEXP REGx(R0900_P1_CORRELEXP)
+#define F0900_P1_CORREL_ABSEXP 0xf42200f0
+#define F0900_P1_CORREL_EXP 0xf422000f
 
 /*P1_PLHMODCOD*/
-#define R0900_P1_PLHMODCOD  0xf424
-#define F0900_P1_SPECINV_DEMOD  0xf4240080
-#define F0900_P1_PLH_MODCOD  0xf424007c
-#define F0900_P1_PLH_TYPE  0xf4240003
-
-/*P1_AGCK32*/
-#define R0900_P1_AGCK32  0xf42b
-#define F0900_P1_R3ADJOFF_32APSK  0xf42b0080
-#define F0900_P1_R2ADJOFF_32APSK  0xf42b0040
-#define F0900_P1_R1ADJOFF_32APSK  0xf42b0020
-#define F0900_P1_RADJ_32APSK  0xf42b001f
+#define R0900_P1_PLHMODCOD 0xf424
+#define PLHMODCOD REGx(R0900_P1_PLHMODCOD)
+#define F0900_P1_SPECINV_DEMOD 0xf4240080
+#define SPECINV_DEMOD FLDx(F0900_P1_SPECINV_DEMOD)
+#define F0900_P1_PLH_MODCOD 0xf424007c
+#define F0900_P1_PLH_TYPE 0xf4240003
+
+/*P1_DMDREG*/
+#define R0900_P1_DMDREG 0xf425
+#define DMDREG REGx(R0900_P1_DMDREG)
+#define F0900_P1_DECIM_PLFRAMES 0xf4250001
 
 /*P1_AGC2O*/
-#define R0900_P1_AGC2O  0xf42c
-#define F0900_P1_AGC2REF_ADJUSTING  0xf42c0080
-#define F0900_P1_AGC2_COARSEFAST  0xf42c0040
-#define F0900_P1_AGC2_LKSQRT  0xf42c0020
-#define F0900_P1_AGC2_LKMODE  0xf42c0010
-#define F0900_P1_AGC2_LKEQUA  0xf42c0008
-#define F0900_P1_AGC2_COEF  0xf42c0007
+#define R0900_P1_AGC2O 0xf42c
+#define AGC2O REGx(R0900_P1_AGC2O)
+#define F0900_P1_AGC2_COEF 0xf42c0007
 
 /*P1_AGC2REF*/
-#define R0900_P1_AGC2REF  0xf42d
-#define F0900_P1_AGC2_REF  0xf42d00ff
+#define R0900_P1_AGC2REF 0xf42d
+#define AGC2REF REGx(R0900_P1_AGC2REF)
+#define F0900_P1_AGC2_REF 0xf42d00ff
 
 /*P1_AGC1ADJ*/
-#define R0900_P1_AGC1ADJ  0xf42e
-#define F0900_P1_AGC1ADJ_MANUAL  0xf42e0080
-#define F0900_P1_AGC1_ADJUSTED  0xf42e017f
+#define R0900_P1_AGC1ADJ 0xf42e
+#define AGC1ADJ REGx(R0900_P1_AGC1ADJ)
+#define F0900_P1_AGC1_ADJUSTED 0xf42e007f
 
 /*P1_AGC2I1*/
-#define R0900_P1_AGC2I1  0xf436
-#define F0900_P1_AGC2_INTEGRATOR1  0xf43600ff
+#define R0900_P1_AGC2I1 0xf436
+#define AGC2I1 REGx(R0900_P1_AGC2I1)
+#define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff
 
 /*P1_AGC2I0*/
-#define R0900_P1_AGC2I0  0xf437
-#define F0900_P1_AGC2_INTEGRATOR0  0xf43700ff
+#define R0900_P1_AGC2I0 0xf437
+#define AGC2I0 REGx(R0900_P1_AGC2I0)
+#define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff
 
 /*P1_CARCFG*/
-#define R0900_P1_CARCFG  0xf438
-#define F0900_P1_CFRUPLOW_AUTO  0xf4380080
-#define F0900_P1_CFRUPLOW_TEST  0xf4380040
-#define F0900_P1_EN_CAR2CENTER  0xf4380020
-#define F0900_P1_CARHDR_NODIV8  0xf4380010
-#define F0900_P1_I2C_ROTA  0xf4380008
-#define F0900_P1_ROTAON  0xf4380004
-#define F0900_P1_PH_DET_ALGO  0xf4380003
+#define R0900_P1_CARCFG 0xf438
+#define CARCFG REGx(R0900_P1_CARCFG)
+#define F0900_P1_CFRUPLOW_AUTO 0xf4380080
+#define F0900_P1_CFRUPLOW_TEST 0xf4380040
+#define F0900_P1_ROTAON 0xf4380004
+#define F0900_P1_PH_DET_ALGO 0xf4380003
 
 /*P1_ACLC*/
-#define R0900_P1_ACLC  0xf439
-#define F0900_P1_STOP_S2ALPHA  0xf43900c0
-#define F0900_P1_CAR_ALPHA_MANT  0xf4390030
-#define F0900_P1_CAR_ALPHA_EXP  0xf439000f
+#define R0900_P1_ACLC 0xf439
+#define ACLC REGx(R0900_P1_ACLC)
+#define F0900_P1_CAR_ALPHA_MANT 0xf4390030
+#define F0900_P1_CAR_ALPHA_EXP 0xf439000f
 
 /*P1_BCLC*/
-#define R0900_P1_BCLC  0xf43a
-#define F0900_P1_STOP_S2BETA  0xf43a00c0
-#define F0900_P1_CAR_BETA_MANT  0xf43a0030
-#define F0900_P1_CAR_BETA_EXP  0xf43a000f
+#define R0900_P1_BCLC 0xf43a
+#define BCLC REGx(R0900_P1_BCLC)
+#define F0900_P1_CAR_BETA_MANT 0xf43a0030
+#define F0900_P1_CAR_BETA_EXP 0xf43a000f
 
 /*P1_CARFREQ*/
-#define R0900_P1_CARFREQ  0xf43d
-#define F0900_P1_KC_COARSE_EXP  0xf43d00f0
-#define F0900_P1_BETA_FREQ  0xf43d000f
+#define R0900_P1_CARFREQ 0xf43d
+#define CARFREQ REGx(R0900_P1_CARFREQ)
+#define F0900_P1_KC_COARSE_EXP 0xf43d00f0
+#define F0900_P1_BETA_FREQ 0xf43d000f
 
 /*P1_CARHDR*/
-#define R0900_P1_CARHDR  0xf43e
-#define F0900_P1_K_FREQ_HDR  0xf43e00ff
+#define R0900_P1_CARHDR 0xf43e
+#define CARHDR REGx(R0900_P1_CARHDR)
+#define F0900_P1_K_FREQ_HDR 0xf43e00ff
 
 /*P1_LDT*/
-#define R0900_P1_LDT  0xf43f
-#define F0900_P1_CARLOCK_THRES  0xf43f01ff
+#define R0900_P1_LDT 0xf43f
+#define LDT REGx(R0900_P1_LDT)
+#define F0900_P1_CARLOCK_THRES 0xf43f01ff
 
 /*P1_LDT2*/
-#define R0900_P1_LDT2  0xf440
-#define F0900_P1_CARLOCK_THRES2  0xf44001ff
+#define R0900_P1_LDT2 0xf440
+#define LDT2 REGx(R0900_P1_LDT2)
+#define F0900_P1_CARLOCK_THRES2 0xf44001ff
 
 /*P1_CFRICFG*/
-#define R0900_P1_CFRICFG  0xf441
-#define F0900_P1_CFRINIT_UNVALRNG  0xf4410080
-#define F0900_P1_CFRINIT_LUNVALCPT  0xf4410040
-#define F0900_P1_CFRINIT_ABORTDBL  0xf4410020
-#define F0900_P1_CFRINIT_ABORTPRED  0xf4410010
-#define F0900_P1_CFRINIT_UNVALSKIP  0xf4410008
-#define F0900_P1_CFRINIT_CSTINC  0xf4410004
-#define F0900_P1_NEG_CFRSTEP  0xf4410001
+#define R0900_P1_CFRICFG 0xf441
+#define CFRICFG REGx(R0900_P1_CFRICFG)
+#define F0900_P1_NEG_CFRSTEP 0xf4410001
 
 /*P1_CFRUP1*/
-#define R0900_P1_CFRUP1  0xf442
-#define F0900_P1_CFR_UP1  0xf44201ff
+#define R0900_P1_CFRUP1 0xf442
+#define CFRUP1 REGx(R0900_P1_CFRUP1)
+#define F0900_P1_CFR_UP1 0xf44201ff
+#define CFR_UP1 FLDx(F0900_P1_CFR_UP1)
 
 /*P1_CFRUP0*/
-#define R0900_P1_CFRUP0  0xf443
-#define F0900_P1_CFR_UP0  0xf44300ff
+#define R0900_P1_CFRUP0 0xf443
+#define CFRUP0 REGx(R0900_P1_CFRUP0)
+#define F0900_P1_CFR_UP0 0xf44300ff
+#define CFR_UP0 FLDx(F0900_P1_CFR_UP0)
 
 /*P1_CFRLOW1*/
-#define R0900_P1_CFRLOW1  0xf446
-#define F0900_P1_CFR_LOW1  0xf44601ff
+#define R0900_P1_CFRLOW1 0xf446
+#define CFRLOW1 REGx(R0900_P1_CFRLOW1)
+#define F0900_P1_CFR_LOW1 0xf44601ff
+#define CFR_LOW1 FLDx(F0900_P1_CFR_LOW1)
 
 /*P1_CFRLOW0*/
-#define R0900_P1_CFRLOW0  0xf447
-#define F0900_P1_CFR_LOW0  0xf44700ff
+#define R0900_P1_CFRLOW0 0xf447
+#define CFRLOW0 REGx(R0900_P1_CFRLOW0)
+#define F0900_P1_CFR_LOW0 0xf44700ff
+#define CFR_LOW0 FLDx(F0900_P1_CFR_LOW0)
 
 /*P1_CFRINIT1*/
-#define R0900_P1_CFRINIT1  0xf448
-#define F0900_P1_CFR_INIT1  0xf44801ff
+#define R0900_P1_CFRINIT1 0xf448
+#define CFRINIT1 REGx(R0900_P1_CFRINIT1)
+#define F0900_P1_CFR_INIT1 0xf44801ff
+#define CFR_INIT1 FLDx(F0900_P1_CFR_INIT1)
 
 /*P1_CFRINIT0*/
-#define R0900_P1_CFRINIT0  0xf449
-#define F0900_P1_CFR_INIT0  0xf44900ff
+#define R0900_P1_CFRINIT0 0xf449
+#define CFRINIT0 REGx(R0900_P1_CFRINIT0)
+#define F0900_P1_CFR_INIT0 0xf44900ff
+#define CFR_INIT0 FLDx(F0900_P1_CFR_INIT0)
 
 /*P1_CFRINC1*/
-#define R0900_P1_CFRINC1  0xf44a
-#define F0900_P1_MANUAL_CFRINC  0xf44a0080
-#define F0900_P1_CFR_INC1  0xf44a017f
+#define R0900_P1_CFRINC1 0xf44a
+#define CFRINC1 REGx(R0900_P1_CFRINC1)
+#define F0900_P1_MANUAL_CFRINC 0xf44a0080
+#define F0900_P1_CFR_INC1 0xf44a003f
 
 /*P1_CFRINC0*/
-#define R0900_P1_CFRINC0  0xf44b
-#define F0900_P1_CFR_INC0  0xf44b00f0
+#define R0900_P1_CFRINC0 0xf44b
+#define CFRINC0 REGx(R0900_P1_CFRINC0)
+#define F0900_P1_CFR_INC0 0xf44b00f8
 
 /*P1_CFR2*/
-#define R0900_P1_CFR2  0xf44c
-#define F0900_P1_CAR_FREQ2  0xf44c01ff
+#define R0900_P1_CFR2 0xf44c
+#define CFR2 REGx(R0900_P1_CFR2)
+#define F0900_P1_CAR_FREQ2 0xf44c01ff
+#define CAR_FREQ2 FLDx(F0900_P1_CAR_FREQ2)
 
 /*P1_CFR1*/
-#define R0900_P1_CFR1  0xf44d
-#define F0900_P1_CAR_FREQ1  0xf44d00ff
+#define R0900_P1_CFR1 0xf44d
+#define CFR1 REGx(R0900_P1_CFR1)
+#define F0900_P1_CAR_FREQ1 0xf44d00ff
+#define CAR_FREQ1 FLDx(F0900_P1_CAR_FREQ1)
 
 /*P1_CFR0*/
-#define R0900_P1_CFR0  0xf44e
-#define F0900_P1_CAR_FREQ0  0xf44e00ff
+#define R0900_P1_CFR0 0xf44e
+#define CFR0 REGx(R0900_P1_CFR0)
+#define F0900_P1_CAR_FREQ0 0xf44e00ff
+#define CAR_FREQ0 FLDx(F0900_P1_CAR_FREQ0)
 
 /*P1_LDI*/
-#define R0900_P1_LDI  0xf44f
-#define F0900_P1_LOCK_DET_INTEGR  0xf44f01ff
+#define R0900_P1_LDI 0xf44f
+#define LDI REGx(R0900_P1_LDI)
+#define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff
 
 /*P1_TMGCFG*/
-#define R0900_P1_TMGCFG  0xf450
-#define F0900_P1_TMGLOCK_BETA  0xf45000c0
-#define F0900_P1_NOTMG_GROUPDELAY  0xf4500020
-#define F0900_P1_DO_TIMING_CORR  0xf4500010
-#define F0900_P1_MANUAL_SCAN  0xf450000c
-#define F0900_P1_TMG_MINFREQ  0xf4500003
+#define R0900_P1_TMGCFG 0xf450
+#define TMGCFG REGx(R0900_P1_TMGCFG)
+#define F0900_P1_TMGLOCK_BETA 0xf45000c0
+#define F0900_P1_DO_TIMING_CORR 0xf4500010
+#define F0900_P1_TMG_MINFREQ 0xf4500003
 
 /*P1_RTC*/
-#define R0900_P1_RTC  0xf451
-#define F0900_P1_TMGALPHA_EXP  0xf45100f0
-#define F0900_P1_TMGBETA_EXP  0xf451000f
+#define R0900_P1_RTC 0xf451
+#define RTC REGx(R0900_P1_RTC)
+#define F0900_P1_TMGALPHA_EXP 0xf45100f0
+#define F0900_P1_TMGBETA_EXP 0xf451000f
 
 /*P1_RTCS2*/
-#define R0900_P1_RTCS2  0xf452
-#define F0900_P1_TMGALPHAS2_EXP  0xf45200f0
-#define F0900_P1_TMGBETAS2_EXP  0xf452000f
+#define R0900_P1_RTCS2 0xf452
+#define RTCS2 REGx(R0900_P1_RTCS2)
+#define F0900_P1_TMGALPHAS2_EXP 0xf45200f0
+#define F0900_P1_TMGBETAS2_EXP 0xf452000f
 
 /*P1_TMGTHRISE*/
-#define R0900_P1_TMGTHRISE  0xf453
-#define F0900_P1_TMGLOCK_THRISE  0xf45300ff
+#define R0900_P1_TMGTHRISE 0xf453
+#define TMGTHRISE REGx(R0900_P1_TMGTHRISE)
+#define F0900_P1_TMGLOCK_THRISE 0xf45300ff
 
 /*P1_TMGTHFALL*/
-#define R0900_P1_TMGTHFALL  0xf454
-#define F0900_P1_TMGLOCK_THFALL  0xf45400ff
+#define R0900_P1_TMGTHFALL 0xf454
+#define TMGTHFALL REGx(R0900_P1_TMGTHFALL)
+#define F0900_P1_TMGLOCK_THFALL 0xf45400ff
 
 /*P1_SFRUPRATIO*/
-#define R0900_P1_SFRUPRATIO  0xf455
-#define F0900_P1_SFR_UPRATIO  0xf45500ff
+#define R0900_P1_SFRUPRATIO 0xf455
+#define SFRUPRATIO REGx(R0900_P1_SFRUPRATIO)
+#define F0900_P1_SFR_UPRATIO 0xf45500ff
 
 /*P1_SFRLOWRATIO*/
-#define R0900_P1_SFRLOWRATIO  0xf456
-#define F0900_P1_SFR_LOWRATIO  0xf45600ff
+#define R0900_P1_SFRLOWRATIO 0xf456
+#define F0900_P1_SFR_LOWRATIO 0xf45600ff
 
 /*P1_KREFTMG*/
-#define R0900_P1_KREFTMG  0xf458
-#define F0900_P1_KREF_TMG  0xf45800ff
+#define R0900_P1_KREFTMG 0xf458
+#define KREFTMG REGx(R0900_P1_KREFTMG)
+#define F0900_P1_KREF_TMG 0xf45800ff
 
 /*P1_SFRSTEP*/
-#define R0900_P1_SFRSTEP  0xf459
-#define F0900_P1_SFR_SCANSTEP  0xf45900f0
-#define F0900_P1_SFR_CENTERSTEP  0xf459000f
+#define R0900_P1_SFRSTEP 0xf459
+#define SFRSTEP REGx(R0900_P1_SFRSTEP)
+#define F0900_P1_SFR_SCANSTEP 0xf45900f0
+#define F0900_P1_SFR_CENTERSTEP 0xf459000f
 
 /*P1_TMGCFG2*/
-#define R0900_P1_TMGCFG2  0xf45a
-#define F0900_P1_DIS_AUTOSAMP  0xf45a0008
-#define F0900_P1_SCANINIT_QUART  0xf45a0004
-#define F0900_P1_NOTMG_DVBS1DERAT  0xf45a0002
-#define F0900_P1_SFRRATIO_FINE  0xf45a0001
+#define R0900_P1_TMGCFG2 0xf45a
+#define TMGCFG2 REGx(R0900_P1_TMGCFG2)
+#define F0900_P1_SFRRATIO_FINE 0xf45a0001
+
+/*P1_KREFTMG2*/
+#define R0900_P1_KREFTMG2 0xf45b
+#define KREFTMG2 REGx(R0900_P1_KREFTMG2)
+#define F0900_P1_KREF_TMG2 0xf45b00ff
 
 /*P1_SFRINIT1*/
-#define R0900_P1_SFRINIT1  0xf45e
-#define F0900_P1_SFR_INIT1  0xf45e00ff
+#define R0900_P1_SFRINIT1 0xf45e
+#define SFRINIT1 REGx(R0900_P1_SFRINIT1)
+#define F0900_P1_SFR_INIT1 0xf45e007f
 
 /*P1_SFRINIT0*/
-#define R0900_P1_SFRINIT0  0xf45f
-#define F0900_P1_SFR_INIT0  0xf45f00ff
+#define R0900_P1_SFRINIT0 0xf45f
+#define SFRINIT0 REGx(R0900_P1_SFRINIT0)
+#define F0900_P1_SFR_INIT0 0xf45f00ff
 
 /*P1_SFRUP1*/
-#define R0900_P1_SFRUP1  0xf460
-#define F0900_P1_AUTO_GUP  0xf4600080
-#define F0900_P1_SYMB_FREQ_UP1  0xf460007f
+#define R0900_P1_SFRUP1 0xf460
+#define SFRUP1 REGx(R0900_P1_SFRUP1)
+#define F0900_P1_AUTO_GUP 0xf4600080
+#define AUTO_GUP FLDx(F0900_P1_AUTO_GUP)
+#define F0900_P1_SYMB_FREQ_UP1 0xf460007f
 
 /*P1_SFRUP0*/
-#define R0900_P1_SFRUP0  0xf461
-#define F0900_P1_SYMB_FREQ_UP0  0xf46100ff
+#define R0900_P1_SFRUP0 0xf461
+#define SFRUP0 REGx(R0900_P1_SFRUP0)
+#define F0900_P1_SYMB_FREQ_UP0 0xf46100ff
 
 /*P1_SFRLOW1*/
-#define R0900_P1_SFRLOW1  0xf462
-#define F0900_P1_AUTO_GLOW  0xf4620080
-#define F0900_P1_SYMB_FREQ_LOW1  0xf462007f
+#define R0900_P1_SFRLOW1 0xf462
+#define SFRLOW1 REGx(R0900_P1_SFRLOW1)
+#define F0900_P1_AUTO_GLOW 0xf4620080
+#define AUTO_GLOW FLDx(F0900_P1_AUTO_GLOW)
+#define F0900_P1_SYMB_FREQ_LOW1 0xf462007f
 
 /*P1_SFRLOW0*/
-#define R0900_P1_SFRLOW0  0xf463
-#define F0900_P1_SYMB_FREQ_LOW0  0xf46300ff
+#define R0900_P1_SFRLOW0 0xf463
+#define SFRLOW0 REGx(R0900_P1_SFRLOW0)
+#define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff
 
 /*P1_SFR3*/
-#define R0900_P1_SFR3  0xf464
-#define F0900_P1_SYMB_FREQ3  0xf46400ff
+#define R0900_P1_SFR3 0xf464
+#define SFR3 REGx(R0900_P1_SFR3)
+#define F0900_P1_SYMB_FREQ3 0xf46400ff
+#define SYMB_FREQ3 FLDx(F0900_P1_SYMB_FREQ3)
 
 /*P1_SFR2*/
-#define R0900_P1_SFR2  0xf465
-#define F0900_P1_SYMB_FREQ2  0xf46500ff
+#define R0900_P1_SFR2 0xf465
+#define SFR2 REGx(R0900_P1_SFR2)
+#define F0900_P1_SYMB_FREQ2 0xf46500ff
+#define SYMB_FREQ2 FLDx(F0900_P1_SYMB_FREQ2)
 
 /*P1_SFR1*/
-#define R0900_P1_SFR1  0xf466
-#define F0900_P1_SYMB_FREQ1  0xf46600ff
+#define R0900_P1_SFR1 0xf466
+#define SFR1 REGx(R0900_P1_SFR1)
+#define F0900_P1_SYMB_FREQ1 0xf46600ff
+#define SYMB_FREQ1 FLDx(F0900_P1_SYMB_FREQ1)
 
 /*P1_SFR0*/
-#define R0900_P1_SFR0  0xf467
-#define F0900_P1_SYMB_FREQ0  0xf46700ff
+#define R0900_P1_SFR0 0xf467
+#define SFR0 REGx(R0900_P1_SFR0)
+#define F0900_P1_SYMB_FREQ0 0xf46700ff
+#define SYMB_FREQ0 FLDx(F0900_P1_SYMB_FREQ0)
 
 /*P1_TMGREG2*/
-#define R0900_P1_TMGREG2  0xf468
-#define F0900_P1_TMGREG2  0xf46800ff
+#define R0900_P1_TMGREG2 0xf468
+#define TMGREG2 REGx(R0900_P1_TMGREG2)
+#define F0900_P1_TMGREG2 0xf46800ff
 
 /*P1_TMGREG1*/
-#define R0900_P1_TMGREG1  0xf469
-#define F0900_P1_TMGREG1  0xf46900ff
+#define R0900_P1_TMGREG1 0xf469
+#define TMGREG1 REGx(R0900_P1_TMGREG1)
+#define F0900_P1_TMGREG1 0xf46900ff
 
 /*P1_TMGREG0*/
-#define R0900_P1_TMGREG0  0xf46a
-#define F0900_P1_TMGREG0  0xf46a00ff
+#define R0900_P1_TMGREG0 0xf46a
+#define TMGREG0 REGx(R0900_P1_TMGREG0)
+#define F0900_P1_TMGREG0 0xf46a00ff
 
 /*P1_TMGLOCK1*/
-#define R0900_P1_TMGLOCK1  0xf46b
-#define F0900_P1_TMGLOCK_LEVEL1  0xf46b01ff
+#define R0900_P1_TMGLOCK1 0xf46b
+#define TMGLOCK1 REGx(R0900_P1_TMGLOCK1)
+#define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff
 
 /*P1_TMGLOCK0*/
-#define R0900_P1_TMGLOCK0  0xf46c
-#define F0900_P1_TMGLOCK_LEVEL0  0xf46c00ff
+#define R0900_P1_TMGLOCK0 0xf46c
+#define TMGLOCK0 REGx(R0900_P1_TMGLOCK0)
+#define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff
 
 /*P1_TMGOBS*/
-#define R0900_P1_TMGOBS  0xf46d
-#define F0900_P1_ROLLOFF_STATUS  0xf46d00c0
-#define F0900_P1_SCAN_SIGN  0xf46d0030
-#define F0900_P1_TMG_SCANNING  0xf46d0008
-#define F0900_P1_CHCENTERING_MODE  0xf46d0004
-#define F0900_P1_TMG_SCANFAIL  0xf46d0002
+#define R0900_P1_TMGOBS 0xf46d
+#define TMGOBS REGx(R0900_P1_TMGOBS)
+#define F0900_P1_ROLLOFF_STATUS 0xf46d00c0
+#define ROLLOFF_STATUS FLDx(F0900_P1_ROLLOFF_STATUS)
 
 /*P1_EQUALCFG*/
-#define R0900_P1_EQUALCFG  0xf46f
-#define F0900_P1_NOTMG_NEGALWAIT  0xf46f0080
-#define F0900_P1_EQUAL_ON  0xf46f0040
-#define F0900_P1_SEL_EQUALCOR  0xf46f0038
-#define F0900_P1_MU_EQUALDFE  0xf46f0007
+#define R0900_P1_EQUALCFG 0xf46f
+#define EQUALCFG REGx(R0900_P1_EQUALCFG)
+#define F0900_P1_EQUAL_ON 0xf46f0040
+#define F0900_P1_MU_EQUALDFE 0xf46f0007
 
 /*P1_EQUAI1*/
-#define R0900_P1_EQUAI1  0xf470
-#define F0900_P1_EQUA_ACCI1  0xf47001ff
+#define R0900_P1_EQUAI1 0xf470
+#define EQUAI1 REGx(R0900_P1_EQUAI1)
+#define F0900_P1_EQUA_ACCI1 0xf47001ff
 
 /*P1_EQUAQ1*/
-#define R0900_P1_EQUAQ1  0xf471
-#define F0900_P1_EQUA_ACCQ1  0xf47101ff
+#define R0900_P1_EQUAQ1 0xf471
+#define EQUAQ1 REGx(R0900_P1_EQUAQ1)
+#define F0900_P1_EQUA_ACCQ1 0xf47101ff
 
 /*P1_EQUAI2*/
-#define R0900_P1_EQUAI2  0xf472
-#define F0900_P1_EQUA_ACCI2  0xf47201ff
+#define R0900_P1_EQUAI2 0xf472
+#define EQUAI2 REGx(R0900_P1_EQUAI2)
+#define F0900_P1_EQUA_ACCI2 0xf47201ff
 
 /*P1_EQUAQ2*/
-#define R0900_P1_EQUAQ2  0xf473
-#define F0900_P1_EQUA_ACCQ2  0xf47301ff
+#define R0900_P1_EQUAQ2 0xf473
+#define EQUAQ2 REGx(R0900_P1_EQUAQ2)
+#define F0900_P1_EQUA_ACCQ2 0xf47301ff
 
 /*P1_EQUAI3*/
-#define R0900_P1_EQUAI3  0xf474
-#define F0900_P1_EQUA_ACCI3  0xf47401ff
+#define R0900_P1_EQUAI3 0xf474
+#define EQUAI3 REGx(R0900_P1_EQUAI3)
+#define F0900_P1_EQUA_ACCI3 0xf47401ff
 
 /*P1_EQUAQ3*/
-#define R0900_P1_EQUAQ3  0xf475
-#define F0900_P1_EQUA_ACCQ3  0xf47501ff
+#define R0900_P1_EQUAQ3 0xf475
+#define EQUAQ3 REGx(R0900_P1_EQUAQ3)
+#define F0900_P1_EQUA_ACCQ3 0xf47501ff
 
 /*P1_EQUAI4*/
-#define R0900_P1_EQUAI4  0xf476
-#define F0900_P1_EQUA_ACCI4  0xf47601ff
+#define R0900_P1_EQUAI4 0xf476
+#define EQUAI4 REGx(R0900_P1_EQUAI4)
+#define F0900_P1_EQUA_ACCI4 0xf47601ff
 
 /*P1_EQUAQ4*/
-#define R0900_P1_EQUAQ4  0xf477
-#define F0900_P1_EQUA_ACCQ4  0xf47701ff
+#define R0900_P1_EQUAQ4 0xf477
+#define EQUAQ4 REGx(R0900_P1_EQUAQ4)
+#define F0900_P1_EQUA_ACCQ4 0xf47701ff
 
 /*P1_EQUAI5*/
-#define R0900_P1_EQUAI5  0xf478
-#define F0900_P1_EQUA_ACCI5  0xf47801ff
+#define R0900_P1_EQUAI5 0xf478
+#define EQUAI5 REGx(R0900_P1_EQUAI5)
+#define F0900_P1_EQUA_ACCI5 0xf47801ff
 
 /*P1_EQUAQ5*/
-#define R0900_P1_EQUAQ5  0xf479
-#define F0900_P1_EQUA_ACCQ5  0xf47901ff
+#define R0900_P1_EQUAQ5 0xf479
+#define EQUAQ5 REGx(R0900_P1_EQUAQ5)
+#define F0900_P1_EQUA_ACCQ5 0xf47901ff
 
 /*P1_EQUAI6*/
-#define R0900_P1_EQUAI6  0xf47a
-#define F0900_P1_EQUA_ACCI6  0xf47a01ff
+#define R0900_P1_EQUAI6 0xf47a
+#define EQUAI6 REGx(R0900_P1_EQUAI6)
+#define F0900_P1_EQUA_ACCI6 0xf47a01ff
 
 /*P1_EQUAQ6*/
-#define R0900_P1_EQUAQ6  0xf47b
-#define F0900_P1_EQUA_ACCQ6  0xf47b01ff
+#define R0900_P1_EQUAQ6 0xf47b
+#define EQUAQ6 REGx(R0900_P1_EQUAQ6)
+#define F0900_P1_EQUA_ACCQ6 0xf47b01ff
 
 /*P1_EQUAI7*/
-#define R0900_P1_EQUAI7  0xf47c
-#define F0900_P1_EQUA_ACCI7  0xf47c01ff
+#define R0900_P1_EQUAI7 0xf47c
+#define EQUAI7 REGx(R0900_P1_EQUAI7)
+#define F0900_P1_EQUA_ACCI7 0xf47c01ff
 
 /*P1_EQUAQ7*/
-#define R0900_P1_EQUAQ7  0xf47d
-#define F0900_P1_EQUA_ACCQ7  0xf47d01ff
+#define R0900_P1_EQUAQ7 0xf47d
+#define EQUAQ7 REGx(R0900_P1_EQUAQ7)
+#define F0900_P1_EQUA_ACCQ7 0xf47d01ff
 
 /*P1_EQUAI8*/
-#define R0900_P1_EQUAI8  0xf47e
-#define F0900_P1_EQUA_ACCI8  0xf47e01ff
+#define R0900_P1_EQUAI8 0xf47e
+#define EQUAI8 REGx(R0900_P1_EQUAI8)
+#define F0900_P1_EQUA_ACCI8 0xf47e01ff
 
 /*P1_EQUAQ8*/
-#define R0900_P1_EQUAQ8  0xf47f
-#define F0900_P1_EQUA_ACCQ8  0xf47f01ff
+#define R0900_P1_EQUAQ8 0xf47f
+#define EQUAQ8 REGx(R0900_P1_EQUAQ8)
+#define F0900_P1_EQUA_ACCQ8 0xf47f01ff
 
 /*P1_NNOSDATAT1*/
-#define R0900_P1_NNOSDATAT1  0xf480
-#define F0900_P1_NOSDATAT_NORMED1  0xf48000ff
+#define R0900_P1_NNOSDATAT1 0xf480
+#define NNOSDATAT1 REGx(R0900_P1_NNOSDATAT1)
+#define F0900_P1_NOSDATAT_NORMED1 0xf48000ff
+#define NOSDATAT_NORMED1 FLDx(F0900_P1_NOSDATAT_NORMED1)
 
 /*P1_NNOSDATAT0*/
-#define R0900_P1_NNOSDATAT0  0xf481
-#define F0900_P1_NOSDATAT_NORMED0  0xf48100ff
+#define R0900_P1_NNOSDATAT0 0xf481
+#define NNOSDATAT0 REGx(R0900_P1_NNOSDATAT0)
+#define F0900_P1_NOSDATAT_NORMED0 0xf48100ff
+#define NOSDATAT_NORMED0 FLDx(F0900_P1_NOSDATAT_NORMED0)
 
 /*P1_NNOSDATA1*/
-#define R0900_P1_NNOSDATA1  0xf482
-#define F0900_P1_NOSDATA_NORMED1  0xf48200ff
+#define R0900_P1_NNOSDATA1 0xf482
+#define NNOSDATA1 REGx(R0900_P1_NNOSDATA1)
+#define F0900_P1_NOSDATA_NORMED1 0xf48200ff
 
 /*P1_NNOSDATA0*/
-#define R0900_P1_NNOSDATA0  0xf483
-#define F0900_P1_NOSDATA_NORMED0  0xf48300ff
+#define R0900_P1_NNOSDATA0 0xf483
+#define NNOSDATA0 REGx(R0900_P1_NNOSDATA0)
+#define F0900_P1_NOSDATA_NORMED0 0xf48300ff
 
 /*P1_NNOSPLHT1*/
-#define R0900_P1_NNOSPLHT1  0xf484
-#define F0900_P1_NOSPLHT_NORMED1  0xf48400ff
+#define R0900_P1_NNOSPLHT1 0xf484
+#define NNOSPLHT1 REGx(R0900_P1_NNOSPLHT1)
+#define F0900_P1_NOSPLHT_NORMED1 0xf48400ff
+#define NOSPLHT_NORMED1 FLDx(F0900_P1_NOSPLHT_NORMED1)
 
 /*P1_NNOSPLHT0*/
-#define R0900_P1_NNOSPLHT0  0xf485
-#define F0900_P1_NOSPLHT_NORMED0  0xf48500ff
+#define R0900_P1_NNOSPLHT0 0xf485
+#define NNOSPLHT0 REGx(R0900_P1_NNOSPLHT0)
+#define F0900_P1_NOSPLHT_NORMED0 0xf48500ff
+#define NOSPLHT_NORMED0 FLDx(F0900_P1_NOSPLHT_NORMED0)
 
 /*P1_NNOSPLH1*/
-#define R0900_P1_NNOSPLH1  0xf486
-#define F0900_P1_NOSPLH_NORMED1  0xf48600ff
+#define R0900_P1_NNOSPLH1 0xf486
+#define NNOSPLH1 REGx(R0900_P1_NNOSPLH1)
+#define F0900_P1_NOSPLH_NORMED1 0xf48600ff
 
 /*P1_NNOSPLH0*/
-#define R0900_P1_NNOSPLH0  0xf487
-#define F0900_P1_NOSPLH_NORMED0  0xf48700ff
+#define R0900_P1_NNOSPLH0 0xf487
+#define NNOSPLH0 REGx(R0900_P1_NNOSPLH0)
+#define F0900_P1_NOSPLH_NORMED0 0xf48700ff
 
 /*P1_NOSDATAT1*/
-#define R0900_P1_NOSDATAT1  0xf488
-#define F0900_P1_NOSDATAT_UNNORMED1  0xf48800ff
+#define R0900_P1_NOSDATAT1 0xf488
+#define NOSDATAT1 REGx(R0900_P1_NOSDATAT1)
+#define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff
 
 /*P1_NOSDATAT0*/
-#define R0900_P1_NOSDATAT0  0xf489
-#define F0900_P1_NOSDATAT_UNNORMED0  0xf48900ff
+#define R0900_P1_NOSDATAT0 0xf489
+#define NOSDATAT0 REGx(R0900_P1_NOSDATAT0)
+#define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff
 
 /*P1_NOSDATA1*/
-#define R0900_P1_NOSDATA1  0xf48a
-#define F0900_P1_NOSDATA_UNNORMED1  0xf48a00ff
+#define R0900_P1_NOSDATA1 0xf48a
+#define NOSDATA1 REGx(R0900_P1_NOSDATA1)
+#define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff
 
 /*P1_NOSDATA0*/
-#define R0900_P1_NOSDATA0  0xf48b
-#define F0900_P1_NOSDATA_UNNORMED0  0xf48b00ff
+#define R0900_P1_NOSDATA0 0xf48b
+#define NOSDATA0 REGx(R0900_P1_NOSDATA0)
+#define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff
 
 /*P1_NOSPLHT1*/
-#define R0900_P1_NOSPLHT1  0xf48c
-#define F0900_P1_NOSPLHT_UNNORMED1  0xf48c00ff
+#define R0900_P1_NOSPLHT1 0xf48c
+#define NOSPLHT1 REGx(R0900_P1_NOSPLHT1)
+#define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff
 
 /*P1_NOSPLHT0*/
-#define R0900_P1_NOSPLHT0  0xf48d
-#define F0900_P1_NOSPLHT_UNNORMED0  0xf48d00ff
+#define R0900_P1_NOSPLHT0 0xf48d
+#define NOSPLHT0 REGx(R0900_P1_NOSPLHT0)
+#define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff
 
 /*P1_NOSPLH1*/
-#define R0900_P1_NOSPLH1  0xf48e
-#define F0900_P1_NOSPLH_UNNORMED1  0xf48e00ff
+#define R0900_P1_NOSPLH1 0xf48e
+#define NOSPLH1 REGx(R0900_P1_NOSPLH1)
+#define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff
 
 /*P1_NOSPLH0*/
-#define R0900_P1_NOSPLH0  0xf48f
-#define F0900_P1_NOSPLH_UNNORMED0  0xf48f00ff
+#define R0900_P1_NOSPLH0 0xf48f
+#define NOSPLH0 REGx(R0900_P1_NOSPLH0)
+#define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff
 
 /*P1_CAR2CFG*/
-#define R0900_P1_CAR2CFG  0xf490
-#define F0900_P1_DESCRAMB_OFF  0xf4900080
-#define F0900_P1_PN4_SELECT  0xf4900040
-#define F0900_P1_CFR2_STOPDVBS1  0xf4900020
-#define F0900_P1_STOP_CFR2UPDATE  0xf4900010
-#define F0900_P1_STOP_NCO2UPDATE  0xf4900008
-#define F0900_P1_ROTA2ON  0xf4900004
-#define F0900_P1_PH_DET_ALGO2  0xf4900003
-
-/*P1_ACLC2*/
-#define R0900_P1_ACLC2  0xf491
-#define F0900_P1_CAR2_PUNCT_ADERAT  0xf4910040
-#define F0900_P1_CAR2_ALPHA_MANT  0xf4910030
-#define F0900_P1_CAR2_ALPHA_EXP  0xf491000f
-
-/*P1_BCLC2*/
-#define R0900_P1_BCLC2  0xf492
-#define F0900_P1_DVBS2_NIP  0xf4920080
-#define F0900_P1_CAR2_PUNCT_BDERAT  0xf4920040
-#define F0900_P1_CAR2_BETA_MANT  0xf4920030
-#define F0900_P1_CAR2_BETA_EXP  0xf492000f
+#define R0900_P1_CAR2CFG 0xf490
+#define CAR2CFG REGx(R0900_P1_CAR2CFG)
+#define F0900_P1_CARRIER3_DISABLE 0xf4900040
+#define F0900_P1_ROTA2ON 0xf4900004
+#define F0900_P1_PH_DET_ALGO2 0xf4900003
+
+/*P1_CFR2CFR1*/
+#define R0900_P1_CFR2CFR1 0xf491
+#define CFR2CFR1 REGx(R0900_P1_CFR2CFR1)
+#define F0900_P1_CFR2TOCFR1_DVBS1 0xf49100c0
+#define F0900_P1_EN_S2CAR2CENTER 0xf4910020
+#define F0900_P1_DIS_BCHERRCFR2 0xf4910010
+#define F0900_P1_CFR2TOCFR1_BETA 0xf4910007
 
 /*P1_CFR22*/
-#define R0900_P1_CFR22  0xf493
-#define F0900_P1_CAR2_FREQ2  0xf49301ff
+#define R0900_P1_CFR22 0xf493
+#define CFR22 REGx(R0900_P1_CFR22)
+#define F0900_P1_CAR2_FREQ2 0xf49301ff
 
 /*P1_CFR21*/
-#define R0900_P1_CFR21  0xf494
-#define F0900_P1_CAR2_FREQ1  0xf49400ff
+#define R0900_P1_CFR21 0xf494
+#define CFR21 REGx(R0900_P1_CFR21)
+#define F0900_P1_CAR2_FREQ1 0xf49400ff
 
 /*P1_CFR20*/
-#define R0900_P1_CFR20  0xf495
-#define F0900_P1_CAR2_FREQ0  0xf49500ff
+#define R0900_P1_CFR20 0xf495
+#define CFR20 REGx(R0900_P1_CFR20)
+#define F0900_P1_CAR2_FREQ0 0xf49500ff
 
 /*P1_ACLC2S2Q*/
-#define R0900_P1_ACLC2S2Q  0xf497
-#define F0900_P1_ENAB_SPSKSYMB  0xf4970080
-#define F0900_P1_CAR2S2_QADERAT  0xf4970040
-#define F0900_P1_CAR2S2_Q_ALPH_M  0xf4970030
-#define F0900_P1_CAR2S2_Q_ALPH_E  0xf497000f
+#define R0900_P1_ACLC2S2Q 0xf497
+#define ACLC2S2Q REGx(R0900_P1_ACLC2S2Q)
+#define F0900_P1_ENAB_SPSKSYMB 0xf4970080
+#define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030
+#define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f
 
 /*P1_ACLC2S28*/
-#define R0900_P1_ACLC2S28  0xf498
-#define F0900_P1_OLDI3Q_MODE  0xf4980080
-#define F0900_P1_CAR2S2_8ADERAT  0xf4980040
-#define F0900_P1_CAR2S2_8_ALPH_M  0xf4980030
-#define F0900_P1_CAR2S2_8_ALPH_E  0xf498000f
+#define R0900_P1_ACLC2S28 0xf498
+#define ACLC2S28 REGx(R0900_P1_ACLC2S28)
+#define F0900_P1_OLDI3Q_MODE 0xf4980080
+#define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030
+#define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f
 
 /*P1_ACLC2S216A*/
-#define R0900_P1_ACLC2S216A  0xf499
-#define F0900_P1_CAR2S2_16ADERAT  0xf4990040
-#define F0900_P1_CAR2S2_16A_ALPH_M  0xf4990030
-#define F0900_P1_CAR2S2_16A_ALPH_E  0xf499000f
+#define R0900_P1_ACLC2S216A 0xf499
+#define ACLC2S216A REGx(R0900_P1_ACLC2S216A)
+#define F0900_P1_DIS_C3STOPA2 0xf4990080
+#define F0900_P1_CAR2S2_16ADERAT 0xf4990040
+#define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030
+#define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f
 
 /*P1_ACLC2S232A*/
-#define R0900_P1_ACLC2S232A  0xf49a
-#define F0900_P1_CAR2S2_32ADERAT  0xf49a0040
-#define F0900_P1_CAR2S2_32A_ALPH_M  0xf49a0030
-#define F0900_P1_CAR2S2_32A_ALPH_E  0xf49a000f
+#define R0900_P1_ACLC2S232A 0xf49a
+#define ACLC2S232A REGx(R0900_P1_ACLC2S232A)
+#define F0900_P1_CAR2S2_32ADERAT 0xf49a0040
+#define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030
+#define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f
 
 /*P1_BCLC2S2Q*/
-#define R0900_P1_BCLC2S2Q  0xf49c
-#define F0900_P1_DVBS2S2Q_NIP  0xf49c0080
-#define F0900_P1_CAR2S2_QBDERAT  0xf49c0040
-#define F0900_P1_CAR2S2_Q_BETA_M  0xf49c0030
-#define F0900_P1_CAR2S2_Q_BETA_E  0xf49c000f
+#define R0900_P1_BCLC2S2Q 0xf49c
+#define BCLC2S2Q REGx(R0900_P1_BCLC2S2Q)
+#define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030
+#define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f
 
 /*P1_BCLC2S28*/
-#define R0900_P1_BCLC2S28  0xf49d
-#define F0900_P1_DVBS2S28_NIP  0xf49d0080
-#define F0900_P1_CAR2S2_8BDERAT  0xf49d0040
-#define F0900_P1_CAR2S2_8_BETA_M  0xf49d0030
-#define F0900_P1_CAR2S2_8_BETA_E  0xf49d000f
+#define R0900_P1_BCLC2S28 0xf49d
+#define BCLC2S28 REGx(R0900_P1_BCLC2S28)
+#define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030
+#define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f
 
 /*P1_BCLC2S216A*/
-#define R0900_P1_BCLC2S216A  0xf49e
-#define F0900_P1_DVBS2S216A_NIP  0xf49e0080
-#define F0900_P1_CAR2S2_16BDERAT  0xf49e0040
-#define F0900_P1_CAR2S2_16A_BETA_M  0xf49e0030
-#define F0900_P1_CAR2S2_16A_BETA_E  0xf49e000f
+#define R0900_P1_BCLC2S216A 0xf49e
+#define BCLC2S216A REGx(R0900_P1_BCLC2S216A)
 
 /*P1_BCLC2S232A*/
-#define R0900_P1_BCLC2S232A  0xf49f
-#define F0900_P1_DVBS2S232A_NIP  0xf49f0080
-#define F0900_P1_CAR2S2_32BDERAT  0xf49f0040
-#define F0900_P1_CAR2S2_32A_BETA_M  0xf49f0030
-#define F0900_P1_CAR2S2_32A_BETA_E  0xf49f000f
+#define R0900_P1_BCLC2S232A 0xf49f
+#define BCLC2S232A REGx(R0900_P1_BCLC2S232A)
 
 /*P1_PLROOT2*/
-#define R0900_P1_PLROOT2  0xf4ac
-#define F0900_P1_SHORTFR_DISABLE  0xf4ac0080
-#define F0900_P1_LONGFR_DISABLE  0xf4ac0040
-#define F0900_P1_DUMMYPL_DISABLE  0xf4ac0020
-#define F0900_P1_SHORTFR_AVOID  0xf4ac0010
-#define F0900_P1_PLSCRAMB_MODE  0xf4ac000c
-#define F0900_P1_PLSCRAMB_ROOT2  0xf4ac0003
+#define R0900_P1_PLROOT2 0xf4ac
+#define PLROOT2 REGx(R0900_P1_PLROOT2)
+#define F0900_P1_PLSCRAMB_MODE 0xf4ac000c
+#define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003
 
 /*P1_PLROOT1*/
-#define R0900_P1_PLROOT1  0xf4ad
-#define F0900_P1_PLSCRAMB_ROOT1  0xf4ad00ff
+#define R0900_P1_PLROOT1 0xf4ad
+#define PLROOT1 REGx(R0900_P1_PLROOT1)
+#define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff
 
 /*P1_PLROOT0*/
-#define R0900_P1_PLROOT0  0xf4ae
-#define F0900_P1_PLSCRAMB_ROOT0  0xf4ae00ff
+#define R0900_P1_PLROOT0 0xf4ae
+#define PLROOT0 REGx(R0900_P1_PLROOT0)
+#define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff
 
 /*P1_MODCODLST0*/
-#define R0900_P1_MODCODLST0  0xf4b0
-#define F0900_P1_EN_TOKEN31  0xf4b00080
-#define F0900_P1_SYNCTAG_SELECT  0xf4b00040
-#define F0900_P1_MODCODRQ_MODE  0xf4b00030
+#define R0900_P1_MODCODLST0 0xf4b0
+#define MODCODLST0 REGx(R0900_P1_MODCODLST0)
 
 /*P1_MODCODLST1*/
-#define R0900_P1_MODCODLST1  0xf4b1
-#define F0900_P1_DIS_MODCOD29  0xf4b100f0
-#define F0900_P1_DIS_32PSK_9_10  0xf4b1000f
+#define R0900_P1_MODCODLST1 0xf4b1
+#define MODCODLST1 REGx(R0900_P1_MODCODLST1)
+#define F0900_P1_DIS_MODCOD29 0xf4b100f0
+#define F0900_P1_DIS_32PSK_9_10 0xf4b1000f
 
 /*P1_MODCODLST2*/
-#define R0900_P1_MODCODLST2  0xf4b2
-#define F0900_P1_DIS_32PSK_8_9  0xf4b200f0
-#define F0900_P1_DIS_32PSK_5_6  0xf4b2000f
+#define R0900_P1_MODCODLST2 0xf4b2
+#define MODCODLST2 REGx(R0900_P1_MODCODLST2)
+#define F0900_P1_DIS_32PSK_8_9 0xf4b200f0
+#define F0900_P1_DIS_32PSK_5_6 0xf4b2000f
 
 /*P1_MODCODLST3*/
-#define R0900_P1_MODCODLST3  0xf4b3
-#define F0900_P1_DIS_32PSK_4_5  0xf4b300f0
-#define F0900_P1_DIS_32PSK_3_4  0xf4b3000f
+#define R0900_P1_MODCODLST3 0xf4b3
+#define MODCODLST3 REGx(R0900_P1_MODCODLST3)
+#define F0900_P1_DIS_32PSK_4_5 0xf4b300f0
+#define F0900_P1_DIS_32PSK_3_4 0xf4b3000f
 
 /*P1_MODCODLST4*/
-#define R0900_P1_MODCODLST4  0xf4b4
-#define F0900_P1_DIS_16PSK_9_10  0xf4b400f0
-#define F0900_P1_DIS_16PSK_8_9  0xf4b4000f
+#define R0900_P1_MODCODLST4 0xf4b4
+#define MODCODLST4 REGx(R0900_P1_MODCODLST4)
+#define F0900_P1_DIS_16PSK_9_10 0xf4b400f0
+#define F0900_P1_DIS_16PSK_8_9 0xf4b4000f
 
 /*P1_MODCODLST5*/
-#define R0900_P1_MODCODLST5  0xf4b5
-#define F0900_P1_DIS_16PSK_5_6  0xf4b500f0
-#define F0900_P1_DIS_16PSK_4_5  0xf4b5000f
+#define R0900_P1_MODCODLST5 0xf4b5
+#define MODCODLST5 REGx(R0900_P1_MODCODLST5)
+#define F0900_P1_DIS_16PSK_5_6 0xf4b500f0
+#define F0900_P1_DIS_16PSK_4_5 0xf4b5000f
 
 /*P1_MODCODLST6*/
-#define R0900_P1_MODCODLST6  0xf4b6
-#define F0900_P1_DIS_16PSK_3_4  0xf4b600f0
-#define F0900_P1_DIS_16PSK_2_3  0xf4b6000f
+#define R0900_P1_MODCODLST6 0xf4b6
+#define MODCODLST6 REGx(R0900_P1_MODCODLST6)
+#define F0900_P1_DIS_16PSK_3_4 0xf4b600f0
+#define F0900_P1_DIS_16PSK_2_3 0xf4b6000f
 
 /*P1_MODCODLST7*/
-#define R0900_P1_MODCODLST7  0xf4b7
-#define F0900_P1_DIS_8P_9_10  0xf4b700f0
-#define F0900_P1_DIS_8P_8_9  0xf4b7000f
+#define R0900_P1_MODCODLST7 0xf4b7
+#define MODCODLST7 REGx(R0900_P1_MODCODLST7)
+#define F0900_P1_DIS_8P_9_10 0xf4b700f0
+#define F0900_P1_DIS_8P_8_9 0xf4b7000f
 
 /*P1_MODCODLST8*/
-#define R0900_P1_MODCODLST8  0xf4b8
-#define F0900_P1_DIS_8P_5_6  0xf4b800f0
-#define F0900_P1_DIS_8P_3_4  0xf4b8000f
+#define R0900_P1_MODCODLST8 0xf4b8
+#define MODCODLST8 REGx(R0900_P1_MODCODLST8)
+#define F0900_P1_DIS_8P_5_6 0xf4b800f0
+#define F0900_P1_DIS_8P_3_4 0xf4b8000f
 
 /*P1_MODCODLST9*/
-#define R0900_P1_MODCODLST9  0xf4b9
-#define F0900_P1_DIS_8P_2_3  0xf4b900f0
-#define F0900_P1_DIS_8P_3_5  0xf4b9000f
+#define R0900_P1_MODCODLST9 0xf4b9
+#define MODCODLST9 REGx(R0900_P1_MODCODLST9)
+#define F0900_P1_DIS_8P_2_3 0xf4b900f0
+#define F0900_P1_DIS_8P_3_5 0xf4b9000f
 
 /*P1_MODCODLSTA*/
-#define R0900_P1_MODCODLSTA  0xf4ba
-#define F0900_P1_DIS_QP_9_10  0xf4ba00f0
-#define F0900_P1_DIS_QP_8_9  0xf4ba000f
+#define R0900_P1_MODCODLSTA 0xf4ba
+#define MODCODLSTA REGx(R0900_P1_MODCODLSTA)
+#define F0900_P1_DIS_QP_9_10 0xf4ba00f0
+#define F0900_P1_DIS_QP_8_9 0xf4ba000f
 
 /*P1_MODCODLSTB*/
-#define R0900_P1_MODCODLSTB  0xf4bb
-#define F0900_P1_DIS_QP_5_6  0xf4bb00f0
-#define F0900_P1_DIS_QP_4_5  0xf4bb000f
+#define R0900_P1_MODCODLSTB 0xf4bb
+#define MODCODLSTB REGx(R0900_P1_MODCODLSTB)
+#define F0900_P1_DIS_QP_5_6 0xf4bb00f0
+#define F0900_P1_DIS_QP_4_5 0xf4bb000f
 
 /*P1_MODCODLSTC*/
-#define R0900_P1_MODCODLSTC  0xf4bc
-#define F0900_P1_DIS_QP_3_4  0xf4bc00f0
-#define F0900_P1_DIS_QP_2_3  0xf4bc000f
+#define R0900_P1_MODCODLSTC 0xf4bc
+#define MODCODLSTC REGx(R0900_P1_MODCODLSTC)
+#define F0900_P1_DIS_QP_3_4 0xf4bc00f0
+#define F0900_P1_DIS_QP_2_3 0xf4bc000f
 
 /*P1_MODCODLSTD*/
-#define R0900_P1_MODCODLSTD  0xf4bd
-#define F0900_P1_DIS_QP_3_5  0xf4bd00f0
-#define F0900_P1_DIS_QP_1_2  0xf4bd000f
+#define R0900_P1_MODCODLSTD 0xf4bd
+#define MODCODLSTD REGx(R0900_P1_MODCODLSTD)
+#define F0900_P1_DIS_QP_3_5 0xf4bd00f0
+#define F0900_P1_DIS_QP_1_2 0xf4bd000f
 
 /*P1_MODCODLSTE*/
-#define R0900_P1_MODCODLSTE  0xf4be
-#define F0900_P1_DIS_QP_2_5  0xf4be00f0
-#define F0900_P1_DIS_QP_1_3  0xf4be000f
+#define R0900_P1_MODCODLSTE 0xf4be
+#define MODCODLSTE REGx(R0900_P1_MODCODLSTE)
+#define F0900_P1_DIS_QP_2_5 0xf4be00f0
+#define F0900_P1_DIS_QP_1_3 0xf4be000f
 
 /*P1_MODCODLSTF*/
-#define R0900_P1_MODCODLSTF  0xf4bf
-#define F0900_P1_DIS_QP_1_4  0xf4bf00f0
-#define F0900_P1_DDEMOD_SET  0xf4bf0002
-#define F0900_P1_DDEMOD_MASK  0xf4bf0001
+#define R0900_P1_MODCODLSTF 0xf4bf
+#define MODCODLSTF REGx(R0900_P1_MODCODLSTF)
+#define F0900_P1_DIS_QP_1_4 0xf4bf00f0
+
+/*P1_GAUSSR0*/
+#define R0900_P1_GAUSSR0 0xf4c0
+#define GAUSSR0 REGx(R0900_P1_GAUSSR0)
+#define F0900_P1_EN_CCIMODE 0xf4c00080
+#define F0900_P1_R0_GAUSSIEN 0xf4c0007f
+
+/*P1_CCIR0*/
+#define R0900_P1_CCIR0 0xf4c1
+#define CCIR0 REGx(R0900_P1_CCIR0)
+#define F0900_P1_CCIDETECT_PLHONLY 0xf4c10080
+#define F0900_P1_R0_CCI 0xf4c1007f
+
+/*P1_CCIQUANT*/
+#define R0900_P1_CCIQUANT 0xf4c2
+#define CCIQUANT REGx(R0900_P1_CCIQUANT)
+#define F0900_P1_CCI_BETA 0xf4c200e0
+#define F0900_P1_CCI_QUANT 0xf4c2001f
+
+/*P1_CCITHRES*/
+#define R0900_P1_CCITHRES 0xf4c3
+#define CCITHRES REGx(R0900_P1_CCITHRES)
+#define F0900_P1_CCI_THRESHOLD 0xf4c300ff
+
+/*P1_CCIACC*/
+#define R0900_P1_CCIACC 0xf4c4
+#define CCIACC REGx(R0900_P1_CCIACC)
+#define F0900_P1_CCI_VALUE 0xf4c400ff
 
 /*P1_DMDRESCFG*/
-#define R0900_P1_DMDRESCFG  0xf4c6
-#define F0900_P1_DMDRES_RESET  0xf4c60080
-#define F0900_P1_DMDRES_NOISESQR  0xf4c60010
-#define F0900_P1_DMDRES_STRALL  0xf4c60008
-#define F0900_P1_DMDRES_NEWONLY  0xf4c60004
-#define F0900_P1_DMDRES_NOSTORE  0xf4c60002
-#define F0900_P1_DMDRES_AGC2MEM  0xf4c60001
+#define R0900_P1_DMDRESCFG 0xf4c6
+#define DMDRESCFG REGx(R0900_P1_DMDRESCFG)
+#define F0900_P1_DMDRES_RESET 0xf4c60080
+#define F0900_P1_DMDRES_STRALL 0xf4c60008
+#define F0900_P1_DMDRES_NEWONLY 0xf4c60004
+#define F0900_P1_DMDRES_NOSTORE 0xf4c60002
 
 /*P1_DMDRESADR*/
-#define R0900_P1_DMDRESADR  0xf4c7
-#define F0900_P1_SUSP_PREDCANAL  0xf4c70080
-#define F0900_P1_DMDRES_VALIDCFR  0xf4c70040
-#define F0900_P1_DMDRES_MEMFULL  0xf4c70030
-#define F0900_P1_DMDRES_RESNBR  0xf4c7000f
+#define R0900_P1_DMDRESADR 0xf4c7
+#define DMDRESADR REGx(R0900_P1_DMDRESADR)
+#define F0900_P1_DMDRES_VALIDCFR 0xf4c70040
+#define F0900_P1_DMDRES_MEMFULL 0xf4c70030
+#define F0900_P1_DMDRES_RESNBR 0xf4c7000f
 
 /*P1_DMDRESDATA7*/
-#define R0900_P1_DMDRESDATA7  0xf4c8
-#define F0900_P1_DMDRES_DATA7  0xf4c800ff
+#define R0900_P1_DMDRESDATA7 0xf4c8
+#define F0900_P1_DMDRES_DATA7 0xf4c800ff
 
 /*P1_DMDRESDATA6*/
-#define R0900_P1_DMDRESDATA6  0xf4c9
-#define F0900_P1_DMDRES_DATA6  0xf4c900ff
+#define R0900_P1_DMDRESDATA6 0xf4c9
+#define F0900_P1_DMDRES_DATA6 0xf4c900ff
 
 /*P1_DMDRESDATA5*/
-#define R0900_P1_DMDRESDATA5  0xf4ca
-#define F0900_P1_DMDRES_DATA5  0xf4ca00ff
+#define R0900_P1_DMDRESDATA5 0xf4ca
+#define F0900_P1_DMDRES_DATA5 0xf4ca00ff
 
 /*P1_DMDRESDATA4*/
-#define R0900_P1_DMDRESDATA4  0xf4cb
-#define F0900_P1_DMDRES_DATA4  0xf4cb00ff
+#define R0900_P1_DMDRESDATA4 0xf4cb
+#define F0900_P1_DMDRES_DATA4 0xf4cb00ff
 
 /*P1_DMDRESDATA3*/
-#define R0900_P1_DMDRESDATA3  0xf4cc
-#define F0900_P1_DMDRES_DATA3  0xf4cc00ff
+#define R0900_P1_DMDRESDATA3 0xf4cc
+#define F0900_P1_DMDRES_DATA3 0xf4cc00ff
 
 /*P1_DMDRESDATA2*/
-#define R0900_P1_DMDRESDATA2  0xf4cd
-#define F0900_P1_DMDRES_DATA2  0xf4cd00ff
+#define R0900_P1_DMDRESDATA2 0xf4cd
+#define F0900_P1_DMDRES_DATA2 0xf4cd00ff
 
 /*P1_DMDRESDATA1*/
-#define R0900_P1_DMDRESDATA1  0xf4ce
-#define F0900_P1_DMDRES_DATA1  0xf4ce00ff
+#define R0900_P1_DMDRESDATA1 0xf4ce
+#define F0900_P1_DMDRES_DATA1 0xf4ce00ff
 
 /*P1_DMDRESDATA0*/
-#define R0900_P1_DMDRESDATA0  0xf4cf
-#define F0900_P1_DMDRES_DATA0  0xf4cf00ff
+#define R0900_P1_DMDRESDATA0 0xf4cf
+#define F0900_P1_DMDRES_DATA0 0xf4cf00ff
 
 /*P1_FFEI1*/
-#define R0900_P1_FFEI1  0xf4d0
-#define F0900_P1_FFE_ACCI1  0xf4d001ff
+#define R0900_P1_FFEI1 0xf4d0
+#define FFEI1 REGx(R0900_P1_FFEI1)
+#define F0900_P1_FFE_ACCI1 0xf4d001ff
 
 /*P1_FFEQ1*/
-#define R0900_P1_FFEQ1  0xf4d1
-#define F0900_P1_FFE_ACCQ1  0xf4d101ff
+#define R0900_P1_FFEQ1 0xf4d1
+#define FFEQ1 REGx(R0900_P1_FFEQ1)
+#define F0900_P1_FFE_ACCQ1 0xf4d101ff
 
 /*P1_FFEI2*/
-#define R0900_P1_FFEI2  0xf4d2
-#define F0900_P1_FFE_ACCI2  0xf4d201ff
+#define R0900_P1_FFEI2 0xf4d2
+#define FFEI2 REGx(R0900_P1_FFEI2)
+#define F0900_P1_FFE_ACCI2 0xf4d201ff
 
 /*P1_FFEQ2*/
-#define R0900_P1_FFEQ2  0xf4d3
-#define F0900_P1_FFE_ACCQ2  0xf4d301ff
+#define R0900_P1_FFEQ2 0xf4d3
+#define FFEQ2 REGx(R0900_P1_FFEQ2)
+#define F0900_P1_FFE_ACCQ2 0xf4d301ff
 
 /*P1_FFEI3*/
-#define R0900_P1_FFEI3  0xf4d4
-#define F0900_P1_FFE_ACCI3  0xf4d401ff
+#define R0900_P1_FFEI3 0xf4d4
+#define FFEI3 REGx(R0900_P1_FFEI3)
+#define F0900_P1_FFE_ACCI3 0xf4d401ff
 
 /*P1_FFEQ3*/
-#define R0900_P1_FFEQ3  0xf4d5
-#define F0900_P1_FFE_ACCQ3  0xf4d501ff
+#define R0900_P1_FFEQ3 0xf4d5
+#define FFEQ3 REGx(R0900_P1_FFEQ3)
+#define F0900_P1_FFE_ACCQ3 0xf4d501ff
 
 /*P1_FFEI4*/
-#define R0900_P1_FFEI4  0xf4d6
-#define F0900_P1_FFE_ACCI4  0xf4d601ff
+#define R0900_P1_FFEI4 0xf4d6
+#define FFEI4 REGx(R0900_P1_FFEI4)
+#define F0900_P1_FFE_ACCI4 0xf4d601ff
 
 /*P1_FFEQ4*/
-#define R0900_P1_FFEQ4  0xf4d7
-#define F0900_P1_FFE_ACCQ4  0xf4d701ff
+#define R0900_P1_FFEQ4 0xf4d7
+#define FFEQ4 REGx(R0900_P1_FFEQ4)
+#define F0900_P1_FFE_ACCQ4 0xf4d701ff
 
 /*P1_FFECFG*/
-#define R0900_P1_FFECFG  0xf4d8
-#define F0900_P1_EQUALFFE_ON  0xf4d80040
-#define F0900_P1_EQUAL_USEDSYMB  0xf4d80030
-#define F0900_P1_MU_EQUALFFE  0xf4d80007
+#define R0900_P1_FFECFG 0xf4d8
+#define FFECFG REGx(R0900_P1_FFECFG)
+#define F0900_P1_EQUALFFE_ON 0xf4d80040
+#define F0900_P1_MU_EQUALFFE 0xf4d80007
 
 /*P1_TNRCFG*/
-#define R0900_P1_TNRCFG  0xf4e0
-#define F0900_P1_TUN_ACKFAIL  0xf4e00080
-#define F0900_P1_TUN_TYPE  0xf4e00070
-#define F0900_P1_TUN_SECSTOP  0xf4e00008
-#define F0900_P1_TUN_VCOSRCH  0xf4e00004
-#define F0900_P1_TUN_MADDRESS  0xf4e00003
+#define R0900_P1_TNRCFG 0xf4e0
+#define TNRCFG REGx(R0900_P1_TNRCFG)
+#define F0900_P1_TUN_ACKFAIL 0xf4e00080
+#define F0900_P1_TUN_TYPE 0xf4e00070
+#define F0900_P1_TUN_SECSTOP 0xf4e00008
+#define F0900_P1_TUN_VCOSRCH 0xf4e00004
+#define F0900_P1_TUN_MADDRESS 0xf4e00003
 
 /*P1_TNRCFG2*/
-#define R0900_P1_TNRCFG2  0xf4e1
-#define F0900_P1_TUN_IQSWAP  0xf4e10080
-#define F0900_P1_STB6110_STEP2MHZ  0xf4e10040
-#define F0900_P1_STB6120_DBLI2C  0xf4e10020
-#define F0900_P1_DIS_FCCK  0xf4e10010
-#define F0900_P1_DIS_LPEN  0xf4e10008
-#define F0900_P1_DIS_BWCALC  0xf4e10004
-#define F0900_P1_SHORT_WAITSTATES  0xf4e10002
-#define F0900_P1_DIS_2BWAGC1  0xf4e10001
+#define R0900_P1_TNRCFG2 0xf4e1
+#define TNRCFG2 REGx(R0900_P1_TNRCFG2)
+#define F0900_P1_TUN_IQSWAP 0xf4e10080
+#define F0900_P1_DIS_BWCALC 0xf4e10004
+#define F0900_P1_SHORT_WAITSTATES 0xf4e10002
 
 /*P1_TNRXTAL*/
-#define R0900_P1_TNRXTAL  0xf4e4
-#define F0900_P1_TUN_MCLKDECIMAL  0xf4e400e0
-#define F0900_P1_TUN_XTALFREQ  0xf4e4001f
+#define R0900_P1_TNRXTAL 0xf4e4
+#define TNRXTAL REGx(R0900_P1_TNRXTAL)
+#define F0900_P1_TUN_XTALFREQ 0xf4e4001f
 
 /*P1_TNRSTEPS*/
-#define R0900_P1_TNRSTEPS  0xf4e7
-#define F0900_P1_TUNER_BW1P6  0xf4e70080
-#define F0900_P1_BWINC_OFFSET  0xf4e70070
-#define F0900_P1_SOFTSTEP_RNG  0xf4e70008
-#define F0900_P1_TUN_BWOFFSET  0xf4e70107
+#define R0900_P1_TNRSTEPS 0xf4e7
+#define TNRSTEPS REGx(R0900_P1_TNRSTEPS)
+#define F0900_P1_TUNER_BW0P125 0xf4e70080
+#define F0900_P1_BWINC_OFFSET 0xf4e70170
+#define F0900_P1_SOFTSTEP_RNG 0xf4e70008
+#define F0900_P1_TUN_BWOFFSET 0xf4e70007
 
 /*P1_TNRGAIN*/
-#define R0900_P1_TNRGAIN  0xf4e8
-#define F0900_P1_TUN_KDIVEN  0xf4e800c0
-#define F0900_P1_STB6X00_OCK  0xf4e80030
-#define F0900_P1_TUN_GAIN  0xf4e8000f
+#define R0900_P1_TNRGAIN 0xf4e8
+#define TNRGAIN REGx(R0900_P1_TNRGAIN)
+#define F0900_P1_TUN_KDIVEN 0xf4e800c0
+#define F0900_P1_STB6X00_OCK 0xf4e80030
+#define F0900_P1_TUN_GAIN 0xf4e8000f
 
 /*P1_TNRRF1*/
-#define R0900_P1_TNRRF1  0xf4e9
-#define F0900_P1_TUN_RFFREQ2  0xf4e900ff
+#define R0900_P1_TNRRF1 0xf4e9
+#define TNRRF1 REGx(R0900_P1_TNRRF1)
+#define F0900_P1_TUN_RFFREQ2 0xf4e900ff
+#define TUN_RFFREQ2 FLDx(F0900_P1_TUN_RFFREQ2)
 
 /*P1_TNRRF0*/
-#define R0900_P1_TNRRF0  0xf4ea
-#define F0900_P1_TUN_RFFREQ1  0xf4ea00ff
+#define R0900_P1_TNRRF0 0xf4ea
+#define TNRRF0 REGx(R0900_P1_TNRRF0)
+#define F0900_P1_TUN_RFFREQ1 0xf4ea00ff
+#define TUN_RFFREQ1 FLDx(F0900_P1_TUN_RFFREQ1)
 
 /*P1_TNRBW*/
-#define R0900_P1_TNRBW  0xf4eb
-#define F0900_P1_TUN_RFFREQ0  0xf4eb00c0
-#define F0900_P1_TUN_BW  0xf4eb003f
+#define R0900_P1_TNRBW 0xf4eb
+#define TNRBW REGx(R0900_P1_TNRBW)
+#define F0900_P1_TUN_RFFREQ0 0xf4eb00c0
+#define TUN_RFFREQ0 FLDx(F0900_P1_TUN_RFFREQ0)
+#define F0900_P1_TUN_BW 0xf4eb003f
+#define TUN_BW FLDx(F0900_P1_TUN_BW)
 
 /*P1_TNRADJ*/
-#define R0900_P1_TNRADJ  0xf4ec
-#define F0900_P1_STB61X0_RCLK  0xf4ec0080
-#define F0900_P1_STB61X0_CALTIME  0xf4ec0040
-#define F0900_P1_STB6X00_DLB  0xf4ec0038
-#define F0900_P1_STB6000_FCL  0xf4ec0007
+#define R0900_P1_TNRADJ 0xf4ec
+#define TNRADJ REGx(R0900_P1_TNRADJ)
+#define F0900_P1_STB61X0_CALTIME 0xf4ec0040
 
 /*P1_TNRCTL2*/
-#define R0900_P1_TNRCTL2  0xf4ed
-#define F0900_P1_STB61X0_LCP1_RCCKOFF  0xf4ed0080
-#define F0900_P1_STB61X0_LCP0  0xf4ed0040
-#define F0900_P1_STB61X0_XTOUT_RFOUTS  0xf4ed0020
-#define F0900_P1_STB61X0_XTON_MCKDV  0xf4ed0010
-#define F0900_P1_STB61X0_CALOFF_DCOFF  0xf4ed0008
-#define F0900_P1_STB6110_LPT  0xf4ed0004
-#define F0900_P1_STB6110_RX  0xf4ed0002
-#define F0900_P1_STB6110_SYN  0xf4ed0001
+#define R0900_P1_TNRCTL2 0xf4ed
+#define TNRCTL2 REGx(R0900_P1_TNRCTL2)
+#define F0900_P1_STB61X0_RCCKOFF 0xf4ed0080
+#define F0900_P1_STB61X0_ICP_SDOFF 0xf4ed0040
+#define F0900_P1_STB61X0_DCLOOPOFF 0xf4ed0020
+#define F0900_P1_STB61X0_REFOUTSEL 0xf4ed0010
+#define F0900_P1_STB61X0_CALOFF 0xf4ed0008
+#define F0900_P1_STB6XX0_LPT_BEN 0xf4ed0004
+#define F0900_P1_STB6XX0_RX_OSCP 0xf4ed0002
+#define F0900_P1_STB6XX0_SYN 0xf4ed0001
 
 /*P1_TNRCFG3*/
-#define R0900_P1_TNRCFG3  0xf4ee
-#define F0900_P1_STB6120_DISCTRL1  0xf4ee0080
-#define F0900_P1_STB6120_INVORDER  0xf4ee0040
-#define F0900_P1_STB6120_ENCTRL6  0xf4ee0020
-#define F0900_P1_TUN_PLLFREQ  0xf4ee001c
-#define F0900_P1_TUN_I2CFREQ_MODE  0xf4ee0003
+#define R0900_P1_TNRCFG3 0xf4ee
+#define TNRCFG3 REGx(R0900_P1_TNRCFG3)
+#define F0900_P1_TUN_PLLFREQ 0xf4ee001c
+#define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003
 
 /*P1_TNRLAUNCH*/
-#define R0900_P1_TNRLAUNCH  0xf4f0
+#define R0900_P1_TNRLAUNCH 0xf4f0
+#define TNRLAUNCH REGx(R0900_P1_TNRLAUNCH)
 
 /*P1_TNRLD*/
-#define R0900_P1_TNRLD  0xf4f0
-#define F0900_P1_TUNLD_VCOING  0xf4f00080
-#define F0900_P1_TUN_REG1FAIL  0xf4f00040
-#define F0900_P1_TUN_REG2FAIL  0xf4f00020
-#define F0900_P1_TUN_REG3FAIL  0xf4f00010
-#define F0900_P1_TUN_REG4FAIL  0xf4f00008
-#define F0900_P1_TUN_REG5FAIL  0xf4f00004
-#define F0900_P1_TUN_BWING  0xf4f00002
-#define F0900_P1_TUN_LOCKED  0xf4f00001
+#define R0900_P1_TNRLD 0xf4f0
+#define TNRLD REGx(R0900_P1_TNRLD)
+#define F0900_P1_TUNLD_VCOING 0xf4f00080
+#define F0900_P1_TUN_REG1FAIL 0xf4f00040
+#define F0900_P1_TUN_REG2FAIL 0xf4f00020
+#define F0900_P1_TUN_REG3FAIL 0xf4f00010
+#define F0900_P1_TUN_REG4FAIL 0xf4f00008
+#define F0900_P1_TUN_REG5FAIL 0xf4f00004
+#define F0900_P1_TUN_BWING 0xf4f00002
+#define F0900_P1_TUN_LOCKED 0xf4f00001
 
 /*P1_TNROBSL*/
-#define R0900_P1_TNROBSL  0xf4f6
-#define F0900_P1_TUN_I2CABORTED  0xf4f60080
-#define F0900_P1_TUN_LPEN  0xf4f60040
-#define F0900_P1_TUN_FCCK  0xf4f60020
-#define F0900_P1_TUN_I2CLOCKED  0xf4f60010
-#define F0900_P1_TUN_PROGDONE  0xf4f6000c
-#define F0900_P1_TUN_RFRESTE1  0xf4f60003
+#define R0900_P1_TNROBSL 0xf4f6
+#define TNROBSL REGx(R0900_P1_TNROBSL)
+#define F0900_P1_TUN_I2CABORTED 0xf4f60080
+#define F0900_P1_TUN_LPEN 0xf4f60040
+#define F0900_P1_TUN_FCCK 0xf4f60020
+#define F0900_P1_TUN_I2CLOCKED 0xf4f60010
+#define F0900_P1_TUN_PROGDONE 0xf4f6000c
+#define F0900_P1_TUN_RFRESTE1 0xf4f60003
+#define TUN_RFRESTE1 FLDx(F0900_P1_TUN_RFRESTE1)
 
 /*P1_TNRRESTE*/
-#define R0900_P1_TNRRESTE  0xf4f7
-#define F0900_P1_TUN_RFRESTE0  0xf4f700ff
+#define R0900_P1_TNRRESTE 0xf4f7
+#define TNRRESTE REGx(R0900_P1_TNRRESTE)
+#define F0900_P1_TUN_RFRESTE0 0xf4f700ff
+#define TUN_RFRESTE0 FLDx(F0900_P1_TUN_RFRESTE0)
 
 /*P1_SMAPCOEF7*/
-#define R0900_P1_SMAPCOEF7  0xf500
-#define F0900_P1_DIS_QSCALE  0xf5000080
-#define F0900_P1_SMAPCOEF_Q_LLR12  0xf500017f
+#define R0900_P1_SMAPCOEF7 0xf500
+#define SMAPCOEF7 REGx(R0900_P1_SMAPCOEF7)
+#define F0900_P1_DIS_QSCALE 0xf5000080
+#define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f
 
 /*P1_SMAPCOEF6*/
-#define R0900_P1_SMAPCOEF6  0xf501
-#define F0900_P1_DIS_NEWSCALE  0xf5010008
-#define F0900_P1_ADJ_8PSKLLR1  0xf5010004
-#define F0900_P1_OLD_8PSKLLR1  0xf5010002
-#define F0900_P1_DIS_AB8PSK  0xf5010001
+#define R0900_P1_SMAPCOEF6 0xf501
+#define SMAPCOEF6 REGx(R0900_P1_SMAPCOEF6)
+#define F0900_P1_ADJ_8PSKLLR1 0xf5010004
+#define F0900_P1_OLD_8PSKLLR1 0xf5010002
+#define F0900_P1_DIS_AB8PSK 0xf5010001
 
 /*P1_SMAPCOEF5*/
-#define R0900_P1_SMAPCOEF5  0xf502
-#define F0900_P1_DIS_8SCALE  0xf5020080
-#define F0900_P1_SMAPCOEF_8P_LLR23  0xf502017f
+#define R0900_P1_SMAPCOEF5 0xf502
+#define SMAPCOEF5 REGx(R0900_P1_SMAPCOEF5)
+#define F0900_P1_DIS_8SCALE 0xf5020080
+#define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f
+
+/*P1_NCO2MAX1*/
+#define R0900_P1_NCO2MAX1 0xf514
+#define NCO2MAX1 REGx(R0900_P1_NCO2MAX1)
+#define F0900_P1_TETA2_MAXVABS1 0xf51400ff
+
+/*P1_NCO2MAX0*/
+#define R0900_P1_NCO2MAX0 0xf515
+#define NCO2MAX0 REGx(R0900_P1_NCO2MAX0)
+#define F0900_P1_TETA2_MAXVABS0 0xf51500ff
+
+/*P1_NCO2FR1*/
+#define R0900_P1_NCO2FR1 0xf516
+#define NCO2FR1 REGx(R0900_P1_NCO2FR1)
+#define F0900_P1_NCO2FINAL_ANGLE1 0xf51600ff
+
+/*P1_NCO2FR0*/
+#define R0900_P1_NCO2FR0 0xf517
+#define NCO2FR0 REGx(R0900_P1_NCO2FR0)
+#define F0900_P1_NCO2FINAL_ANGLE0 0xf51700ff
+
+/*P1_CFR2AVRGE1*/
+#define R0900_P1_CFR2AVRGE1 0xf518
+#define CFR2AVRGE1 REGx(R0900_P1_CFR2AVRGE1)
+#define F0900_P1_I2C_CFR2AVERAGE1 0xf51800ff
+
+/*P1_CFR2AVRGE0*/
+#define R0900_P1_CFR2AVRGE0 0xf519
+#define CFR2AVRGE0 REGx(R0900_P1_CFR2AVRGE0)
+#define F0900_P1_I2C_CFR2AVERAGE0 0xf51900ff
 
 /*P1_DMDPLHSTAT*/
-#define R0900_P1_DMDPLHSTAT  0xf520
-#define F0900_P1_PLH_STATISTIC  0xf52000ff
+#define R0900_P1_DMDPLHSTAT 0xf520
+#define DMDPLHSTAT REGx(R0900_P1_DMDPLHSTAT)
+#define F0900_P1_PLH_STATISTIC 0xf52000ff
 
 /*P1_LOCKTIME3*/
-#define R0900_P1_LOCKTIME3  0xf522
-#define F0900_P1_DEMOD_LOCKTIME3  0xf52200ff
+#define R0900_P1_LOCKTIME3 0xf522
+#define LOCKTIME3 REGx(R0900_P1_LOCKTIME3)
+#define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff
 
 /*P1_LOCKTIME2*/
-#define R0900_P1_LOCKTIME2  0xf523
-#define F0900_P1_DEMOD_LOCKTIME2  0xf52300ff
+#define R0900_P1_LOCKTIME2 0xf523
+#define LOCKTIME2 REGx(R0900_P1_LOCKTIME2)
+#define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff
 
 /*P1_LOCKTIME1*/
-#define R0900_P1_LOCKTIME1  0xf524
-#define F0900_P1_DEMOD_LOCKTIME1  0xf52400ff
+#define R0900_P1_LOCKTIME1 0xf524
+#define LOCKTIME1 REGx(R0900_P1_LOCKTIME1)
+#define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff
 
 /*P1_LOCKTIME0*/
-#define R0900_P1_LOCKTIME0  0xf525
-#define F0900_P1_DEMOD_LOCKTIME0  0xf52500ff
+#define R0900_P1_LOCKTIME0 0xf525
+#define LOCKTIME0 REGx(R0900_P1_LOCKTIME0)
+#define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff
 
 /*P1_VITSCALE*/
-#define R0900_P1_VITSCALE  0xf532
-#define F0900_P1_NVTH_NOSRANGE  0xf5320080
-#define F0900_P1_VERROR_MAXMODE  0xf5320040
-#define F0900_P1_KDIV_MODE  0xf5320030
-#define F0900_P1_NSLOWSN_LOCKED  0xf5320008
-#define F0900_P1_DELOCK_PRFLOSS  0xf5320004
-#define F0900_P1_DIS_RSFLOCK  0xf5320002
+#define R0900_P1_VITSCALE 0xf532
+#define VITSCALE REGx(R0900_P1_VITSCALE)
+#define F0900_P1_NVTH_NOSRANGE 0xf5320080
+#define F0900_P1_VERROR_MAXMODE 0xf5320040
+#define F0900_P1_NSLOWSN_LOCKED 0xf5320008
+#define F0900_P1_DIS_RSFLOCK 0xf5320002
 
 /*P1_FECM*/
-#define R0900_P1_FECM  0xf533
-#define F0900_P1_DSS_DVB  0xf5330080
-#define F0900_P1_DEMOD_BYPASS  0xf5330040
-#define F0900_P1_CMP_SLOWMODE  0xf5330020
-#define F0900_P1_DSS_SRCH  0xf5330010
-#define F0900_P1_DIFF_MODEVIT  0xf5330004
-#define F0900_P1_SYNCVIT  0xf5330002
-#define F0900_P1_IQINV  0xf5330001
+#define R0900_P1_FECM 0xf533
+#define FECM REGx(R0900_P1_FECM)
+#define F0900_P1_DSS_DVB 0xf5330080
+#define DSS_DVB FLDx(F0900_P1_DSS_DVB)
+#define F0900_P1_DSS_SRCH 0xf5330010
+#define F0900_P1_SYNCVIT 0xf5330002
+#define F0900_P1_IQINV 0xf5330001
+#define IQINV FLDx(F0900_P1_IQINV)
 
 /*P1_VTH12*/
-#define R0900_P1_VTH12  0xf534
-#define F0900_P1_VTH12  0xf53400ff
+#define R0900_P1_VTH12 0xf534
+#define VTH12 REGx(R0900_P1_VTH12)
+#define F0900_P1_VTH12 0xf53400ff
 
 /*P1_VTH23*/
-#define R0900_P1_VTH23  0xf535
-#define F0900_P1_VTH23  0xf53500ff
+#define R0900_P1_VTH23 0xf535
+#define VTH23 REGx(R0900_P1_VTH23)
+#define F0900_P1_VTH23 0xf53500ff
 
 /*P1_VTH34*/
-#define R0900_P1_VTH34  0xf536
-#define F0900_P1_VTH34  0xf53600ff
+#define R0900_P1_VTH34 0xf536
+#define VTH34 REGx(R0900_P1_VTH34)
+#define F0900_P1_VTH34 0xf53600ff
 
 /*P1_VTH56*/
-#define R0900_P1_VTH56  0xf537
-#define F0900_P1_VTH56  0xf53700ff
+#define R0900_P1_VTH56 0xf537
+#define VTH56 REGx(R0900_P1_VTH56)
+#define F0900_P1_VTH56 0xf53700ff
 
 /*P1_VTH67*/
-#define R0900_P1_VTH67  0xf538
-#define F0900_P1_VTH67  0xf53800ff
+#define R0900_P1_VTH67 0xf538
+#define VTH67 REGx(R0900_P1_VTH67)
+#define F0900_P1_VTH67 0xf53800ff
 
 /*P1_VTH78*/
-#define R0900_P1_VTH78  0xf539
-#define F0900_P1_VTH78  0xf53900ff
+#define R0900_P1_VTH78 0xf539
+#define VTH78 REGx(R0900_P1_VTH78)
+#define F0900_P1_VTH78 0xf53900ff
 
 /*P1_VITCURPUN*/
-#define R0900_P1_VITCURPUN  0xf53a
-#define F0900_P1_VIT_MAPPING  0xf53a00e0
-#define F0900_P1_VIT_CURPUN  0xf53a001f
+#define R0900_P1_VITCURPUN 0xf53a
+#define VITCURPUN REGx(R0900_P1_VITCURPUN)
+#define F0900_P1_VIT_CURPUN 0xf53a001f
+#define VIT_CURPUN FLDx(F0900_P1_VIT_CURPUN)
 
 /*P1_VERROR*/
-#define R0900_P1_VERROR  0xf53b
-#define F0900_P1_REGERR_VIT  0xf53b00ff
+#define R0900_P1_VERROR 0xf53b
+#define VERROR REGx(R0900_P1_VERROR)
+#define F0900_P1_REGERR_VIT 0xf53b00ff
 
 /*P1_PRVIT*/
-#define R0900_P1_PRVIT  0xf53c
-#define F0900_P1_DIS_VTHLOCK  0xf53c0040
-#define F0900_P1_E7_8VIT  0xf53c0020
-#define F0900_P1_E6_7VIT  0xf53c0010
-#define F0900_P1_E5_6VIT  0xf53c0008
-#define F0900_P1_E3_4VIT  0xf53c0004
-#define F0900_P1_E2_3VIT  0xf53c0002
-#define F0900_P1_E1_2VIT  0xf53c0001
+#define R0900_P1_PRVIT 0xf53c
+#define PRVIT REGx(R0900_P1_PRVIT)
+#define F0900_P1_DIS_VTHLOCK 0xf53c0040
+#define F0900_P1_E7_8VIT 0xf53c0020
+#define F0900_P1_E6_7VIT 0xf53c0010
+#define F0900_P1_E5_6VIT 0xf53c0008
+#define F0900_P1_E3_4VIT 0xf53c0004
+#define F0900_P1_E2_3VIT 0xf53c0002
+#define F0900_P1_E1_2VIT 0xf53c0001
 
 /*P1_VAVSRVIT*/
-#define R0900_P1_VAVSRVIT  0xf53d
-#define F0900_P1_AMVIT  0xf53d0080
-#define F0900_P1_FROZENVIT  0xf53d0040
-#define F0900_P1_SNVIT  0xf53d0030
-#define F0900_P1_TOVVIT  0xf53d000c
-#define F0900_P1_HYPVIT  0xf53d0003
+#define R0900_P1_VAVSRVIT 0xf53d
+#define VAVSRVIT REGx(R0900_P1_VAVSRVIT)
+#define F0900_P1_AMVIT 0xf53d0080
+#define F0900_P1_FROZENVIT 0xf53d0040
+#define F0900_P1_SNVIT 0xf53d0030
+#define F0900_P1_TOVVIT 0xf53d000c
+#define F0900_P1_HYPVIT 0xf53d0003
 
 /*P1_VSTATUSVIT*/
-#define R0900_P1_VSTATUSVIT  0xf53e
-#define F0900_P1_VITERBI_ON  0xf53e0080
-#define F0900_P1_END_LOOPVIT  0xf53e0040
-#define F0900_P1_VITERBI_DEPRF  0xf53e0020
-#define F0900_P1_PRFVIT  0xf53e0010
-#define F0900_P1_LOCKEDVIT  0xf53e0008
-#define F0900_P1_VITERBI_DELOCK  0xf53e0004
-#define F0900_P1_VIT_DEMODSEL  0xf53e0002
-#define F0900_P1_VITERBI_COMPOUT  0xf53e0001
+#define R0900_P1_VSTATUSVIT 0xf53e
+#define VSTATUSVIT REGx(R0900_P1_VSTATUSVIT)
+#define F0900_P1_PRFVIT 0xf53e0010
+#define PRFVIT FLDx(F0900_P1_PRFVIT)
+#define F0900_P1_LOCKEDVIT 0xf53e0008
+#define LOCKEDVIT FLDx(F0900_P1_LOCKEDVIT)
 
 /*P1_VTHINUSE*/
-#define R0900_P1_VTHINUSE  0xf53f
-#define F0900_P1_VIT_INUSE  0xf53f00ff
+#define R0900_P1_VTHINUSE 0xf53f
+#define VTHINUSE REGx(R0900_P1_VTHINUSE)
+#define F0900_P1_VIT_INUSE 0xf53f00ff
 
 /*P1_KDIV12*/
-#define R0900_P1_KDIV12  0xf540
-#define F0900_P1_KDIV12_MANUAL  0xf5400080
-#define F0900_P1_K_DIVIDER_12  0xf540007f
+#define R0900_P1_KDIV12 0xf540
+#define KDIV12 REGx(R0900_P1_KDIV12)
+#define F0900_P1_K_DIVIDER_12 0xf540007f
 
 /*P1_KDIV23*/
-#define R0900_P1_KDIV23  0xf541
-#define F0900_P1_KDIV23_MANUAL  0xf5410080
-#define F0900_P1_K_DIVIDER_23  0xf541007f
+#define R0900_P1_KDIV23 0xf541
+#define KDIV23 REGx(R0900_P1_KDIV23)
+#define F0900_P1_K_DIVIDER_23 0xf541007f
 
 /*P1_KDIV34*/
-#define R0900_P1_KDIV34  0xf542
-#define F0900_P1_KDIV34_MANUAL  0xf5420080
-#define F0900_P1_K_DIVIDER_34  0xf542007f
+#define R0900_P1_KDIV34 0xf542
+#define KDIV34 REGx(R0900_P1_KDIV34)
+#define F0900_P1_K_DIVIDER_34 0xf542007f
 
 /*P1_KDIV56*/
-#define R0900_P1_KDIV56  0xf543
-#define F0900_P1_KDIV56_MANUAL  0xf5430080
-#define F0900_P1_K_DIVIDER_56  0xf543007f
+#define R0900_P1_KDIV56 0xf543
+#define KDIV56 REGx(R0900_P1_KDIV56)
+#define F0900_P1_K_DIVIDER_56 0xf543007f
 
 /*P1_KDIV67*/
-#define R0900_P1_KDIV67  0xf544
-#define F0900_P1_KDIV67_MANUAL  0xf5440080
-#define F0900_P1_K_DIVIDER_67  0xf544007f
+#define R0900_P1_KDIV67 0xf544
+#define KDIV67 REGx(R0900_P1_KDIV67)
+#define F0900_P1_K_DIVIDER_67 0xf544007f
 
 /*P1_KDIV78*/
-#define R0900_P1_KDIV78  0xf545
-#define F0900_P1_KDIV78_MANUAL  0xf5450080
-#define F0900_P1_K_DIVIDER_78  0xf545007f
+#define R0900_P1_KDIV78 0xf545
+#define KDIV78 REGx(R0900_P1_KDIV78)
+#define F0900_P1_K_DIVIDER_78 0xf545007f
 
 /*P1_PDELCTRL1*/
-#define R0900_P1_PDELCTRL1  0xf550
-#define F0900_P1_INV_MISMASK  0xf5500080
-#define F0900_P1_FORCE_ACCEPTED  0xf5500040
-#define F0900_P1_FILTER_EN  0xf5500020
-#define F0900_P1_FORCE_PKTDELINUSE  0xf5500010
-#define F0900_P1_HYSTEN  0xf5500008
-#define F0900_P1_HYSTSWRST  0xf5500004
-#define F0900_P1_EN_MIS00  0xf5500002
-#define F0900_P1_ALGOSWRST  0xf5500001
+#define R0900_P1_PDELCTRL1 0xf550
+#define PDELCTRL1 REGx(R0900_P1_PDELCTRL1)
+#define F0900_P1_INV_MISMASK 0xf5500080
+#define F0900_P1_FILTER_EN 0xf5500020
+#define F0900_P1_EN_MIS00 0xf5500002
+#define F0900_P1_ALGOSWRST 0xf5500001
+#define ALGOSWRST FLDx(F0900_P1_ALGOSWRST)
 
 /*P1_PDELCTRL2*/
-#define R0900_P1_PDELCTRL2  0xf551
-#define F0900_P1_FORCE_CONTINUOUS  0xf5510080
-#define F0900_P1_RESET_UPKO_COUNT  0xf5510040
-#define F0900_P1_USER_PKTDELIN_NB  0xf5510020
-#define F0900_P1_FORCE_LOCKED  0xf5510010
-#define F0900_P1_DATA_UNBBSCRAM  0xf5510008
-#define F0900_P1_FORCE_LONGPKT  0xf5510004
-#define F0900_P1_FRAME_MODE  0xf5510002
+#define R0900_P1_PDELCTRL2 0xf551
+#define PDELCTRL2 REGx(R0900_P1_PDELCTRL2)
+#define F0900_P1_RESET_UPKO_COUNT 0xf5510040
+#define RESET_UPKO_COUNT FLDx(F0900_P1_RESET_UPKO_COUNT)
+#define F0900_P1_FRAME_MODE 0xf5510002
+#define F0900_P1_NOBCHERRFLG_USE 0xf5510001
 
 /*P1_HYSTTHRESH*/
-#define R0900_P1_HYSTTHRESH  0xf554
-#define F0900_P1_UNLCK_THRESH  0xf55400f0
-#define F0900_P1_DELIN_LCK_THRESH  0xf554000f
+#define R0900_P1_HYSTTHRESH 0xf554
+#define HYSTTHRESH REGx(R0900_P1_HYSTTHRESH)
+#define F0900_P1_UNLCK_THRESH 0xf55400f0
+#define F0900_P1_DELIN_LCK_THRESH 0xf554000f
 
 /*P1_ISIENTRY*/
-#define R0900_P1_ISIENTRY  0xf55e
-#define F0900_P1_ISI_ENTRY  0xf55e00ff
+#define R0900_P1_ISIENTRY 0xf55e
+#define ISIENTRY REGx(R0900_P1_ISIENTRY)
+#define F0900_P1_ISI_ENTRY 0xf55e00ff
 
 /*P1_ISIBITENA*/
-#define R0900_P1_ISIBITENA  0xf55f
-#define F0900_P1_ISI_BIT_EN  0xf55f00ff
+#define R0900_P1_ISIBITENA 0xf55f
+#define ISIBITENA REGx(R0900_P1_ISIBITENA)
+#define F0900_P1_ISI_BIT_EN 0xf55f00ff
 
 /*P1_MATSTR1*/
-#define R0900_P1_MATSTR1  0xf560
-#define F0900_P1_MATYPE_CURRENT1  0xf56000ff
+#define R0900_P1_MATSTR1 0xf560
+#define MATSTR1 REGx(R0900_P1_MATSTR1)
+#define F0900_P1_MATYPE_CURRENT1 0xf56000ff
 
 /*P1_MATSTR0*/
-#define R0900_P1_MATSTR0  0xf561
-#define F0900_P1_MATYPE_CURRENT0  0xf56100ff
+#define R0900_P1_MATSTR0 0xf561
+#define MATSTR0 REGx(R0900_P1_MATSTR0)
+#define F0900_P1_MATYPE_CURRENT0 0xf56100ff
 
 /*P1_UPLSTR1*/
-#define R0900_P1_UPLSTR1  0xf562
-#define F0900_P1_UPL_CURRENT1  0xf56200ff
+#define R0900_P1_UPLSTR1 0xf562
+#define UPLSTR1 REGx(R0900_P1_UPLSTR1)
+#define F0900_P1_UPL_CURRENT1 0xf56200ff
 
 /*P1_UPLSTR0*/
-#define R0900_P1_UPLSTR0  0xf563
-#define F0900_P1_UPL_CURRENT0  0xf56300ff
+#define R0900_P1_UPLSTR0 0xf563
+#define UPLSTR0 REGx(R0900_P1_UPLSTR0)
+#define F0900_P1_UPL_CURRENT0 0xf56300ff
 
 /*P1_DFLSTR1*/
-#define R0900_P1_DFLSTR1  0xf564
-#define F0900_P1_DFL_CURRENT1  0xf56400ff
+#define R0900_P1_DFLSTR1 0xf564
+#define DFLSTR1 REGx(R0900_P1_DFLSTR1)
+#define F0900_P1_DFL_CURRENT1 0xf56400ff
 
 /*P1_DFLSTR0*/
-#define R0900_P1_DFLSTR0  0xf565
-#define F0900_P1_DFL_CURRENT0  0xf56500ff
+#define R0900_P1_DFLSTR0 0xf565
+#define DFLSTR0 REGx(R0900_P1_DFLSTR0)
+#define F0900_P1_DFL_CURRENT0 0xf56500ff
 
 /*P1_SYNCSTR*/
-#define R0900_P1_SYNCSTR  0xf566
-#define F0900_P1_SYNC_CURRENT  0xf56600ff
+#define R0900_P1_SYNCSTR 0xf566
+#define SYNCSTR REGx(R0900_P1_SYNCSTR)
+#define F0900_P1_SYNC_CURRENT 0xf56600ff
 
 /*P1_SYNCDSTR1*/
-#define R0900_P1_SYNCDSTR1  0xf567
-#define F0900_P1_SYNCD_CURRENT1  0xf56700ff
+#define R0900_P1_SYNCDSTR1 0xf567
+#define SYNCDSTR1 REGx(R0900_P1_SYNCDSTR1)
+#define F0900_P1_SYNCD_CURRENT1 0xf56700ff
 
 /*P1_SYNCDSTR0*/
-#define R0900_P1_SYNCDSTR0  0xf568
-#define F0900_P1_SYNCD_CURRENT0  0xf56800ff
+#define R0900_P1_SYNCDSTR0 0xf568
+#define SYNCDSTR0 REGx(R0900_P1_SYNCDSTR0)
+#define F0900_P1_SYNCD_CURRENT0 0xf56800ff
 
 /*P1_PDELSTATUS1*/
-#define R0900_P1_PDELSTATUS1  0xf569
-#define F0900_P1_PKTDELIN_DELOCK  0xf5690080
-#define F0900_P1_SYNCDUPDFL_BADDFL  0xf5690040
-#define F0900_P1_CONTINUOUS_STREAM  0xf5690020
-#define F0900_P1_UNACCEPTED_STREAM  0xf5690010
-#define F0900_P1_BCH_ERROR_FLAG  0xf5690008
-#define F0900_P1_BBHCRCKO  0xf5690004
-#define F0900_P1_PKTDELIN_LOCK  0xf5690002
-#define F0900_P1_FIRST_LOCK  0xf5690001
+#define R0900_P1_PDELSTATUS1 0xf569
+#define F0900_P1_PKTDELIN_DELOCK 0xf5690080
+#define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040
+#define F0900_P1_CONTINUOUS_STREAM 0xf5690020
+#define F0900_P1_UNACCEPTED_STREAM 0xf5690010
+#define F0900_P1_BCH_ERROR_FLAG 0xf5690008
+#define F0900_P1_PKTDELIN_LOCK 0xf5690002
+#define PKTDELIN_LOCK FLDx(F0900_P1_PKTDELIN_LOCK)
+#define F0900_P1_FIRST_LOCK 0xf5690001
 
 /*P1_PDELSTATUS2*/
-#define R0900_P1_PDELSTATUS2  0xf56a
-#define F0900_P1_PKTDEL_DEMODSEL  0xf56a0080
-#define F0900_P1_FRAME_MODCOD  0xf56a007c
-#define F0900_P1_FRAME_TYPE  0xf56a0003
+#define R0900_P1_PDELSTATUS2 0xf56a
+#define F0900_P1_FRAME_MODCOD 0xf56a007c
+#define F0900_P1_FRAME_TYPE 0xf56a0003
 
 /*P1_BBFCRCKO1*/
-#define R0900_P1_BBFCRCKO1  0xf56b
-#define F0900_P1_BBHCRC_KOCNT1  0xf56b00ff
+#define R0900_P1_BBFCRCKO1 0xf56b
+#define BBFCRCKO1 REGx(R0900_P1_BBFCRCKO1)
+#define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff
 
 /*P1_BBFCRCKO0*/
-#define R0900_P1_BBFCRCKO0  0xf56c
-#define F0900_P1_BBHCRC_KOCNT0  0xf56c00ff
+#define R0900_P1_BBFCRCKO0 0xf56c
+#define BBFCRCKO0 REGx(R0900_P1_BBFCRCKO0)
+#define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff
 
 /*P1_UPCRCKO1*/
-#define R0900_P1_UPCRCKO1  0xf56d
-#define F0900_P1_PKTCRC_KOCNT1  0xf56d00ff
+#define R0900_P1_UPCRCKO1 0xf56d
+#define UPCRCKO1 REGx(R0900_P1_UPCRCKO1)
+#define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff
 
 /*P1_UPCRCKO0*/
-#define R0900_P1_UPCRCKO0  0xf56e
-#define F0900_P1_PKTCRC_KOCNT0  0xf56e00ff
+#define R0900_P1_UPCRCKO0 0xf56e
+#define UPCRCKO0 REGx(R0900_P1_UPCRCKO0)
+#define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff
+
+/*P1_PDELCTRL3*/
+#define R0900_P1_PDELCTRL3 0xf56f
+#define PDELCTRL3 REGx(R0900_P1_PDELCTRL3)
+#define F0900_P1_PKTDEL_CONTFAIL 0xf56f0080
+#define F0900_P1_NOFIFO_BCHERR 0xf56f0020
 
 /*P1_TSSTATEM*/
-#define R0900_P1_TSSTATEM  0xf570
-#define F0900_P1_TSDIL_ON  0xf5700080
-#define F0900_P1_TSSKIPRS_ON  0xf5700040
-#define F0900_P1_TSRS_ON  0xf5700020
-#define F0900_P1_TSDESCRAMB_ON  0xf5700010
-#define F0900_P1_TSFRAME_MODE  0xf5700008
-#define F0900_P1_TS_DISABLE  0xf5700004
-#define F0900_P1_TSACM_MODE  0xf5700002
-#define F0900_P1_TSOUT_NOSYNC  0xf5700001
+#define R0900_P1_TSSTATEM 0xf570
+#define TSSTATEM REGx(R0900_P1_TSSTATEM)
+#define F0900_P1_TSDIL_ON 0xf5700080
+#define F0900_P1_TSRS_ON 0xf5700020
+#define F0900_P1_TSDESCRAMB_ON 0xf5700010
+#define F0900_P1_TSFRAME_MODE 0xf5700008
+#define F0900_P1_TS_DISABLE 0xf5700004
+#define F0900_P1_TSOUT_NOSYNC 0xf5700001
 
 /*P1_TSCFGH*/
-#define R0900_P1_TSCFGH  0xf572
-#define F0900_P1_TSFIFO_DVBCI  0xf5720080
-#define F0900_P1_TSFIFO_SERIAL  0xf5720040
-#define F0900_P1_TSFIFO_TEIUPDATE  0xf5720020
-#define F0900_P1_TSFIFO_DUTY50  0xf5720010
-#define F0900_P1_TSFIFO_HSGNLOUT  0xf5720008
-#define F0900_P1_TSFIFO_ERRMODE  0xf5720006
-#define F0900_P1_RST_HWARE  0xf5720001
+#define R0900_P1_TSCFGH 0xf572
+#define TSCFGH REGx(R0900_P1_TSCFGH)
+#define F0900_P1_TSFIFO_DVBCI 0xf5720080
+#define F0900_P1_TSFIFO_SERIAL 0xf5720040
+#define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020
+#define F0900_P1_TSFIFO_DUTY50 0xf5720010
+#define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008
+#define F0900_P1_TSFIFO_ERRMODE 0xf5720006
+#define F0900_P1_RST_HWARE 0xf5720001
+#define RST_HWARE FLDx(F0900_P1_RST_HWARE)
 
 /*P1_TSCFGM*/
-#define R0900_P1_TSCFGM  0xf573
-#define F0900_P1_TSFIFO_MANSPEED  0xf57300c0
-#define F0900_P1_TSFIFO_PERMDATA  0xf5730020
-#define F0900_P1_TSFIFO_NONEWSGNL  0xf5730010
-#define F0900_P1_TSFIFO_BITSPEED  0xf5730008
-#define F0900_P1_NPD_SPECDVBS2  0xf5730004
-#define F0900_P1_TSFIFO_STOPCKDIS  0xf5730002
-#define F0900_P1_TSFIFO_INVDATA  0xf5730001
+#define R0900_P1_TSCFGM 0xf573
+#define TSCFGM REGx(R0900_P1_TSCFGM)
+#define F0900_P1_TSFIFO_MANSPEED 0xf57300c0
+#define F0900_P1_TSFIFO_PERMDATA 0xf5730020
+#define F0900_P1_TSFIFO_DPUNACT 0xf5730002
+#define F0900_P1_TSFIFO_INVDATA 0xf5730001
 
 /*P1_TSCFGL*/
-#define R0900_P1_TSCFGL  0xf574
-#define F0900_P1_TSFIFO_BCLKDEL1CK  0xf57400c0
-#define F0900_P1_BCHERROR_MODE  0xf5740030
-#define F0900_P1_TSFIFO_NSGNL2DATA  0xf5740008
-#define F0900_P1_TSFIFO_EMBINDVB  0xf5740004
-#define F0900_P1_TSFIFO_DPUNACT  0xf5740002
-#define F0900_P1_TSFIFO_NPDOFF  0xf5740001
+#define R0900_P1_TSCFGL 0xf574
+#define TSCFGL REGx(R0900_P1_TSCFGL)
+#define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0
+#define F0900_P1_BCHERROR_MODE 0xf5740030
+#define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008
+#define F0900_P1_TSFIFO_EMBINDVB 0xf5740004
+#define F0900_P1_TSFIFO_BITSPEED 0xf5740003
 
 /*P1_TSINSDELH*/
-#define R0900_P1_TSINSDELH  0xf576
-#define F0900_P1_TSDEL_SYNCBYTE  0xf5760080
-#define F0900_P1_TSDEL_XXHEADER  0xf5760040
-#define F0900_P1_TSDEL_BBHEADER  0xf5760020
-#define F0900_P1_TSDEL_DATAFIELD  0xf5760010
-#define F0900_P1_TSINSDEL_ISCR  0xf5760008
-#define F0900_P1_TSINSDEL_NPD  0xf5760004
-#define F0900_P1_TSINSDEL_RSPARITY  0xf5760002
-#define F0900_P1_TSINSDEL_CRC8  0xf5760001
+#define R0900_P1_TSINSDELH 0xf576
+#define TSINSDELH REGx(R0900_P1_TSINSDELH)
+#define F0900_P1_TSDEL_SYNCBYTE 0xf5760080
+#define F0900_P1_TSDEL_XXHEADER 0xf5760040
+#define F0900_P1_TSDEL_BBHEADER 0xf5760020
+#define F0900_P1_TSDEL_DATAFIELD 0xf5760010
+#define F0900_P1_TSINSDEL_ISCR 0xf5760008
+#define F0900_P1_TSINSDEL_NPD 0xf5760004
+#define F0900_P1_TSINSDEL_RSPARITY 0xf5760002
+#define F0900_P1_TSINSDEL_CRC8 0xf5760001
+
+/*P1_TSDIVN*/
+#define R0900_P1_TSDIVN 0xf579
+#define TSDIVN REGx(R0900_P1_TSDIVN)
+#define F0900_P1_TSFIFO_SPEEDMODE 0xf57900c0
+
+/*P1_TSCFG4*/
+#define R0900_P1_TSCFG4 0xf57a
+#define TSCFG4 REGx(R0900_P1_TSCFG4)
+#define F0900_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0
 
 /*P1_TSSPEED*/
-#define R0900_P1_TSSPEED  0xf580
-#define F0900_P1_TSFIFO_OUTSPEED  0xf58000ff
+#define R0900_P1_TSSPEED 0xf580
+#define TSSPEED REGx(R0900_P1_TSSPEED)
+#define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff
 
 /*P1_TSSTATUS*/
-#define R0900_P1_TSSTATUS  0xf581
-#define F0900_P1_TSFIFO_LINEOK  0xf5810080
-#define F0900_P1_TSFIFO_ERROR  0xf5810040
-#define F0900_P1_TSFIFO_DATA7  0xf5810020
-#define F0900_P1_TSFIFO_NOSYNC  0xf5810010
-#define F0900_P1_ISCR_INITIALIZED  0xf5810008
-#define F0900_P1_ISCR_UPDATED  0xf5810004
-#define F0900_P1_SOFFIFO_UNREGUL  0xf5810002
-#define F0900_P1_DIL_READY  0xf5810001
+#define R0900_P1_TSSTATUS 0xf581
+#define TSSTATUS REGx(R0900_P1_TSSTATUS)
+#define F0900_P1_TSFIFO_LINEOK 0xf5810080
+#define TSFIFO_LINEOK FLDx(F0900_P1_TSFIFO_LINEOK)
+#define F0900_P1_TSFIFO_ERROR 0xf5810040
+#define F0900_P1_DIL_READY 0xf5810001
 
 /*P1_TSSTATUS2*/
-#define R0900_P1_TSSTATUS2  0xf582
-#define F0900_P1_TSFIFO_DEMODSEL  0xf5820080
-#define F0900_P1_TSFIFOSPEED_STORE  0xf5820040
-#define F0900_P1_DILXX_RESET  0xf5820020
-#define F0900_P1_TSSERIAL_IMPOS  0xf5820010
-#define F0900_P1_TSFIFO_LINENOK  0xf5820008
-#define F0900_P1_BITSPEED_EVENT  0xf5820004
-#define F0900_P1_SCRAMBDETECT  0xf5820002
-#define F0900_P1_ULDTV67_FALSELOCK  0xf5820001
+#define R0900_P1_TSSTATUS2 0xf582
+#define TSSTATUS2 REGx(R0900_P1_TSSTATUS2)
+#define F0900_P1_TSFIFO_DEMODSEL 0xf5820080
+#define F0900_P1_TSFIFOSPEED_STORE 0xf5820040
+#define F0900_P1_DILXX_RESET 0xf5820020
+#define F0900_P1_TSSERIAL_IMPOS 0xf5820010
+#define F0900_P1_SCRAMBDETECT 0xf5820002
 
 /*P1_TSBITRATE1*/
-#define R0900_P1_TSBITRATE1  0xf583
-#define F0900_P1_TSFIFO_BITRATE1  0xf58300ff
+#define R0900_P1_TSBITRATE1 0xf583
+#define TSBITRATE1 REGx(R0900_P1_TSBITRATE1)
+#define F0900_P1_TSFIFO_BITRATE1 0xf58300ff
 
 /*P1_TSBITRATE0*/
-#define R0900_P1_TSBITRATE0  0xf584
-#define F0900_P1_TSFIFO_BITRATE0  0xf58400ff
+#define R0900_P1_TSBITRATE0 0xf584
+#define TSBITRATE0 REGx(R0900_P1_TSBITRATE0)
+#define F0900_P1_TSFIFO_BITRATE0 0xf58400ff
 
 /*P1_ERRCTRL1*/
-#define R0900_P1_ERRCTRL1  0xf598
-#define F0900_P1_ERR_SOURCE1  0xf59800f0
-#define F0900_P1_NUM_EVENT1  0xf5980007
+#define R0900_P1_ERRCTRL1 0xf598
+#define ERRCTRL1 REGx(R0900_P1_ERRCTRL1)
+#define F0900_P1_ERR_SOURCE1 0xf59800f0
+#define F0900_P1_NUM_EVENT1 0xf5980007
 
 /*P1_ERRCNT12*/
-#define R0900_P1_ERRCNT12  0xf599
-#define F0900_P1_ERRCNT1_OLDVALUE  0xf5990080
-#define F0900_P1_ERR_CNT12  0xf599007f
+#define R0900_P1_ERRCNT12 0xf599
+#define ERRCNT12 REGx(R0900_P1_ERRCNT12)
+#define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080
+#define F0900_P1_ERR_CNT12 0xf599007f
+#define ERR_CNT12 FLDx(F0900_P1_ERR_CNT12)
 
 /*P1_ERRCNT11*/
-#define R0900_P1_ERRCNT11  0xf59a
-#define F0900_P1_ERR_CNT11  0xf59a00ff
+#define R0900_P1_ERRCNT11 0xf59a
+#define ERRCNT11 REGx(R0900_P1_ERRCNT11)
+#define F0900_P1_ERR_CNT11 0xf59a00ff
+#define ERR_CNT11 FLDx(F0900_P1_ERR_CNT11)
 
 /*P1_ERRCNT10*/
-#define R0900_P1_ERRCNT10  0xf59b
-#define F0900_P1_ERR_CNT10  0xf59b00ff
+#define R0900_P1_ERRCNT10 0xf59b
+#define ERRCNT10 REGx(R0900_P1_ERRCNT10)
+#define F0900_P1_ERR_CNT10 0xf59b00ff
+#define ERR_CNT10 FLDx(F0900_P1_ERR_CNT10)
 
 /*P1_ERRCTRL2*/
-#define R0900_P1_ERRCTRL2  0xf59c
-#define F0900_P1_ERR_SOURCE2  0xf59c00f0
-#define F0900_P1_NUM_EVENT2  0xf59c0007
+#define R0900_P1_ERRCTRL2 0xf59c
+#define ERRCTRL2 REGx(R0900_P1_ERRCTRL2)
+#define F0900_P1_ERR_SOURCE2 0xf59c00f0
+#define F0900_P1_NUM_EVENT2 0xf59c0007
 
 /*P1_ERRCNT22*/
-#define R0900_P1_ERRCNT22  0xf59d
-#define F0900_P1_ERRCNT2_OLDVALUE  0xf59d0080
-#define F0900_P1_ERR_CNT22  0xf59d007f
+#define R0900_P1_ERRCNT22 0xf59d
+#define ERRCNT22 REGx(R0900_P1_ERRCNT22)
+#define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080
+#define F0900_P1_ERR_CNT22 0xf59d007f
+#define ERR_CNT22 FLDx(F0900_P1_ERR_CNT22)
 
 /*P1_ERRCNT21*/
-#define R0900_P1_ERRCNT21  0xf59e
-#define F0900_P1_ERR_CNT21  0xf59e00ff
+#define R0900_P1_ERRCNT21 0xf59e
+#define ERRCNT21 REGx(R0900_P1_ERRCNT21)
+#define F0900_P1_ERR_CNT21 0xf59e00ff
+#define ERR_CNT21 FLDx(F0900_P1_ERR_CNT21)
 
 /*P1_ERRCNT20*/
-#define R0900_P1_ERRCNT20  0xf59f
-#define F0900_P1_ERR_CNT20  0xf59f00ff
+#define R0900_P1_ERRCNT20 0xf59f
+#define ERRCNT20 REGx(R0900_P1_ERRCNT20)
+#define F0900_P1_ERR_CNT20 0xf59f00ff
+#define ERR_CNT20 FLDx(F0900_P1_ERR_CNT20)
 
 /*P1_FECSPY*/
-#define R0900_P1_FECSPY  0xf5a0
-#define F0900_P1_SPY_ENABLE  0xf5a00080
-#define F0900_P1_NO_SYNCBYTE  0xf5a00040
-#define F0900_P1_SERIAL_MODE  0xf5a00020
-#define F0900_P1_UNUSUAL_PACKET  0xf5a00010
-#define F0900_P1_BER_PACKMODE  0xf5a00008
-#define F0900_P1_BERMETER_LMODE  0xf5a00002
-#define F0900_P1_BERMETER_RESET  0xf5a00001
+#define R0900_P1_FECSPY 0xf5a0
+#define FECSPY REGx(R0900_P1_FECSPY)
+#define F0900_P1_SPY_ENABLE 0xf5a00080
+#define F0900_P1_NO_SYNCBYTE 0xf5a00040
+#define F0900_P1_SERIAL_MODE 0xf5a00020
+#define F0900_P1_UNUSUAL_PACKET 0xf5a00010
+#define F0900_P1_BERMETER_DATAMODE 0xf5a00008
+#define F0900_P1_BERMETER_LMODE 0xf5a00002
+#define F0900_P1_BERMETER_RESET 0xf5a00001
 
 /*P1_FSPYCFG*/
-#define R0900_P1_FSPYCFG  0xf5a1
-#define F0900_P1_FECSPY_INPUT  0xf5a100c0
-#define F0900_P1_RST_ON_ERROR  0xf5a10020
-#define F0900_P1_ONE_SHOT  0xf5a10010
-#define F0900_P1_I2C_MODE  0xf5a1000c
-#define F0900_P1_SPY_HYSTERESIS  0xf5a10003
+#define R0900_P1_FSPYCFG 0xf5a1
+#define FSPYCFG REGx(R0900_P1_FSPYCFG)
+#define F0900_P1_FECSPY_INPUT 0xf5a100c0
+#define F0900_P1_RST_ON_ERROR 0xf5a10020
+#define F0900_P1_ONE_SHOT 0xf5a10010
+#define F0900_P1_I2C_MODE 0xf5a1000c
+#define F0900_P1_SPY_HYSTERESIS 0xf5a10003
 
 /*P1_FSPYDATA*/
-#define R0900_P1_FSPYDATA  0xf5a2
-#define F0900_P1_SPY_STUFFING  0xf5a20080
-#define F0900_P1_NOERROR_PKTJITTER  0xf5a20040
-#define F0900_P1_SPY_CNULLPKT  0xf5a20020
-#define F0900_P1_SPY_OUTDATA_MODE  0xf5a2001f
+#define R0900_P1_FSPYDATA 0xf5a2
+#define FSPYDATA REGx(R0900_P1_FSPYDATA)
+#define F0900_P1_SPY_STUFFING 0xf5a20080
+#define F0900_P1_SPY_CNULLPKT 0xf5a20020
+#define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f
 
 /*P1_FSPYOUT*/
-#define R0900_P1_FSPYOUT  0xf5a3
-#define F0900_P1_FSPY_DIRECT  0xf5a30080
-#define F0900_P1_SPY_OUTDATA_BUS  0xf5a30038
-#define F0900_P1_STUFF_MODE  0xf5a30007
+#define R0900_P1_FSPYOUT 0xf5a3
+#define FSPYOUT REGx(R0900_P1_FSPYOUT)
+#define F0900_P1_FSPY_DIRECT 0xf5a30080
+#define F0900_P1_STUFF_MODE 0xf5a30007
 
 /*P1_FSTATUS*/
-#define R0900_P1_FSTATUS  0xf5a4
-#define F0900_P1_SPY_ENDSIM  0xf5a40080
-#define F0900_P1_VALID_SIM  0xf5a40040
-#define F0900_P1_FOUND_SIGNAL  0xf5a40020
-#define F0900_P1_DSS_SYNCBYTE  0xf5a40010
-#define F0900_P1_RESULT_STATE  0xf5a4000f
+#define R0900_P1_FSTATUS 0xf5a4
+#define FSTATUS REGx(R0900_P1_FSTATUS)
+#define F0900_P1_SPY_ENDSIM 0xf5a40080
+#define F0900_P1_VALID_SIM 0xf5a40040
+#define F0900_P1_FOUND_SIGNAL 0xf5a40020
+#define F0900_P1_DSS_SYNCBYTE 0xf5a40010
+#define F0900_P1_RESULT_STATE 0xf5a4000f
 
 /*P1_FBERCPT4*/
-#define R0900_P1_FBERCPT4  0xf5a8
-#define F0900_P1_FBERMETER_CPT4  0xf5a800ff
+#define R0900_P1_FBERCPT4 0xf5a8
+#define FBERCPT4 REGx(R0900_P1_FBERCPT4)
+#define F0900_P1_FBERMETER_CPT4 0xf5a800ff
 
 /*P1_FBERCPT3*/
-#define R0900_P1_FBERCPT3  0xf5a9
-#define F0900_P1_FBERMETER_CPT3  0xf5a900ff
+#define R0900_P1_FBERCPT3 0xf5a9
+#define FBERCPT3 REGx(R0900_P1_FBERCPT3)
+#define F0900_P1_FBERMETER_CPT3 0xf5a900ff
 
 /*P1_FBERCPT2*/
-#define R0900_P1_FBERCPT2  0xf5aa
-#define F0900_P1_FBERMETER_CPT2  0xf5aa00ff
+#define R0900_P1_FBERCPT2 0xf5aa
+#define FBERCPT2 REGx(R0900_P1_FBERCPT2)
+#define F0900_P1_FBERMETER_CPT2 0xf5aa00ff
 
 /*P1_FBERCPT1*/
-#define R0900_P1_FBERCPT1  0xf5ab
-#define F0900_P1_FBERMETER_CPT1  0xf5ab00ff
+#define R0900_P1_FBERCPT1 0xf5ab
+#define FBERCPT1 REGx(R0900_P1_FBERCPT1)
+#define F0900_P1_FBERMETER_CPT1 0xf5ab00ff
 
 /*P1_FBERCPT0*/
-#define R0900_P1_FBERCPT0  0xf5ac
-#define F0900_P1_FBERMETER_CPT0  0xf5ac00ff
+#define R0900_P1_FBERCPT0 0xf5ac
+#define FBERCPT0 REGx(R0900_P1_FBERCPT0)
+#define F0900_P1_FBERMETER_CPT0 0xf5ac00ff
 
 /*P1_FBERERR2*/
-#define R0900_P1_FBERERR2  0xf5ad
-#define F0900_P1_FBERMETER_ERR2  0xf5ad00ff
+#define R0900_P1_FBERERR2 0xf5ad
+#define FBERERR2 REGx(R0900_P1_FBERERR2)
+#define F0900_P1_FBERMETER_ERR2 0xf5ad00ff
 
 /*P1_FBERERR1*/
-#define R0900_P1_FBERERR1  0xf5ae
-#define F0900_P1_FBERMETER_ERR1  0xf5ae00ff
+#define R0900_P1_FBERERR1 0xf5ae
+#define FBERERR1 REGx(R0900_P1_FBERERR1)
+#define F0900_P1_FBERMETER_ERR1 0xf5ae00ff
 
 /*P1_FBERERR0*/
-#define R0900_P1_FBERERR0  0xf5af
-#define F0900_P1_FBERMETER_ERR0  0xf5af00ff
+#define R0900_P1_FBERERR0 0xf5af
+#define FBERERR0 REGx(R0900_P1_FBERERR0)
+#define F0900_P1_FBERMETER_ERR0 0xf5af00ff
 
 /*P1_FSPYBER*/
-#define R0900_P1_FSPYBER  0xf5b2
-#define F0900_P1_FSPYOBS_XORREAD  0xf5b20040
-#define F0900_P1_FSPYBER_OBSMODE  0xf5b20020
-#define F0900_P1_FSPYBER_SYNCBYTE  0xf5b20010
-#define F0900_P1_FSPYBER_UNSYNC  0xf5b20008
-#define F0900_P1_FSPYBER_CTIME  0xf5b20007
-
-/*RCCFGH*/
-#define R0900_RCCFGH  0xf600
-#define F0900_TSRCFIFO_DVBCI  0xf6000080
-#define F0900_TSRCFIFO_SERIAL  0xf6000040
-#define F0900_TSRCFIFO_DISABLE  0xf6000020
-#define F0900_TSFIFO_2TORC  0xf6000010
-#define F0900_TSRCFIFO_HSGNLOUT  0xf6000008
-#define F0900_TSRCFIFO_ERRMODE  0xf6000006
+#define R0900_P1_FSPYBER 0xf5b2
+#define FSPYBER REGx(R0900_P1_FSPYBER)
+#define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010
+#define F0900_P1_FSPYBER_UNSYNC 0xf5b20008
+#define F0900_P1_FSPYBER_CTIME 0xf5b20007
+
+/*RCCFG2*/
+#define R0900_RCCFG2 0xf600
 
 /*TSGENERAL*/
-#define R0900_TSGENERAL  0xf630
-#define F0900_TSFIFO_BCLK1ALL  0xf6300020
-#define F0900_MUXSTREAM_OUTMODE  0xf6300008
-#define F0900_TSFIFO_PERMPARAL  0xf6300006
-#define F0900_RST_REEDSOLO  0xf6300001
+#define R0900_TSGENERAL 0xf630
+#define F0900_TSFIFO_DISTS2PAR 0xf6300040
+#define F0900_MUXSTREAM_OUTMODE 0xf6300008
+#define F0900_TSFIFO_PERMPARAL 0xf6300006
 
 /*TSGENERAL1X*/
-#define R0900_TSGENERAL1X  0xf670
-#define F0900_TSFIFO1X_BCLK1ALL  0xf6700020
-#define F0900_MUXSTREAM1X_OUTMODE  0xf6700008
-#define F0900_TSFIFO1X_PERMPARAL  0xf6700006
-#define F0900_RST1X_REEDSOLO  0xf6700001
+#define R0900_TSGENERAL1X 0xf670
 
 /*NBITER_NF4*/
-#define R0900_NBITER_NF4  0xfa03
-#define F0900_NBITER_NF_QP_1_2  0xfa0300ff
+#define R0900_NBITER_NF4 0xfa03
+#define F0900_NBITER_NF_QP_1_2 0xfa0300ff
 
 /*NBITER_NF5*/
-#define R0900_NBITER_NF5  0xfa04
-#define F0900_NBITER_NF_QP_3_5  0xfa0400ff
+#define R0900_NBITER_NF5 0xfa04
+#define F0900_NBITER_NF_QP_3_5 0xfa0400ff
 
 /*NBITER_NF6*/
-#define R0900_NBITER_NF6  0xfa05
-#define F0900_NBITER_NF_QP_2_3  0xfa0500ff
+#define R0900_NBITER_NF6 0xfa05
+#define F0900_NBITER_NF_QP_2_3 0xfa0500ff
 
 /*NBITER_NF7*/
-#define R0900_NBITER_NF7  0xfa06
-#define F0900_NBITER_NF_QP_3_4  0xfa0600ff
+#define R0900_NBITER_NF7 0xfa06
+#define F0900_NBITER_NF_QP_3_4 0xfa0600ff
 
 /*NBITER_NF8*/
-#define R0900_NBITER_NF8  0xfa07
-#define F0900_NBITER_NF_QP_4_5  0xfa0700ff
+#define R0900_NBITER_NF8 0xfa07
+#define F0900_NBITER_NF_QP_4_5 0xfa0700ff
 
 /*NBITER_NF9*/
-#define R0900_NBITER_NF9  0xfa08
-#define F0900_NBITER_NF_QP_5_6  0xfa0800ff
+#define R0900_NBITER_NF9 0xfa08
+#define F0900_NBITER_NF_QP_5_6 0xfa0800ff
 
 /*NBITER_NF10*/
-#define R0900_NBITER_NF10  0xfa09
-#define F0900_NBITER_NF_QP_8_9  0xfa0900ff
+#define R0900_NBITER_NF10 0xfa09
+#define F0900_NBITER_NF_QP_8_9 0xfa0900ff
 
 /*NBITER_NF11*/
-#define R0900_NBITER_NF11  0xfa0a
-#define F0900_NBITER_NF_QP_9_10  0xfa0a00ff
+#define R0900_NBITER_NF11 0xfa0a
+#define F0900_NBITER_NF_QP_9_10 0xfa0a00ff
 
 /*NBITER_NF12*/
-#define R0900_NBITER_NF12  0xfa0b
-#define F0900_NBITER_NF_8P_3_5  0xfa0b00ff
+#define R0900_NBITER_NF12 0xfa0b
+#define F0900_NBITER_NF_8P_3_5 0xfa0b00ff
 
 /*NBITER_NF13*/
-#define R0900_NBITER_NF13  0xfa0c
-#define F0900_NBITER_NF_8P_2_3  0xfa0c00ff
+#define R0900_NBITER_NF13 0xfa0c
+#define F0900_NBITER_NF_8P_2_3 0xfa0c00ff
 
 /*NBITER_NF14*/
-#define R0900_NBITER_NF14  0xfa0d
-#define F0900_NBITER_NF_8P_3_4  0xfa0d00ff
+#define R0900_NBITER_NF14 0xfa0d
+#define F0900_NBITER_NF_8P_3_4 0xfa0d00ff
 
 /*NBITER_NF15*/
-#define R0900_NBITER_NF15  0xfa0e
-#define F0900_NBITER_NF_8P_5_6  0xfa0e00ff
+#define R0900_NBITER_NF15 0xfa0e
+#define F0900_NBITER_NF_8P_5_6 0xfa0e00ff
 
 /*NBITER_NF16*/
-#define R0900_NBITER_NF16  0xfa0f
-#define F0900_NBITER_NF_8P_8_9  0xfa0f00ff
+#define R0900_NBITER_NF16 0xfa0f
+#define F0900_NBITER_NF_8P_8_9 0xfa0f00ff
 
 /*NBITER_NF17*/
-#define R0900_NBITER_NF17  0xfa10
-#define F0900_NBITER_NF_8P_9_10  0xfa1000ff
+#define R0900_NBITER_NF17 0xfa10
+#define F0900_NBITER_NF_8P_9_10 0xfa1000ff
 
 /*NBITERNOERR*/
-#define R0900_NBITERNOERR  0xfa3f
-#define F0900_NBITER_STOP_CRIT  0xfa3f000f
+#define R0900_NBITERNOERR 0xfa3f
+#define F0900_NBITER_STOP_CRIT 0xfa3f000f
 
 /*GAINLLR_NF4*/
-#define R0900_GAINLLR_NF4  0xfa43
-#define F0900_GAINLLR_NF_QP_1_2  0xfa43007f
+#define R0900_GAINLLR_NF4 0xfa43
+#define F0900_GAINLLR_NF_QP_1_2 0xfa43007f
 
 /*GAINLLR_NF5*/
-#define R0900_GAINLLR_NF5  0xfa44
-#define F0900_GAINLLR_NF_QP_3_5  0xfa44007f
+#define R0900_GAINLLR_NF5 0xfa44
+#define F0900_GAINLLR_NF_QP_3_5 0xfa44007f
 
 /*GAINLLR_NF6*/
-#define R0900_GAINLLR_NF6  0xfa45
-#define F0900_GAINLLR_NF_QP_2_3  0xfa45007f
+#define R0900_GAINLLR_NF6 0xfa45
+#define F0900_GAINLLR_NF_QP_2_3 0xfa45007f
 
 /*GAINLLR_NF7*/
-#define R0900_GAINLLR_NF7  0xfa46
-#define F0900_GAINLLR_NF_QP_3_4  0xfa46007f
+#define R0900_GAINLLR_NF7 0xfa46
+#define F0900_GAINLLR_NF_QP_3_4 0xfa46007f
 
 /*GAINLLR_NF8*/
-#define R0900_GAINLLR_NF8  0xfa47
-#define F0900_GAINLLR_NF_QP_4_5  0xfa47007f
+#define R0900_GAINLLR_NF8 0xfa47
+#define F0900_GAINLLR_NF_QP_4_5 0xfa47007f
 
 /*GAINLLR_NF9*/
-#define R0900_GAINLLR_NF9  0xfa48
-#define F0900_GAINLLR_NF_QP_5_6  0xfa48007f
+#define R0900_GAINLLR_NF9 0xfa48
+#define F0900_GAINLLR_NF_QP_5_6 0xfa48007f
 
 /*GAINLLR_NF10*/
-#define R0900_GAINLLR_NF10  0xfa49
-#define F0900_GAINLLR_NF_QP_8_9  0xfa49007f
+#define R0900_GAINLLR_NF10 0xfa49
+#define F0900_GAINLLR_NF_QP_8_9 0xfa49007f
 
 /*GAINLLR_NF11*/
-#define R0900_GAINLLR_NF11  0xfa4a
-#define F0900_GAINLLR_NF_QP_9_10  0xfa4a007f
+#define R0900_GAINLLR_NF11 0xfa4a
+#define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f
 
 /*GAINLLR_NF12*/
-#define R0900_GAINLLR_NF12  0xfa4b
-#define F0900_GAINLLR_NF_8P_3_5  0xfa4b007f
+#define R0900_GAINLLR_NF12 0xfa4b
+#define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f
 
 /*GAINLLR_NF13*/
-#define R0900_GAINLLR_NF13  0xfa4c
-#define F0900_GAINLLR_NF_8P_2_3  0xfa4c007f
+#define R0900_GAINLLR_NF13 0xfa4c
+#define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f
 
 /*GAINLLR_NF14*/
-#define R0900_GAINLLR_NF14  0xfa4d
-#define F0900_GAINLLR_NF_8P_3_4  0xfa4d007f
+#define R0900_GAINLLR_NF14 0xfa4d
+#define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f
 
 /*GAINLLR_NF15*/
-#define R0900_GAINLLR_NF15  0xfa4e
-#define F0900_GAINLLR_NF_8P_5_6  0xfa4e007f
+#define R0900_GAINLLR_NF15 0xfa4e
+#define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f
 
 /*GAINLLR_NF16*/
-#define R0900_GAINLLR_NF16  0xfa4f
-#define F0900_GAINLLR_NF_8P_8_9  0xfa4f007f
+#define R0900_GAINLLR_NF16 0xfa4f
+#define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f
 
 /*GAINLLR_NF17*/
-#define R0900_GAINLLR_NF17  0xfa50
-#define F0900_GAINLLR_NF_8P_9_10  0xfa50007f
+#define R0900_GAINLLR_NF17 0xfa50
+#define F0900_GAINLLR_NF_8P_9_10 0xfa50007f
 
 /*CFGEXT*/
-#define R0900_CFGEXT  0xfa80
-#define F0900_STAGMODE  0xfa800080
-#define F0900_BYPBCH  0xfa800040
-#define F0900_BYPLDPC  0xfa800020
-#define F0900_LDPCMODE  0xfa800010
-#define F0900_INVLLRSIGN  0xfa800008
-#define F0900_SHORTMULT  0xfa800004
-#define F0900_EXTERNTX  0xfa800001
+#define R0900_CFGEXT 0xfa80
+#define F0900_STAGMODE 0xfa800080
+#define F0900_BYPBCH 0xfa800040
+#define F0900_BYPLDPC 0xfa800020
+#define F0900_LDPCMODE 0xfa800010
+#define F0900_INVLLRSIGN 0xfa800008
+#define F0900_SHORTMULT 0xfa800004
+#define F0900_EXTERNTX 0xfa800001
 
 /*GENCFG*/
-#define R0900_GENCFG  0xfa86
-#define F0900_BROADCAST  0xfa860010
-#define F0900_NOSHFRD2  0xfa860008
-#define F0900_BCHERRFLAG  0xfa860004
-#define F0900_PRIORITY  0xfa860002
-#define F0900_DDEMOD  0xfa860001
+#define R0900_GENCFG 0xfa86
+#define F0900_BROADCAST 0xfa860010
+#define F0900_PRIORITY 0xfa860002
+#define F0900_DDEMOD 0xfa860001
 
 /*LDPCERR1*/
-#define R0900_LDPCERR1  0xfa96
-#define F0900_LDPC_ERRORS_COUNTER1  0xfa9600ff
+#define R0900_LDPCERR1 0xfa96
+#define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff
 
 /*LDPCERR0*/
-#define R0900_LDPCERR0  0xfa97
-#define F0900_LDPC_ERRORS_COUNTER0  0xfa9700ff
+#define R0900_LDPCERR0 0xfa97
+#define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff
 
 /*BCHERR*/
-#define R0900_BCHERR  0xfa98
-#define F0900_ERRORFLAG  0xfa980010
-#define F0900_BCH_ERRORS_COUNTER  0xfa98000f
+#define R0900_BCHERR 0xfa98
+#define F0900_ERRORFLAG 0xfa980010
+#define F0900_BCH_ERRORS_COUNTER 0xfa98000f
 
 /*TSTRES0*/
-#define R0900_TSTRES0  0xff11
-#define F0900_FRESFEC  0xff110080
-#define F0900_FRESTS  0xff110040
-#define F0900_FRESVIT1  0xff110020
-#define F0900_FRESVIT2  0xff110010
-#define F0900_FRESSYM1  0xff110008
-#define F0900_FRESSYM2  0xff110004
-#define F0900_FRESMAS  0xff110002
-#define F0900_FRESINT  0xff110001
+#define R0900_TSTRES0 0xff11
+#define F0900_FRESFEC 0xff110080
+
+/*P2_TCTL4*/
+#define R0900_P2_TCTL4 0xff28
+#define F0900_P2_PN4_SELECT 0xff280020
+
+/*P1_TCTL4*/
+#define R0900_P1_TCTL4 0xff48
+#define TCTL4 shiftx(R0900_P1_TCTL4, demod, 0x20)
+#define F0900_P1_PN4_SELECT 0xff480020
 
 /*P2_TSTDISRX*/
-#define R0900_P2_TSTDISRX  0xff65
-#define F0900_P2_EN_DISRX  0xff650080
-#define F0900_P2_TST_CURRSRC  0xff650040
-#define F0900_P2_IN_DIGSIGNAL  0xff650020
-#define F0900_P2_HIZ_CURRENTSRC  0xff650010
-#define F0900_TST_P2_PIN_SELECT  0xff650008
-#define F0900_P2_TST_DISRX  0xff650007
+#define R0900_P2_TSTDISRX 0xff65
+#define F0900_P2_PIN_SELECT1 0xff650008
 
 /*P1_TSTDISRX*/
-#define R0900_P1_TSTDISRX  0xff67
-#define F0900_P1_EN_DISRX  0xff670080
-#define F0900_P1_TST_CURRSRC  0xff670040
-#define F0900_P1_IN_DIGSIGNAL  0xff670020
-#define F0900_P1_HIZ_CURRENTSRC  0xff670010
-#define F0900_TST_P1_PIN_SELECT  0xff670008
-#define F0900_P1_TST_DISRX  0xff670007
-
-#define STV0900_NBREGS          684
-#define STV0900_NBFIELDS                1702
+#define R0900_P1_TSTDISRX 0xff67
+#define TSTDISRX shiftx(R0900_P1_TSTDISRX, demod, 2)
+#define F0900_P1_PIN_SELECT1 0xff670008
+#define PIN_SELECT1 shiftx(F0900_P1_PIN_SELECT1, demod, 0x20000)
+
+#define STV0900_NBREGS 723
+#define STV0900_NBFIELDS 1420
 
 #endif
 
diff --git a/drivers/media/dvb/frontends/stv0900_sw.c b/drivers/media/dvb/frontends/stv0900_sw.c
index 962fde1437ce..ba0709b2d433 100644
--- a/drivers/media/dvb/frontends/stv0900_sw.c
+++ b/drivers/media/dvb/frontends/stv0900_sw.c
@@ -27,56 +27,45 @@
 #include "stv0900_reg.h"
 #include "stv0900_priv.h"
 
-int stv0900_check_signal_presence(struct stv0900_internal *i_params,
+s32 shiftx(s32 x, int demod, s32 shift)
+{
+        if (demod == 1)
+                return x - shift;
+
+        return x;
+}
+
+int stv0900_check_signal_presence(struct stv0900_internal *intp,
                                         enum fe_stv0900_demod_num demod)
 {
-        s32 carr_offset,
-        agc2_integr,
-        max_carrier;
+        s32     carr_offset,
+                agc2_integr,
+                max_carrier;
 
-        int no_signal;
+        int no_signal = FALSE;
 
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                carr_offset = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8)
-                                                | stv0900_read_reg(i_params,
-                                                R0900_P1_CFR1);
-                carr_offset = ge2comp(carr_offset, 16);
-                agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
-                                                | stv0900_read_reg(i_params,
-                                                R0900_P1_AGC2I0);
-                max_carrier = i_params->dmd1_srch_range / 1000;
-                break;
-        case STV0900_DEMOD_2:
-                carr_offset = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8)
-                                                | stv0900_read_reg(i_params,
-                                                R0900_P2_CFR1);
-                carr_offset = ge2comp(carr_offset, 16);
-                agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
-                                                | stv0900_read_reg(i_params,
-                                                R0900_P2_AGC2I0);
-                max_carrier = i_params->dmd2_srch_range / 1000;
-                break;
-        }
+        carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
+                                        | stv0900_read_reg(intp, CFR1);
+        carr_offset = ge2comp(carr_offset, 16);
+        agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
+                                        | stv0900_read_reg(intp, AGC2I0);
+        max_carrier = intp->srch_range[demod] / 1000;
 
         max_carrier += (max_carrier / 10);
         max_carrier = 65536 * (max_carrier / 2);
-        max_carrier /= i_params->mclk / 1000;
+        max_carrier /= intp->mclk / 1000;
         if (max_carrier > 0x4000)
                 max_carrier = 0x4000;
 
         if ((agc2_integr > 0x2000)
-                        || (carr_offset > + 2*max_carrier)
-                        || (carr_offset < -2*max_carrier))
+                        || (carr_offset > (2 * max_carrier))
+                        || (carr_offset < (-2 * max_carrier)))
                 no_signal = TRUE;
-        else
-                no_signal = FALSE;
 
         return no_signal;
 }
 
-static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
+static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
                                 s32 *frequency_inc, s32 *sw_timeout,
                                 s32 *steps,
                                 enum fe_stv0900_demod_num demod)
@@ -85,30 +74,19 @@ static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
 
         enum fe_stv0900_search_standard standard;
 
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                srate = i_params->dmd1_symbol_rate;
-                max_carrier = i_params->dmd1_srch_range / 1000;
-                max_carrier += max_carrier / 10;
-                standard = i_params->dmd1_srch_standard;
-                break;
-        case STV0900_DEMOD_2:
-                srate = i_params->dmd2_symbol_rate;
-                max_carrier = i_params->dmd2_srch_range / 1000;
-                max_carrier += max_carrier / 10;
-                standard = i_params->dmd2_srch_stndrd;
-                break;
-        }
+        srate = intp->symbol_rate[demod];
+        max_carrier = intp->srch_range[demod] / 1000;
+        max_carrier += max_carrier / 10;
+        standard = intp->srch_standard[demod];
 
         max_carrier = 65536 * (max_carrier / 2);
-        max_carrier /= i_params->mclk / 1000;
+        max_carrier /= intp->mclk / 1000;
 
         if (max_carrier > 0x4000)
                 max_carrier = 0x4000;
 
         freq_inc = srate;
-        freq_inc /= i_params->mclk >> 10;
+        freq_inc /= intp->mclk >> 10;
         freq_inc = freq_inc << 6;
 
         switch (standard) {
@@ -154,7 +132,7 @@ static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
 
 }
 
-static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
+static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
                                 s32 FreqIncr, s32 Timeout, int zigzag,
                                 s32 MaxStep, enum fe_stv0900_demod_num demod)
 {
@@ -164,20 +142,11 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
                 freqOffset,
                 max_carrier;
 
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                max_carrier = i_params->dmd1_srch_range / 1000;
-                max_carrier += (max_carrier / 10);
-                break;
-        case STV0900_DEMOD_2:
-                max_carrier = i_params->dmd2_srch_range / 1000;
-                max_carrier += (max_carrier / 10);
-                break;
-        }
+        max_carrier = intp->srch_range[demod] / 1000;
+        max_carrier += (max_carrier / 10);
 
         max_carrier = 65536 * (max_carrier / 2);
-        max_carrier /= i_params->mclk / 1000;
+        max_carrier /= intp->mclk / 1000;
 
         if (max_carrier > 0x4000)
                 max_carrier = 0x4000;
@@ -190,40 +159,15 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
         stepCpt = 0;
 
         do {
-                switch (demod) {
-                case STV0900_DEMOD_1:
-                default:
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
-                        stv0900_write_reg(i_params, R0900_P1_CFRINIT1,
-                                        (freqOffset / 256) & 0xFF);
-                        stv0900_write_reg(i_params, R0900_P1_CFRINIT0,
-                                         freqOffset & 0xFF);
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
-                        stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
-
-                        if (i_params->chip_id == 0x12) {
-                                stv0900_write_bits(i_params,
-                                                F0900_P1_RST_HWARE, 1);
-                                stv0900_write_bits(i_params,
-                                                F0900_P1_RST_HWARE, 0);
-                        }
-                        break;
-                case STV0900_DEMOD_2:
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
-                        stv0900_write_reg(i_params, R0900_P2_CFRINIT1,
-                                        (freqOffset / 256) & 0xFF);
-                        stv0900_write_reg(i_params, R0900_P2_CFRINIT0,
-                                        freqOffset & 0xFF);
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
-                        stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
-
-                        if (i_params->chip_id == 0x12) {
-                                stv0900_write_bits(i_params,
-                                                F0900_P2_RST_HWARE, 1);
-                                stv0900_write_bits(i_params,
-                                                F0900_P2_RST_HWARE, 0);
-                        }
-                        break;
+                stv0900_write_reg(intp, DMDISTATE, 0x1c);
+                stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
+                stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
+                stv0900_write_reg(intp, DMDISTATE, 0x18);
+                stv0900_write_bits(intp, ALGOSWRST, 1);
+
+                if (intp->chip_id == 0x12) {
+                        stv0900_write_bits(intp, RST_HWARE, 1);
+                        stv0900_write_bits(intp, RST_HWARE, 0);
                 }
 
                 if (zigzag == TRUE) {
@@ -235,8 +179,8 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
                         freqOffset += + 2 * FreqIncr;
 
                 stepCpt++;
-                lock = stv0900_get_demod_lock(i_params, demod, Timeout);
-                no_signal = stv0900_check_signal_presence(i_params, demod);
+                lock = stv0900_get_demod_lock(intp, demod, Timeout);
+                no_signal = stv0900_check_signal_presence(intp, demod);
 
         } while ((lock == FALSE)
                         && (no_signal == FALSE)
@@ -244,269 +188,138 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
                         && ((freqOffset + FreqIncr) > -max_carrier)
                         && (stepCpt < MaxStep));
 
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
-                break;
-        case STV0900_DEMOD_2:
-                stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
-                break;
-        }
+        stv0900_write_bits(intp, ALGOSWRST, 0);
 
         return lock;
 }
 
-int stv0900_sw_algo(struct stv0900_internal *i_params,
+static int stv0900_sw_algo(struct stv0900_internal *intp,
                                 enum fe_stv0900_demod_num demod)
 {
-        int lock = FALSE;
-
-        int no_signal,
-        zigzag;
-        s32 dvbs2_fly_wheel;
-
-        s32 freqIncrement, softStepTimeout, trialCounter, max_steps;
-
-        stv0900_get_sw_loop_params(i_params, &freqIncrement, &softStepTimeout,
+        int     lock = FALSE,
+                no_signal,
+                zigzag;
+        s32     s2fw,
+                fqc_inc,
+                sft_stp_tout,
+                trial_cntr,
+                max_steps;
+
+        stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
                                         &max_steps, demod);
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                switch (i_params->dmd1_srch_standard) {
-                case STV0900_SEARCH_DVBS1:
-                case STV0900_SEARCH_DSS:
-                        if (i_params->chip_id >= 0x20)
-                                stv0900_write_reg(i_params, R0900_P1_CARFREQ,
-                                                0x3B);
-                        else
-                                stv0900_write_reg(i_params, R0900_P1_CARFREQ,
-                                                0xef);
-
-                        stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x49);
-                        zigzag = FALSE;
-                        break;
-                case STV0900_SEARCH_DVBS2:
-                        if (i_params->chip_id >= 0x20)
-                                stv0900_write_reg(i_params, R0900_P1_CORRELABS,
-                                                0x79);
-                        else
-                                stv0900_write_reg(i_params, R0900_P1_CORRELABS,
-                                                0x68);
+        switch (intp->srch_standard[demod]) {
+        case STV0900_SEARCH_DVBS1:
+        case STV0900_SEARCH_DSS:
+                if (intp->chip_id >= 0x20)
+                        stv0900_write_reg(intp, CARFREQ, 0x3b);
+                else
+                        stv0900_write_reg(intp, CARFREQ, 0xef);
 
-                        stv0900_write_reg(i_params, R0900_P1_DMDCFGMD,
-                                                0x89);
+                stv0900_write_reg(intp, DMDCFGMD, 0x49);
+                zigzag = FALSE;
+                break;
+        case STV0900_SEARCH_DVBS2:
+                if (intp->chip_id >= 0x20)
+                        stv0900_write_reg(intp, CORRELABS, 0x79);
+                else
+                        stv0900_write_reg(intp, CORRELABS, 0x68);
 
-                        zigzag = TRUE;
-                        break;
-                case STV0900_AUTO_SEARCH:
-                default:
-                        if (i_params->chip_id >= 0x20) {
-                                stv0900_write_reg(i_params, R0900_P1_CARFREQ,
-                                                        0x3B);
-                                stv0900_write_reg(i_params, R0900_P1_CORRELABS,
-                                                        0x79);
-                        } else {
-                                stv0900_write_reg(i_params, R0900_P1_CARFREQ,
-                                                        0xef);
-                                stv0900_write_reg(i_params, R0900_P1_CORRELABS,
-                                                        0x68);
-                        }
+                stv0900_write_reg(intp, DMDCFGMD, 0x89);
 
-                        stv0900_write_reg(i_params, R0900_P1_DMDCFGMD,
-                                                        0xc9);
-                        zigzag = FALSE;
-                        break;
+                zigzag = TRUE;
+                break;
+        case STV0900_AUTO_SEARCH:
+        default:
+                if (intp->chip_id >= 0x20) {
+                        stv0900_write_reg(intp, CARFREQ, 0x3b);
+                        stv0900_write_reg(intp, CORRELABS, 0x79);
+                } else {
+                        stv0900_write_reg(intp, CARFREQ, 0xef);
+                        stv0900_write_reg(intp, CORRELABS, 0x68);
                 }
 
-                trialCounter = 0;
-                do {
-                        lock = stv0900_search_carr_sw_loop(i_params,
-                                                        freqIncrement,
-                                                        softStepTimeout,
-                                                        zigzag,
-                                                        max_steps,
-                                                        demod);
-                        no_signal = stv0900_check_signal_presence(i_params,
-                                                                demod);
-                        trialCounter++;
-                        if ((lock == TRUE)
-                                        || (no_signal == TRUE)
-                                        || (trialCounter == 2)) {
-
-                                if (i_params->chip_id >= 0x20) {
-                                        stv0900_write_reg(i_params,
-                                                        R0900_P1_CARFREQ,
-                                                        0x49);
-                                        stv0900_write_reg(i_params,
-                                                        R0900_P1_CORRELABS,
-                                                        0x9e);
-                                } else {
-                                        stv0900_write_reg(i_params,
-                                                        R0900_P1_CARFREQ,
-                                                        0xed);
-                                        stv0900_write_reg(i_params,
-                                                        R0900_P1_CORRELABS,
-                                                        0x88);
-                                }
-
-                                if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS2_FOUND)) {
-                                        msleep(softStepTimeout);
-                                        dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
-
-                                        if (dvbs2_fly_wheel < 0xd) {
-                                                msleep(softStepTimeout);
-                                                dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
-                                        }
-
-                                        if (dvbs2_fly_wheel < 0xd) {
-                                                lock = FALSE;
-
-                                                if (trialCounter < 2) {
-                                                        if (i_params->chip_id >= 0x20)
-                                                                stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x79);
-                                                        else
-                                                                stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x68);
-
-                                                        stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x89);
-                                                }
-                                        }
-                                }
-                        }
-
-                } while ((lock == FALSE)
-                        && (trialCounter < 2)
-                        && (no_signal == FALSE));
-
+                stv0900_write_reg(intp, DMDCFGMD, 0xc9);
+                zigzag = FALSE;
                 break;
-        case STV0900_DEMOD_2:
-                switch (i_params->dmd2_srch_stndrd) {
-                case STV0900_SEARCH_DVBS1:
-                case STV0900_SEARCH_DSS:
-                        if (i_params->chip_id >= 0x20)
-                                stv0900_write_reg(i_params, R0900_P2_CARFREQ,
-                                                0x3b);
-                        else
-                                stv0900_write_reg(i_params, R0900_P2_CARFREQ,
-                                                0xef);
-
-                        stv0900_write_reg(i_params, R0900_P2_DMDCFGMD,
-                                                0x49);
-                        zigzag = FALSE;
-                        break;
-                case STV0900_SEARCH_DVBS2:
-                        if (i_params->chip_id >= 0x20)
-                                stv0900_write_reg(i_params, R0900_P2_CORRELABS,
-                                                0x79);
-                        else
-                                stv0900_write_reg(i_params, R0900_P2_CORRELABS,
-                                                0x68);
+        }
 
-                        stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89);
-                        zigzag = TRUE;
-                        break;
-                case STV0900_AUTO_SEARCH:
-                default:
-                        if (i_params->chip_id >= 0x20) {
-                                stv0900_write_reg(i_params, R0900_P2_CARFREQ,
-                                                0x3b);
-                                stv0900_write_reg(i_params, R0900_P2_CORRELABS,
-                                                0x79);
+        trial_cntr = 0;
+        do {
+                lock = stv0900_search_carr_sw_loop(intp,
+                                                fqc_inc,
+                                                sft_stp_tout,
+                                                zigzag,
+                                                max_steps,
+                                                demod);
+                no_signal = stv0900_check_signal_presence(intp, demod);
+                trial_cntr++;
+                if ((lock == TRUE)
+                                || (no_signal == TRUE)
+                                || (trial_cntr == 2)) {
+
+                        if (intp->chip_id >= 0x20) {
+                                stv0900_write_reg(intp, CARFREQ, 0x49);
+                                stv0900_write_reg(intp, CORRELABS, 0x9e);
                         } else {
-                                stv0900_write_reg(i_params, R0900_P2_CARFREQ,
-                                                0xef);
-                                stv0900_write_reg(i_params, R0900_P2_CORRELABS,
-                                                0x68);
+                                stv0900_write_reg(intp, CARFREQ, 0xed);
+                                stv0900_write_reg(intp, CORRELABS, 0x88);
                         }
 
-                        stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0xc9);
-
-                        zigzag = FALSE;
-                        break;
-                }
-
-                trialCounter = 0;
+                        if ((stv0900_get_bits(intp, HEADER_MODE) ==
+                                                STV0900_DVBS2_FOUND) &&
+                                                        (lock == TRUE)) {
+                                msleep(sft_stp_tout);
+                                s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
 
-                do {
-                        lock = stv0900_search_carr_sw_loop(i_params,
-                                                        freqIncrement,
-                                                        softStepTimeout,
-                                                        zigzag,
-                                                        max_steps,
-                                                        demod);
-                        no_signal = stv0900_check_signal_presence(i_params,
-                                                                demod);
-                        trialCounter++;
-                        if ((lock == TRUE)
-                                        || (no_signal == TRUE)
-                                        || (trialCounter == 2)) {
-                                if (i_params->chip_id >= 0x20) {
-                                        stv0900_write_reg(i_params,
-                                                        R0900_P2_CARFREQ,
-                                                        0x49);
-                                        stv0900_write_reg(i_params,
-                                                        R0900_P2_CORRELABS,
-                                                        0x9e);
-                                } else {
-                                        stv0900_write_reg(i_params,
-                                                        R0900_P2_CARFREQ,
-                                                        0xed);
-                                        stv0900_write_reg(i_params,
-                                                        R0900_P2_CORRELABS,
-                                                        0x88);
+                                if (s2fw < 0xd) {
+                                        msleep(sft_stp_tout);
+                                        s2fw = stv0900_get_bits(intp,
+                                                                FLYWHEEL_CPT);
                                 }
 
-                                if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS2_FOUND)) {
-                                        msleep(softStepTimeout);
-                                        dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
-                                        if (dvbs2_fly_wheel < 0xd) {
-                                                msleep(softStepTimeout);
-                                                dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
-                                        }
+                                if (s2fw < 0xd) {
+                                        lock = FALSE;
 
-                                        if (dvbs2_fly_wheel < 0xd) {
-                                                lock = FALSE;
-                                                if (trialCounter < 2) {
-                                                        if (i_params->chip_id >= 0x20)
-                                                                stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x79);
-                                                        else
-                                                                stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x68);
+                                        if (trial_cntr < 2) {
+                                                if (intp->chip_id >= 0x20)
+                                                        stv0900_write_reg(intp,
+                                                                CORRELABS,
+                                                                0x79);
+                                                else
+                                                        stv0900_write_reg(intp,
+                                                                CORRELABS,
+                                                                0x68);
 
-                                                        stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89);
-                                                }
+                                                stv0900_write_reg(intp,
+                                                                DMDCFGMD,
+                                                                0x89);
                                         }
                                 }
                         }
+                }
 
-                } while ((lock == FALSE) && (trialCounter < 2) && (no_signal == FALSE));
-
-                break;
-        }
+        } while ((lock == FALSE)
+                && (trial_cntr < 2)
+                && (no_signal == FALSE));
 
         return lock;
 }
 
-static u32 stv0900_get_symbol_rate(struct stv0900_internal *i_params,
+static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
                                         u32 mclk,
                                         enum fe_stv0900_demod_num demod)
 {
-        s32 sfr_field3, sfr_field2, sfr_field1, sfr_field0,
-        rem1, rem2, intval1, intval2, srate;
-
-        dmd_reg(sfr_field3, F0900_P1_SYMB_FREQ3, F0900_P2_SYMB_FREQ3);
-        dmd_reg(sfr_field2, F0900_P1_SYMB_FREQ2, F0900_P2_SYMB_FREQ2);
-        dmd_reg(sfr_field1, F0900_P1_SYMB_FREQ1, F0900_P2_SYMB_FREQ1);
-        dmd_reg(sfr_field0, F0900_P1_SYMB_FREQ0, F0900_P2_SYMB_FREQ0);
-
-        srate = (stv0900_get_bits(i_params, sfr_field3) << 24) +
-                (stv0900_get_bits(i_params, sfr_field2) << 16) +
-                (stv0900_get_bits(i_params, sfr_field1) << 8) +
-                (stv0900_get_bits(i_params, sfr_field0));
+        s32     rem1, rem2, intval1, intval2, srate;
+
+        srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
+                (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
+                (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
+                (stv0900_get_bits(intp, SYMB_FREQ0));
         dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
-                srate, stv0900_get_bits(i_params, sfr_field0),
-                stv0900_get_bits(i_params, sfr_field1),
-                stv0900_get_bits(i_params, sfr_field2),
-                stv0900_get_bits(i_params, sfr_field3));
+                srate, stv0900_get_bits(intp, SYMB_FREQ0),
+                stv0900_get_bits(intp, SYMB_FREQ1),
+                stv0900_get_bits(intp, SYMB_FREQ2),
+                stv0900_get_bits(intp, SYMB_FREQ3));
 
         intval1 = (mclk) >> 16;
         intval2 = (srate) >> 16;
@@ -520,18 +333,15 @@ static u32 stv0900_get_symbol_rate(struct stv0900_internal *i_params,
         return srate;
 }
 
-static void stv0900_set_symbol_rate(struct stv0900_internal *i_params,
+static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
                                         u32 mclk, u32 srate,
                                         enum fe_stv0900_demod_num demod)
 {
-        s32 sfr_init_reg;
         u32 symb;
 
-        dprintk(KERN_INFO "%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
+        dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
                                                         srate, demod);
 
-        dmd_reg(sfr_init_reg, R0900_P1_SFRINIT1, R0900_P2_SFRINIT1);
-
         if (srate > 60000000) {
                 symb = srate << 4;
                 symb /= (mclk >> 12);
@@ -543,19 +353,16 @@ static void stv0900_set_symbol_rate(struct stv0900_internal *i_params,
                 symb /= (mclk >> 7);
         }
 
-        stv0900_write_reg(i_params, sfr_init_reg, (symb >> 8) & 0x7F);
-        stv0900_write_reg(i_params, sfr_init_reg + 1, (symb & 0xFF));
+        stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
+        stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
 }
 
-static void stv0900_set_max_symbol_rate(struct stv0900_internal *i_params,
+static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
                                         u32 mclk, u32 srate,
                                         enum fe_stv0900_demod_num demod)
 {
-        s32 sfr_max_reg;
         u32 symb;
 
-        dmd_reg(sfr_max_reg, R0900_P1_SFRUP1, R0900_P2_SFRUP1);
-
         srate = 105 * (srate / 100);
 
         if (srate > 60000000) {
@@ -570,23 +377,20 @@ static void stv0900_set_max_symbol_rate(struct stv0900_internal *i_params,
         }
 
         if (symb < 0x7fff) {
-                stv0900_write_reg(i_params, sfr_max_reg, (symb >> 8) & 0x7F);
-                stv0900_write_reg(i_params, sfr_max_reg + 1, (symb & 0xFF));
+                stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
+                stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
         } else {
-                stv0900_write_reg(i_params, sfr_max_reg, 0x7F);
-                stv0900_write_reg(i_params, sfr_max_reg + 1, 0xFF);
+                stv0900_write_reg(intp, SFRUP1, 0x7f);
+                stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
         }
 }
 
-static void stv0900_set_min_symbol_rate(struct stv0900_internal *i_params,
+static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
                                         u32 mclk, u32 srate,
                                         enum fe_stv0900_demod_num demod)
 {
-        s32 sfr_min_reg;
         u32     symb;
 
-        dmd_reg(sfr_min_reg, R0900_P1_SFRLOW1, R0900_P2_SFRLOW1);
-
         srate = 95 * (srate / 100);
         if (srate > 60000000) {
                 symb = srate << 4;
@@ -601,22 +405,20 @@ static void stv0900_set_min_symbol_rate(struct stv0900_internal *i_params,
                 symb /= (mclk >> 7);
         }
 
-        stv0900_write_reg(i_params, sfr_min_reg, (symb >> 8) & 0xFF);
-        stv0900_write_reg(i_params, sfr_min_reg + 1, (symb & 0xFF));
+        stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
+        stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
 }
 
-static s32 stv0900_get_timing_offst(struct stv0900_internal *i_params,
+static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
                                         u32 srate,
                                         enum fe_stv0900_demod_num demod)
 {
-        s32 tmgreg,
-        timingoffset;
+        s32 timingoffset;
 
-        dmd_reg(tmgreg, R0900_P1_TMGREG2, R0900_P2_TMGREG2);
 
-        timingoffset = (stv0900_read_reg(i_params, tmgreg) << 16) +
-                       (stv0900_read_reg(i_params, tmgreg + 1) << 8) +
-                       (stv0900_read_reg(i_params, tmgreg + 2));
+        timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
+                       (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
+                       (stv0900_read_reg(intp, TMGREG2 + 2));
 
         timingoffset = ge2comp(timingoffset, 24);
 
@@ -630,22 +432,19 @@ static s32 stv0900_get_timing_offst(struct stv0900_internal *i_params,
         return timingoffset;
 }
 
-static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *i_params,
+static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
                                         enum fe_stv0900_demod_num demod)
 {
-        s32 rolloff, man_fld, matstr_reg, rolloff_ctl_fld;
-
-        dmd_reg(man_fld, F0900_P1_MANUAL_ROLLOFF, F0900_P2_MANUAL_ROLLOFF);
-        dmd_reg(matstr_reg, R0900_P1_MATSTR1, R0900_P2_MATSTR1);
-        dmd_reg(rolloff_ctl_fld, F0900_P1_ROLLOFF_CONTROL,
-                                F0900_P2_ROLLOFF_CONTROL);
-
-        if (i_params->chip_id == 0x10) {
-                stv0900_write_bits(i_params, man_fld, 1);
-                rolloff = stv0900_read_reg(i_params, matstr_reg) & 0x03;
-                stv0900_write_bits(i_params, rolloff_ctl_fld, rolloff);
-        } else
-                stv0900_write_bits(i_params, man_fld, 0);
+        s32 rolloff;
+
+        if (intp->chip_id == 0x10) {
+                stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
+                rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
+                stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
+        } else if (intp->chip_id <= 0x20)
+                stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
+        else /* cut 3.0 */
+                stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
 }
 
 static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
@@ -668,84 +467,47 @@ static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
         return srate  + (srate * rolloff) / 100;
 }
 
-static int stv0900_check_timing_lock(struct stv0900_internal *i_params,
+static int stv0900_check_timing_lock(struct stv0900_internal *intp,
                                 enum fe_stv0900_demod_num demod)
 {
         int timingLock = FALSE;
-        s32 i,
-        timingcpt = 0;
-        u8 carFreq,
-        tmgTHhigh,
-        tmgTHLow;
-
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                carFreq = stv0900_read_reg(i_params, R0900_P1_CARFREQ);
-                tmgTHhigh = stv0900_read_reg(i_params, R0900_P1_TMGTHRISE);
-                tmgTHLow = stv0900_read_reg(i_params, R0900_P1_TMGTHFALL);
-                stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20);
-                stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x0);
-                stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
-                stv0900_write_reg(i_params, R0900_P1_RTC, 0x80);
-                stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x40);
-                stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x0);
-                stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0x0);
-                stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0x0);
-                stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x65);
-                stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
-                msleep(7);
-
-                for (i = 0; i < 10; i++) {
-                        if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2)
-                                timingcpt++;
-
-                        msleep(1);
-                }
-
-                if (timingcpt >= 3)
-                        timingLock = TRUE;
-
-                stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
-                stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
-                stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
-                stv0900_write_reg(i_params, R0900_P1_CARFREQ, carFreq);
-                stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, tmgTHhigh);
-                stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, tmgTHLow);
-                break;
-        case STV0900_DEMOD_2:
-                carFreq = stv0900_read_reg(i_params, R0900_P2_CARFREQ);
-                tmgTHhigh = stv0900_read_reg(i_params, R0900_P2_TMGTHRISE);
-                tmgTHLow = stv0900_read_reg(i_params, R0900_P2_TMGTHFALL);
-                stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20);
-                stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0);
-                stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
-                stv0900_write_reg(i_params, R0900_P2_RTC, 0x80);
-                stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x40);
-                stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x0);
-                stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0x0);
-                stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0x0);
-                stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x65);
-                stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
-                msleep(5);
-                for (i = 0; i < 10; i++) {
-                        if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2)
-                                timingcpt++;
+        s32     i,
+                timingcpt = 0;
+        u8      car_freq,
+                tmg_th_high,
+                tmg_th_low;
+
+        car_freq = stv0900_read_reg(intp, CARFREQ);
+        tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
+        tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
+        stv0900_write_reg(intp, TMGTHRISE, 0x20);
+        stv0900_write_reg(intp, TMGTHFALL, 0x0);
+        stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
+        stv0900_write_reg(intp, RTC, 0x80);
+        stv0900_write_reg(intp, RTCS2, 0x40);
+        stv0900_write_reg(intp, CARFREQ, 0x0);
+        stv0900_write_reg(intp, CFRINIT1, 0x0);
+        stv0900_write_reg(intp, CFRINIT0, 0x0);
+        stv0900_write_reg(intp, AGC2REF, 0x65);
+        stv0900_write_reg(intp, DMDISTATE, 0x18);
+        msleep(7);
+
+        for (i = 0; i < 10; i++) {
+                if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
+                        timingcpt++;
+
+                msleep(1);
+        }
 
-                        msleep(1);
-                }
+        if (timingcpt >= 3)
+                timingLock = TRUE;
 
-                if (timingcpt >= 3)
-                        timingLock = TRUE;
-
-                stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
-                stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
-                stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
-                stv0900_write_reg(i_params, R0900_P2_CARFREQ, carFreq);
-                stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, tmgTHhigh);
-                stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, tmgTHLow);
-                break;
-        }
+        stv0900_write_reg(intp, AGC2REF, 0x38);
+        stv0900_write_reg(intp, RTC, 0x88);
+        stv0900_write_reg(intp, RTCS2, 0x68);
+        stv0900_write_reg(intp, CARFREQ, car_freq);
+        stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
+        stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
 
         return  timingLock;
 }
@@ -754,142 +516,119 @@ static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
                                         s32 demod_timeout)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
+        int     lock = FALSE,
+                d = demod;
+        s32     srate,
+                search_range,
+                locktimeout,
+                currier_step,
+                nb_steps,
+                current_step,
+                direction,
+                tuner_freq,
+                timeout,
+                freq;
 
-        int lock = FALSE;
-        s32 srate, search_range, locktimeout,
-                currier_step, nb_steps, current_step,
-                direction, tuner_freq, timeout;
-
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                srate = i_params->dmd1_symbol_rate;
-                search_range = i_params->dmd1_srch_range;
-                break;
-
-        case STV0900_DEMOD_2:
-                srate = i_params->dmd2_symbol_rate;
-                search_range = i_params->dmd2_srch_range;
-                break;
-        }
+        srate = intp->symbol_rate[d];
+        search_range = intp->srch_range[d];
 
         if (srate >= 10000000)
                 locktimeout = demod_timeout / 3;
         else
                 locktimeout = demod_timeout / 2;
 
-        lock = stv0900_get_demod_lock(i_params, demod, locktimeout);
-
-        if (lock == FALSE) {
-                if (srate >= 10000000) {
-                        if (stv0900_check_timing_lock(i_params, demod) == TRUE) {
-                                switch (demod) {
-                                case STV0900_DEMOD_1:
-                                default:
-                                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
-                                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
-                                        break;
-                                case STV0900_DEMOD_2:
-                                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
-                                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
-                                        break;
-                                }
+        lock = stv0900_get_demod_lock(intp, d, locktimeout);
 
-                                lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
-                        } else
-                                lock = FALSE;
-                } else {
-                        if (srate <= 4000000)
-                                currier_step = 1000;
-                        else if (srate <= 7000000)
-                                currier_step = 2000;
-                        else if (srate <= 10000000)
-                                currier_step = 3000;
-                        else
-                                currier_step = 5000;
-
-                        nb_steps = ((search_range / 1000) / currier_step);
-                        nb_steps /= 2;
-                        nb_steps = (2 * (nb_steps + 1));
-                        if (nb_steps < 0)
-                                nb_steps = 2;
-                        else if (nb_steps > 12)
-                                nb_steps = 12;
-
-                        current_step = 1;
-                        direction = 1;
+        if (lock != FALSE)
+                return lock;
+
+        if (srate >= 10000000) {
+                if (stv0900_check_timing_lock(intp, d) == TRUE) {
+                        stv0900_write_reg(intp, DMDISTATE, 0x1f);
+                        stv0900_write_reg(intp, DMDISTATE, 0x15);
+                        lock = stv0900_get_demod_lock(intp, d, demod_timeout);
+                } else
+                        lock = FALSE;
+
+                return lock;
+        }
+
+        if (intp->chip_id <= 0x20) {
+                if (srate <= 1000000)
+                        currier_step = 500;
+                else if (srate <= 4000000)
+                        currier_step = 1000;
+                else if (srate <= 7000000)
+                        currier_step = 2000;
+                else if (srate <= 10000000)
+                        currier_step = 3000;
+                else
+                        currier_step = 5000;
+
+                if (srate >= 2000000) {
                         timeout = (demod_timeout / 3);
                         if (timeout > 1000)
                                 timeout = 1000;
+                } else
+                        timeout = (demod_timeout / 2);
+        } else {
+                /*cut 3.0 */
+                currier_step = srate / 4000;
+                timeout = (demod_timeout * 3) / 4;
+        }
 
-                        switch (demod) {
-                        case STV0900_DEMOD_1:
-                        default:
-                                if (lock == FALSE) {
-                                        tuner_freq = i_params->tuner1_freq;
-                                        i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + i_params->dmd1_symbol_rate;
+        nb_steps = ((search_range / 1000) / currier_step);
 
-                                        while ((current_step <= nb_steps) && (lock == FALSE)) {
+        if ((nb_steps % 2) != 0)
+                nb_steps += 1;
 
-                                                if (direction > 0)
-                                                        tuner_freq += (current_step * currier_step);
-                                                else
-                                                        tuner_freq -= (current_step * currier_step);
-
-                                                stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw);
-                                                stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
-                                                if (i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS2) {
-                                                        stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
-                                                        stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
-                                                        stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
-                                                        stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
-                                                }
-
-                                                stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
-                                                stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
-                                                stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
-                                                stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
-                                                lock = stv0900_get_demod_lock(i_params, demod, timeout);
-                                                direction *= -1;
-                                                current_step++;
-                                        }
-                                }
-                                break;
-                        case STV0900_DEMOD_2:
-                                if (lock == FALSE) {
-                                        tuner_freq = i_params->tuner2_freq;
-                                        i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + srate;
+        if (nb_steps <= 0)
+                nb_steps = 2;
+        else if (nb_steps > 12)
+                nb_steps = 12;
 
-                                        while ((current_step <= nb_steps) && (lock == FALSE)) {
+        current_step = 1;
+        direction = 1;
 
-                                                if (direction > 0)
-                                                        tuner_freq += (current_step * currier_step);
-                                                else
-                                                        tuner_freq -= (current_step * currier_step);
-
-                                                stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw);
-                                                stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
-                                                if (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS2) {
-                                                        stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
-                                                        stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
-                                                        stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
-                                                        stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
-                                                }
-
-                                                stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0);
-                                                stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0);
-                                                stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
-                                                stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
-                                                lock = stv0900_get_demod_lock(i_params, demod, timeout);
-                                                direction *= -1;
-                                                current_step++;
-                                        }
-                                }
-                                break;
-                        }
+        if (intp->chip_id <= 0x20) {
+                tuner_freq = intp->freq[d];
+                intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
+                                intp->rolloff) + intp->symbol_rate[d];
+        } else
+                tuner_freq = 0;
+
+        while ((current_step <= nb_steps) && (lock == FALSE)) {
+                if (direction > 0)
+                        tuner_freq += (current_step * currier_step);
+                else
+                        tuner_freq -= (current_step * currier_step);
+
+                if (intp->chip_id <= 0x20) {
+                        if (intp->tuner_type[d] == 3)
+                                stv0900_set_tuner_auto(intp, tuner_freq,
+                                                intp->bw[d], demod);
+                        else
+                                stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
+
+                        stv0900_write_reg(intp, DMDISTATE, 0x1c);
+                        stv0900_write_reg(intp, CFRINIT1, 0);
+                        stv0900_write_reg(intp, CFRINIT0, 0);
+                        stv0900_write_reg(intp, DMDISTATE, 0x1f);
+                        stv0900_write_reg(intp, DMDISTATE, 0x15);
+                } else {
+                        stv0900_write_reg(intp, DMDISTATE, 0x1c);
+                        freq = (tuner_freq * 65536) / (intp->mclk / 1000);
+                        stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
+                        stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
+                        stv0900_write_reg(intp, DMDISTATE, 0x1f);
+                        stv0900_write_reg(intp, DMDISTATE, 0x05);
                 }
+
+                lock = stv0900_get_demod_lock(intp, d, timeout);
+                direction *= -1;
+                current_step++;
         }
 
         return  lock;
@@ -931,9 +670,7 @@ static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
                 } else if (srate <= 20000000) {
                         (*demod_timeout) = 400;
                         (*fec_timeout) = 130;
-                }
-
-                else {
+                } else {
                         (*demod_timeout) = 300;
                         (*fec_timeout) = 100;
                 }
@@ -946,95 +683,77 @@ static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
                 (*demod_timeout) /= 2;
 }
 
-static void stv0900_set_viterbi_tracq(struct stv0900_internal *i_params,
+static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
                                         enum fe_stv0900_demod_num demod)
 {
 
-        s32 vth_reg;
+        s32 vth_reg = VTH12;
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
-        dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12);
-
-        stv0900_write_reg(i_params, vth_reg++, 0xd0);
-        stv0900_write_reg(i_params, vth_reg++, 0x7d);
-        stv0900_write_reg(i_params, vth_reg++, 0x53);
-        stv0900_write_reg(i_params, vth_reg++, 0x2F);
-        stv0900_write_reg(i_params, vth_reg++, 0x24);
-        stv0900_write_reg(i_params, vth_reg++, 0x1F);
+        stv0900_write_reg(intp, vth_reg++, 0xd0);
+        stv0900_write_reg(intp, vth_reg++, 0x7d);
+        stv0900_write_reg(intp, vth_reg++, 0x53);
+        stv0900_write_reg(intp, vth_reg++, 0x2f);
+        stv0900_write_reg(intp, vth_reg++, 0x24);
+        stv0900_write_reg(intp, vth_reg++, 0x1f);
 }
 
-static void stv0900_set_viterbi_standard(struct stv0900_internal *i_params,
-                                   enum fe_stv0900_search_standard Standard,
-                                   enum fe_stv0900_fec PunctureRate,
+static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
+                                   enum fe_stv0900_search_standard standard,
+                                   enum fe_stv0900_fec fec,
                                    enum fe_stv0900_demod_num demod)
 {
+        dprintk("%s: ViterbiStandard = ", __func__);
 
-        s32 fecmReg,
-        prvitReg;
-
-        dprintk(KERN_INFO "%s: ViterbiStandard = ", __func__);
-
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                fecmReg = R0900_P1_FECM;
-                prvitReg = R0900_P1_PRVIT;
-                break;
-        case STV0900_DEMOD_2:
-                fecmReg = R0900_P2_FECM;
-                prvitReg = R0900_P2_PRVIT;
-                break;
-        }
-
-        switch (Standard) {
+        switch (standard) {
         case STV0900_AUTO_SEARCH:
                 dprintk("Auto\n");
-                stv0900_write_reg(i_params, fecmReg, 0x10);
-                stv0900_write_reg(i_params, prvitReg, 0x3F);
+                stv0900_write_reg(intp, FECM, 0x10);
+                stv0900_write_reg(intp, PRVIT, 0x3f);
                 break;
         case STV0900_SEARCH_DVBS1:
                 dprintk("DVBS1\n");
-                stv0900_write_reg(i_params, fecmReg, 0x00);
-                switch (PunctureRate) {
+                stv0900_write_reg(intp, FECM, 0x00);
+                switch (fec) {
                 case STV0900_FEC_UNKNOWN:
                 default:
-                        stv0900_write_reg(i_params, prvitReg, 0x2F);
+                        stv0900_write_reg(intp, PRVIT, 0x2f);
                         break;
                 case STV0900_FEC_1_2:
-                        stv0900_write_reg(i_params, prvitReg, 0x01);
+                        stv0900_write_reg(intp, PRVIT, 0x01);
                         break;
                 case STV0900_FEC_2_3:
-                        stv0900_write_reg(i_params, prvitReg, 0x02);
+                        stv0900_write_reg(intp, PRVIT, 0x02);
                         break;
                 case STV0900_FEC_3_4:
-                        stv0900_write_reg(i_params, prvitReg, 0x04);
+                        stv0900_write_reg(intp, PRVIT, 0x04);
                         break;
                 case STV0900_FEC_5_6:
-                        stv0900_write_reg(i_params, prvitReg, 0x08);
+                        stv0900_write_reg(intp, PRVIT, 0x08);
                         break;
                 case STV0900_FEC_7_8:
-                        stv0900_write_reg(i_params, prvitReg, 0x20);
+                        stv0900_write_reg(intp, PRVIT, 0x20);
                         break;
                 }
 
                 break;
         case STV0900_SEARCH_DSS:
                 dprintk("DSS\n");
-                stv0900_write_reg(i_params, fecmReg, 0x80);
-                switch (PunctureRate) {
+                stv0900_write_reg(intp, FECM, 0x80);
+                switch (fec) {
                 case STV0900_FEC_UNKNOWN:
                 default:
-                        stv0900_write_reg(i_params, prvitReg, 0x13);
+                        stv0900_write_reg(intp, PRVIT, 0x13);
                         break;
                 case STV0900_FEC_1_2:
-                        stv0900_write_reg(i_params, prvitReg, 0x01);
+                        stv0900_write_reg(intp, PRVIT, 0x01);
                         break;
                 case STV0900_FEC_2_3:
-                        stv0900_write_reg(i_params, prvitReg, 0x02);
+                        stv0900_write_reg(intp, PRVIT, 0x02);
                         break;
                 case STV0900_FEC_6_7:
-                        stv0900_write_reg(i_params, prvitReg, 0x10);
+                        stv0900_write_reg(intp, PRVIT, 0x10);
                         break;
                 }
                 break;
@@ -1043,340 +762,285 @@ static void stv0900_set_viterbi_standard(struct stv0900_internal *i_params,
         }
 }
 
-static void stv0900_track_optimization(struct dvb_frontend *fe)
+static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
+                                                enum fe_stv0900_demod_num demod)
 {
-        struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
-        enum fe_stv0900_demod_num demod = state->demod;
+        enum fe_stv0900_fec prate;
+        s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
 
-        s32 srate, pilots, aclc, freq1, freq0,
-                i = 0, timed, timef, blindTunSw = 0;
+        switch (rate_fld) {
+        case 13:
+                prate = STV0900_FEC_1_2;
+                break;
+        case 18:
+                prate = STV0900_FEC_2_3;
+                break;
+        case 21:
+                prate = STV0900_FEC_3_4;
+                break;
+        case 24:
+                prate = STV0900_FEC_5_6;
+                break;
+        case 25:
+                prate = STV0900_FEC_6_7;
+                break;
+        case 26:
+                prate = STV0900_FEC_7_8;
+                break;
+        default:
+                prate = STV0900_FEC_UNKNOWN;
+                break;
+        }
 
-        enum fe_stv0900_rolloff rolloff;
-        enum fe_stv0900_modcode foundModcod;
+        return prate;
+}
 
-        dprintk(KERN_INFO "%s\n", __func__);
+static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
+                                        enum fe_stv0900_demod_num demod,
+                                        u32 srate)
+{
+        if (intp->chip_id >= 0x30) {
+                if (srate >= 15000000) {
+                        stv0900_write_reg(intp, ACLC, 0x2b);
+                        stv0900_write_reg(intp, BCLC, 0x1a);
+                } else if ((srate >= 7000000) && (15000000 > srate)) {
+                        stv0900_write_reg(intp, ACLC, 0x0c);
+                        stv0900_write_reg(intp, BCLC, 0x1b);
+                } else if (srate < 7000000) {
+                        stv0900_write_reg(intp, ACLC, 0x2c);
+                        stv0900_write_reg(intp, BCLC, 0x1c);
+                }
 
-        srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
-        srate += stv0900_get_timing_offst(i_params, srate, demod);
+        } else { /*cut 2.0 and 1.x*/
+                stv0900_write_reg(intp, ACLC, 0x1a);
+                stv0900_write_reg(intp, BCLC, 0x09);
+        }
 
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                switch (i_params->dmd1_rslts.standard) {
-                case STV0900_DVBS1_STANDARD:
-                        if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
-                                stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
-                                stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
-                        }
+}
 
-                        stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff);
-                        stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
-                        stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
-                        break;
-                case STV0900_DSS_STANDARD:
-                        if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
-                                stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
-                                stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
-                        }
+static void stv0900_track_optimization(struct dvb_frontend *fe)
+{
+        struct stv0900_state *state = fe->demodulator_priv;
+        struct stv0900_internal *intp = state->internal;
+        enum fe_stv0900_demod_num demod = state->demod;
 
-                        stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff);
-                        stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
-                        stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
-                        break;
-                case STV0900_DVBS2_STANDARD:
-                        stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
-                        stv0900_write_reg(i_params, R0900_P1_ACLC, 0);
-                        stv0900_write_reg(i_params, R0900_P1_BCLC, 0);
-                        if (i_params->dmd1_rslts.frame_length == STV0900_LONG_FRAME) {
-                                foundModcod = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD);
-                                pilots = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01;
-                                aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
-                                if (foundModcod <= STV0900_QPSK_910)
-                                        stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
-                                else if (foundModcod <= STV0900_8PSK_910) {
-                                        stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
-                                        stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
-                                }
+        s32     srate,
+                pilots,
+                aclc,
+                freq1,
+                freq0,
+                i = 0,
+                timed,
+                timef,
+                blind_tun_sw = 0,
+                modulation;
 
-                                if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) {
-                                        if (foundModcod <= STV0900_16APSK_910) {
-                                                stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
-                                                stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
-                                        } else if (foundModcod <= STV0900_32APSK_910) {
-                                                stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
-                                                stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
-                                        }
-                                }
+        enum fe_stv0900_rolloff rolloff;
+        enum fe_stv0900_modcode foundModcod;
 
-                        } else {
-                                aclc = stv0900_get_optim_short_carr_loop(srate, i_params->dmd1_rslts.modulation, i_params->chip_id);
-                                if (i_params->dmd1_rslts.modulation == STV0900_QPSK)
-                                        stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
-
-                                else if (i_params->dmd1_rslts.modulation == STV0900_8PSK) {
-                                        stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
-                                        stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
-                                } else if (i_params->dmd1_rslts.modulation == STV0900_16APSK) {
-                                        stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
-                                        stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
-                                } else if (i_params->dmd1_rslts.modulation == STV0900_32APSK) {
-                                        stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
-                                        stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
-                                }
+        dprintk("%s\n", __func__);
 
-                        }
+        srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
+        srate += stv0900_get_timing_offst(intp, srate, demod);
 
-                        if (i_params->chip_id <= 0x11) {
-                                if (i_params->demod_mode != STV0900_SINGLE)
-                                        stv0900_activate_s2_modcode(i_params, demod);
+        switch (intp->result[demod].standard) {
+        case STV0900_DVBS1_STANDARD:
+        case STV0900_DSS_STANDARD:
+                dprintk("%s: found DVB-S or DSS\n", __func__);
+                if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
+                        stv0900_write_bits(intp, DVBS1_ENABLE, 1);
+                        stv0900_write_bits(intp, DVBS2_ENABLE, 0);
+                }
 
-                        }
+                stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
+                stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
 
-                        stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67);
-                        break;
-                case STV0900_UNKNOWN_STANDARD:
-                default:
-                        stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
+                if (intp->chip_id < 0x30) {
+                        stv0900_write_reg(intp, ERRCTRL1, 0x75);
                         break;
                 }
 
-                freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2);
-                freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1);
-                rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS);
-                if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
-                        stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
-                        stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
-                        stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
-                        stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
-                        stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
-                        stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
-                        blindTunSw = 1;
+                if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
+                        stv0900_write_reg(intp, GAUSSR0, 0x98);
+                        stv0900_write_reg(intp, CCIR0, 0x18);
+                } else {
+                        stv0900_write_reg(intp, GAUSSR0, 0x18);
+                        stv0900_write_reg(intp, CCIR0, 0x18);
                 }
 
-                if (i_params->chip_id >= 0x20) {
-                        if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
-                                stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0a);
-                                stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x0);
+                stv0900_write_reg(intp, ERRCTRL1, 0x75);
+                break;
+        case STV0900_DVBS2_STANDARD:
+                dprintk("%s: found DVB-S2\n", __func__);
+                stv0900_write_bits(intp, DVBS1_ENABLE, 0);
+                stv0900_write_bits(intp, DVBS2_ENABLE, 1);
+                stv0900_write_reg(intp, ACLC, 0);
+                stv0900_write_reg(intp, BCLC, 0);
+                if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
+                        foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
+                        pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
+                        aclc = stv0900_get_optim_carr_loop(srate,
+                                                        foundModcod,
+                                                        pilots,
+                                                        intp->chip_id);
+                        if (foundModcod <= STV0900_QPSK_910)
+                                stv0900_write_reg(intp, ACLC2S2Q, aclc);
+                        else if (foundModcod <= STV0900_8PSK_910) {
+                                stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+                                stv0900_write_reg(intp, ACLC2S28, aclc);
                         }
-                }
-
-                if (i_params->chip_id < 0x20)
-                        stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x08);
-
-                if (i_params->chip_id == 0x10)
-                        stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0x0A);
 
-                stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
-
-                if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd1_symbol_rate < 10000000)) {
-                        stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
-                        stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
-                        i_params->tuner1_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000;
-
-                        if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) {
-                                if (i_params->dmd1_srch_algo != STV0900_WARM_START)
-                                        stv0900_set_bandwidth(fe, i_params->tuner1_bw);
+                        if ((intp->demod_mode == STV0900_SINGLE) &&
+                                        (foundModcod > STV0900_8PSK_910)) {
+                                if (foundModcod <= STV0900_16APSK_910) {
+                                        stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+                                        stv0900_write_reg(intp, ACLC2S216A,
+                                                                        aclc);
+                                } else if (foundModcod <= STV0900_32APSK_910) {
+                                        stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+                                        stv0900_write_reg(intp, ACLC2S232A,
+                                                                        aclc);
+                                }
                         }
 
-                        if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000))
-                                msleep(50);
-                        else
-                                msleep(5);
-
-                        stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START);
-
-                        if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) {
-                                stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
-                                stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
-                                stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
-                                stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
-                                i = 0;
-                                while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) {
-                                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
-                                        stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
-                                        stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
-                                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
-                                        i++;
-                                }
+                } else {
+                        modulation = intp->result[demod].modulation;
+                        aclc = stv0900_get_optim_short_carr_loop(srate,
+                                        modulation, intp->chip_id);
+                        if (modulation == STV0900_QPSK)
+                                stv0900_write_reg(intp, ACLC2S2Q, aclc);
+                        else if (modulation == STV0900_8PSK) {
+                                stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+                                stv0900_write_reg(intp, ACLC2S28, aclc);
+                        } else if (modulation == STV0900_16APSK) {
+                                stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+                                stv0900_write_reg(intp, ACLC2S216A, aclc);
+                        } else if (modulation == STV0900_32APSK) {
+                                stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+                                stv0900_write_reg(intp, ACLC2S232A, aclc);
                         }
 
                 }
 
-                if (i_params->chip_id >= 0x20)
-                        stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49);
+                if (intp->chip_id <= 0x11) {
+                        if (intp->demod_mode != STV0900_SINGLE)
+                                stv0900_activate_s2_modcod(intp, demod);
 
-                if ((i_params->dmd1_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd1_rslts.standard == STV0900_DSS_STANDARD))
-                        stv0900_set_viterbi_tracq(i_params, demod);
+                }
 
+                stv0900_write_reg(intp, ERRCTRL1, 0x67);
                 break;
+        case STV0900_UNKNOWN_STANDARD:
+        default:
+                dprintk("%s: found unknown standard\n", __func__);
+                stv0900_write_bits(intp, DVBS1_ENABLE, 1);
+                stv0900_write_bits(intp, DVBS2_ENABLE, 1);
+                break;
+        }
 
-        case STV0900_DEMOD_2:
-                switch (i_params->dmd2_rslts.standard) {
-                case STV0900_DVBS1_STANDARD:
-
-                        if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) {
-                                stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
-                                stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
-                        }
-
-                        stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff);
-                        stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
-                        stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
-                        break;
-                case STV0900_DSS_STANDARD:
-                        if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) {
-                                stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
-                                stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
-                        }
-
-                        stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff);
-                        stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
-                        stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
-                        break;
-                case STV0900_DVBS2_STANDARD:
-                        stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
-                        stv0900_write_reg(i_params, R0900_P2_ACLC, 0);
-                        stv0900_write_reg(i_params, R0900_P2_BCLC, 0);
-                        if (i_params->dmd2_rslts.frame_length == STV0900_LONG_FRAME) {
-                                foundModcod = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
-                                pilots = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
-                                aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
-                                if (foundModcod <= STV0900_QPSK_910)
-                                        stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
-                                else if (foundModcod <= STV0900_8PSK_910) {
-                                        stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
-                                        stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
-                                }
+        freq1 = stv0900_read_reg(intp, CFR2);
+        freq0 = stv0900_read_reg(intp, CFR1);
+        rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
+        if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
+                stv0900_write_reg(intp, SFRSTEP, 0x00);
+                stv0900_write_bits(intp, SCAN_ENABLE, 0);
+                stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
+                stv0900_write_reg(intp, TMGCFG2, 0xc1);
+                stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
+                blind_tun_sw = 1;
+                if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
+                        stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
 
-                                if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) {
-                                        if (foundModcod <= STV0900_16APSK_910) {
-                                                stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
-                                                stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
-                                        } else if (foundModcod <= STV0900_32APSK_910) {
-                                                stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
-                                                stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
-                                        }
+        }
 
-                                }
+        if (intp->chip_id >= 0x20) {
+                if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
+                                (intp->srch_standard[demod] ==
+                                                        STV0900_SEARCH_DSS) ||
+                                (intp->srch_standard[demod] ==
+                                                        STV0900_AUTO_SEARCH)) {
+                        stv0900_write_reg(intp, VAVSRVIT, 0x0a);
+                        stv0900_write_reg(intp, VITSCALE, 0x0);
+                }
+        }
 
-                        } else {
-                                aclc = stv0900_get_optim_short_carr_loop(srate,
-                                                                        i_params->dmd2_rslts.modulation,
-                                                                        i_params->chip_id);
-
-                                if (i_params->dmd2_rslts.modulation == STV0900_QPSK)
-                                        stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
-
-                                else if (i_params->dmd2_rslts.modulation == STV0900_8PSK) {
-                                        stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
-                                        stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
-                                } else if (i_params->dmd2_rslts.modulation == STV0900_16APSK) {
-                                        stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
-                                        stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
-                                } else if (i_params->dmd2_rslts.modulation == STV0900_32APSK) {
-                                        stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
-                                        stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
-                                }
-                        }
+        if (intp->chip_id < 0x20)
+                stv0900_write_reg(intp, CARHDR, 0x08);
 
-                        stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67);
+        if (intp->chip_id == 0x10)
+                stv0900_write_reg(intp, CORRELEXP, 0x0a);
 
-                        break;
-                case STV0900_UNKNOWN_STANDARD:
-                default:
-                        stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
-                        break;
-                }
+        stv0900_write_reg(intp, AGC2REF, 0x38);
 
-                freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2);
-                freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1);
-                rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS);
-                if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
-                        stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00);
-                        stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
-                        stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
-                        stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
-                        stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
-                        stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
-                        blindTunSw = 1;
-                }
+        if ((intp->chip_id >= 0x20) ||
+                        (blind_tun_sw == 1) ||
+                        (intp->symbol_rate[demod] < 10000000)) {
+                stv0900_write_reg(intp, CFRINIT1, freq1);
+                stv0900_write_reg(intp, CFRINIT0, freq0);
+                intp->bw[demod] = stv0900_carrier_width(srate,
+                                        intp->rolloff) + 10000000;
 
-                if (i_params->chip_id >= 0x20) {
-                        if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
-                                stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0a);
-                                stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x0);
+                if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
+                        if (intp->srch_algo[demod] != STV0900_WARM_START) {
+                                if (intp->tuner_type[demod] == 3)
+                                        stv0900_set_tuner_auto(intp,
+                                                        intp->freq[demod],
+                                                        intp->bw[demod],
+                                                        demod);
+                                else
+                                        stv0900_set_bandwidth(fe,
+                                                        intp->bw[demod]);
                         }
                 }
 
-                if (i_params->chip_id < 0x20)
-                        stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x08);
-
-                if (i_params->chip_id == 0x10)
-                        stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0x0a);
-
-                stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
-                if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd2_symbol_rate < 10000000)) {
-                        stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
-                        stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
-                        i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000;
+                if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
+                                (intp->symbol_rate[demod] < 10000000))
+                        msleep(50);
+                else
+                        msleep(5);
 
-                        if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) {
-                                if (i_params->dmd2_srch_algo != STV0900_WARM_START)
-                                        stv0900_set_bandwidth(fe, i_params->tuner2_bw);
-                        }
+                stv0900_get_lock_timeout(&timed, &timef, srate,
+                                                STV0900_WARM_START);
 
-                        if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000))
-                                msleep(50);
-                        else
-                                msleep(5);
-
-                        stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START);
-                        if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) {
-                                stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
-                                stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
-                                stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
-                                stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
-                                i = 0;
-                                while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) {
-                                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
-                                        stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
-                                        stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
-                                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
-                                        i++;
-                                }
+                if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
+                        stv0900_write_reg(intp, DMDISTATE, 0x1f);
+                        stv0900_write_reg(intp, CFRINIT1, freq1);
+                        stv0900_write_reg(intp, CFRINIT0, freq0);
+                        stv0900_write_reg(intp, DMDISTATE, 0x18);
+                        i = 0;
+                        while ((stv0900_get_demod_lock(intp,
+                                                        demod,
+                                                        timed / 2) == FALSE) &&
+                                                (i <= 2)) {
+                                stv0900_write_reg(intp, DMDISTATE, 0x1f);
+                                stv0900_write_reg(intp, CFRINIT1, freq1);
+                                stv0900_write_reg(intp, CFRINIT0, freq0);
+                                stv0900_write_reg(intp, DMDISTATE, 0x18);
+                                i++;
                         }
                 }
 
-                if (i_params->chip_id >= 0x20)
-                        stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
+        }
 
-                if ((i_params->dmd2_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd2_rslts.standard == STV0900_DSS_STANDARD))
-                        stv0900_set_viterbi_tracq(i_params, demod);
+        if (intp->chip_id >= 0x20)
+                stv0900_write_reg(intp, CARFREQ, 0x49);
+
+        if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
+                        (intp->result[demod].standard == STV0900_DSS_STANDARD))
+                stv0900_set_viterbi_tracq(intp, demod);
 
-                break;
-        }
 }
 
-static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv0900_demod_num demod, s32 time_out)
+static int stv0900_get_fec_lock(struct stv0900_internal *intp,
+                                enum fe_stv0900_demod_num demod, s32 time_out)
 {
-        s32 timer = 0, lock = 0, header_field, pktdelin_field, lock_vit_field;
+        s32 timer = 0, lock = 0;
 
         enum fe_stv0900_search_state dmd_state;
 
-        dprintk(KERN_INFO "%s\n", __func__);
-
-        dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
-        dmd_reg(pktdelin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
-        dmd_reg(lock_vit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
+        dprintk("%s\n", __func__);
 
-        dmd_state = stv0900_get_bits(i_params, header_field);
+        dmd_state = stv0900_get_bits(intp, HEADER_MODE);
 
         while ((timer < time_out) && (lock == 0)) {
                 switch (dmd_state) {
@@ -1386,10 +1050,10 @@ static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv09
                         lock = 0;
                         break;
                 case STV0900_DVBS2_FOUND:
-                        lock = stv0900_get_bits(i_params, pktdelin_field);
+                        lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
                         break;
                 case STV0900_DVBS_FOUND:
-                        lock = stv0900_get_bits(i_params, lock_vit_field);
+                        lock = stv0900_get_bits(intp, LOCKEDVIT);
                         break;
                 }
 
@@ -1400,46 +1064,44 @@ static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv09
         }
 
         if (lock)
-                dprintk("DEMOD FEC LOCK OK\n");
+                dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
         else
-                dprintk("DEMOD FEC LOCK FAIL\n");
+                dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
 
         return lock;
 }
 
-static int stv0900_wait_for_lock(struct stv0900_internal *i_params,
+static int stv0900_wait_for_lock(struct stv0900_internal *intp,
                                 enum fe_stv0900_demod_num demod,
                                 s32 dmd_timeout, s32 fec_timeout)
 {
 
-        s32 timer = 0, lock = 0, str_merg_rst_fld, str_merg_lock_fld;
+        s32 timer = 0, lock = 0;
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
-        dmd_reg(str_merg_rst_fld, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
-        dmd_reg(str_merg_lock_fld, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
-
-        lock = stv0900_get_demod_lock(i_params, demod, dmd_timeout);
+        lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
 
         if (lock)
-                lock = lock && stv0900_get_fec_lock(i_params, demod, fec_timeout);
+                lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout);
 
         if (lock) {
                 lock = 0;
 
-                dprintk(KERN_INFO "%s: Timer = %d, time_out = %d\n", __func__, timer, fec_timeout);
+                dprintk("%s: Timer = %d, time_out = %d\n",
+                                __func__, timer, fec_timeout);
 
                 while ((timer < fec_timeout) && (lock == 0)) {
-                        lock = stv0900_get_bits(i_params, str_merg_lock_fld);
+                        lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
                         msleep(1);
                         timer++;
                 }
         }
 
         if (lock)
-                dprintk(KERN_INFO "%s: DEMOD LOCK OK\n", __func__);
+                dprintk("%s: DEMOD LOCK OK\n", __func__);
         else
-                dprintk(KERN_INFO "%s: DEMOD LOCK FAIL\n", __func__);
+                dprintk("%s: DEMOD LOCK FAIL\n", __func__);
 
         if (lock)
                 return TRUE;
@@ -1451,43 +1113,43 @@ enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
                                                 enum fe_stv0900_demod_num demod)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_tracking_standard fnd_standard;
-        s32 state_field,
-        dss_dvb_field;
-
-        dprintk(KERN_INFO "%s\n", __func__);
 
-        dmd_reg(state_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
-        dmd_reg(dss_dvb_field, F0900_P1_DSS_DVB, F0900_P2_DSS_DVB);
+        int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
 
-        if (stv0900_get_bits(i_params, state_field) == 2)
+        switch (hdr_mode) {
+        case 2:
                 fnd_standard = STV0900_DVBS2_STANDARD;
-
-        else if (stv0900_get_bits(i_params, state_field) == 3) {
-                if (stv0900_get_bits(i_params, dss_dvb_field) == 1)
+                break;
+        case 3:
+                if (stv0900_get_bits(intp, DSS_DVB) == 1)
                         fnd_standard = STV0900_DSS_STANDARD;
                 else
                         fnd_standard = STV0900_DVBS1_STANDARD;
-        } else
+
+                break;
+        default:
                 fnd_standard = STV0900_UNKNOWN_STANDARD;
+        }
+
+        dprintk("%s: standard %d\n", __func__, fnd_standard);
 
         return fnd_standard;
 }
 
-static s32 stv0900_get_carr_freq(struct stv0900_internal *i_params, u32 mclk,
+static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
                                         enum fe_stv0900_demod_num demod)
 {
-        s32 cfr_field2, cfr_field1, cfr_field0,
-                derot, rem1, rem2, intval1, intval2;
-
-        dmd_reg(cfr_field2, F0900_P1_CAR_FREQ2, F0900_P2_CAR_FREQ2);
-        dmd_reg(cfr_field1, F0900_P1_CAR_FREQ1, F0900_P2_CAR_FREQ1);
-        dmd_reg(cfr_field0, F0900_P1_CAR_FREQ0, F0900_P2_CAR_FREQ0);
+        s32     derot,
+                rem1,
+                rem2,
+                intval1,
+                intval2;
 
-        derot = (stv0900_get_bits(i_params, cfr_field2) << 16) +
-                (stv0900_get_bits(i_params, cfr_field1) << 8) +
-                (stv0900_get_bits(i_params, cfr_field0));
+        derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
+                (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
+                (stv0900_get_bits(intp, CAR_FREQ0));
 
         derot = ge2comp(derot, 24);
         intval1 = mclk >> 12;
@@ -1505,7 +1167,7 @@ static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
 {
         struct dvb_frontend_ops *frontend_ops = NULL;
         struct dvb_tuner_ops *tuner_ops = NULL;
-        u32 frequency = 0;
+        u32 freq = 0;
 
         if (&fe->ops)
                 frontend_ops = &fe->ops;
@@ -1514,304 +1176,170 @@ static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
                 tuner_ops = &frontend_ops->tuner_ops;
 
         if (tuner_ops->get_frequency) {
-                if ((tuner_ops->get_frequency(fe, &frequency)) < 0)
+                if ((tuner_ops->get_frequency(fe, &freq)) < 0)
                         dprintk("%s: Invalid parameter\n", __func__);
                 else
-                        dprintk("%s: Frequency=%d\n", __func__, frequency);
+                        dprintk("%s: Frequency=%d\n", __func__, freq);
 
         }
 
-        return frequency;
-}
-
-static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *i_params,
-                                                enum fe_stv0900_demod_num demod)
-{
-        s32 rate_fld, vit_curpun_fld;
-        enum fe_stv0900_fec prate;
-
-        dmd_reg(vit_curpun_fld, F0900_P1_VIT_CURPUN, F0900_P2_VIT_CURPUN);
-        rate_fld = stv0900_get_bits(i_params, vit_curpun_fld);
-
-        switch (rate_fld) {
-        case 13:
-                prate = STV0900_FEC_1_2;
-                break;
-        case 18:
-                prate = STV0900_FEC_2_3;
-                break;
-        case 21:
-                prate = STV0900_FEC_3_4;
-                break;
-        case 24:
-                prate = STV0900_FEC_5_6;
-                break;
-        case 25:
-                prate = STV0900_FEC_6_7;
-                break;
-        case 26:
-                prate = STV0900_FEC_7_8;
-                break;
-        default:
-                prate = STV0900_FEC_UNKNOWN;
-                break;
-        }
-
-        return prate;
+        return freq;
 }
 
-static enum fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
+static enum
+fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
         enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
-        s32 offsetFreq,
-        srate_offset,
-        i = 0;
+        struct stv0900_signal_info *result = &intp->result[demod];
+        s32     offsetFreq,
+                srate_offset;
+        int     i = 0,
+                d = demod;
 
         u8 timing;
 
         msleep(5);
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
-                        timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2);
-                        i = 0;
-                        stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x5c);
-
-                        while ((i <= 50) && (timing != 0) && (timing != 0xFF)) {
-                                timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2);
-                                msleep(5);
-                                i += 5;
-                        }
-                }
-
-                i_params->dmd1_rslts.standard = stv0900_get_standard(fe, demod);
-                i_params->dmd1_rslts.frequency = stv0900_get_tuner_freq(fe);
-                offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000;
-                i_params->dmd1_rslts.frequency += offsetFreq;
-                i_params->dmd1_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
-                srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd1_rslts.symbol_rate, demod);
-                i_params->dmd1_rslts.symbol_rate += srate_offset;
-                i_params->dmd1_rslts.fec = stv0900_get_vit_fec(i_params, demod);
-                i_params->dmd1_rslts.modcode = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD);
-                i_params->dmd1_rslts.pilot = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01;
-                i_params->dmd1_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE)) >> 1;
-                i_params->dmd1_rslts.rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS);
-                switch (i_params->dmd1_rslts.standard) {
-                case STV0900_DVBS2_STANDARD:
-                        i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_SPECINV_DEMOD);
-                        if (i_params->dmd1_rslts.modcode <= STV0900_QPSK_910)
-                                i_params->dmd1_rslts.modulation = STV0900_QPSK;
-                        else if (i_params->dmd1_rslts.modcode <= STV0900_8PSK_910)
-                                i_params->dmd1_rslts.modulation = STV0900_8PSK;
-                        else if (i_params->dmd1_rslts.modcode <= STV0900_16APSK_910)
-                                i_params->dmd1_rslts.modulation = STV0900_16APSK;
-                        else if (i_params->dmd1_rslts.modcode <= STV0900_32APSK_910)
-                                i_params->dmd1_rslts.modulation = STV0900_32APSK;
-                        else
-                                i_params->dmd1_rslts.modulation = STV0900_UNKNOWN;
-                        break;
-                case STV0900_DVBS1_STANDARD:
-                case STV0900_DSS_STANDARD:
-                        i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_IQINV);
-                        i_params->dmd1_rslts.modulation = STV0900_QPSK;
-                        break;
-                default:
-                        break;
+        if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
+                timing = stv0900_read_reg(intp, TMGREG2);
+                i = 0;
+                stv0900_write_reg(intp, SFRSTEP, 0x5c);
+
+                while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
+                        timing = stv0900_read_reg(intp, TMGREG2);
+                        msleep(5);
+                        i += 5;
                 }
+        }
 
-                if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000)) {
-                        offsetFreq =    i_params->dmd1_rslts.frequency - i_params->tuner1_freq;
-                        i_params->tuner1_freq = stv0900_get_tuner_freq(fe);
-                        if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500))
-                                range = STV0900_RANGEOK;
-                        else
-                                if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd1_rslts.symbol_rate, i_params->dmd1_rslts.rolloff) / 2000))
-                                        range = STV0900_RANGEOK;
-                                else
-                                        range = STV0900_OUTOFRANGE;
-
-                } else {
-                        if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500))
-                                range = STV0900_RANGEOK;
-                        else
-                                range = STV0900_OUTOFRANGE;
-                }
+        result->standard = stv0900_get_standard(fe, d);
+        if (intp->tuner_type[demod] == 3)
+                result->frequency = stv0900_get_freq_auto(intp, d);
+        else
+                result->frequency = stv0900_get_tuner_freq(fe);
+
+        offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
+        result->frequency += offsetFreq;
+        result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
+        srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
+        result->symbol_rate += srate_offset;
+        result->fec = stv0900_get_vit_fec(intp, d);
+        result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
+        result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
+        result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
+        result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
+
+        dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
+
+        switch (result->standard) {
+        case STV0900_DVBS2_STANDARD:
+                result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
+                if (result->modcode <= STV0900_QPSK_910)
+                        result->modulation = STV0900_QPSK;
+                else if (result->modcode <= STV0900_8PSK_910)
+                        result->modulation = STV0900_8PSK;
+                else if (result->modcode <= STV0900_16APSK_910)
+                        result->modulation = STV0900_16APSK;
+                else if (result->modcode <= STV0900_32APSK_910)
+                        result->modulation = STV0900_32APSK;
+                else
+                        result->modulation = STV0900_UNKNOWN;
                 break;
-        case STV0900_DEMOD_2:
-                if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
-                        timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2);
-                        i = 0;
-                        stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x5c);
-
-                        while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
-                                timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2);
-                                msleep(5);
-                                i += 5;
-                        }
-                }
+        case STV0900_DVBS1_STANDARD:
+        case STV0900_DSS_STANDARD:
+                result->spectrum = stv0900_get_bits(intp, IQINV);
+                result->modulation = STV0900_QPSK;
+                break;
+        default:
+                break;
+        }
 
-                i_params->dmd2_rslts.standard = stv0900_get_standard(fe, demod);
-                i_params->dmd2_rslts.frequency = stv0900_get_tuner_freq(fe);
-                offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000;
-                i_params->dmd2_rslts.frequency += offsetFreq;
-                i_params->dmd2_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
-                srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd2_rslts.symbol_rate, demod);
-                i_params->dmd2_rslts.symbol_rate += srate_offset;
-                i_params->dmd2_rslts.fec = stv0900_get_vit_fec(i_params, demod);
-                i_params->dmd2_rslts.modcode = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
-                i_params->dmd2_rslts.pilot = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
-                i_params->dmd2_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE)) >> 1;
-                i_params->dmd2_rslts.rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS);
-                switch (i_params->dmd2_rslts.standard) {
-                case STV0900_DVBS2_STANDARD:
-                        i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_SPECINV_DEMOD);
-                        if (i_params->dmd2_rslts.modcode <= STV0900_QPSK_910)
-                                i_params->dmd2_rslts.modulation = STV0900_QPSK;
-                        else if (i_params->dmd2_rslts.modcode <= STV0900_8PSK_910)
-                                i_params->dmd2_rslts.modulation = STV0900_8PSK;
-                        else if (i_params->dmd2_rslts.modcode <= STV0900_16APSK_910)
-                                i_params->dmd2_rslts.modulation = STV0900_16APSK;
-                        else if (i_params->dmd2_rslts.modcode <= STV0900_32APSK_910)
-                                i_params->dmd2_rslts.modulation = STV0900_32APSK;
-                        else
-                                i_params->dmd2_rslts.modulation = STV0900_UNKNOWN;
-                        break;
-                case STV0900_DVBS1_STANDARD:
-                case STV0900_DSS_STANDARD:
-                        i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_IQINV);
-                        i_params->dmd2_rslts.modulation = STV0900_QPSK;
-                        break;
-                default:
-                        break;
-                }
+        if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
+                                (intp->symbol_rate[d] < 10000000)) {
+                offsetFreq = result->frequency - intp->freq[d];
+                if (intp->tuner_type[demod] == 3)
+                        intp->freq[d] = stv0900_get_freq_auto(intp, d);
+                else
+                        intp->freq[d] = stv0900_get_tuner_freq(fe);
 
-                if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000)) {
-                        offsetFreq =    i_params->dmd2_rslts.frequency - i_params->tuner2_freq;
-                        i_params->tuner2_freq = stv0900_get_tuner_freq(fe);
+                if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
+                        range = STV0900_RANGEOK;
+                else if (ABS(offsetFreq) <=
+                                (stv0900_carrier_width(result->symbol_rate,
+                                                result->rolloff) / 2000))
+                        range = STV0900_RANGEOK;
 
-                        if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500))
-                                range = STV0900_RANGEOK;
-                        else
-                                if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd2_rslts.symbol_rate, i_params->dmd2_rslts.rolloff) / 2000))
-                                        range = STV0900_RANGEOK;
-                                else
-                                        range = STV0900_OUTOFRANGE;
-                } else {
-                        if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500))
-                                range = STV0900_RANGEOK;
-                        else
-                                range = STV0900_OUTOFRANGE;
-                }
+        } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
+                range = STV0900_RANGEOK;
 
-                break;
-        }
+        dprintk("%s: range %d\n", __func__, range);
 
         return range;
 }
 
-static enum fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
+static enum
+fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
-
-        s32 srate, demod_timeout,
-                fec_timeout, freq1, freq0;
         enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
 
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                i_params->dmd1_rslts.locked = FALSE;
-                if (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) {
-                        srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
-                        srate += stv0900_get_timing_offst(i_params, srate, demod);
-                        if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH)
-                                stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
-
-                        stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START);
-                        freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2);
-                        freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1);
-                        stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
-                        stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED);
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
-                        stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
-                        stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
-                        if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
-                                i_params->dmd1_rslts.locked = TRUE;
-                                signal_type = stv0900_get_signal_params(fe);
-                                stv0900_track_optimization(fe);
-                        } else {
-                                stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL);
-                                stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1c);
-                                stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
-                                stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
-                                stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
-                                if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
-                                        i_params->dmd1_rslts.locked = TRUE;
-                                        signal_type = stv0900_get_signal_params(fe);
-                                        stv0900_track_optimization(fe);
-                                }
-
-                        }
-
-                } else
-                        i_params->dmd1_rslts.locked = FALSE;
-
-                break;
-        case STV0900_DEMOD_2:
-                i_params->dmd2_rslts.locked = FALSE;
-                if (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) {
-                        srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
-                        srate += stv0900_get_timing_offst(i_params, srate, demod);
-
-                        if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH)
-                                stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
-
-                        stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START);
-                        freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2);
-                        freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1);
-                        stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
-                        stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED);
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
-                        stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
-                        stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
-
-                        if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
-                                i_params->dmd2_rslts.locked = TRUE;
+        s32     srate,
+                demod_timeout,
+                fec_timeout,
+                freq1,
+                freq0;
+
+        intp->result[demod].locked = FALSE;
+
+        if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
+                srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
+                srate += stv0900_get_timing_offst(intp, srate, demod);
+                if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
+                        stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
+
+                stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
+                                        srate, STV0900_WARM_START);
+                freq1 = stv0900_read_reg(intp, CFR2);
+                freq0 = stv0900_read_reg(intp, CFR1);
+                stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
+                stv0900_write_bits(intp, SPECINV_CONTROL,
+                                        STV0900_IQ_FORCE_SWAPPED);
+                stv0900_write_reg(intp, DMDISTATE, 0x1c);
+                stv0900_write_reg(intp, CFRINIT1, freq1);
+                stv0900_write_reg(intp, CFRINIT0, freq0);
+                stv0900_write_reg(intp, DMDISTATE, 0x18);
+                if (stv0900_wait_for_lock(intp, demod,
+                                demod_timeout, fec_timeout) == TRUE) {
+                        intp->result[demod].locked = TRUE;
+                        signal_type = stv0900_get_signal_params(fe);
+                        stv0900_track_optimization(fe);
+                } else {
+                        stv0900_write_bits(intp, SPECINV_CONTROL,
+                                        STV0900_IQ_FORCE_NORMAL);
+                        stv0900_write_reg(intp, DMDISTATE, 0x1c);
+                        stv0900_write_reg(intp, CFRINIT1, freq1);
+                        stv0900_write_reg(intp, CFRINIT0, freq0);
+                        stv0900_write_reg(intp, DMDISTATE, 0x18);
+                        if (stv0900_wait_for_lock(intp, demod,
+                                        demod_timeout, fec_timeout) == TRUE) {
+                                intp->result[demod].locked = TRUE;
                                 signal_type = stv0900_get_signal_params(fe);
                                 stv0900_track_optimization(fe);
-                        } else {
-                                stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL);
-                                stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1c);
-                                stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
-                                stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
-                                stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
-
-                                if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
-                                        i_params->dmd2_rslts.locked = TRUE;
-                                        signal_type = stv0900_get_signal_params(fe);
-                                        stv0900_track_optimization(fe);
-                                }
-
                         }
 
-                } else
-                        i_params->dmd1_rslts.locked = FALSE;
+                }
 
-                break;
-        }
+        } else
+                intp->result[demod].locked = FALSE;
 
         return signal_type;
 }
 
-static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
+static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
                                         enum fe_stv0900_demod_num demod)
 {
         u32 minagc2level = 0xffff,
@@ -1820,105 +1348,54 @@ static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
 
         s32 i, j, nb_steps, direction;
 
-        dprintk(KERN_INFO "%s\n", __func__);
-
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
-                stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1);
-                stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1);
-
-                stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83);
-                stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0);
-
-                stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82);
-                stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0);
-                stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0);
+        dprintk("%s\n", __func__);
 
-                stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
-                nb_steps = -1 + (i_params->dmd1_srch_range / 1000000);
-                nb_steps /= 2;
-                nb_steps = (2 * nb_steps) + 1;
+        stv0900_write_reg(intp, AGC2REF, 0x38);
+        stv0900_write_bits(intp, SCAN_ENABLE, 0);
+        stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
 
-                if (nb_steps < 0)
-                        nb_steps = 1;
+        stv0900_write_bits(intp, AUTO_GUP, 1);
+        stv0900_write_bits(intp, AUTO_GLOW, 1);
 
-                direction = 1;
+        stv0900_write_reg(intp, DMDT0M, 0x0);
 
-                freq_step = (1000000 << 8) / (i_params->mclk >> 8);
+        stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
+        nb_steps = -1 + (intp->srch_range[demod] / 1000000);
+        nb_steps /= 2;
+        nb_steps = (2 * nb_steps) + 1;
 
-                init_freq = 0;
+        if (nb_steps < 0)
+                nb_steps = 1;
 
-                for (i = 0; i < nb_steps; i++) {
-                        if (direction > 0)
-                                init_freq = init_freq + (freq_step * i);
-                        else
-                                init_freq = init_freq - (freq_step * i);
+        direction = 1;
 
-                        direction *= -1;
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C);
-                        stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (init_freq >> 8) & 0xff);
-                        stv0900_write_reg(i_params, R0900_P1_CFRINIT0, init_freq  & 0xff);
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x58);
-                        msleep(10);
-                        agc2level = 0;
+        freq_step = (1000000 << 8) / (intp->mclk >> 8);
 
-                        for (j = 0; j < 10; j++)
-                                agc2level += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
-                                                | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
+        init_freq = 0;
 
-                        agc2level /= 10;
-
-                        if (agc2level < minagc2level)
-                                minagc2level = agc2level;
-                }
-                break;
-        case STV0900_DEMOD_2:
-                stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
-                stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
-                stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
-                stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
-                stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
-                stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
-                stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
-                stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
-                stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
-                nb_steps = -1 + (i_params->dmd2_srch_range / 1000000);
-                nb_steps /= 2;
-                nb_steps = (2 * nb_steps) + 1;
-
-                if (nb_steps < 0)
-                        nb_steps = 1;
-
-                direction = 1;
-                freq_step = (1000000 << 8) / (i_params->mclk >> 8);
-                init_freq = 0;
-                for (i = 0; i < nb_steps; i++) {
-                        if (direction > 0)
-                                init_freq = init_freq + (freq_step * i);
-                        else
-                                init_freq = init_freq - (freq_step * i);
+        for (i = 0; i < nb_steps; i++) {
+                if (direction > 0)
+                        init_freq = init_freq + (freq_step * i);
+                else
+                        init_freq = init_freq - (freq_step * i);
 
-                        direction *= -1;
+                direction *= -1;
+                stv0900_write_reg(intp, DMDISTATE, 0x5C);
+                stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
+                stv0900_write_reg(intp, CFRINIT0, init_freq  & 0xff);
+                stv0900_write_reg(intp, DMDISTATE, 0x58);
+                msleep(10);
+                agc2level = 0;
 
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C);
-                        stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (init_freq >> 8) & 0xff);
-                        stv0900_write_reg(i_params, R0900_P2_CFRINIT0, init_freq  & 0xff);
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x58);
+                for (j = 0; j < 10; j++)
+                        agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
+                                        | stv0900_read_reg(intp, AGC2I0);
 
-                        msleep(10);
-                        agc2level = 0;
-                        for (j = 0; j < 10; j++)
-                                agc2level += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
-                                                | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
+                agc2level /= 10;
 
-                        agc2level /= 10;
+                if (agc2level < minagc2level)
+                        minagc2level = agc2level;
 
-                        if (agc2level < minagc2level)
-                                minagc2level = agc2level;
-                }
-                break;
         }
 
         return (u16)minagc2level;
@@ -1927,336 +1404,197 @@ static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
 static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
-        int timingLock = FALSE;
+        int timing_lck = FALSE;
         s32 i, timingcpt = 0,
                 direction = 1,
                 nb_steps,
                 current_step = 0,
                 tuner_freq;
+        u32 agc2_th,
+                coarse_srate = 0,
+                agc2_integr = 0,
+                currier_step = 1200;
 
-        u32 coarse_srate = 0, agc2_integr = 0, currier_step = 1200;
-
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1F);
-                stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0x12);
-                stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xf0);
-                stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xe0);
-                stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1);
-                stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1);
-                stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83);
-                stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0);
-                stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82);
-                stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0);
-                stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0);
-                stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x50);
-
-                if (i_params->chip_id >= 0x20) {
-                        stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x6a);
-                        stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x95);
-                } else {
-                        stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
-                        stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x73);
-                }
+        if (intp->chip_id >= 0x30)
+                agc2_th = 0x2e00;
+        else
+                agc2_th = 0x1f00;
+
+        stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
+        stv0900_write_reg(intp, TMGCFG, 0x12);
+        stv0900_write_reg(intp, TMGTHRISE, 0xf0);
+        stv0900_write_reg(intp, TMGTHFALL, 0xe0);
+        stv0900_write_bits(intp, SCAN_ENABLE, 1);
+        stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
+        stv0900_write_reg(intp, SFRUP1, 0x83);
+        stv0900_write_reg(intp, SFRUP0, 0xc0);
+        stv0900_write_reg(intp, SFRLOW1, 0x82);
+        stv0900_write_reg(intp, SFRLOW0, 0xa0);
+        stv0900_write_reg(intp, DMDT0M, 0x0);
+        stv0900_write_reg(intp, AGC2REF, 0x50);
+
+        if (intp->chip_id >= 0x30) {
+                stv0900_write_reg(intp, CARFREQ, 0x99);
+                stv0900_write_reg(intp, SFRSTEP, 0x98);
+        } else if (intp->chip_id >= 0x20) {
+                stv0900_write_reg(intp, CARFREQ, 0x6a);
+                stv0900_write_reg(intp, SFRSTEP, 0x95);
+        } else {
+                stv0900_write_reg(intp, CARFREQ, 0xed);
+                stv0900_write_reg(intp, SFRSTEP, 0x73);
+        }
 
-                if (i_params->dmd1_symbol_rate <= 2000000)
-                        currier_step = 1000;
-                else if (i_params->dmd1_symbol_rate <= 5000000)
-                        currier_step = 2000;
-                else if (i_params->dmd1_symbol_rate <= 12000000)
-                        currier_step = 3000;
-                else
+        if (intp->symbol_rate[demod] <= 2000000)
+                currier_step = 1000;
+        else if (intp->symbol_rate[demod] <= 5000000)
+                currier_step = 2000;
+        else if (intp->symbol_rate[demod] <= 12000000)
+                currier_step = 3000;
+        else
                         currier_step = 5000;
 
-                nb_steps = -1 + ((i_params->dmd1_srch_range / 1000) / currier_step);
-                nb_steps /= 2;
-                nb_steps = (2 * nb_steps) + 1;
-
-                if (nb_steps < 0)
-                        nb_steps = 1;
-
-                else if (nb_steps > 10) {
-                        nb_steps = 11;
-                        currier_step = (i_params->dmd1_srch_range / 1000) / 10;
-                }
-
-                current_step = 0;
-
-                direction = 1;
-                tuner_freq = i_params->tuner1_freq;
-
-                while ((timingLock == FALSE) && (current_step < nb_steps)) {
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5F);
-                        stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x0);
-
-                        msleep(50);
-
-                        for (i = 0; i < 10; i++) {
-                                if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2)
-                                        timingcpt++;
-
-                                agc2_integr += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8) | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
-
-                        }
-
-                        agc2_integr /= 10;
-                        coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
-                        current_step++;
-                        direction *= -1;
-
-                        dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n", tuner_freq, agc2_integr, coarse_srate, timingcpt);
+        nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
+        nb_steps /= 2;
+        nb_steps = (2 * nb_steps) + 1;
 
-                        if ((timingcpt >= 5) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000)) {
-                                timingLock = TRUE;
-                        }
-
-                        else if (current_step < nb_steps) {
-                                if (direction > 0)
-                                        tuner_freq += (current_step * currier_step);
-                                else
-                                        tuner_freq -= (current_step * currier_step);
+        if (nb_steps < 0)
+                nb_steps = 1;
+        else if (nb_steps > 10) {
+                nb_steps = 11;
+                currier_step = (intp->srch_range[demod] / 1000) / 10;
+        }
 
-                                stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw);
-                        }
-                }
+        current_step = 0;
+        direction = 1;
 
-                if (timingLock == FALSE)
-                        coarse_srate = 0;
-                else
-                        coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
-                break;
-        case STV0900_DEMOD_2:
-                stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1F);
-                stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0x12);
-                stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xf0);
-                stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xe0);
-                stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
-                stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
-                stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
-                stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
-                stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
-                stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
-                stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
-                stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x50);
-
-                if (i_params->chip_id >= 0x20) {
-                        stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x6a);
-                        stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x95);
-                } else {
-                        stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
-                        stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x73);
-                }
+        tuner_freq = intp->freq[demod];
 
-                if (i_params->dmd2_symbol_rate <= 2000000)
-                        currier_step = 1000;
-                else if (i_params->dmd2_symbol_rate <= 5000000)
-                        currier_step = 2000;
-                else if (i_params->dmd2_symbol_rate <= 12000000)
-                        currier_step = 3000;
-                else
-                        currier_step = 5000;
+        while ((timing_lck == FALSE) && (current_step < nb_steps)) {
+                stv0900_write_reg(intp, DMDISTATE, 0x5f);
+                stv0900_write_bits(intp, DEMOD_MODE, 0);
 
+                msleep(50);
 
-                nb_steps = -1 + ((i_params->dmd2_srch_range / 1000) / currier_step);
-                nb_steps /= 2;
-                nb_steps = (2 * nb_steps) + 1;
+                for (i = 0; i < 10; i++) {
+                        if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
+                                timingcpt++;
 
-                if (nb_steps < 0)
-                        nb_steps = 1;
-                else if (nb_steps > 10) {
-                        nb_steps = 11;
-                        currier_step = (i_params->dmd2_srch_range / 1000) / 10;
+                        agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
+                                        stv0900_read_reg(intp, AGC2I0);
                 }
 
-                current_step = 0;
-                direction = 1;
-                tuner_freq = i_params->tuner2_freq;
-
-                while ((timingLock == FALSE) && (current_step < nb_steps)) {
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5F);
-                        stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x0);
-
-                        msleep(50);
-                        timingcpt = 0;
-
-                        for (i = 0; i < 20; i++) {
-                                if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2)
-                                        timingcpt++;
-                                agc2_integr += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
-                                                                | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
-                        }
-
-                        agc2_integr /= 20;
-                        coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
-                        if ((timingcpt >= 10) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000))
-                                timingLock = TRUE;
-                        else {
-                                current_step++;
-                                direction *= -1;
-
-                                if (direction > 0)
-                                        tuner_freq += (current_step * currier_step);
-                                else
-                                        tuner_freq -= (current_step * currier_step);
+                agc2_integr /= 10;
+                coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
+                current_step++;
+                direction *= -1;
+
+                dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started."
+                        " tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
+                        tuner_freq, agc2_integr, coarse_srate, timingcpt);
+
+                if ((timingcpt >= 5) &&
+                                (agc2_integr < agc2_th) &&
+                                (coarse_srate < 55000000) &&
+                                (coarse_srate > 850000))
+                        timing_lck = TRUE;
+                else if (current_step < nb_steps) {
+                        if (direction > 0)
+                                tuner_freq += (current_step * currier_step);
+                        else
+                                tuner_freq -= (current_step * currier_step);
 
-                                stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw);
-                        }
+                        if (intp->tuner_type[demod] == 3)
+                                stv0900_set_tuner_auto(intp, tuner_freq,
+                                                intp->bw[demod], demod);
+                        else
+                                stv0900_set_tuner(fe, tuner_freq,
+                                                intp->bw[demod]);
                 }
-
-                if (timingLock == FALSE)
-                        coarse_srate = 0;
-                else
-                        coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
-                break;
         }
 
+        if (timing_lck == FALSE)
+                coarse_srate = 0;
+        else
+                coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
+
         return coarse_srate;
 }
 
 static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
-        u32 coarse_srate,
-        coarse_freq,
-        symb;
+        u32     coarse_srate,
+                coarse_freq,
+                symb,
+                symbmax,
+                symbmin,
+                symbcomp;
+
+        coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
+
+        if (coarse_srate > 3000000) {
+                symbmax = 13 * (coarse_srate / 10);
+                symbmax = (symbmax / 1000) * 65536;
+                symbmax /= (intp->mclk / 1000);
+
+                symbmin = 10 * (coarse_srate / 13);
+                symbmin = (symbmin / 1000)*65536;
+                symbmin /= (intp->mclk / 1000);
+
+                symb = (coarse_srate / 1000) * 65536;
+                symb /= (intp->mclk / 1000);
+        } else {
+                symbmax = 13 * (coarse_srate / 10);
+                symbmax = (symbmax / 100) * 65536;
+                symbmax /= (intp->mclk / 100);
 
-        coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
+                symbmin = 10 * (coarse_srate / 14);
+                symbmin = (symbmin / 100) * 65536;
+                symbmin /= (intp->mclk / 100);
 
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                coarse_freq = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8)
-                                                | stv0900_read_reg(i_params, R0900_P1_CFR1);
-                symb = 13 * (coarse_srate / 10);
-
-                if (symb < i_params->dmd1_symbol_rate)
-                        coarse_srate = 0;
-                else {
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
-                        stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
-                        stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20);
-                        stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x00);
-                        stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
-                        stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
-
-                        if (i_params->chip_id >= 0x20)
-                                stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49);
-                        else
-                                stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
-
-                        if (coarse_srate > 3000000) {
-                                symb = 13 * (coarse_srate / 10);
-                                symb = (symb / 1000) * 65536;
-                                symb /= (i_params->mclk / 1000);
-                                stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
-                                stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
-
-                                symb = 10 * (coarse_srate / 13);
-                                symb = (symb / 1000) * 65536;
-                                symb /= (i_params->mclk / 1000);
-
-                                stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
-                                stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
-
-                                symb = (coarse_srate / 1000) * 65536;
-                                symb /= (i_params->mclk / 1000);
-                                stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
-                                stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
-                        } else {
-                                symb = 13 * (coarse_srate / 10);
-                                symb = (symb / 100) * 65536;
-                                symb /= (i_params->mclk / 100);
-                                stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
-                                stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
-
-                                symb = 10 * (coarse_srate / 14);
-                                symb = (symb / 100) * 65536;
-                                symb /= (i_params->mclk / 100);
-                                stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
-                                stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
-
-                                symb = (coarse_srate / 100) * 65536;
-                                symb /= (i_params->mclk / 100);
-                                stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
-                                stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
-                        }
+                symb = (coarse_srate / 100) * 65536;
+                symb /= (intp->mclk / 100);
+        }
 
-                        stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20);
-                        stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (coarse_freq >> 8) & 0xff);
-                        stv0900_write_reg(i_params, R0900_P1_CFRINIT0, coarse_freq  & 0xff);
-                        stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
-                }
-                break;
-        case STV0900_DEMOD_2:
-                coarse_freq = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8)
-                                                | stv0900_read_reg(i_params, R0900_P2_CFR1);
-
-                symb = 13 * (coarse_srate / 10);
-
-                if (symb < i_params->dmd2_symbol_rate)
-                        coarse_srate = 0;
-                else {
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
-                        stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
-                        stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20);
-                        stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0x00);
-                        stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2);
-                        stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
-
-                        if (i_params->chip_id >= 0x20)
-                                stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
-                        else
-                                stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
-
-                        if (coarse_srate > 3000000) {
-                                symb = 13 * (coarse_srate / 10);
-                                symb = (symb / 1000) * 65536;
-                                symb /= (i_params->mclk / 1000);
-                                stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
-                                stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
-
-                                symb = 10 * (coarse_srate / 13);
-                                symb = (symb / 1000) * 65536;
-                                symb /= (i_params->mclk / 1000);
-
-                                stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
-                                stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
-
-                                symb = (coarse_srate / 1000) * 65536;
-                                symb /= (i_params->mclk / 1000);
-                                stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
-                                stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
-                        } else {
-                                symb = 13 * (coarse_srate / 10);
-                                symb = (symb / 100) * 65536;
-                                symb /= (i_params->mclk / 100);
-                                stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
-                                stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
-
-                                symb = 10 * (coarse_srate / 14);
-                                symb = (symb / 100) * 65536;
-                                symb /= (i_params->mclk / 100);
-                                stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
-                                stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
-
-                                symb = (coarse_srate / 100) * 65536;
-                                symb /= (i_params->mclk / 100);
-                                stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
-                                stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
-                        }
+        symbcomp = 13 * (coarse_srate / 10);
+                coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
+                                        | stv0900_read_reg(intp, CFR1);
+
+        if (symbcomp < intp->symbol_rate[demod])
+                coarse_srate = 0;
+        else {
+                stv0900_write_reg(intp, DMDISTATE, 0x1f);
+                stv0900_write_reg(intp, TMGCFG2, 0xc1);
+                stv0900_write_reg(intp, TMGTHRISE, 0x20);
+                stv0900_write_reg(intp, TMGTHFALL, 0x00);
+                stv0900_write_reg(intp, TMGCFG, 0xd2);
+                stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
+                stv0900_write_reg(intp, AGC2REF, 0x38);
+
+                if (intp->chip_id >= 0x30)
+                        stv0900_write_reg(intp, CARFREQ, 0x79);
+                else if (intp->chip_id >= 0x20)
+                        stv0900_write_reg(intp, CARFREQ, 0x49);
+                else
+                        stv0900_write_reg(intp, CARFREQ, 0xed);
 
-                        stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20);
-                        stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (coarse_freq >> 8) & 0xff);
-                        stv0900_write_reg(i_params, R0900_P2_CFRINIT0, coarse_freq  & 0xff);
-                        stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
-                }
+                stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
+                stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
 
-                break;
+                stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
+                stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
+
+                stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
+                stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
+
+                stv0900_write_reg(intp, DMDT0M, 0x20);
+                stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
+                stv0900_write_reg(intp, CFRINIT0, coarse_freq  & 0xff);
+                stv0900_write_reg(intp, DMDISTATE, 0x15);
         }
 
         return coarse_srate;
@@ -2265,163 +1603,136 @@ static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
 static int stv0900_blind_search_algo(struct dvb_frontend *fe)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
-        u8 k_ref_tmg, k_ref_tmg_max, k_ref_tmg_min;
-        u32 coarse_srate;
-        int lock = FALSE, coarse_fail = FALSE;
-        s32 demod_timeout = 500, fec_timeout = 50, kref_tmg_reg, fail_cpt, i, agc2_overflow;
-        u16 agc2_integr;
-        u8 dstatus2;
-
-        dprintk(KERN_INFO "%s\n", __func__);
-
-        if (i_params->chip_id < 0x20) {
+        u8      k_ref_tmg,
+                k_ref_tmg_max,
+                k_ref_tmg_min;
+        u32     coarse_srate,
+                agc2_th;
+        int     lock = FALSE,
+                coarse_fail = FALSE;
+        s32     demod_timeout = 500,
+                fec_timeout = 50,
+                fail_cpt,
+                i,
+                agc2_overflow;
+        u16     agc2_int;
+        u8      dstatus2;
+
+        dprintk("%s\n", __func__);
+
+        if (intp->chip_id < 0x20) {
                 k_ref_tmg_max = 233;
                 k_ref_tmg_min = 143;
         } else {
-                k_ref_tmg_max = 120;
-                k_ref_tmg_min = 30;
+                k_ref_tmg_max = 110;
+                k_ref_tmg_min = 10;
         }
 
-        agc2_integr = stv0900_blind_check_agc2_min_level(i_params, demod);
-
-        if (agc2_integr > STV0900_BLIND_SEARCH_AGC2_TH) {
-                lock = FALSE;
-
-        } else {
-                switch (demod) {
-                case STV0900_DEMOD_1:
-                default:
-                        if (i_params->chip_id == 0x10)
-                                stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xAA);
-
-                        if (i_params->chip_id < 0x20)
-                                stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
-
-                        stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xC4);
-                        stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
-
-                        if (i_params->chip_id >= 0x20) {
-                                stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
-                                stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
-                                stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
-                                stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
-                        }
-
-                        kref_tmg_reg = R0900_P1_KREFTMG;
-                        break;
-                case STV0900_DEMOD_2:
-                        if (i_params->chip_id == 0x10)
-                                stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xAA);
-
-                        if (i_params->chip_id < 0x20)
-                                stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
+        if (intp->chip_id <= 0x20)
+                agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
+        else
+                agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
 
-                        stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xC4);
-                        stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
+        agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
 
-                        if (i_params->chip_id >= 0x20) {
-                                stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41);
-                                stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
-                                stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
-                                stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
-                        }
+        dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
+        if (agc2_int > agc2_th)
+                return FALSE;
 
-                        kref_tmg_reg = R0900_P2_KREFTMG;
-                        break;
-                }
+        if (intp->chip_id == 0x10)
+                stv0900_write_reg(intp, CORRELEXP, 0xaa);
 
-                k_ref_tmg = k_ref_tmg_max;
+        if (intp->chip_id < 0x20)
+                stv0900_write_reg(intp, CARHDR, 0x55);
+        else
+                stv0900_write_reg(intp, CARHDR, 0x20);
 
-                do {
-                        stv0900_write_reg(i_params, kref_tmg_reg, k_ref_tmg);
-                        if (stv0900_search_srate_coarse(fe) != 0) {
-                                coarse_srate = stv0900_search_srate_fine(fe);
+        if (intp->chip_id <= 0x20)
+                stv0900_write_reg(intp, CARCFG, 0xc4);
+        else
+                stv0900_write_reg(intp, CARCFG, 0x6);
 
-                                if (coarse_srate != 0) {
-                                        stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, coarse_srate, STV0900_BLIND_SEARCH);
-                                        lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
-                                } else
-                                        lock = FALSE;
-                        } else {
-                                fail_cpt = 0;
-                                agc2_overflow = 0;
+        stv0900_write_reg(intp, RTCS2, 0x44);
 
-                                switch (demod) {
-                                case STV0900_DEMOD_1:
-                                default:
-                                        for (i = 0; i < 10; i++) {
-                                                agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
-                                                                | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
+        if (intp->chip_id >= 0x20) {
+                stv0900_write_reg(intp, EQUALCFG, 0x41);
+                stv0900_write_reg(intp, FFECFG, 0x41);
+                stv0900_write_reg(intp, VITSCALE, 0x82);
+                stv0900_write_reg(intp, VAVSRVIT, 0x0);
+        }
 
-                                                if (agc2_integr >= 0xff00)
-                                                        agc2_overflow++;
+        k_ref_tmg = k_ref_tmg_max;
 
-                                                dstatus2 = stv0900_read_reg(i_params, R0900_P1_DSTATUS2);
+        do {
+                stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
+                if (stv0900_search_srate_coarse(fe) != 0) {
+                        coarse_srate = stv0900_search_srate_fine(fe);
+
+                        if (coarse_srate != 0) {
+                                stv0900_get_lock_timeout(&demod_timeout,
+                                                        &fec_timeout,
+                                                        coarse_srate,
+                                                        STV0900_BLIND_SEARCH);
+                                lock = stv0900_get_demod_lock(intp,
+                                                        demod,
+                                                        demod_timeout);
+                        } else
+                                lock = FALSE;
+                } else {
+                        fail_cpt = 0;
+                        agc2_overflow = 0;
 
-                                                if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1))
-                                                        fail_cpt++;
-                                        }
-                                        break;
-                                case STV0900_DEMOD_2:
-                                        for (i = 0; i < 10; i++) {
-                                                agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
-                                                                | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
+                        for (i = 0; i < 10; i++) {
+                                agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
+                                        | stv0900_read_reg(intp, AGC2I0);
 
-                                                if (agc2_integr >= 0xff00)
-                                                        agc2_overflow++;
+                                if (agc2_int >= 0xff00)
+                                        agc2_overflow++;
 
-                                                dstatus2 = stv0900_read_reg(i_params, R0900_P2_DSTATUS2);
+                                dstatus2 = stv0900_read_reg(intp, DSTATUS2);
 
-                                                if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1))
-                                                        fail_cpt++;
-                                        }
-                                        break;
-                                }
+                                if (((dstatus2 & 0x1) == 0x1) &&
+                                                ((dstatus2 >> 7) == 1))
+                                        fail_cpt++;
+                        }
 
-                                if ((fail_cpt > 7) || (agc2_overflow > 7))
-                                        coarse_fail = TRUE;
+                        if ((fail_cpt > 7) || (agc2_overflow > 7))
+                                coarse_fail = TRUE;
 
-                                lock = FALSE;
-                        }
-                        k_ref_tmg -= 30;
-                } while ((k_ref_tmg >= k_ref_tmg_min) && (lock == FALSE) && (coarse_fail == FALSE));
-        }
+                        lock = FALSE;
+                }
+                k_ref_tmg -= 30;
+        } while ((k_ref_tmg >= k_ref_tmg_min) &&
+                                (lock == FALSE) &&
+                                (coarse_fail == FALSE));
 
         return lock;
 }
 
-static void stv0900_set_viterbi_acq(struct stv0900_internal *i_params,
+static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
                                         enum fe_stv0900_demod_num demod)
 {
-        s32 vth_reg;
+        s32 vth_reg = VTH12;
 
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
-        dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12);
-
-        stv0900_write_reg(i_params, vth_reg++, 0x96);
-        stv0900_write_reg(i_params, vth_reg++, 0x64);
-        stv0900_write_reg(i_params, vth_reg++, 0x36);
-        stv0900_write_reg(i_params, vth_reg++, 0x23);
-        stv0900_write_reg(i_params, vth_reg++, 0x1E);
-        stv0900_write_reg(i_params, vth_reg++, 0x19);
+        stv0900_write_reg(intp, vth_reg++, 0x96);
+        stv0900_write_reg(intp, vth_reg++, 0x64);
+        stv0900_write_reg(intp, vth_reg++, 0x36);
+        stv0900_write_reg(intp, vth_reg++, 0x23);
+        stv0900_write_reg(intp, vth_reg++, 0x1e);
+        stv0900_write_reg(intp, vth_reg++, 0x19);
 }
 
-static void stv0900_set_search_standard(struct stv0900_internal *i_params,
+static void stv0900_set_search_standard(struct stv0900_internal *intp,
                                         enum fe_stv0900_demod_num demod)
 {
 
-        int sstndrd;
-
-        dprintk(KERN_INFO "%s\n", __func__);
+        dprintk("%s\n", __func__);
 
-        sstndrd = i_params->dmd1_srch_standard;
-        if (demod == 1)
-                sstndrd = i_params->dmd2_srch_stndrd;
-
-        switch (sstndrd) {
+        switch (intp->srch_standard[demod]) {
         case STV0900_SEARCH_DVBS1:
                 dprintk("Search Standard = DVBS1\n");
                 break;
@@ -2436,129 +1747,74 @@ static void stv0900_set_search_standard(struct stv0900_internal *i_params,
                 break;
         }
 
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                switch (i_params->dmd1_srch_standard) {
-                case STV0900_SEARCH_DVBS1:
-                case STV0900_SEARCH_DSS:
-                        stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
-
-                        stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0);
-                        stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
-                        stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
-                        stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x22);
-
-                        stv0900_set_viterbi_acq(i_params, demod);
-                        stv0900_set_viterbi_standard(i_params,
-                                                i_params->dmd1_srch_standard,
-                                                i_params->dmd1_fec, demod);
-
-                        break;
-                case STV0900_SEARCH_DVBS2:
-                        stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 1);
-                        stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
-                        stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
-                        stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
-                        if (i_params->demod_mode != STV0900_SINGLE) {
-                                if (i_params->chip_id <= 0x11)
-                                        stv0900_stop_all_s2_modcod(i_params, demod);
-                                else
-                                        stv0900_activate_s2_modcode(i_params, demod);
-
-                        } else
-                                stv0900_activate_s2_modcode_single(i_params, demod);
-
-                        stv0900_set_viterbi_tracq(i_params, demod);
-
-                        break;
-                case STV0900_AUTO_SEARCH:
-                default:
-                        stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0);
-                        stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
-                        stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
-                        stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
-                        if (i_params->demod_mode != STV0900_SINGLE) {
-                                if (i_params->chip_id <= 0x11)
-                                        stv0900_stop_all_s2_modcod(i_params, demod);
-                                else
-                                        stv0900_activate_s2_modcode(i_params, demod);
+        switch (intp->srch_standard[demod]) {
+        case STV0900_SEARCH_DVBS1:
+        case STV0900_SEARCH_DSS:
+                stv0900_write_bits(intp, DVBS1_ENABLE, 1);
+                stv0900_write_bits(intp, DVBS2_ENABLE, 0);
+                stv0900_write_bits(intp, STOP_CLKVIT, 0);
+                stv0900_set_dvbs1_track_car_loop(intp,
+                                                demod,
+                                                intp->symbol_rate[demod]);
+                stv0900_write_reg(intp, CAR2CFG, 0x22);
+
+                stv0900_set_viterbi_acq(intp, demod);
+                stv0900_set_viterbi_standard(intp,
+                                        intp->srch_standard[demod],
+                                        intp->fec[demod], demod);
 
-                        } else
-                                stv0900_activate_s2_modcode_single(i_params, demod);
+                break;
+        case STV0900_SEARCH_DVBS2:
+                stv0900_write_bits(intp, DVBS1_ENABLE, 0);
+                stv0900_write_bits(intp, DVBS2_ENABLE, 1);
+                stv0900_write_bits(intp, STOP_CLKVIT, 1);
+                stv0900_write_reg(intp, ACLC, 0x1a);
+                stv0900_write_reg(intp, BCLC, 0x09);
+                if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
+                        stv0900_write_reg(intp, CAR2CFG, 0x26);
+                else
+                        stv0900_write_reg(intp, CAR2CFG, 0x66);
 
-                        if (i_params->dmd1_symbol_rate >= 2000000)
-                                stv0900_set_viterbi_acq(i_params, demod);
+                if (intp->demod_mode != STV0900_SINGLE) {
+                        if (intp->chip_id <= 0x11)
+                                stv0900_stop_all_s2_modcod(intp, demod);
                         else
-                                stv0900_set_viterbi_tracq(i_params, demod);
+                                stv0900_activate_s2_modcod(intp, demod);
 
-                        stv0900_set_viterbi_standard(i_params, i_params->dmd1_srch_standard, i_params->dmd1_fec, demod);
+                } else
+                        stv0900_activate_s2_modcod_single(intp, demod);
 
-                        break;
-                }
-                break;
-        case STV0900_DEMOD_2:
-                switch (i_params->dmd2_srch_stndrd) {
-                case STV0900_SEARCH_DVBS1:
-                case STV0900_SEARCH_DSS:
-                        stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0);
-                        stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
-                        stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
-                        stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x22);
-                        stv0900_set_viterbi_acq(i_params, demod);
-                        stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod);
-                        break;
-                case STV0900_SEARCH_DVBS2:
-                        stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 1);
-                        stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
-                        stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
-                        stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26);
-                        if (i_params->demod_mode != STV0900_SINGLE)
-                                stv0900_activate_s2_modcode(i_params, demod);
-                        else
-                                stv0900_activate_s2_modcode_single(i_params, demod);
+                stv0900_set_viterbi_tracq(intp, demod);
 
-                        stv0900_set_viterbi_tracq(i_params, demod);
-                        break;
-                case STV0900_AUTO_SEARCH:
-                default:
-                        stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
-                        stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
-                        stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0);
-                        stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
-                        stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
-                        stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26);
-                        if (i_params->demod_mode != STV0900_SINGLE)
-                                stv0900_activate_s2_modcode(i_params, demod);
-                        else
-                                stv0900_activate_s2_modcode_single(i_params, demod);
+                break;
+        case STV0900_AUTO_SEARCH:
+        default:
+                stv0900_write_bits(intp, DVBS1_ENABLE, 1);
+                stv0900_write_bits(intp, DVBS2_ENABLE, 1);
+                stv0900_write_bits(intp, STOP_CLKVIT, 0);
+                stv0900_write_reg(intp, ACLC, 0x1a);
+                stv0900_write_reg(intp, BCLC, 0x09);
+                stv0900_set_dvbs1_track_car_loop(intp,
+                                                demod,
+                                                intp->symbol_rate[demod]);
+                if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
+                        stv0900_write_reg(intp, CAR2CFG, 0x26);
+                else
+                        stv0900_write_reg(intp, CAR2CFG, 0x66);
 
-                        if (i_params->dmd2_symbol_rate >= 2000000)
-                                stv0900_set_viterbi_acq(i_params, demod);
+                if (intp->demod_mode != STV0900_SINGLE) {
+                        if (intp->chip_id <= 0x11)
+                                stv0900_stop_all_s2_modcod(intp, demod);
                         else
-                                stv0900_set_viterbi_tracq(i_params, demod);
+                                stv0900_activate_s2_modcod(intp, demod);
 
-                        stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod);
+                } else
+                        stv0900_activate_s2_modcod_single(intp, demod);
 
-                        break;
-                }
+                stv0900_set_viterbi_tracq(intp, demod);
+                stv0900_set_viterbi_standard(intp,
+                                                intp->srch_standard[demod],
+                                                intp->fec[demod], demod);
 
                 break;
         }
@@ -2567,10 +1823,11 @@ static void stv0900_set_search_standard(struct stv0900_internal *i_params,
 enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
 {
         struct stv0900_state *state = fe->demodulator_priv;
-        struct stv0900_internal *i_params = state->internal;
+        struct stv0900_internal *intp = state->internal;
         enum fe_stv0900_demod_num demod = state->demod;
 
-        s32 demod_timeout = 500, fec_timeout = 50, stream_merger_field;
+        s32 demod_timeout = 500, fec_timeout = 50;
+        s32 aq_power, agc1_power, i;
 
         int lock = FALSE, low_sr = FALSE;
 
@@ -2578,157 +1835,121 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
         enum fe_stv0900_search_algo algo;
         int no_signal = FALSE;
 
-        dprintk(KERN_INFO "%s\n", __func__);
-
-        switch (demod) {
-        case STV0900_DEMOD_1:
-        default:
-                algo = i_params->dmd1_srch_algo;
-
-                stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1);
-                stream_merger_field = F0900_P1_RST_HWARE;
-
-                stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C);
+        dprintk("%s\n", __func__);
 
-                if (i_params->chip_id >= 0x20)
-                        stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x9e);
+        algo = intp->srch_algo[demod];
+        stv0900_write_bits(intp, RST_HWARE, 1);
+        stv0900_write_reg(intp, DMDISTATE, 0x5c);
+        if (intp->chip_id >= 0x20) {
+                if (intp->symbol_rate[demod] > 5000000)
+                        stv0900_write_reg(intp, CORRELABS, 0x9e);
                 else
-                        stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x88);
-
-                stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd1_symbol_rate, i_params->dmd1_srch_algo);
-
-                if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
-                        i_params->tuner1_bw = 2 * 36000000;
-
-                        stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x00);
-                        stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
-
-                        stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
-                } else {
-                        stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20);
-                        stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
-
-                        if (i_params->dmd1_symbol_rate < 2000000)
-                                stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x63);
-                        else
-                                stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
-
-                        stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
-                        if (i_params->chip_id >= 0x20) {
-                                stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0x5a);
-
-                                if (i_params->dmd1_srch_algo == STV0900_COLD_START)
-                                        i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
-                                else if (i_params->dmd1_srch_algo == STV0900_WARM_START)
-                                        i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000;
-                        } else {
-                                stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0xc1);
-                                i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
-                        }
-
-                        stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
-
-                        stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
-                        stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
-                        stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
-                        if (i_params->dmd1_symbol_rate >= 10000000)
-                                low_sr = FALSE;
-                        else
-                                low_sr = TRUE;
-
-                }
-
-                stv0900_set_tuner(fe, i_params->tuner1_freq, i_params->tuner1_bw);
-
-                stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, i_params->dmd1_srch_iq_inv);
-                stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
-
-                stv0900_set_search_standard(i_params, demod);
+                        stv0900_write_reg(intp, CORRELABS, 0x82);
+        } else
+                stv0900_write_reg(intp, CORRELABS, 0x88);
 
-                if (i_params->dmd1_srch_algo != STV0900_BLIND_SEARCH)
-                        stv0900_start_search(i_params, demod);
-                break;
-        case STV0900_DEMOD_2:
-                algo = i_params->dmd2_srch_algo;
+        stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
+                                intp->symbol_rate[demod],
+                                intp->srch_algo[demod]);
 
-                stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1);
+        if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
+                intp->bw[demod] = 2 * 36000000;
 
-                stream_merger_field = F0900_P2_RST_HWARE;
+                stv0900_write_reg(intp, TMGCFG2, 0xc0);
+                stv0900_write_reg(intp, CORRELMANT, 0x70);
 
-                stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C);
+                stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
+        } else {
+                stv0900_write_reg(intp, DMDT0M, 0x20);
+                stv0900_write_reg(intp, TMGCFG, 0xd2);
 
-                if (i_params->chip_id >= 0x20)
-                        stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x9e);
+                if (intp->symbol_rate[demod] < 2000000)
+                        stv0900_write_reg(intp, CORRELMANT, 0x63);
                 else
-                        stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x88);
+                        stv0900_write_reg(intp, CORRELMANT, 0x70);
 
-                stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd2_symbol_rate, i_params->dmd2_srch_algo);
+                stv0900_write_reg(intp, AGC2REF, 0x38);
 
-                if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
-                        i_params->tuner2_bw = 2 * 36000000;
+                intp->bw[demod] =
+                                stv0900_carrier_width(intp->symbol_rate[demod],
+                                                                intp->rolloff);
+                if (intp->chip_id >= 0x20) {
+                        stv0900_write_reg(intp, KREFTMG, 0x5a);
 
-                        stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x00);
-                        stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70);
+                        if (intp->srch_algo[demod] == STV0900_COLD_START) {
+                                intp->bw[demod] += 10000000;
+                                intp->bw[demod] *= 15;
+                                intp->bw[demod] /= 10;
+                        } else if (intp->srch_algo[demod] == STV0900_WARM_START)
+                                intp->bw[demod] += 10000000;
 
-                        stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
                 } else {
-                        stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20);
-                        stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2);
+                        stv0900_write_reg(intp, KREFTMG, 0xc1);
+                        intp->bw[demod] += 10000000;
+                        intp->bw[demod] *= 15;
+                        intp->bw[demod] /= 10;
+                }
 
-                        if (i_params->dmd2_symbol_rate < 2000000)
-                                stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x63);
-                        else
-                                stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70);
+                stv0900_write_reg(intp, TMGCFG2, 0xc1);
 
-                        if (i_params->dmd2_symbol_rate >= 10000000)
-                                stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
-                        else
-                                stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x60);
+                stv0900_set_symbol_rate(intp, intp->mclk,
+                                        intp->symbol_rate[demod], demod);
+                stv0900_set_max_symbol_rate(intp, intp->mclk,
+                                        intp->symbol_rate[demod], demod);
+                stv0900_set_min_symbol_rate(intp, intp->mclk,
+                                        intp->symbol_rate[demod], demod);
+                if (intp->symbol_rate[demod] >= 10000000)
+                        low_sr = FALSE;
+                else
+                        low_sr = TRUE;
 
-                        if (i_params->chip_id >= 0x20) {
-                                stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0x5a);
+        }
 
-                                if (i_params->dmd2_srch_algo == STV0900_COLD_START)
-                                        i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
-                                                        i_params->rolloff) + 10000000)) / 10;
-                                else if (i_params->dmd2_srch_algo == STV0900_WARM_START)
-                                        i_params->tuner2_bw = stv0900_carrier_width(i_params->dmd2_symbol_rate,
-                                                        i_params->rolloff) + 10000000;
-                        } else {
-                                stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0xc1);
-                                i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
-                                                                        i_params->rolloff) + 10000000)) / 10;
-                        }
+        if (intp->tuner_type[demod] == 3)
+                stv0900_set_tuner_auto(intp, intp->freq[demod],
+                                intp->bw[demod], demod);
+        else
+                stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
 
-                        stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
+        agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
+                                stv0900_get_bits(intp, AGCIQ_VALUE0));
 
-                        stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
-                        stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
-                        stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
-                        if (i_params->dmd2_symbol_rate >= 10000000)
-                                low_sr = FALSE;
-                        else
-                                low_sr = TRUE;
+        aq_power = 0;
 
-                }
+        if (agc1_power == 0) {
+                for (i = 0; i < 5; i++)
+                        aq_power += (stv0900_get_bits(intp, POWER_I) +
+                                        stv0900_get_bits(intp, POWER_Q)) / 2;
 
-                stv0900_set_tuner(fe, i_params->tuner2_freq, i_params->tuner2_bw);
+                aq_power /= 5;
+        }
 
-                stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, i_params->dmd2_srch_iq_inv);
-                stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
+        if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
+                intp->result[demod].locked = FALSE;
+                signal_type = STV0900_NOAGC1;
+                dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
+        } else {
+                stv0900_write_bits(intp, SPECINV_CONTROL,
+                                        intp->srch_iq_inv[demod]);
+                if (intp->chip_id <= 0x20) /*cut 2.0*/
+                        stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
+                else /*cut 3.0*/
+                        stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
 
-                stv0900_set_search_standard(i_params, demod);
+                stv0900_set_search_standard(intp, demod);
 
-                if (i_params->dmd2_srch_algo != STV0900_BLIND_SEARCH)
-                        stv0900_start_search(i_params, demod);
-                break;
+                if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
+                        stv0900_start_search(intp, demod);
         }
 
-        if (i_params->chip_id == 0x12) {
-                stv0900_write_bits(i_params, stream_merger_field, 0);
+        if (signal_type == STV0900_NOAGC1)
+                return signal_type;
+
+        if (intp->chip_id == 0x12) {
+                stv0900_write_bits(intp, RST_HWARE, 0);
                 msleep(3);
-                stv0900_write_bits(i_params, stream_merger_field, 1);
-                stv0900_write_bits(i_params, stream_merger_field, 0);
+                stv0900_write_bits(intp, RST_HWARE, 1);
+                stv0900_write_bits(intp, RST_HWARE, 0);
         }
 
         if (algo == STV0900_BLIND_SEARCH)
@@ -2736,12 +1957,12 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
         else if (algo == STV0900_COLD_START)
                 lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
         else if (algo == STV0900_WARM_START)
-                lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
+                lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
 
         if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
                 if (low_sr == FALSE) {
-                        if (stv0900_check_timing_lock(i_params, demod) == TRUE)
-                                lock = stv0900_sw_algo(i_params, demod);
+                        if (stv0900_check_timing_lock(intp, demod) == TRUE)
+                                lock = stv0900_sw_algo(intp, demod);
                 }
         }
 
@@ -2750,98 +1971,64 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
 
         if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
                 stv0900_track_optimization(fe);
-                if (i_params->chip_id <= 0x11) {
-                        if ((stv0900_get_standard(fe, STV0900_DEMOD_1) == STV0900_DVBS1_STANDARD) && (stv0900_get_standard(fe, STV0900_DEMOD_2) == STV0900_DVBS1_STANDARD)) {
+                if (intp->chip_id <= 0x11) {
+                        if ((stv0900_get_standard(fe, 0) ==
+                                                STV0900_DVBS1_STANDARD) &&
+                           (stv0900_get_standard(fe, 1) ==
+                                                STV0900_DVBS1_STANDARD)) {
                                 msleep(20);
-                                stv0900_write_bits(i_params, stream_merger_field, 0);
+                                stv0900_write_bits(intp, RST_HWARE, 0);
                         } else {
-                                stv0900_write_bits(i_params, stream_merger_field, 0);
+                                stv0900_write_bits(intp, RST_HWARE, 0);
                                 msleep(3);
-                                stv0900_write_bits(i_params, stream_merger_field, 1);
-                                stv0900_write_bits(i_params, stream_merger_field, 0);
+                                stv0900_write_bits(intp, RST_HWARE, 1);
+                                stv0900_write_bits(intp, RST_HWARE, 0);
                         }
-                } else if (i_params->chip_id == 0x20) {
-                        stv0900_write_bits(i_params, stream_merger_field, 0);
+
+                } else if (intp->chip_id >= 0x20) {
+                        stv0900_write_bits(intp, RST_HWARE, 0);
                         msleep(3);
-                        stv0900_write_bits(i_params, stream_merger_field, 1);
-                        stv0900_write_bits(i_params, stream_merger_field, 0);
+                        stv0900_write_bits(intp, RST_HWARE, 1);
+                        stv0900_write_bits(intp, RST_HWARE, 0);
                 }
 
-                if (stv0900_wait_for_lock(i_params, demod, fec_timeout, fec_timeout) == TRUE) {
+                if (stv0900_wait_for_lock(intp, demod,
+                                        fec_timeout, fec_timeout) == TRUE) {
                         lock = TRUE;
-                        switch (demod) {
-                        case STV0900_DEMOD_1:
-                        default:
-                                i_params->dmd1_rslts.locked = TRUE;
-                                if (i_params->dmd1_rslts.standard == STV0900_DVBS2_STANDARD) {
-                                        stv0900_set_dvbs2_rolloff(i_params, demod);
-                                        stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0x40);
-                                        stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0);
-                                        stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67);
-                                } else {
-                                        stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
-                                }
-
-                                stv0900_write_reg(i_params, R0900_P1_FBERCPT4, 0);
-                                stv0900_write_reg(i_params, R0900_P1_ERRCTRL2, 0xc1);
-                                break;
-                        case STV0900_DEMOD_2:
-                                i_params->dmd2_rslts.locked = TRUE;
-
-                                if (i_params->dmd2_rslts.standard == STV0900_DVBS2_STANDARD) {
-                                        stv0900_set_dvbs2_rolloff(i_params, demod);
-                                        stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x60);
-                                        stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x20);
-                                        stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67);
-                                } else {
-                                        stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
-                                }
-
-                                stv0900_write_reg(i_params, R0900_P2_FBERCPT4, 0);
-
-                                stv0900_write_reg(i_params, R0900_P2_ERRCTRL2, 0xc1);
-                                break;
+                        intp->result[demod].locked = TRUE;
+                        if (intp->result[demod].standard ==
+                                                STV0900_DVBS2_STANDARD) {
+                                stv0900_set_dvbs2_rolloff(intp, demod);
+                                stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
+                                stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
+                                stv0900_write_reg(intp, ERRCTRL1, 0x67);
+                        } else {
+                                stv0900_write_reg(intp, ERRCTRL1, 0x75);
                         }
+
+                        stv0900_write_reg(intp, FBERCPT4, 0);
+                        stv0900_write_reg(intp, ERRCTRL2, 0xc1);
                 } else {
                         lock = FALSE;
                         signal_type = STV0900_NODATA;
-                        no_signal = stv0900_check_signal_presence(i_params, demod);
-
-                        switch (demod) {
-                        case STV0900_DEMOD_1:
-                        default:
-                                i_params->dmd1_rslts.locked = FALSE;
-                                break;
-                        case STV0900_DEMOD_2:
-                                i_params->dmd2_rslts.locked = FALSE;
-                                break;
-                        }
+                        no_signal = stv0900_check_signal_presence(intp, demod);
+
+                                intp->result[demod].locked = FALSE;
                 }
         }
 
-        if ((signal_type == STV0900_NODATA) && (no_signal == FALSE)) {
-                switch (demod) {
-                case STV0900_DEMOD_1:
-                default:
-                        if (i_params->chip_id <= 0x11) {
-                                if ((stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) &&
-                                                (i_params->dmd1_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
-                                        signal_type = stv0900_dvbs1_acq_workaround(fe);
-                        } else
-                                i_params->dmd1_rslts.locked = FALSE;
+        if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
+                return signal_type;
 
-                        break;
-                case STV0900_DEMOD_2:
-                        if (i_params->chip_id <= 0x11) {
-                                if ((stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) &&
-                                                (i_params->dmd2_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
-                                        signal_type = stv0900_dvbs1_acq_workaround(fe);
-                        } else
-                                i_params->dmd2_rslts.locked = FALSE;
-                        break;
-                }
+        if (intp->chip_id > 0x11) {
+                intp->result[demod].locked = FALSE;
+                return signal_type;
         }
 
+        if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
+           (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
+                signal_type = stv0900_dvbs1_acq_workaround(fe);
+
         return signal_type;
 }
 
diff --git a/drivers/media/dvb/frontends/stv090x.c b/drivers/media/dvb/frontends/stv090x.c
index 488bdfb34fb3..96972804f4ad 100644
--- a/drivers/media/dvb/frontends/stv090x.c
+++ b/drivers/media/dvb/frontends/stv090x.c
@@ -23,6 +23,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/string.h>
+#include <linux/slab.h>
 #include <linux/mutex.h>
 
 #include <linux/dvb/frontend.h>
@@ -37,7 +38,82 @@
 static unsigned int verbose;
 module_param(verbose, int, 0644);
 
-struct mutex demod_lock;
+/* internal params node */
+struct stv090x_dev {
+        /* pointer for internal params, one for each pair of demods */
+        struct stv090x_internal         *internal;
+        struct stv090x_dev              *next_dev;
+};
+
+/* first internal params */
+static struct stv090x_dev *stv090x_first_dev;
+
+/* find chip by i2c adapter and i2c address */
+static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
+                                        u8 i2c_addr)
+{
+        struct stv090x_dev *temp_dev = stv090x_first_dev;
+
+        /*
+         Search of the last stv0900 chip or
+         find it by i2c adapter and i2c address */
+        while ((temp_dev != NULL) &&
+                ((temp_dev->internal->i2c_adap != i2c_adap) ||
+                (temp_dev->internal->i2c_addr != i2c_addr))) {
+
+                temp_dev = temp_dev->next_dev;
+        }
+
+        return temp_dev;
+}
+
+/* deallocating chip */
+static void remove_dev(struct stv090x_internal *internal)
+{
+        struct stv090x_dev *prev_dev = stv090x_first_dev;
+        struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
+                                                internal->i2c_addr);
+
+        if (del_dev != NULL) {
+                if (del_dev == stv090x_first_dev) {
+                        stv090x_first_dev = del_dev->next_dev;
+                } else {
+                        while (prev_dev->next_dev != del_dev)
+                                prev_dev = prev_dev->next_dev;
+
+                        prev_dev->next_dev = del_dev->next_dev;
+                }
+
+                kfree(del_dev);
+        }
+}
+
+/* allocating new chip */
+static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
+{
+        struct stv090x_dev *new_dev;
+        struct stv090x_dev *temp_dev;
+
+        new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
+        if (new_dev != NULL) {
+                new_dev->internal = internal;
+                new_dev->next_dev = NULL;
+
+                /* append to list */
+                if (stv090x_first_dev == NULL) {
+                        stv090x_first_dev = new_dev;
+                } else {
+                        temp_dev = stv090x_first_dev;
+                        while (temp_dev->next_dev != NULL)
+                                temp_dev = temp_dev->next_dev;
+
+                        temp_dev->next_dev = new_dev;
+                }
+        }
+
+        return new_dev;
+}
+
 
 /* DVBS1 and DSS C/N Lookup table */
 static const struct stv090x_tab stv090x_s1cn_tab[] = {
@@ -683,6 +759,9 @@ static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
         struct stv090x_state *state = fe->demodulator_priv;
         u32 reg;
 
+        if (enable)
+                mutex_lock(&state->internal->tuner_lock);
+
         reg = STV090x_READ_DEMOD(state, I2CRPT);
         if (enable) {
                 dprintk(FE_DEBUG, 1, "Enable Gate");
@@ -696,9 +775,14 @@ static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
                 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
                         goto err;
         }
+
+        if (!enable)
+                mutex_unlock(&state->internal->tuner_lock);
+
         return 0;
 err:
         dprintk(FE_ERROR, 1, "I/O error");
+        mutex_unlock(&state->internal->tuner_lock);
         return -1;
 }
 
@@ -755,13 +839,13 @@ static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
 
         if (srate > 60000000) {
                 sym  = (srate << 4); /* SR * 2^16 / master_clk */
-                sym /= (state->mclk >> 12);
+                sym /= (state->internal->mclk >> 12);
         } else if (srate > 6000000) {
                 sym  = (srate << 6);
-                sym /= (state->mclk >> 10);
+                sym /= (state->internal->mclk >> 10);
         } else {
                 sym  = (srate << 9);
-                sym /= (state->mclk >> 7);
+                sym /= (state->internal->mclk >> 7);
         }
 
         if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
@@ -782,13 +866,13 @@ static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate
         srate = 105 * (srate / 100);
         if (srate > 60000000) {
                 sym  = (srate << 4); /* SR * 2^16 / master_clk */
-                sym /= (state->mclk >> 12);
+                sym /= (state->internal->mclk >> 12);
         } else if (srate > 6000000) {
                 sym  = (srate << 6);
-                sym /= (state->mclk >> 10);
+                sym /= (state->internal->mclk >> 10);
         } else {
                 sym  = (srate << 9);
-                sym /= (state->mclk >> 7);
+                sym /= (state->internal->mclk >> 7);
         }
 
         if (sym < 0x7fff) {
@@ -816,16 +900,16 @@ static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate
         srate = 95 * (srate / 100);
         if (srate > 60000000) {
                 sym  = (srate << 4); /* SR * 2^16 / master_clk */
-                sym /= (state->mclk >> 12);
+                sym /= (state->internal->mclk >> 12);
         } else if (srate > 6000000) {
                 sym  = (srate << 6);
-                sym /= (state->mclk >> 10);
+                sym /= (state->internal->mclk >> 10);
         } else {
                 sym  = (srate << 9);
-                sym /= (state->mclk >> 7);
+                sym /= (state->internal->mclk >> 7);
         }
 
-        if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */
+        if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
                 goto err;
         if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
                 goto err;
@@ -1103,21 +1187,21 @@ static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
 
         switch (state->demod) {
         case STV090x_DEMODULATOR_0:
-                mutex_lock(&demod_lock);
+                mutex_lock(&state->internal->demod_lock);
                 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
                 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
                 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
                         goto err;
-                mutex_unlock(&demod_lock);
+                mutex_unlock(&state->internal->demod_lock);
                 break;
 
         case STV090x_DEMODULATOR_1:
-                mutex_lock(&demod_lock);
+                mutex_lock(&state->internal->demod_lock);
                 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
                 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
                 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
                         goto err;
-                mutex_unlock(&demod_lock);
+                mutex_unlock(&state->internal->demod_lock);
                 break;
 
         default:
@@ -1126,14 +1210,14 @@ static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
         }
         return 0;
 err:
-        mutex_unlock(&demod_lock);
+        mutex_unlock(&state->internal->demod_lock);
         dprintk(FE_ERROR, 1, "I/O error");
         return -1;
 }
 
 static int stv090x_dvbs_track_crl(struct stv090x_state *state)
 {
-        if (state->dev_ver >= 0x30) {
+        if (state->internal->dev_ver >= 0x30) {
                 /* Set ACLC BCLC optimised value vs SR */
                 if (state->srate >= 15000000) {
                         if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
@@ -1215,7 +1299,7 @@ static int stv090x_delivery_search(struct stv090x_state *state)
                 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
                         goto err;
 
-                if (state->dev_ver <= 0x20) {
+                if (state->internal->dev_ver <= 0x20) {
                         /* enable S2 carrier loop */
                         if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
                                 goto err;
@@ -1238,12 +1322,18 @@ static int stv090x_delivery_search(struct stv090x_state *state)
                                 goto err;
                 }
 
+                if (stv090x_set_vit_thtracq(state) < 0)
+                        goto err;
                 break;
 
         case STV090x_SEARCH_AUTO:
         default:
                 /* enable DVB-S2 and DVB-S2 in Auto MODE */
                 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+                STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
+                STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                        goto err;
                 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
                 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
                 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
@@ -1255,7 +1345,7 @@ static int stv090x_delivery_search(struct stv090x_state *state)
                 if (stv090x_dvbs_track_crl(state) < 0)
                         goto err;
 
-                if (state->dev_ver <= 0x20) {
+                if (state->internal->dev_ver <= 0x20) {
                         /* enable S2 carrier loop */
                         if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
                                 goto err;
@@ -1278,17 +1368,8 @@ static int stv090x_delivery_search(struct stv090x_state *state)
                                 goto err;
                 }
 
-                if (state->srate >= 2000000) {
-                        /* Srate >= 2MSPS, Viterbi threshold to acquire */
-                        if (stv090x_set_vit_thacq(state) < 0)
-                                goto err;
-                } else {
-                        /* Srate < 2MSPS, Reset Viterbi thresholdto track
-                         * and then re-acquire
-                         */
-                        if (stv090x_set_vit_thtracq(state) < 0)
-                                goto err;
-                }
+                if (stv090x_set_vit_thacq(state) < 0)
+                        goto err;
 
                 if (stv090x_set_viterbi(state) < 0)
                         goto err;
@@ -1311,13 +1392,13 @@ static int stv090x_start_search(struct stv090x_state *state)
         if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
                 goto err;
 
-        if (state->dev_ver <= 0x20) {
+        if (state->internal->dev_ver <= 0x20) {
                 if (state->srate <= 5000000) {
                         if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
                                 goto err;
                         if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
                                 goto err;
-                        if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0)
+                        if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
                                 goto err;
                         if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
                                 goto err;
@@ -1355,7 +1436,7 @@ static int stv090x_start_search(struct stv090x_state *state)
                          * CFR max = +1MHz
                          */
                         freq_abs  = 1000 << 16;
-                        freq_abs /= (state->mclk / 1000);
+                        freq_abs /= (state->internal->mclk / 1000);
                         freq      = (s16) freq_abs;
                 } else {
                         /* COLD Start
@@ -1365,13 +1446,13 @@ static int stv090x_start_search(struct stv090x_state *state)
                          */
                         freq_abs  = (state->search_range / 2000) + 600;
                         freq_abs  = freq_abs << 16;
-                        freq_abs /= (state->mclk / 1000);
+                        freq_abs /= (state->internal->mclk / 1000);
                         freq      = (s16) freq_abs;
                 }
 
                 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
                         goto err;
-                if (STV090x_WRITE_DEMOD(state, CFRUP1, LSB(freq)) < 0)
+                if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
                         goto err;
 
                 freq *= -1;
@@ -1388,7 +1469,7 @@ static int stv090x_start_search(struct stv090x_state *state)
         if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
                 goto err;
 
-        if (state->dev_ver >= 0x20) {
+        if (state->internal->dev_ver >= 0x20) {
                 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
                         goto err;
                 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
@@ -1422,28 +1503,33 @@ static int stv090x_start_search(struct stv090x_state *state)
         if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
                 goto err;
 
-        if (state->dev_ver >= 0x20) {
+        if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
+                goto err;
+
+        if (state->internal->dev_ver >= 0x20) {
                 /*Frequency offset detector setting*/
                 if (state->srate < 2000000) {
-                        if (state->dev_ver <= 0x20) {
+                        if (state->internal->dev_ver <= 0x20) {
                                 /* Cut 2 */
                                 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
                                         goto err;
                         } else {
-                                /* Cut 2 */
+                                /* Cut 3 */
                                 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
                                         goto err;
                         }
                         if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
                                 goto err;
-                }
-
-                if (state->srate < 10000000) {
+                } else if (state->srate < 10000000) {
                         if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
                                 goto err;
+                        if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
+                                goto err;
                 } else {
                         if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
                                 goto err;
+                        if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
+                                goto err;
                 }
         } else {
                 if (state->srate < 10000000) {
@@ -1485,14 +1571,14 @@ err:
 
 static int stv090x_get_agc2_min_level(struct stv090x_state *state)
 {
-        u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg;
+        u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
         s32 i, j, steps, dir;
 
         if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
                 goto err;
         reg = STV090x_READ_DEMOD(state, DMDCFGMD);
-        STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
-        STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
+        STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
+        STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
         if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
                 goto err;
 
@@ -1509,14 +1595,12 @@ static int stv090x_get_agc2_min_level(struct stv090x_state *state)
         if (stv090x_set_srate(state, 1000000) < 0)
                 goto err;
 
-        steps  = -1 + state->search_range / 1000000;
-        steps /= 2;
-        steps  = (2 * steps) + 1;
-        if (steps < 0)
+        steps  = state->search_range / 1000000;
+        if (steps <= 0)
                 steps = 1;
 
         dir = 1;
-        freq_step = (1000000 * 256) / (state->mclk / 256);
+        freq_step = (1000000 * 256) / (state->internal->mclk / 256);
         freq_init = 0;
 
         for (i = 0; i < steps; i++) {
@@ -1525,7 +1609,7 @@ static int stv090x_get_agc2_min_level(struct stv090x_state *state)
                 else
                         freq_init = freq_init - (freq_step * i);
 
-                dir = -1;
+                dir *= -1;
 
                 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
                         goto err;
@@ -1536,13 +1620,14 @@ static int stv090x_get_agc2_min_level(struct stv090x_state *state)
                 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
                         goto err;
                 msleep(10);
+
+                agc2 = 0;
                 for (j = 0; j < 10; j++) {
-                        agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
-                        agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
+                        agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
+                                STV090x_READ_DEMOD(state, AGC2I0);
                 }
                 agc2 /= 10;
-                agc2_min = 0xffff;
-                if (agc2 < 0xffff)
+                if (agc2 < agc2_min)
                         agc2_min = agc2;
         }
 
@@ -1584,6 +1669,12 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
         int tmg_lock = 0, i;
         s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
         u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
+        u32 agc2th;
+
+        if (state->internal->dev_ver >= 0x30)
+                agc2th = 0x2e00;
+        else
+                agc2th = 0x1f00;
 
         reg = STV090x_READ_DEMOD(state, DMDISTATE);
         STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
@@ -1591,13 +1682,15 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
                 goto err;
         if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
                 goto err;
+        if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
+                goto err;
         if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
                 goto err;
         if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
                 goto err;
         reg = STV090x_READ_DEMOD(state, DMDCFGMD);
         STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
-        STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
+        STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
         if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
                 goto err;
 
@@ -1611,16 +1704,16 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
                 goto err;
         if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
                 goto err;
-        if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0)
+        if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
                 goto err;
 
-        if (state->dev_ver >= 0x30) {
+        if (state->internal->dev_ver >= 0x30) {
                 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
                         goto err;
-                if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
+                if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
                         goto err;
 
-        } else if (state->dev_ver >= 0x20) {
+        } else if (state->internal->dev_ver >= 0x20) {
                 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
                         goto err;
                 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
@@ -1652,23 +1745,31 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
         while ((!tmg_lock) && (cur_step < steps)) {
                 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
                         goto err;
-                reg = STV090x_READ_DEMOD(state, DMDISTATE);
-                STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
-                if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
+                if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
+                        goto err;
+                /* trigger acquisition */
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
                         goto err;
                 msleep(50);
                 for (i = 0; i < 10; i++) {
                         reg = STV090x_READ_DEMOD(state, DSTATUS);
                         if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
                                 tmg_cpt++;
-                        agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
-                        agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
+                        agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
+                                STV090x_READ_DEMOD(state, AGC2I0);
                 }
                 agc2 /= 10;
-                srate_coarse = stv090x_get_srate(state, state->mclk);
+                srate_coarse = stv090x_get_srate(state, state->internal->mclk);
                 cur_step++;
                 dir *= -1;
-                if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000))
+                if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
+                    (srate_coarse < 50000000) && (srate_coarse > 850000))
                         tmg_lock = 1;
                 else if (cur_step < steps) {
                         if (dir > 0)
@@ -1681,13 +1782,13 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
                                 goto err;
 
                         if (state->config->tuner_set_frequency) {
-                                if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
-                                        goto err;
+                                if (state->config->tuner_set_frequency(fe, freq) < 0)
+                                        goto err_gateoff;
                         }
 
                         if (state->config->tuner_set_bandwidth) {
                                 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
-                                        goto err;
+                                        goto err_gateoff;
                         }
 
                         if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
@@ -1700,7 +1801,7 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
 
                         if (state->config->tuner_get_status) {
                                 if (state->config->tuner_get_status(fe, &reg) < 0)
-                                        goto err;
+                                        goto err_gateoff;
                         }
 
                         if (reg)
@@ -1716,9 +1817,12 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
         if (!tmg_lock)
                 srate_coarse = 0;
         else
-                srate_coarse = stv090x_get_srate(state, state->mclk);
+                srate_coarse = stv090x_get_srate(state, state->internal->mclk);
 
         return srate_coarse;
+
+err_gateoff:
+        stv090x_i2c_gate_ctrl(fe, 0);
 err:
         dprintk(FE_ERROR, 1, "I/O error");
         return -1;
@@ -1728,7 +1832,7 @@ static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
 {
         u32 srate_coarse, freq_coarse, sym, reg;
 
-        srate_coarse = stv090x_get_srate(state, state->mclk);
+        srate_coarse = stv090x_get_srate(state, state->internal->mclk);
         freq_coarse  = STV090x_READ_DEMOD(state, CFR2) << 8;
         freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
         sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
@@ -1738,7 +1842,7 @@ static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
         else {
                 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
                         goto err;
-                if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
+                if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
                         goto err;
                 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
                         goto err;
@@ -1751,10 +1855,13 @@ static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
                 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
                         goto err;
 
-                if (state->dev_ver >= 0x30) {
+                if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
+                        goto err;
+
+                if (state->internal->dev_ver >= 0x30) {
                         if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
                                 goto err;
-                } else if (state->dev_ver >= 0x20) {
+                } else if (state->internal->dev_ver >= 0x20) {
                         if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
                                 goto err;
                 }
@@ -1762,20 +1869,20 @@ static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
                 if (srate_coarse > 3000000) {
                         sym  = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
                         sym  = (sym / 1000) * 65536;
-                        sym /= (state->mclk / 1000);
+                        sym /= (state->internal->mclk / 1000);
                         if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
                                 goto err;
                         if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
                                 goto err;
                         sym  = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
                         sym  = (sym / 1000) * 65536;
-                        sym /= (state->mclk / 1000);
+                        sym /= (state->internal->mclk / 1000);
                         if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
                                 goto err;
                         if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
                                 goto err;
                         sym  = (srate_coarse / 1000) * 65536;
-                        sym /= (state->mclk / 1000);
+                        sym /= (state->internal->mclk / 1000);
                         if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
                                 goto err;
                         if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
@@ -1783,20 +1890,20 @@ static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
                 } else {
                         sym  = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
                         sym  = (sym / 100) * 65536;
-                        sym /= (state->mclk / 100);
+                        sym /= (state->internal->mclk / 100);
                         if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
                                 goto err;
                         if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
                                 goto err;
                         sym  = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
                         sym  = (sym / 100) * 65536;
-                        sym /= (state->mclk / 100);
+                        sym /= (state->internal->mclk / 100);
                         if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
                                 goto err;
                         if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
                                 goto err;
                         sym  = (srate_coarse / 100) * 65536;
-                        sym /= (state->mclk / 100);
+                        sym /= (state->internal->mclk / 100);
                         if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
                                 goto err;
                         if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
@@ -1856,20 +1963,21 @@ static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
 static int stv090x_blind_search(struct stv090x_state *state)
 {
         u32 agc2, reg, srate_coarse;
-        s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
+        s32 cpt_fail, agc2_ovflw, i;
         u8 k_ref, k_max, k_min;
-        int coarse_fail, lock;
+        int coarse_fail = 0;
+        int lock;
 
-        k_max = 120;
-        k_min = 30;
+        k_max = 110;
+        k_min = 10;
 
         agc2 = stv090x_get_agc2_min_level(state);
 
-        if (agc2 > STV090x_SEARCH_AGC2_TH(state->dev_ver)) {
+        if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
                 lock = 0;
         } else {
 
-                if (state->dev_ver <= 0x20) {
+                if (state->internal->dev_ver <= 0x20) {
                         if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
                                 goto err;
                 } else {
@@ -1881,7 +1989,7 @@ static int stv090x_blind_search(struct stv090x_state *state)
                 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
                         goto err;
 
-                if (state->dev_ver >= 0x20) {
+                if (state->internal->dev_ver >= 0x20) {
                         if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
                                 goto err;
                         if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
@@ -1900,7 +2008,8 @@ static int stv090x_blind_search(struct stv090x_state *state)
                                 srate_coarse = stv090x_srate_srch_fine(state);
                                 if (srate_coarse != 0) {
                                         stv090x_get_lock_tmg(state);
-                                        lock = stv090x_get_dmdlock(state, timeout_dmd);
+                                        lock = stv090x_get_dmdlock(state,
+                                                        state->DemodTimeout);
                                 } else {
                                         lock = 0;
                                 }
@@ -1908,8 +2017,8 @@ static int stv090x_blind_search(struct stv090x_state *state)
                                 cpt_fail = 0;
                                 agc2_ovflw = 0;
                                 for (i = 0; i < 10; i++) {
-                                        agc2  = STV090x_READ_DEMOD(state, AGC2I1) << 8;
-                                        agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
+                                        agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
+                                                STV090x_READ_DEMOD(state, AGC2I0);
                                         if (agc2 >= 0xff00)
                                                 agc2_ovflw++;
                                         reg = STV090x_READ_DEMOD(state, DSTATUS2);
@@ -1923,7 +2032,7 @@ static int stv090x_blind_search(struct stv090x_state *state)
 
                                 lock = 0;
                         }
-                        k_ref -= 30;
+                        k_ref -= 20;
                 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
         }
 
@@ -1939,7 +2048,7 @@ static int stv090x_chk_tmg(struct stv090x_state *state)
         u32 reg;
         s32 tmg_cpt = 0, i;
         u8 freq, tmg_thh, tmg_thl;
-        int tmg_lock;
+        int tmg_lock = 0;
 
         freq = STV090x_READ_DEMOD(state, CARFREQ);
         tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
@@ -2062,13 +2171,13 @@ static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
                                                 goto err;
 
                                         if (state->config->tuner_set_frequency) {
-                                                if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
-                                                        goto err;
+                                                if (state->config->tuner_set_frequency(fe, freq) < 0)
+                                                        goto err_gateoff;
                                         }
 
                                         if (state->config->tuner_set_bandwidth) {
                                                 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
-                                                        goto err;
+                                                        goto err_gateoff;
                                         }
 
                                         if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
@@ -2081,7 +2190,7 @@ static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
 
                                         if (state->config->tuner_get_status) {
                                                 if (state->config->tuner_get_status(fe, &reg) < 0)
-                                                        goto err;
+                                                        goto err_gateoff;
                                         }
 
                                         if (reg)
@@ -2093,17 +2202,6 @@ static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
                                                 goto err;
 
                                         STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
-                                        if (state->delsys == STV090x_DVBS2) {
-                                                reg = STV090x_READ_DEMOD(state, DMDCFGMD);
-                                                STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
-                                                STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
-                                                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
-                                                        goto err;
-                                                STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
-                                                STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
-                                                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
-                                                        goto err;
-                                        }
                                         if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
                                                 goto err;
                                         if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
@@ -2123,6 +2221,8 @@ static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
 
         return lock;
 
+err_gateoff:
+        stv090x_i2c_gate_ctrl(fe, 0);
 err:
         dprintk(FE_ERROR, 1, "I/O error");
         return -1;
@@ -2136,13 +2236,13 @@ static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s
         car_max = state->search_range / 1000;
         car_max += car_max / 10;
         car_max  = 65536 * (car_max / 2);
-        car_max /= (state->mclk / 1000);
+        car_max /= (state->internal->mclk / 1000);
 
         if (car_max > 0x4000)
                 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
 
         inc  = srate;
-        inc /= state->mclk / 1000;
+        inc /= state->internal->mclk / 1000;
         inc *= 256;
         inc *= 256;
         inc /= 1000;
@@ -2203,7 +2303,7 @@ static int stv090x_chk_signal(struct stv090x_state *state)
 
         car_max += (car_max / 10); /* 10% margin */
         car_max  = (65536 * car_max / 2);
-        car_max /= state->mclk / 1000;
+        car_max /= state->internal->mclk / 1000;
 
         if (car_max > 0x4000)
                 car_max = 0x4000;
@@ -2228,7 +2328,7 @@ static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 tim
         car_max  = state->search_range / 1000;
         car_max += (car_max / 10);
         car_max  = (65536 * car_max / 2);
-        car_max /= (state->mclk / 1000);
+        car_max /= (state->internal->mclk / 1000);
         if (car_max > 0x4000)
                 car_max = 0x4000;
 
@@ -2298,7 +2398,7 @@ static int stv090x_sw_algo(struct stv090x_state *state)
         case STV090x_SEARCH_DVBS1:
         case STV090x_SEARCH_DSS:
                 /* accelerate the frequency detector */
-                if (state->dev_ver >= 0x20) {
+                if (state->internal->dev_ver >= 0x20) {
                         if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
                                 goto err;
                 }
@@ -2309,7 +2409,7 @@ static int stv090x_sw_algo(struct stv090x_state *state)
                 break;
 
         case STV090x_SEARCH_DVBS2:
-                if (state->dev_ver >= 0x20) {
+                if (state->internal->dev_ver >= 0x20) {
                         if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
                                 goto err;
                 }
@@ -2322,7 +2422,7 @@ static int stv090x_sw_algo(struct stv090x_state *state)
         case STV090x_SEARCH_AUTO:
         default:
                 /* accelerate the frequency detector */
-                if (state->dev_ver >= 0x20) {
+                if (state->internal->dev_ver >= 0x20) {
                         if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
                                 goto err;
                         if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
@@ -2344,7 +2444,7 @@ static int stv090x_sw_algo(struct stv090x_state *state)
                 /*run the SW search 2 times maximum*/
                 if (lock || no_signal || (trials == 2)) {
                         /*Check if the demod is not losing lock in DVBS2*/
-                        if (state->dev_ver >= 0x20) {
+                        if (state->internal->dev_ver >= 0x20) {
                                 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
                                         goto err;
                                 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
@@ -2366,7 +2466,7 @@ static int stv090x_sw_algo(struct stv090x_state *state)
                                         /*FALSE lock, The demod is loosing lock */
                                         lock = 0;
                                         if (trials < 2) {
-                                                if (state->dev_ver >= 0x20) {
+                                                if (state->internal->dev_ver >= 0x20) {
                                                         if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
                                                                 goto err;
                                                 }
@@ -2416,16 +2516,16 @@ static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
         derot |= STV090x_READ_DEMOD(state, CFR0);
 
         derot = comp2(derot, 24);
-        int_1 = state->mclk >> 12;
+        int_1 = mclk >> 12;
         int_2 = derot >> 12;
 
         /* carrier_frequency = MasterClock * Reg / 2^24 */
-        tmp_1 = state->mclk % 0x1000;
+        tmp_1 = mclk % 0x1000;
         tmp_2 = derot % 0x1000;
 
         derot = (int_1 * int_2) +
                 ((int_1 * tmp_2) >> 12) +
-                ((int_1 * tmp_1) >> 12);
+                ((int_2 * tmp_1) >> 12);
 
         return derot;
 }
@@ -2496,13 +2596,13 @@ static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *st
 
         if (state->config->tuner_get_frequency) {
                 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
-                        goto err;
+                        goto err_gateoff;
         }
 
         if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
                 goto err;
 
-        offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
+        offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
         state->frequency += offst_freq;
 
         if (stv090x_get_viterbi(state) < 0)
@@ -2524,7 +2624,7 @@ static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *st
 
                 if (state->config->tuner_get_frequency) {
                         if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
-                                goto err;
+                                goto err_gateoff;
                 }
 
                 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
@@ -2544,6 +2644,9 @@ static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *st
         }
 
         return STV090x_OUTOFRANGE;
+
+err_gateoff:
+        stv090x_i2c_gate_ctrl(fe, 0);
 err:
         dprintk(FE_ERROR, 1, "I/O error");
         return -1;
@@ -2573,7 +2676,7 @@ static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_mod
         s32 i;
         struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
 
-        if (state->dev_ver == 0x20) {
+        if (state->internal->dev_ver == 0x20) {
                 car_loop                = stv090x_s2_crl_cut20;
                 car_loop_qpsk_low       = stv090x_s2_lowqpsk_crl_cut20;
                 car_loop_apsk_low       = stv090x_s2_apsk_crl_cut20;
@@ -2694,7 +2797,7 @@ static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
                 break;
         }
 
-        if (state->dev_ver >= 0x30) {
+        if (state->internal->dev_ver >= 0x30) {
                 /* Cut 3.0 and up */
                 short_crl = stv090x_s2_short_crl_cut30;
         } else {
@@ -2726,13 +2829,13 @@ static int stv090x_optimize_track(struct stv090x_state *state)
         s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
         u32 reg;
 
-        srate  = stv090x_get_srate(state, state->mclk);
+        srate  = stv090x_get_srate(state, state->internal->mclk);
         srate += stv090x_get_tmgoffst(state, srate);
 
         switch (state->delsys) {
         case STV090x_DVBS1:
         case STV090x_DSS:
-                if (state->algo == STV090x_SEARCH_AUTO) {
+                if (state->search_mode == STV090x_SEARCH_AUTO) {
                         reg = STV090x_READ_DEMOD(state, DMDCFGMD);
                         STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
                         STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
@@ -2745,7 +2848,7 @@ static int stv090x_optimize_track(struct stv090x_state *state)
                 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
                         goto err;
 
-                if (state->dev_ver >= 0x30) {
+                if (state->internal->dev_ver >= 0x30) {
                         if (stv090x_get_viterbi(state) < 0)
                                 goto err;
 
@@ -2857,9 +2960,12 @@ static int stv090x_optimize_track(struct stv090x_state *state)
                 if (stv090x_set_srate(state, srate) < 0)
                         goto err;
                 blind_tune = 1;
+
+                if (stv090x_dvbs_track_crl(state) < 0)
+                        goto err;
         }
 
-        if (state->dev_ver >= 0x20) {
+        if (state->internal->dev_ver >= 0x20) {
                 if ((state->search_mode == STV090x_SEARCH_DVBS1)        ||
                     (state->search_mode == STV090x_SEARCH_DSS)          ||
                     (state->search_mode == STV090x_SEARCH_AUTO)) {
@@ -2881,7 +2987,8 @@ static int stv090x_optimize_track(struct stv090x_state *state)
         if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
                 goto err;
 
-        if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
+        if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
+            (state->srate < 10000000)) {
                 /* update initial carrier freq with the found freq offset */
                 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
                         goto err;
@@ -2889,7 +2996,7 @@ static int stv090x_optimize_track(struct stv090x_state *state)
                         goto err;
                 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
 
-                if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
+                if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
 
                         if (state->algo != STV090x_WARM_SEARCH) {
 
@@ -2898,7 +3005,7 @@ static int stv090x_optimize_track(struct stv090x_state *state)
 
                                 if (state->config->tuner_set_bandwidth) {
                                         if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
-                                                goto err;
+                                                goto err_gateoff;
                                 }
 
                                 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
@@ -2941,7 +3048,7 @@ static int stv090x_optimize_track(struct stv090x_state *state)
 
         }
 
-        if (state->dev_ver >= 0x20) {
+        if (state->internal->dev_ver >= 0x20) {
                 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
                         goto err;
         }
@@ -2950,6 +3057,9 @@ static int stv090x_optimize_track(struct stv090x_state *state)
                 stv090x_set_vit_thtracq(state);
 
         return 0;
+
+err_gateoff:
+        stv090x_i2c_gate_ctrl(fe, 0);
 err:
         dprintk(FE_ERROR, 1, "I/O error");
         return -1;
@@ -3017,7 +3127,7 @@ static int stv090x_set_s2rolloff(struct stv090x_state *state)
 {
         u32 reg;
 
-        if (state->dev_ver <= 0x20) {
+        if (state->internal->dev_ver <= 0x20) {
                 /* rolloff to auto mode if DVBS2 */
                 reg = STV090x_READ_DEMOD(state, DEMOD);
                 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
@@ -3042,7 +3152,7 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
         struct dvb_frontend *fe = &state->frontend;
         enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
         u32 reg;
-        s32 timeout_dmd = 500, timeout_fec = 50, agc1_power, power_iq = 0, i;
+        s32 agc1_power, power_iq = 0, i;
         int lock = 0, low_sr = 0, no_signal = 0;
 
         reg = STV090x_READ_DEMOD(state, TSCFGH);
@@ -3053,9 +3163,14 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
         if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
                 goto err;
 
-        if (state->dev_ver >= 0x20) {
-                if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
-                        goto err;
+        if (state->internal->dev_ver >= 0x20) {
+                if (state->srate > 5000000) {
+                        if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
+                                goto err;
+                } else {
+                        if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
+                                goto err;
+                }
         }
 
         stv090x_get_lock_tmg(state);
@@ -3088,7 +3203,7 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
                 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
                         goto err;
 
-                if (state->dev_ver >= 0x20) {
+                if (state->internal->dev_ver >= 0x20) {
                         if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
                                 goto err;
                         if (state->algo == STV090x_COLD_SEARCH)
@@ -3106,9 +3221,11 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
                 if (stv090x_set_srate(state, state->srate) < 0)
                         goto err;
 
-                if (stv090x_set_max_srate(state, state->mclk, state->srate) < 0)
+                if (stv090x_set_max_srate(state, state->internal->mclk,
+                                          state->srate) < 0)
                         goto err;
-                if (stv090x_set_min_srate(state, state->mclk, state->srate) < 0)
+                if (stv090x_set_min_srate(state, state->internal->mclk,
+                                          state->srate) < 0)
                         goto err;
 
                 if (state->srate >= 10000000)
@@ -3122,18 +3239,21 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
                 goto err;
 
         if (state->config->tuner_set_bbgain) {
-                if (state->config->tuner_set_bbgain(fe, 10) < 0) /* 10dB */
-                        goto err;
+                reg = state->config->tuner_bbgain;
+                if (reg == 0)
+                        reg = 10; /* default: 10dB */
+                if (state->config->tuner_set_bbgain(fe, reg) < 0)
+                        goto err_gateoff;
         }
 
         if (state->config->tuner_set_frequency) {
                 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
-                        goto err;
+                        goto err_gateoff;
         }
 
         if (state->config->tuner_set_bandwidth) {
                 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
-                        goto err;
+                        goto err_gateoff;
         }
 
         if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
@@ -3141,21 +3261,21 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
 
         msleep(50);
 
-        if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
-                goto err;
-
         if (state->config->tuner_get_status) {
+                if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
+                        goto err;
                 if (state->config->tuner_get_status(fe, &reg) < 0)
+                        goto err_gateoff;
+                if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
                         goto err;
-        }
 
-        if (reg)
-                dprintk(FE_DEBUG, 1, "Tuner phase locked");
-        else
-                dprintk(FE_DEBUG, 1, "Tuner unlocked");
-
-        if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
-                goto err;
+                if (reg)
+                        dprintk(FE_DEBUG, 1, "Tuner phase locked");
+                else {
+                        dprintk(FE_DEBUG, 1, "Tuner unlocked");
+                        return STV090x_NOCARRIER;
+                }
+        }
 
         msleep(10);
         agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
@@ -3175,12 +3295,12 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
         if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
                 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
                 lock = 0;
-
+                signal_state = STV090x_NOAGC1;
         } else {
                 reg = STV090x_READ_DEMOD(state, DEMOD);
                 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
 
-                if (state->dev_ver <= 0x20) {
+                if (state->internal->dev_ver <= 0x20) {
                         /* rolloff to auto mode if DVBS2 */
                         STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
                 } else {
@@ -3199,18 +3319,17 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
                 }
         }
 
-        /* need to check for AGC1 state */
-
-
+        if (signal_state == STV090x_NOAGC1)
+                return signal_state;
 
         if (state->algo == STV090x_BLIND_SEARCH)
                 lock = stv090x_blind_search(state);
 
         else if (state->algo == STV090x_COLD_SEARCH)
-                lock = stv090x_get_coldlock(state, timeout_dmd);
+                lock = stv090x_get_coldlock(state, state->DemodTimeout);
 
         else if (state->algo == STV090x_WARM_SEARCH)
-                lock = stv090x_get_dmdlock(state, timeout_dmd);
+                lock = stv090x_get_dmdlock(state, state->DemodTimeout);
 
         if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
                 if (!low_sr) {
@@ -3225,7 +3344,7 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
         if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
                 stv090x_optimize_track(state);
 
-                if (state->dev_ver >= 0x20) {
+                if (state->internal->dev_ver >= 0x20) {
                         /* >= Cut 2.0 :release TS reset after
                          * demod lock and optimized Tracking
                          */
@@ -3245,8 +3364,9 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
                                 goto err;
                 }
 
-                if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
-                        lock = 1;
+                lock = stv090x_get_lock(state, state->FecTimeout,
+                                state->FecTimeout);
+                if (lock) {
                         if (state->delsys == STV090x_DVBS2) {
                                 stv090x_set_s2rolloff(state);
 
@@ -3273,13 +3393,14 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
                         if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
                                 goto err;
                 } else {
-                        lock = 0;
                         signal_state = STV090x_NODATA;
                         no_signal = stv090x_chk_signal(state);
                 }
         }
         return signal_state;
 
+err_gateoff:
+        stv090x_i2c_gate_ctrl(fe, 0);
 err:
         dprintk(FE_ERROR, 1, "I/O error");
         return -1;
@@ -3290,13 +3411,22 @@ static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_fron
         struct stv090x_state *state = fe->demodulator_priv;
         struct dtv_frontend_properties *props = &fe->dtv_property_cache;
 
+        if (p->frequency == 0)
+                return DVBFE_ALGO_SEARCH_INVALID;
+
         state->delsys = props->delivery_system;
         state->frequency = p->frequency;
         state->srate = p->u.qpsk.symbol_rate;
         state->search_mode = STV090x_SEARCH_AUTO;
         state->algo = STV090x_COLD_SEARCH;
         state->fec = STV090x_PRERR;
-        state->search_range = 2000000;
+        if (state->srate > 10000000) {
+                dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
+                state->search_range = 10000000;
+        } else {
+                dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
+                state->search_range = 5000000;
+        }
 
         if (stv090x_algo(state) == STV090x_RANGEOK) {
                 dprintk(FE_DEBUG, 1, "Search success!");
@@ -3309,7 +3439,6 @@ static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_fron
         return DVBFE_ALGO_SEARCH_ERROR;
 }
 
-/* FIXME! */
 static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
 {
         struct stv090x_state *state = fe->demodulator_priv;
@@ -3331,9 +3460,16 @@ static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
                 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
                 reg = STV090x_READ_DEMOD(state, DSTATUS);
                 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
-                        reg = STV090x_READ_DEMOD(state, TSSTATUS);
-                        if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
-                                *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+                        reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
+                        if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
+                                reg = STV090x_READ_DEMOD(state, TSSTATUS);
+                                if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
+                                        *status = FE_HAS_SIGNAL |
+                                                  FE_HAS_CARRIER |
+                                                  FE_HAS_VITERBI |
+                                                  FE_HAS_SYNC |
+                                                  FE_HAS_LOCK;
+                                }
                         }
                 }
                 break;
@@ -3346,7 +3482,11 @@ static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
                         if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
                                 reg = STV090x_READ_DEMOD(state, TSSTATUS);
                                 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
-                                        *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+                                        *status = FE_HAS_SIGNAL |
+                                                  FE_HAS_CARRIER |
+                                                  FE_HAS_VITERBI |
+                                                  FE_HAS_SYNC |
+                                                  FE_HAS_LOCK;
                                 }
                         }
                 }
@@ -3412,14 +3552,12 @@ static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
         int res = 0;
         int min = 0, med;
 
-        if (val < tab[min].read)
-                res = tab[min].real;
-        else if (val >= tab[max].read)
-                res = tab[max].real;
-        else {
+        if ((val >= tab[min].read && val < tab[max].read) ||
+            (val >= tab[max].read && val < tab[min].read)) {
                 while ((max - min) > 1) {
                         med = (max + min) / 2;
-                        if (val >= tab[min].read && val < tab[med].read)
+                        if ((val >= tab[min].read && val < tab[med].read) ||
+                            (val >= tab[med].read && val < tab[min].read))
                                 max = med;
                         else
                                 min = med;
@@ -3428,6 +3566,18 @@ static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
                        (tab[max].real - tab[min].real) /
                        (tab[max].read - tab[min].read)) +
                         tab[min].real;
+        } else {
+                if (tab[min].read < tab[max].read) {
+                        if (val < tab[min].read)
+                                res = tab[min].real;
+                        else if (val >= tab[max].read)
+                                res = tab[max].real;
+                } else {
+                        if (val >= tab[min].read)
+                                res = tab[min].real;
+                        else if (val < tab[max].read)
+                                res = tab[max].real;
+                }
         }
 
         return res;
@@ -3437,16 +3587,22 @@ static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
 {
         struct stv090x_state *state = fe->demodulator_priv;
         u32 reg;
-        s32 agc;
+        s32 agc_0, agc_1, agc;
+        s32 str;
 
         reg = STV090x_READ_DEMOD(state, AGCIQIN1);
-        agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
+        agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
+        reg = STV090x_READ_DEMOD(state, AGCIQIN0);
+        agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
+        agc = MAKEWORD16(agc_1, agc_0);
 
-        *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
+        str = stv090x_table_lookup(stv090x_rf_tab,
+                ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
         if (agc > stv090x_rf_tab[0].read)
-                *strength = 5;
+                str = 0;
         else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
-                *strength = -100;
+                str = -100;
+        *strength = (str + 100) * 0xFFFF / 100;
 
         return 0;
 }
@@ -3457,6 +3613,8 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
         u32 reg_0, reg_1, reg, i;
         s32 val_0, val_1, val = 0;
         u8 lock_f;
+        s32 div;
+        u32 last;
 
         switch (state->delsys) {
         case STV090x_DVBS2:
@@ -3468,14 +3626,15 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
                                 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
                                 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
                                 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
-                                val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
+                                val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
                                 val  += MAKEWORD16(val_1, val_0);
                                 msleep(1);
                         }
                         val /= 16;
-                        *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val);
-                        if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read)
-                                *cnr = 1000;
+                        last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
+                        div = stv090x_s2cn_tab[0].read -
+                              stv090x_s2cn_tab[last].read;
+                        *cnr = 0xFFFF - ((val * 0xFFFF) / div);
                 }
                 break;
 
@@ -3489,14 +3648,15 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
                                 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
                                 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
                                 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
-                                val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
+                                val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
                                 val  += MAKEWORD16(val_1, val_0);
                                 msleep(1);
                         }
                         val /= 16;
-                        *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val);
-                        if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read)
-                                *cnr = 1000;
+                        last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
+                        div = stv090x_s1cn_tab[0].read -
+                              stv090x_s1cn_tab[last].read;
+                        *cnr = 0xFFFF - ((val * 0xFFFF) / div);
                 }
                 break;
         default:
@@ -3553,7 +3713,8 @@ static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_ma
 
         reg = STV090x_READ_DEMOD(state, DISTXCTL);
 
-        STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 2);
+        STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
+                (state->config->diseqc_envelope_mode) ? 4 : 2);
         STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
         if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
                 goto err;
@@ -3605,10 +3766,10 @@ static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t
         reg = STV090x_READ_DEMOD(state, DISTXCTL);
 
         if (burst == SEC_MINI_A) {
-                mode = 3;
+                mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
                 value = 0x00;
         } else {
-                mode = 2;
+                mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
                 value = 0xFF;
         }
 
@@ -3725,6 +3886,15 @@ static void stv090x_release(struct dvb_frontend *fe)
 {
         struct stv090x_state *state = fe->demodulator_priv;
 
+        state->internal->num_used--;
+        if (state->internal->num_used <= 0) {
+
+                dprintk(FE_ERROR, 1, "Actually removing");
+
+                remove_dev(state->internal);
+                kfree(state->internal);
+        }
+
         kfree(state);
 }
 
@@ -3732,6 +3902,8 @@ static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc
 {
         u32 reg = 0;
 
+        reg = stv090x_read_reg(state, STV090x_GENCFG);
+
         switch (ldpc_mode) {
         case STV090x_DUAL:
         default:
@@ -3854,10 +4026,10 @@ static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
         if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
                 goto err;
 
-        state->mclk = stv090x_get_mclk(state);
+        state->internal->mclk = stv090x_get_mclk(state);
 
         /*Set the DiseqC frequency to 22KHz */
-        div = state->mclk / 704000;
+        div = state->internal->mclk / 704000;
         if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
                 goto err;
         if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
@@ -3873,7 +4045,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
 {
         u32 reg;
 
-        if (state->dev_ver >= 0x20) {
+        if (state->internal->dev_ver >= 0x20) {
                 switch (state->config->ts1_mode) {
                 case STV090x_TSMODE_PARALLEL_PUNCTURED:
                 case STV090x_TSMODE_DVBCI:
@@ -4045,6 +4217,71 @@ static int stv090x_set_tspath(struct stv090x_state *state)
         default:
                 break;
         }
+
+        if (state->config->ts1_clk > 0) {
+                u32 speed;
+
+                switch (state->config->ts1_mode) {
+                case STV090x_TSMODE_PARALLEL_PUNCTURED:
+                case STV090x_TSMODE_DVBCI:
+                default:
+                        speed = state->internal->mclk /
+                                (state->config->ts1_clk / 4);
+                        if (speed < 0x08)
+                                speed = 0x08;
+                        if (speed > 0xFF)
+                                speed = 0xFF;
+                        break;
+                case STV090x_TSMODE_SERIAL_PUNCTURED:
+                case STV090x_TSMODE_SERIAL_CONTINUOUS:
+                        speed = state->internal->mclk /
+                                (state->config->ts1_clk / 32);
+                        if (speed < 0x20)
+                                speed = 0x20;
+                        if (speed > 0xFF)
+                                speed = 0xFF;
+                        break;
+                }
+                reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
+                STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
+                if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
+                        goto err;
+                if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
+                        goto err;
+        }
+
+        if (state->config->ts2_clk > 0) {
+                u32 speed;
+
+                switch (state->config->ts2_mode) {
+                case STV090x_TSMODE_PARALLEL_PUNCTURED:
+                case STV090x_TSMODE_DVBCI:
+                default:
+                        speed = state->internal->mclk /
+                                (state->config->ts2_clk / 4);
+                        if (speed < 0x08)
+                                speed = 0x08;
+                        if (speed > 0xFF)
+                                speed = 0xFF;
+                        break;
+                case STV090x_TSMODE_SERIAL_PUNCTURED:
+                case STV090x_TSMODE_SERIAL_CONTINUOUS:
+                        speed = state->internal->mclk /
+                                (state->config->ts2_clk / 32);
+                        if (speed < 0x20)
+                                speed = 0x20;
+                        if (speed > 0xFF)
+                                speed = 0xFF;
+                        break;
+                }
+                reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
+                STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
+                if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
+                        goto err;
+                if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
+                        goto err;
+        }
+
         reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
         STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
         if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
@@ -4073,6 +4310,15 @@ static int stv090x_init(struct dvb_frontend *fe)
         const struct stv090x_config *config = state->config;
         u32 reg;
 
+        if (state->internal->mclk == 0) {
+                stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
+                msleep(5);
+                if (stv090x_write_reg(state, STV090x_SYNTCTRL,
+                                      0x20 | config->clk_mode) < 0)
+                        goto err;
+                stv090x_get_mclk(state);
+        }
+
         if (stv090x_wakeup(fe) < 0) {
                 dprintk(FE_ERROR, 1, "Error waking device");
                 goto err;
@@ -4095,12 +4341,12 @@ static int stv090x_init(struct dvb_frontend *fe)
 
         if (config->tuner_set_mode) {
                 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
-                        goto err;
+                        goto err_gateoff;
         }
 
         if (config->tuner_init) {
                 if (config->tuner_init(fe) < 0)
-                        goto err;
+                        goto err_gateoff;
         }
 
         if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
@@ -4110,6 +4356,9 @@ static int stv090x_init(struct dvb_frontend *fe)
                 goto err;
 
         return 0;
+
+err_gateoff:
+        stv090x_i2c_gate_ctrl(fe, 0);
 err:
         dprintk(FE_ERROR, 1, "I/O error");
         return -1;
@@ -4141,16 +4390,26 @@ static int stv090x_setup(struct dvb_frontend *fe)
         }
 
         /* STV090x init */
-        if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
+
+        /* Stop Demod */
+        if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
+                goto err;
+        if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
                 goto err;
 
         msleep(5);
 
-        if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
+        /* Set No Tuner Mode */
+        if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
+                goto err;
+        if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
                 goto err;
 
+        /* I2C repeater OFF */
         STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
-        if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) /* repeater OFF */
+        if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
+                goto err;
+        if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
                 goto err;
 
         if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
@@ -4169,8 +4428,8 @@ static int stv090x_setup(struct dvb_frontend *fe)
                         goto err;
         }
 
-        state->dev_ver = stv090x_read_reg(state, STV090x_MID);
-        if (state->dev_ver >= 0x20) {
+        state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
+        if (state->internal->dev_ver >= 0x20) {
                 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
                         goto err;
 
@@ -4181,27 +4440,39 @@ static int stv090x_setup(struct dvb_frontend *fe)
                                 goto err;
                 }
 
-        } else if (state->dev_ver < 0x20) {
+        } else if (state->internal->dev_ver < 0x20) {
                 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
-                        state->dev_ver);
+                        state->internal->dev_ver);
 
                 goto err;
-        } else if (state->dev_ver > 0x30) {
+        } else if (state->internal->dev_ver > 0x30) {
                 /* we shouldn't bail out from here */
                 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
-                        state->dev_ver);
+                        state->internal->dev_ver);
         }
 
+        /* ADC1 range */
+        reg = stv090x_read_reg(state, STV090x_TSTTNR1);
+        STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
+                (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
+        if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
+                goto err;
+
+        /* ADC2 range */
+        reg = stv090x_read_reg(state, STV090x_TSTTNR3);
+        STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
+                (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
+        if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
+                goto err;
+
         if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
                 goto err;
         if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
                 goto err;
 
-        stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
-        msleep(5);
-        if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
-                goto err;
-        stv090x_get_mclk(state);
+        /* workaround for stuck DiSEqC output */
+        if (config->diseqc_envelope_mode)
+                stv090x_send_diseqc_burst(fe, SEC_MINI_A);
 
         return 0;
 err:
@@ -4252,6 +4523,7 @@ struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
                                     enum stv090x_demodulator demod)
 {
         struct stv090x_state *state = NULL;
+        struct stv090x_dev *temp_int;
 
         state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
         if (state == NULL)
@@ -4267,8 +4539,32 @@ struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
         state->device                           = config->device;
         state->rolloff                          = STV090x_RO_35; /* default */
 
-        if (state->demod == STV090x_DEMODULATOR_0)
-                mutex_init(&demod_lock);
+        temp_int = find_dev(state->i2c,
+                                state->config->address);
+
+        if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) {
+                state->internal = temp_int->internal;
+                state->internal->num_used++;
+                dprintk(FE_INFO, 1, "Found Internal Structure!");
+                dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
+                        state->device == STV0900 ? "STV0900" : "STV0903",
+                        demod,
+                        state->internal->dev_ver);
+                return &state->frontend;
+        } else {
+                state->internal = kmalloc(sizeof(struct stv090x_internal),
+                                          GFP_KERNEL);
+                temp_int = append_internal(state->internal);
+                state->internal->num_used = 1;
+                state->internal->mclk = 0;
+                state->internal->dev_ver = 0;
+                state->internal->i2c_adap = state->i2c;
+                state->internal->i2c_addr = state->config->address;
+                dprintk(FE_INFO, 1, "Create New Internal Structure!");
+        }
+
+        mutex_init(&state->internal->demod_lock);
+        mutex_init(&state->internal->tuner_lock);
 
         if (stv090x_sleep(&state->frontend) < 0) {
                 dprintk(FE_ERROR, 1, "Error putting device to sleep");
@@ -4284,10 +4580,10 @@ struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
                 goto error;
         }
 
-        dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
+        dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
                state->device == STV0900 ? "STV0900" : "STV0903",
                demod,
-               state->dev_ver);
+               state->internal->dev_ver);
 
         return &state->frontend;
 
diff --git a/drivers/media/dvb/frontends/stv090x.h b/drivers/media/dvb/frontends/stv090x.h
index e968c98bb70f..30f01a6902ac 100644
--- a/drivers/media/dvb/frontends/stv090x.h
+++ b/drivers/media/dvb/frontends/stv090x.h
@@ -60,6 +60,11 @@ enum stv090x_i2crpt {
         STV090x_RPTLEVEL_2      = 7,
 };
 
+enum stv090x_adc_range {
+        STV090x_ADC_2Vpp        = 0,
+        STV090x_ADC_1Vpp        = 1
+};
+
 struct stv090x_config {
         enum stv090x_device     device;
         enum stv090x_mode       demod_mode;
@@ -68,13 +73,19 @@ struct stv090x_config {
         u32 xtal; /* default: 8000000 */
         u8 address; /* default: 0x68 */
 
-        u32 ref_clk; /* default: 16000000 FIXME to tuner config */
-
         u8 ts1_mode;
         u8 ts2_mode;
+        u32 ts1_clk;
+        u32 ts2_clk;
 
         enum stv090x_i2crpt     repeater_level;
 
+        u8                      tuner_bbgain; /* default: 10db */
+        enum stv090x_adc_range  adc1_range; /* default: 2Vpp */
+        enum stv090x_adc_range  adc2_range; /* default: 2Vpp */
+
+        bool diseqc_envelope_mode;
+
         int (*tuner_init) (struct dvb_frontend *fe);
         int (*tuner_set_mode) (struct dvb_frontend *fe, enum tuner_mode mode);
         int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency);
diff --git a/drivers/media/dvb/frontends/stv090x_priv.h b/drivers/media/dvb/frontends/stv090x_priv.h
index 5a4a01740d88..5b780c80d496 100644
--- a/drivers/media/dvb/frontends/stv090x_priv.h
+++ b/drivers/media/dvb/frontends/stv090x_priv.h
@@ -83,7 +83,7 @@
 
 #define STV090x_IQPOWER_THRESHOLD         30
 #define STV090x_SEARCH_AGC2_TH_CUT20     700
-#define STV090x_SEARCH_AGC2_TH_CUT30    1200
+#define STV090x_SEARCH_AGC2_TH_CUT30    1400
 
 #define STV090x_SEARCH_AGC2_TH(__ver)   \
         ((__ver <= 0x20) ?              \
@@ -91,6 +91,7 @@
         STV090x_SEARCH_AGC2_TH_CUT30)
 
 enum stv090x_signal_state {
+        STV090x_NOAGC1,
         STV090x_NOCARRIER,
         STV090x_NODATA,
         STV090x_DATAOK,
@@ -229,11 +230,23 @@ struct stv090x_tab {
         s32 read;
 };
 
+struct stv090x_internal {
+        struct i2c_adapter      *i2c_adap;
+        u8                      i2c_addr;
+
+        struct mutex            demod_lock; /* Lock access to shared register */
+        struct mutex            tuner_lock; /* Lock access to tuners */
+        s32                     mclk; /* Masterclock Divider factor */
+        u32                     dev_ver;
+
+        int                     num_used;
+};
+
 struct stv090x_state {
         enum stv090x_device             device;
         enum stv090x_demodulator        demod;
         enum stv090x_mode               demod_mode;
-        u32                             dev_ver;
+        struct stv090x_internal         *internal;
 
         struct i2c_adapter              *i2c;
         const struct stv090x_config     *config;
@@ -255,11 +268,8 @@ struct stv090x_state {
         u32                             frequency;
         u32                             srate;
 
-        s32                             mclk; /* Masterclock Divider factor */
         s32                             tuner_bw;
 
-        u32                             tuner_refclk;
-
         s32                             search_range;
 
         s32                             DemodTimeout;
diff --git a/drivers/media/dvb/frontends/stv090x_reg.h b/drivers/media/dvb/frontends/stv090x_reg.h
index 57b6abbbd32d..2502855dd784 100644
--- a/drivers/media/dvb/frontends/stv090x_reg.h
+++ b/drivers/media/dvb/frontends/stv090x_reg.h
@@ -44,7 +44,7 @@
 #define STV090x_OFFST_OUTSERRS2_HZ_FIELD        5
 #define STV090x_WIDTH_OUTSERRS2_HZ_FIELD        1
 #define STV090x_OFFST_OUTSERRS3_HZ_FIELD        4
-#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD        1
+#define STV090x_WIDTH_OUTSERRS3_HZ_FIELD        1
 #define STV090x_OFFST_OUTPARRS3_HZ_FIELD        3
 #define STV090x_WIDTH_OUTPARRS3_HZ_FIELD        1
 
@@ -113,24 +113,24 @@
 #define STV090x_IRQMASK3                        0xf124
 #define STV090x_OFFST_MPLL_LOCK_FIELD           5
 #define STV090x_WIDTH_MPLL_LOCK_FIELD           1
-#define STV090x_OFFST_MSTREAM_LCK_3_FIELD       2
-#define STV090x_WIDTH_MSTREAM_LCK_3_FIELD       3
-#define STV090x_OFFST_MSTREAM_LCK_2_FIELD       2
-#define STV090x_WIDTH_MSTREAM_LCK_2_FIELD       3
+#define STV090x_OFFST_MSTREAM_LCK_3_FIELD       4
+#define STV090x_WIDTH_MSTREAM_LCK_3_FIELD       1
+#define STV090x_OFFST_MSTREAM_LCK_2_FIELD       3
+#define STV090x_WIDTH_MSTREAM_LCK_2_FIELD       1
 #define STV090x_OFFST_MSTREAM_LCK_1_FIELD       2
-#define STV090x_WIDTH_MSTREAM_LCK_1_FIELD       3
+#define STV090x_WIDTH_MSTREAM_LCK_1_FIELD       1
 #define STV090x_OFFST_MDVBS1_PRF_2_FIELD        1
 #define STV090x_WIDTH_MDVBS1_PRF_2_FIELD        1
 #define STV090x_OFFST_MDVBS1_PRF_1_FIELD        0
 #define STV090x_WIDTH_MDVBS1_PRF_1_FIELD        1
 
 #define STV090x_IRQMASK2                        0xf125
-#define STV090x_OFFST_MSPY_ENDSIM_3_FIELD       5
-#define STV090x_WIDTH_MSPY_ENDSIM_3_FIELD       3
-#define STV090x_OFFST_MSPY_ENDSIM_2_FIELD       5
-#define STV090x_WIDTH_MSPY_ENDSIM_2_FIELD       3
+#define STV090x_OFFST_MSPY_ENDSIM_3_FIELD       7
+#define STV090x_WIDTH_MSPY_ENDSIM_3_FIELD       1
+#define STV090x_OFFST_MSPY_ENDSIM_2_FIELD       6
+#define STV090x_WIDTH_MSPY_ENDSIM_2_FIELD       1
 #define STV090x_OFFST_MSPY_ENDSIM_1_FIELD       5
-#define STV090x_WIDTH_MSPY_ENDSIM_1_FIELD       3
+#define STV090x_WIDTH_MSPY_ENDSIM_1_FIELD       1
 #define STV090x_OFFST_MPKTDEL_ERROR_2_FIELD     4
 #define STV090x_WIDTH_MPKTDEL_ERROR_2_FIELD     1
 #define STV090x_OFFST_MPKTDEL_LOCKB_2_FIELD     3
@@ -370,7 +370,7 @@
 #define STV090x_OFFST_SELX1RATIO_FIELD          5
 #define STV090x_WIDTH_SELX1RATIO_FIELD          1
 #define STV090x_OFFST_STOP_PLL_FIELD            3
-#define STV090x_WIDTH_SELX1RATIO_FIELD          1
+#define STV090x_WIDTH_STOP_PLL_FIELD            1
 #define STV090x_OFFST_BYPASSPLLFSK_FIELD        2
 #define STV090x_WIDTH_BYPASSPLLFSK_FIELD        1
 #define STV090x_OFFST_SELOSCI_FIELD             1
@@ -616,7 +616,7 @@
 #define STV090x_OFFST_Px_CONT_TONE_FIELD        4
 #define STV090x_WIDTH_Px_CONT_TONE_FIELD        1
 #define STV090x_OFFST_Px_FIFO_4BREADY_FIELD     3
-#define STV090x_WIDTH_Px_FIFO_4BREADY_FIELD     2
+#define STV090x_WIDTH_Px_FIFO_4BREADY_FIELD     1
 #define STV090x_OFFST_Px_FIFO_EMPTY_FIELD       2
 #define STV090x_WIDTH_Px_FIFO_EMPTY_FIELD       1
 #define STV090x_OFFST_Px_ABORT_DISRX_FIELD      0
@@ -847,12 +847,10 @@
 #define STV090x_WIDTH_Px_DVBS2_ENABLE_FIELD     1
 #define STV090x_OFFST_Px_DVBS1_ENABLE_FIELD     6
 #define STV090x_WIDTH_Px_DVBS1_ENABLE_FIELD     1
-#define STV090x_OFFST_Px_CFR_AUTOSCAN_FIELD     5 /* check */
-#define STV090x_WIDTH_Px_CFR_AUTOSCAN_FIELD     1
-#define STV090x_OFFST_Px_SCAN_ENABLE_FIELD      4 /* check */
+#define STV090x_OFFST_Px_SCAN_ENABLE_FIELD      4
 #define STV090x_WIDTH_Px_SCAN_ENABLE_FIELD      1
-#define STV090x_OFFST_Px_TUN_AUTOSCAN_FIELD     3
-#define STV090x_WIDTH_Px_TUN_AUTOSCAN_FIELD     1
+#define STV090x_OFFST_Px_CFR_AUTOSCAN_FIELD     3
+#define STV090x_WIDTH_Px_CFR_AUTOSCAN_FIELD     1
 #define STV090x_OFFST_Px_NOFORCE_RELOCK_FIELD   2
 #define STV090x_WIDTH_Px_NOFORCE_RELOCK_FIELD   1
 #define STV090x_OFFST_Px_TUN_RNG_FIELD          0
@@ -885,7 +883,7 @@
 #define STV090x_P2_DMDFLYW                      STV090x_Px_DMDFLYW(2)
 #define STV090x_OFFST_Px_I2C_IRQVAL_FIELD       4
 #define STV090x_WIDTH_Px_I2C_IRQVAL_FIELD       4
-#define STV090x_OFFST_Px_FLYWHEEL_CPT_FIELD     0 /* check */
+#define STV090x_OFFST_Px_FLYWHEEL_CPT_FIELD     0
 #define STV090x_WIDTH_Px_FLYWHEEL_CPT_FIELD     4
 
 #define STV090x_Px_DSTATUS3(__x)                (0xF41D - (__x - 1) * 0x200)
@@ -1048,12 +1046,12 @@
 #define STV090x_P1_CFRINC1                      STV090x_Px_CFRINC1(1)
 #define STV090x_P2_CFRINC1                      STV090x_Px_CFRINC1(2)
 #define STV090x_OFFST_Px_CFR_INC1_FIELD         0
-#define STV090x_WIDTH_Px_CFR_INC1_FIELD         7
+#define STV090x_WIDTH_Px_CFR_INC1_FIELD         7 /* check */
 
 #define STV090x_Px_CFRINC0(__x)                 (0xF44B - (__x - 1) * 0x200)
 #define STV090x_P1_CFRINC0                      STV090x_Px_CFRINC0(1)
 #define STV090x_P2_CFRINC0                      STV090x_Px_CFRINC0(2)
-#define STV090x_OFFST_Px_CFR_INC0_FIELD         4
+#define STV090x_OFFST_Px_CFR_INC0_FIELD         4 /* check */
 #define STV090x_WIDTH_Px_CFR_INC0_FIELD         4
 
 #define STV090x_Pn_CFRy(__x, __y)               (0xF44E - (__x - 1) * 0x200 - __y * 0x1)
@@ -1145,14 +1143,14 @@
 #define STV090x_Px_SFRINIT1(__x)                (0xF45E - (__x - 1) * 0x200)
 #define STV090x_P1_SFRINIT1                     STV090x_Px_SFRINIT1(1)
 #define STV090x_P2_SFRINIT1                     STV090x_Px_SFRINIT1(2)
-#define STV090x_OFFST_Px_SFR_INIT_FIELD         0
-#define STV090x_WIDTH_Px_SFR_INIT_FIELD         8
+#define STV090x_OFFST_Px_SFR_INIT1_FIELD        0
+#define STV090x_WIDTH_Px_SFR_INIT1_FIELD        7
 
 #define STV090x_Px_SFRINIT0(__x)                (0xF45F - (__x - 1) * 0x200)
 #define STV090x_P1_SFRINIT0                     STV090x_Px_SFRINIT0(1)
 #define STV090x_P2_SFRINIT0                     STV090x_Px_SFRINIT0(2)
-#define STV090x_OFFST_Px_SFR_INIT_FIELD         0
-#define STV090x_WIDTH_Px_SFR_INIT_FIELD         8
+#define STV090x_OFFST_Px_SFR_INIT0_FIELD        0
+#define STV090x_WIDTH_Px_SFR_INIT0_FIELD        8
 
 #define STV090x_Px_SFRUP1(__x)                  (0xF460 - (__x - 1) * 0x200)
 #define STV090x_P1_SFRUP1                       STV090x_Px_SFRUP1(1)
@@ -1178,7 +1176,7 @@
 #define STV090x_OFFST_Px_SYMB_FREQ_LOW0_FIELD   0
 #define STV090x_WIDTH_Px_SYMB_FREQ_LOW0_FIELD   8
 
-#define STV090x_Px_SFRy(__x, __y)               (0xF464 - (__x-1) * 0x200 + (3 - __y))
+#define STV090x_Px_SFRy(__x, __y)               (0xF467 - (__x-1) * 0x200 - __y)
 #define STV090x_P1_SFR0                         STV090x_Px_SFRy(1, 0)
 #define STV090x_P1_SFR1                         STV090x_Px_SFRy(1, 1)
 #define STV090x_P1_SFR2                         STV090x_Px_SFRy(1, 2)
@@ -1188,7 +1186,7 @@
 #define STV090x_P2_SFR2                         STV090x_Px_SFRy(2, 2)
 #define STV090x_P2_SFR3                         STV090x_Px_SFRy(2, 3)
 #define STV090x_OFFST_Px_SYMB_FREQ_FIELD        0
-#define STV090x_WIDTH_Px_SYMB_FREQ_FIELD        32
+#define STV090x_WIDTH_Px_SYMB_FREQ_FIELD        8
 
 #define STV090x_Px_TMGREG2(__x)                 (0xF468 - (__x - 1) * 0x200)
 #define STV090x_P1_TMGREG2                      STV090x_Px_TMGREG2(1)
@@ -1198,7 +1196,7 @@
 
 #define STV090x_Px_TMGREG1(__x)                 (0xF469 - (__x - 1) * 0x200)
 #define STV090x_P1_TMGREG1                      STV090x_Px_TMGREG1(1)
-#define STV090x_P2_TMGREG1                              STV090x_Px_TMGREG1(2)
+#define STV090x_P2_TMGREG1                      STV090x_Px_TMGREG1(2)
 #define STV090x_OFFST_Px_TMGREG_FIELD           0
 #define STV090x_WIDTH_Px_TMGREG_FIELD           8
 
@@ -1230,7 +1228,7 @@
 #define STV090x_OFFST_Px_MU_EQUALDFE_FIELD      0
 #define STV090x_WIDTH_Px_MU_EQUALDFE_FIELD      3
 
-#define STV090x_Px_EQUAIy(__x, __y)             (0xf470 - (__x - 1) * 0x200 + (__y - 1))
+#define STV090x_Px_EQUAIy(__x, __y)     (0xf470 - (__x-1) * 0x200 + 2 * (__y-1))
 #define STV090x_P1_EQUAI1                       STV090x_Px_EQUAIy(1, 1)
 #define STV090x_P1_EQUAI2                       STV090x_Px_EQUAIy(1, 2)
 #define STV090x_P1_EQUAI3                       STV090x_Px_EQUAIy(1, 3)
@@ -1251,7 +1249,7 @@
 #define STV090x_OFFST_Px_EQUA_ACCIy_FIELD       0
 #define STV090x_WIDTH_Px_EQUA_ACCIy_FIELD       8
 
-#define STV090x_Px_EQUAQy(__x, __y)             (0xf471 - (__x - 1) * 0x200 + (__y - 1))
+#define STV090x_Px_EQUAQy(__x, __y)     (0xf471 - (__x-1) * 0x200 + 2 * (__y-1))
 #define STV090x_P1_EQUAQ1                       STV090x_Px_EQUAQy(1, 1)
 #define STV090x_P1_EQUAQ2                       STV090x_Px_EQUAQy(1, 2)
 #define STV090x_P1_EQUAQ3                       STV090x_Px_EQUAQy(1, 3)
@@ -1390,7 +1388,7 @@
 #define STV090x_OFFST_Px_CAR2S2_16A_ALPH_E_FIELD        0
 #define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_E_FIELD        4
 
-#define STV090x_Px_ACLC2S232A(__x)              (0xf499 - (__x - 1) * 0x200)
+#define STV090x_Px_ACLC2S232A(__x)              (0xf49A - (__x - 1) * 0x200)
 #define STV090x_P1_ACLC2S232A                   STV090x_Px_ACLC2S232A(1)
 #define STV090x_P2_ACLC2S232A                   STV090x_Px_ACLC2S232A(2)
 #define STV090x_OFFST_Px_CAR2S2_32A_ALPH_M_FIELD        4
@@ -1414,7 +1412,7 @@
 #define STV090x_OFFST_Px_CAR2S2_8_BETA_E_FIELD  0
 #define STV090x_WIDTH_Px_CAR2S2_8_BETA_E_FIELD  4
 
-#define STV090x_Px_BCLC2S216A(__x)              (0xf49d - (__x - 1) * 0x200)
+#define STV090x_Px_BCLC2S216A(__x)              (0xf49e - (__x - 1) * 0x200)
 #define STV090x_P1_BCLC2S216A                   STV090x_Px_BCLC2S216A(1)
 #define STV090x_P2_BCLC2S216A                   STV090x_Px_BCLC2S216A(1)
 #define STV090x_OFFST_Px_CAR2S2_16A_BETA_M_FIELD        4
@@ -1422,7 +1420,7 @@
 #define STV090x_OFFST_Px_CAR2S2_16A_BETA_E_FIELD        0
 #define STV090x_WIDTH_Px_CAR2S2_16A_BETA_E_FIELD        4
 
-#define STV090x_Px_BCLC2S232A(__x)              (0xf49d - (__x - 1) * 0x200)
+#define STV090x_Px_BCLC2S232A(__x)              (0xf49f - (__x - 1) * 0x200)
 #define STV090x_P1_BCLC2S232A                   STV090x_Px_BCLC2S232A(1)
 #define STV090x_P2_BCLC2S232A                   STV090x_Px_BCLC2S232A(1)
 #define STV090x_OFFST_Px_CAR2S2_32A_BETA_M_FIELD        4
@@ -1458,7 +1456,7 @@
 #define STV090x_P1_MODCODLST1                   STV090x_Px_MODCODLST1(1)
 #define STV090x_P2_MODCODLST1                   STV090x_Px_MODCODLST1(2)
 #define STV090x_OFFST_Px_DIS_MODCOD29_FIELD     4
-#define STV090x_WIDTH_Px_DIS_MODCOD29T_FIELD    4
+#define STV090x_WIDTH_Px_DIS_MODCOD29_FIELD     4
 #define STV090x_OFFST_Px_DIS_32PSK_9_10_FIELD   0
 #define STV090x_WIDTH_Px_DIS_32PSK_9_10_FIELD   4
 
@@ -2180,7 +2178,7 @@
 #define STV090x_WIDTH_Px_TSFIFOSPEED_STORE_FIELD        1
 #define STV090x_OFFST_Px_DILXX_RESET_FIELD              5
 #define STV090x_WIDTH_Px_DILXX_RESET_FIELD              1
-#define STV090x_OFFST_Px_TSSERIAL_IMPOS_FIELD           5
+#define STV090x_OFFST_Px_TSSERIAL_IMPOS_FIELD           4
 #define STV090x_WIDTH_Px_TSSERIAL_IMPOS_FIELD           1
 #define STV090x_OFFST_Px_SCRAMBDETECT_FIELD             1
 #define STV090x_WIDTH_Px_SCRAMBDETECT_FIELD             1
@@ -2190,7 +2188,7 @@
 #define STV090x_P1_TSBITRATE1                           STV090x_Px_TSBITRATEy(1, 1)
 #define STV090x_P2_TSBITRATE0                           STV090x_Px_TSBITRATEy(2, 0)
 #define STV090x_P2_TSBITRATE1                           STV090x_Px_TSBITRATEy(2, 1)
-#define STV090x_OFFST_Px_TSFIFO_BITRATE_FIELD           7
+#define STV090x_OFFST_Px_TSFIFO_BITRATE_FIELD           0
 #define STV090x_WIDTH_Px_TSFIFO_BITRATE_FIELD           8
 
 #define STV090x_Px_ERRCTRL1(__x)                        (0xF598 - (__x - 1) * 0x200)
diff --git a/drivers/media/dvb/frontends/stv6110.c b/drivers/media/dvb/frontends/stv6110.c
index dcf1b21ea974..2dca7c8e5148 100644
--- a/drivers/media/dvb/frontends/stv6110.c
+++ b/drivers/media/dvb/frontends/stv6110.c
@@ -22,6 +22,7 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/dvb/frontend.h>
 
@@ -37,6 +38,7 @@ struct stv6110_priv {
 
         u32 mclk;
         u8 clk_div;
+        u8 gain;
         u8 regs[8];
 };
 
@@ -255,7 +257,7 @@ static int stv6110_set_frequency(struct dvb_frontend *fe, u32 frequency)
         u8 ret = 0x04;
         u32 divider, ref, p, presc, i, result_freq, vco_freq;
         s32 p_calc, p_calc_opt = 1000, r_div, r_div_opt = 0, p_val;
-        s32 srate; u8 gain;
+        s32 srate;
 
         dprintk("%s, freq=%d kHz, mclk=%d Hz\n", __func__,
                                                 frequency, priv->mclk);
@@ -273,15 +275,8 @@ static int stv6110_set_frequency(struct dvb_frontend *fe, u32 frequency)
         } else
                 srate = 15000000;
 
-        if (srate >= 15000000)
-                gain = 3; /* +6 dB */
-        else if (srate >= 5000000)
-                gain = 3; /* +6 dB */
-        else
-                gain = 3; /* +6 dB */
-
         priv->regs[RSTV6110_CTRL2] &= ~0x0f;
-        priv->regs[RSTV6110_CTRL2] |= (gain & 0x0f);
+        priv->regs[RSTV6110_CTRL2] |= (priv->gain & 0x0f);
 
         if (frequency <= 1023000) {
                 p = 1;
@@ -436,6 +431,7 @@ struct dvb_frontend *stv6110_attach(struct dvb_frontend *fe,
         priv->i2c = i2c;
         priv->mclk = config->mclk;
         priv->clk_div = config->clk_div;
+        priv->gain = config->gain;
 
         memcpy(&priv->regs, &reg0[1], 8);
 
diff --git a/drivers/media/dvb/frontends/stv6110.h b/drivers/media/dvb/frontends/stv6110.h
index 9db2402410f6..fe71bba6a26e 100644
--- a/drivers/media/dvb/frontends/stv6110.h
+++ b/drivers/media/dvb/frontends/stv6110.h
@@ -41,6 +41,7 @@
 struct stv6110_config {
         u8 i2c_address;
         u32 mclk;
+        u8 gain;
         u8 clk_div;     /* divisor value for the output clock */
 };
 
diff --git a/drivers/media/dvb/frontends/stv6110x.c b/drivers/media/dvb/frontends/stv6110x.c
index 3d8a2e01c9c4..dea4245f077c 100644
--- a/drivers/media/dvb/frontends/stv6110x.c
+++ b/drivers/media/dvb/frontends/stv6110x.c
@@ -23,6 +23,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/string.h>
 
 #include "dvb_frontend.h"
@@ -35,8 +36,6 @@ static unsigned int verbose;
 module_param(verbose, int, 0644);
 MODULE_PARM_DESC(verbose, "Set Verbosity level");
 
-static u8 stv6110x_regs[] = {0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e};
-
 static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data)
 {
         int ret;
@@ -58,12 +57,23 @@ static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data)
         return 0;
 }
 
-static int stv6110x_write_reg(struct stv6110x_state *stv6110x, u8 reg, u8 data)
+static int stv6110x_write_regs(struct stv6110x_state *stv6110x, int start, u8 data[], int len)
 {
         int ret;
         const struct stv6110x_config *config = stv6110x->config;
-        u8 buf[] = { reg, data };
-        struct i2c_msg msg = { .addr = config->addr, .flags = 0, . buf = buf, .len = 2 };
+        u8 buf[len + 1];
+        struct i2c_msg msg = {
+                .addr = config->addr,
+                .flags = 0,
+                .buf = buf,
+                .len = len + 1
+        };
+
+        if (start + len > 8)
+                return -EINVAL;
+
+        buf[0] = start;
+        memcpy(&buf[1], data, len);
 
         ret = i2c_transfer(stv6110x->i2c, &msg, 1);
         if (ret != 1) {
@@ -74,18 +84,21 @@ static int stv6110x_write_reg(struct stv6110x_state *stv6110x, u8 reg, u8 data)
         return 0;
 }
 
+static int stv6110x_write_reg(struct stv6110x_state *stv6110x, u8 reg, u8 data)
+{
+        return stv6110x_write_regs(stv6110x, reg, &data, 1);
+}
+
 static int stv6110x_init(struct dvb_frontend *fe)
 {
         struct stv6110x_state *stv6110x = fe->tuner_priv;
         int ret;
-        u8 i;
 
-        for (i = 0; i < ARRAY_SIZE(stv6110x_regs); i++) {
-                ret = stv6110x_write_reg(stv6110x, i, stv6110x_regs[i]);
-                if (ret < 0) {
-                        dprintk(FE_ERROR, 1, "Initialization failed");
-                        return -1;
-                }
+        ret = stv6110x_write_regs(stv6110x, 0, stv6110x->regs,
+                                  ARRAY_SIZE(stv6110x->regs));
+        if (ret < 0) {
+                dprintk(FE_ERROR, 1, "Initialization failed");
+                return -1;
         }
 
         return 0;
@@ -95,54 +108,56 @@ static int stv6110x_set_frequency(struct dvb_frontend *fe, u32 frequency)
 {
         struct stv6110x_state *stv6110x = fe->tuner_priv;
         u32 rDiv, divider;
-        s32 pVal, pCalc, rDivOpt = 0;
+        s32 pVal, pCalc, rDivOpt = 0, pCalcOpt = 1000;
         u8 i;
 
-        STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_K, (REFCLOCK_MHz - 16));
+        STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_K, (REFCLOCK_MHz - 16));
 
         if (frequency <= 1023000) {
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
                 pVal = 40;
         } else if (frequency <= 1300000) {
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
                 pVal = 40;
         } else if (frequency <= 2046000) {
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
                 pVal = 20;
         } else {
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
                 pVal = 20;
         }
 
         for (rDiv = 0; rDiv <= 3; rDiv++) {
                 pCalc = (REFCLOCK_kHz / 100) / R_DIV(rDiv);
 
-                if ((abs((s32)(pCalc - pVal))) < (abs((s32)(1000 - pVal))))
+                if ((abs((s32)(pCalc - pVal))) < (abs((s32)(pCalcOpt - pVal))))
                         rDivOpt = rDiv;
+
+                pCalcOpt = (REFCLOCK_kHz / 100) / R_DIV(rDivOpt);
         }
 
         divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz;
         divider = (divider + 5) / 10;
 
-        STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_R_DIV, rDivOpt);
-        STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider));
-        STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider));
+        STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_R_DIV, rDivOpt);
+        STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider));
+        STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider));
 
         /* VCO Auto calibration */
-        STV6110x_SETFIELD(stv6110x_regs[STV6110x_STAT1], STAT1_CALVCO_STRT, 1);
+        STV6110x_SETFIELD(stv6110x->regs[STV6110x_STAT1], STAT1_CALVCO_STRT, 1);
 
-        stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x_regs[STV6110x_CTRL1]);
-        stv6110x_write_reg(stv6110x, STV6110x_TNG1, stv6110x_regs[STV6110x_TNG1]);
-        stv6110x_write_reg(stv6110x, STV6110x_TNG0, stv6110x_regs[STV6110x_TNG0]);
-        stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x_regs[STV6110x_STAT1]);
+        stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x->regs[STV6110x_CTRL1]);
+        stv6110x_write_reg(stv6110x, STV6110x_TNG1, stv6110x->regs[STV6110x_TNG1]);
+        stv6110x_write_reg(stv6110x, STV6110x_TNG0, stv6110x->regs[STV6110x_TNG0]);
+        stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x->regs[STV6110x_STAT1]);
 
         for (i = 0; i < TRIALS; i++) {
-                stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x_regs[STV6110x_STAT1]);
-                if (!STV6110x_GETFIELD(STAT1_CALVCO_STRT, stv6110x_regs[STV6110x_STAT1]))
+                stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]);
+                if (!STV6110x_GETFIELD(STAT1_CALVCO_STRT, stv6110x->regs[STV6110x_STAT1]))
                                 break;
                 msleep(1);
         }
@@ -154,14 +169,14 @@ static int stv6110x_get_frequency(struct dvb_frontend *fe, u32 *frequency)
 {
         struct stv6110x_state *stv6110x = fe->tuner_priv;
 
-        stv6110x_read_reg(stv6110x, STV6110x_TNG1, &stv6110x_regs[STV6110x_TNG1]);
-        stv6110x_read_reg(stv6110x, STV6110x_TNG0, &stv6110x_regs[STV6110x_TNG0]);
+        stv6110x_read_reg(stv6110x, STV6110x_TNG1, &stv6110x->regs[STV6110x_TNG1]);
+        stv6110x_read_reg(stv6110x, STV6110x_TNG0, &stv6110x->regs[STV6110x_TNG0]);
 
-        *frequency = (MAKEWORD16(STV6110x_GETFIELD(TNG1_N_DIV_11_8, stv6110x_regs[STV6110x_TNG1]),
-                                 STV6110x_GETFIELD(TNG0_N_DIV_7_0, stv6110x_regs[STV6110x_TNG0]))) * REFCLOCK_kHz;
+        *frequency = (MAKEWORD16(STV6110x_GETFIELD(TNG1_N_DIV_11_8, stv6110x->regs[STV6110x_TNG1]),
+                                 STV6110x_GETFIELD(TNG0_N_DIV_7_0, stv6110x->regs[STV6110x_TNG0]))) * REFCLOCK_kHz;
 
-        *frequency /= (1 << (STV6110x_GETFIELD(TNG1_R_DIV, stv6110x_regs[STV6110x_TNG1]) +
-                             STV6110x_GETFIELD(TNG1_DIV4SEL, stv6110x_regs[STV6110x_TNG1])));
+        *frequency /= (1 << (STV6110x_GETFIELD(TNG1_R_DIV, stv6110x->regs[STV6110x_TNG1]) +
+                             STV6110x_GETFIELD(TNG1_DIV4SEL, stv6110x->regs[STV6110x_TNG1])));
 
         *frequency >>= 2;
 
@@ -177,27 +192,27 @@ static int stv6110x_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
         halfbw = bandwidth >> 1;
 
         if (halfbw > 36000000)
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_CF, 31); /* LPF */
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, 31); /* LPF */
         else if (halfbw < 5000000)
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_CF, 0); /* LPF */
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, 0); /* LPF */
         else
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_CF, ((halfbw / 1000000) - 5)); /* LPF */
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, ((halfbw / 1000000) - 5)); /* LPF */
 
 
-        STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x0); /* cal. clk activated */
-        STV6110x_SETFIELD(stv6110x_regs[STV6110x_STAT1], STAT1_CALRC_STRT, 0x1); /* LPF auto cal */
+        STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x0); /* cal. clk activated */
+        STV6110x_SETFIELD(stv6110x->regs[STV6110x_STAT1], STAT1_CALRC_STRT, 0x1); /* LPF auto cal */
 
-        stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x_regs[STV6110x_CTRL3]);
-        stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x_regs[STV6110x_STAT1]);
+        stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x->regs[STV6110x_CTRL3]);
+        stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x->regs[STV6110x_STAT1]);
 
         for (i = 0; i < TRIALS; i++) {
-                stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x_regs[STV6110x_STAT1]);
-                if (!STV6110x_GETFIELD(STAT1_CALRC_STRT, stv6110x_regs[STV6110x_STAT1]))
+                stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]);
+                if (!STV6110x_GETFIELD(STAT1_CALRC_STRT, stv6110x->regs[STV6110x_STAT1]))
                         break;
                 msleep(1);
         }
-        STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x1); /* cal. done */
-        stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x_regs[STV6110x_CTRL3]);
+        STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x1); /* cal. done */
+        stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x->regs[STV6110x_CTRL3]);
 
         return 0;
 }
@@ -206,8 +221,8 @@ static int stv6110x_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
 {
         struct stv6110x_state *stv6110x = fe->tuner_priv;
 
-        stv6110x_read_reg(stv6110x, STV6110x_CTRL3, &stv6110x_regs[STV6110x_CTRL3]);
-        *bandwidth = (STV6110x_GETFIELD(CTRL3_CF, stv6110x_regs[STV6110x_CTRL3]) + 5) * 2000000;
+        stv6110x_read_reg(stv6110x, STV6110x_CTRL3, &stv6110x->regs[STV6110x_CTRL3]);
+        *bandwidth = (STV6110x_GETFIELD(CTRL3_CF, stv6110x->regs[STV6110x_CTRL3]) + 5) * 2000000;
 
         return 0;
 }
@@ -220,20 +235,20 @@ static int stv6110x_set_refclock(struct dvb_frontend *fe, u32 refclock)
         switch (refclock) {
         default:
         case 1:
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0);
                 break;
         case 2:
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1);
                 break;
         case 4:
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2);
                 break;
         case 8:
         case 0:
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3);
                 break;
         }
-        stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x_regs[STV6110x_CTRL2]);
+        stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x->regs[STV6110x_CTRL2]);
 
         return 0;
 }
@@ -242,8 +257,8 @@ static int stv6110x_get_bbgain(struct dvb_frontend *fe, u32 *gain)
 {
         struct stv6110x_state *stv6110x = fe->tuner_priv;
 
-        stv6110x_read_reg(stv6110x, STV6110x_CTRL2, &stv6110x_regs[STV6110x_CTRL2]);
-        *gain = 2 * STV6110x_GETFIELD(CTRL2_BBGAIN, stv6110x_regs[STV6110x_CTRL2]);
+        stv6110x_read_reg(stv6110x, STV6110x_CTRL2, &stv6110x->regs[STV6110x_CTRL2]);
+        *gain = 2 * STV6110x_GETFIELD(CTRL2_BBGAIN, stv6110x->regs[STV6110x_CTRL2]);
 
         return 0;
 }
@@ -252,8 +267,8 @@ static int stv6110x_set_bbgain(struct dvb_frontend *fe, u32 gain)
 {
         struct stv6110x_state *stv6110x = fe->tuner_priv;
 
-        STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_BBGAIN, gain / 2);
-        stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x_regs[STV6110x_CTRL2]);
+        STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_BBGAIN, gain / 2);
+        stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x->regs[STV6110x_CTRL2]);
 
         return 0;
 }
@@ -265,19 +280,19 @@ static int stv6110x_set_mode(struct dvb_frontend *fe, enum tuner_mode mode)
 
         switch (mode) {
         case TUNER_SLEEP:
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_SYN, 0);
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_RX, 0);
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_LPT, 0);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_SYN, 0);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_RX, 0);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_LPT, 0);
                 break;
 
         case TUNER_WAKE:
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_SYN, 1);
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_RX, 1);
-                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_LPT, 1);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_SYN, 1);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_RX, 1);
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_LPT, 1);
                 break;
         }
 
-        ret = stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x_regs[STV6110x_CTRL1]);
+        ret = stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x->regs[STV6110x_CTRL1]);
         if (ret < 0) {
                 dprintk(FE_ERROR, 1, "I/O Error");
                 return -EIO;
@@ -295,9 +310,9 @@ static int stv6110x_get_status(struct dvb_frontend *fe, u32 *status)
 {
         struct stv6110x_state *stv6110x = fe->tuner_priv;
 
-        stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x_regs[STV6110x_STAT1]);
+        stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]);
 
-        if (STV6110x_GETFIELD(STAT1_LOCK, stv6110x_regs[STV6110x_STAT1]))
+        if (STV6110x_GETFIELD(STAT1_LOCK, stv6110x->regs[STV6110x_STAT1]))
                 *status = TUNER_PHASELOCKED;
         else
                 *status = 0;
@@ -347,6 +362,8 @@ struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
                                         struct i2c_adapter *i2c)
 {
         struct stv6110x_state *stv6110x;
+        u8 default_regs[] = {0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e};
+        int ret;
 
         stv6110x = kzalloc(sizeof (struct stv6110x_state), GFP_KERNEL);
         if (stv6110x == NULL)
@@ -355,6 +372,44 @@ struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
         stv6110x->i2c           = i2c;
         stv6110x->config        = config;
         stv6110x->devctl        = &stv6110x_ctl;
+        memcpy(stv6110x->regs, default_regs, 8);
+
+        /* setup divider */
+        switch (stv6110x->config->clk_div) {
+        default:
+        case 1:
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0);
+                break;
+        case 2:
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1);
+                break;
+        case 4:
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2);
+                break;
+        case 8:
+        case 0:
+                STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3);
+                break;
+        }
+
+        if (fe->ops.i2c_gate_ctrl) {
+                ret = fe->ops.i2c_gate_ctrl(fe, 1);
+                if (ret < 0)
+                        goto error;
+        }
+
+        ret = stv6110x_write_regs(stv6110x, 0, stv6110x->regs,
+                                  ARRAY_SIZE(stv6110x->regs));
+        if (ret < 0) {
+                dprintk(FE_ERROR, 1, "Initialization failed");
+                goto error;
+        }
+
+        if (fe->ops.i2c_gate_ctrl) {
+                ret = fe->ops.i2c_gate_ctrl(fe, 0);
+                if (ret < 0)
+                        goto error;
+        }
 
         fe->tuner_priv          = stv6110x;
         fe->ops.tuner_ops       = stv6110x_ops;
diff --git a/drivers/media/dvb/frontends/stv6110x.h b/drivers/media/dvb/frontends/stv6110x.h
index a38257080e01..2429ae6d7847 100644
--- a/drivers/media/dvb/frontends/stv6110x.h
+++ b/drivers/media/dvb/frontends/stv6110x.h
@@ -26,6 +26,7 @@
 struct stv6110x_config {
         u8      addr;
         u32     refclk;
+        u8      clk_div; /* divisor value for the output clock */
 };
 
 enum tuner_mode {
diff --git a/drivers/media/dvb/frontends/stv6110x_priv.h b/drivers/media/dvb/frontends/stv6110x_priv.h
index 7260da633d49..0ec936a660a7 100644
--- a/drivers/media/dvb/frontends/stv6110x_priv.h
+++ b/drivers/media/dvb/frontends/stv6110x_priv.h
@@ -68,6 +68,7 @@
 struct stv6110x_state {
         struct i2c_adapter              *i2c;
         const struct stv6110x_config    *config;
+        u8                              regs[8];
 
         struct stv6110x_devctl          *devctl;
 };
diff --git a/drivers/media/dvb/frontends/tda10021.c b/drivers/media/dvb/frontends/tda10021.c
index 6c1dbf9288d8..6ca533ea0f0e 100644
--- a/drivers/media/dvb/frontends/tda10021.c
+++ b/drivers/media/dvb/frontends/tda10021.c
@@ -426,6 +426,10 @@ struct dvb_frontend* tda10021_attach(const struct tda1002x_config* config,
         id = tda10021_readreg(state, 0x1a);
         if ((id & 0xf0) != 0x70) goto error;
 
+        /* Don't claim TDA10023 */
+        if (id == 0x7d)
+                goto error;
+
         printk("TDA10021: i2c-addr = 0x%02x, id = 0x%02x\n",
                state->config->demod_address, id);
 
diff --git a/drivers/media/dvb/frontends/tda665x.c b/drivers/media/dvb/frontends/tda665x.c
new file mode 100644
index 000000000000..2c1c759a4f42
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda665x.c
@@ -0,0 +1,258 @@
+/*
+        TDA665x tuner driver
+        Copyright (C) Manu Abraham (abraham.manu@gmail.com)
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include "dvb_frontend.h"
+#include "tda665x.h"
+
+struct tda665x_state {
+        struct dvb_frontend             *fe;
+        struct i2c_adapter              *i2c;
+        const struct tda665x_config     *config;
+
+        u32 frequency;
+        u32 bandwidth;
+};
+
+static int tda665x_read(struct tda665x_state *state, u8 *buf)
+{
+        const struct tda665x_config *config = state->config;
+        int err = 0;
+        struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD, .buf = buf, .len = 2 };
+
+        err = i2c_transfer(state->i2c, &msg, 1);
+        if (err != 1)
+                goto exit;
+
+        return err;
+exit:
+        printk(KERN_ERR "%s: I/O Error err=<%d>\n", __func__, err);
+        return err;
+}
+
+static int tda665x_write(struct tda665x_state *state, u8 *buf, u8 length)
+{
+        const struct tda665x_config *config = state->config;
+        int err = 0;
+        struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = length };
+
+        err = i2c_transfer(state->i2c, &msg, 1);
+        if (err != 1)
+                goto exit;
+
+        return err;
+exit:
+        printk(KERN_ERR "%s: I/O Error err=<%d>\n", __func__, err);
+        return err;
+}
+
+static int tda665x_get_state(struct dvb_frontend *fe,
+                             enum tuner_param param,
+                             struct tuner_state *tstate)
+{
+        struct tda665x_state *state = fe->tuner_priv;
+        int err = 0;
+
+        switch (param) {
+        case DVBFE_TUNER_FREQUENCY:
+                tstate->frequency = state->frequency;
+                break;
+        case DVBFE_TUNER_BANDWIDTH:
+                break;
+        default:
+                printk(KERN_ERR "%s: Unknown parameter (param=%d)\n", __func__, param);
+                err = -EINVAL;
+                break;
+        }
+
+        return err;
+}
+
+static int tda665x_get_status(struct dvb_frontend *fe, u32 *status)
+{
+        struct tda665x_state *state = fe->tuner_priv;
+        u8 result = 0;
+        int err = 0;
+
+        *status = 0;
+
+        err = tda665x_read(state, &result);
+        if (err < 0)
+                goto exit;
+
+        if ((result >> 6) & 0x01) {
+                printk(KERN_DEBUG "%s: Tuner Phase Locked\n", __func__);
+                *status = 1;
+        }
+
+        return err;
+exit:
+        printk(KERN_ERR "%s: I/O Error\n", __func__);
+        return err;
+}
+
+static int tda665x_set_state(struct dvb_frontend *fe,
+                             enum tuner_param param,
+                             struct tuner_state *tstate)
+{
+        struct tda665x_state *state = fe->tuner_priv;
+        const struct tda665x_config *config = state->config;
+        u32 frequency, status = 0;
+        u8 buf[4];
+        int err = 0;
+
+        if (param & DVBFE_TUNER_FREQUENCY) {
+
+                frequency = tstate->frequency;
+                if ((frequency < config->frequency_max) || (frequency > config->frequency_min)) {
+                        printk(KERN_ERR "%s: Frequency beyond limits, frequency=%d\n", __func__, frequency);
+                        return -EINVAL;
+                }
+
+                frequency += config->frequency_offst;
+                frequency *= config->ref_multiplier;
+                frequency += config->ref_divider >> 1;
+                frequency /= config->ref_divider;
+
+                buf[0] = (u8) ((frequency & 0x7f00) >> 8);
+                buf[1] = (u8) (frequency & 0x00ff) >> 0;
+                buf[2] = 0x80 | 0x40 | 0x02;
+                buf[3] = 0x00;
+
+                /* restore frequency */
+                frequency = tstate->frequency;
+
+                if (frequency < 153000000) {
+                        /* VHF-L */
+                        buf[3] |= 0x01; /* fc, Low Band, 47 - 153 MHz */
+                        if (frequency < 68000000)
+                                buf[3] |= 0x40; /* 83uA */
+                        if (frequency < 1040000000)
+                                buf[3] |= 0x60; /* 122uA */
+                        if (frequency < 1250000000)
+                                buf[3] |= 0x80; /* 163uA */
+                        else
+                                buf[3] |= 0xa0; /* 254uA */
+                } else if (frequency < 438000000) {
+                        /* VHF-H */
+                        buf[3] |= 0x02; /* fc, Mid Band, 153 - 438 MHz */
+                        if (frequency < 230000000)
+                                buf[3] |= 0x40;
+                        if (frequency < 300000000)
+                                buf[3] |= 0x60;
+                        else
+                                buf[3] |= 0x80;
+                } else {
+                        /* UHF */
+                        buf[3] |= 0x04; /* fc, High Band, 438 - 862 MHz */
+                        if (frequency < 470000000)
+                                buf[3] |= 0x60;
+                        if (frequency < 526000000)
+                                buf[3] |= 0x80;
+                        else
+                                buf[3] |= 0xa0;
+                }
+
+                /* Set params */
+                err = tda665x_write(state, buf, 5);
+                if (err < 0)
+                        goto exit;
+
+                /* sleep for some time */
+                printk(KERN_DEBUG "%s: Waiting to Phase LOCK\n", __func__);
+                msleep(20);
+                /* check status */
+                err = tda665x_get_status(fe, &status);
+                if (err < 0)
+                        goto exit;
+
+                if (status == 1) {
+                        printk(KERN_DEBUG "%s: Tuner Phase locked: status=%d\n", __func__, status);
+                        state->frequency = frequency; /* cache successful state */
+                } else {
+                        printk(KERN_ERR "%s: No Phase lock: status=%d\n", __func__, status);
+                }
+        } else {
+                printk(KERN_ERR "%s: Unknown parameter (param=%d)\n", __func__, param);
+                return -EINVAL;
+        }
+
+        return 0;
+exit:
+        printk(KERN_ERR "%s: I/O Error\n", __func__);
+        return err;
+}
+
+static int tda665x_release(struct dvb_frontend *fe)
+{
+        struct tda665x_state *state = fe->tuner_priv;
+
+        fe->tuner_priv = NULL;
+        kfree(state);
+        return 0;
+}
+
+static struct dvb_tuner_ops tda665x_ops = {
+
+        .set_state      = tda665x_set_state,
+        .get_state      = tda665x_get_state,
+        .get_status     = tda665x_get_status,
+        .release        = tda665x_release
+};
+
+struct dvb_frontend *tda665x_attach(struct dvb_frontend *fe,
+                                    const struct tda665x_config *config,
+                                    struct i2c_adapter *i2c)
+{
+        struct tda665x_state *state = NULL;
+        struct dvb_tuner_info *info;
+
+        state = kzalloc(sizeof(struct tda665x_state), GFP_KERNEL);
+        if (state == NULL)
+                goto exit;
+
+        state->config           = config;
+        state->i2c              = i2c;
+        state->fe               = fe;
+        fe->tuner_priv          = state;
+        fe->ops.tuner_ops       = tda665x_ops;
+        info                     = &fe->ops.tuner_ops.info;
+
+        memcpy(info->name, config->name, sizeof(config->name));
+        info->frequency_min     = config->frequency_min;
+        info->frequency_max     = config->frequency_max;
+        info->frequency_step    = config->frequency_offst;
+
+        printk(KERN_DEBUG "%s: Attaching TDA665x (%s) tuner\n", __func__, info->name);
+
+        return fe;
+
+exit:
+        kfree(state);
+        return NULL;
+}
+EXPORT_SYMBOL(tda665x_attach);
+
+MODULE_DESCRIPTION("TDA665x driver");
+MODULE_AUTHOR("Manu Abraham");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/tda665x.h b/drivers/media/dvb/frontends/tda665x.h
new file mode 100644
index 000000000000..ec7927aa75ae
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda665x.h
@@ -0,0 +1,52 @@
+/*
+        TDA665x tuner driver
+        Copyright (C) Manu Abraham (abraham.manu@gmail.com)
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __TDA665x_H
+#define __TDA665x_H
+
+struct tda665x_config {
+        char name[128];
+
+        u8      addr;
+        u32     frequency_min;
+        u32     frequency_max;
+        u32     frequency_offst;
+        u32     ref_multiplier;
+        u32     ref_divider;
+};
+
+#if defined(CONFIG_DVB_TDA665x) || (defined(CONFIG_DVB_TDA665x_MODULE) && defined(MODULE))
+
+extern struct dvb_frontend *tda665x_attach(struct dvb_frontend *fe,
+                                           const struct tda665x_config *config,
+                                           struct i2c_adapter *i2c);
+
+#else
+
+static inline struct dvb_frontend *tda665x_attach(struct dvb_frontend *fe,
+                                                  const struct tda665x_config *config,
+                                                  struct i2c_adapter *i2c)
+{
+        printk(KERN_WARNING "%s: Driver disabled by Kconfig\n", __func__);
+        return NULL;
+}
+
+#endif /* CONFIG_DVB_TDA665x */
+
+#endif /* __TDA665x_H */
diff --git a/drivers/media/dvb/frontends/tda8261.c b/drivers/media/dvb/frontends/tda8261.c
index 320c3c36d8b2..1742056a34e8 100644
--- a/drivers/media/dvb/frontends/tda8261.c
+++ b/drivers/media/dvb/frontends/tda8261.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 
 #include "dvb_frontend.h"
 #include "tda8261.h"
@@ -39,7 +40,7 @@ static int tda8261_read(struct tda8261_state *state, u8 *buf)
 {
         const struct tda8261_config *config = state->config;
         int err = 0;
-        struct i2c_msg msg = { .addr    = config->addr, .flags = I2C_M_RD,.buf = buf,  .len = 2 };
+        struct i2c_msg msg = { .addr    = config->addr, .flags = I2C_M_RD,.buf = buf,  .len = 1 };
 
         if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1)
                 printk("%s: read error, err=%d\n", __func__, err);
diff --git a/drivers/media/dvb/frontends/tda826x.c b/drivers/media/dvb/frontends/tda826x.c
index a051554b5e25..06c94800b940 100644
--- a/drivers/media/dvb/frontends/tda826x.c
+++ b/drivers/media/dvb/frontends/tda826x.c
@@ -20,6 +20,7 @@
 
   */
 
+#include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/dvb/frontend.h>
 #include <asm/types.h>
diff --git a/drivers/media/dvb/frontends/tua6100.c b/drivers/media/dvb/frontends/tua6100.c
index 1790baee014c..bcb95c2ef296 100644
--- a/drivers/media/dvb/frontends/tua6100.c
+++ b/drivers/media/dvb/frontends/tua6100.c
@@ -28,6 +28,7 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/dvb/frontend.h>
 #include <asm/types.h>
diff --git a/drivers/media/dvb/frontends/zl10036.c b/drivers/media/dvb/frontends/zl10036.c
index 4e814ff22b23..4627f491656b 100644
--- a/drivers/media/dvb/frontends/zl10036.c
+++ b/drivers/media/dvb/frontends/zl10036.c
@@ -29,6 +29,7 @@
 
 #include <linux/module.h>
 #include <linux/dvb/frontend.h>
+#include <linux/slab.h>
 #include <linux/types.h>
 
 #include "zl10036.h"
@@ -411,7 +412,7 @@ static int zl10036_init_regs(struct zl10036_state *state)
         state->bf = 0xff;
 
         if (!state->config->rf_loop_enable)
-                zl10036_init_tab[1][2] |= 0x01;
+                zl10036_init_tab[1][0] |= 0x01;
 
         deb_info("%s\n", __func__);
 
diff --git a/drivers/media/dvb/frontends/zl10039.c b/drivers/media/dvb/frontends/zl10039.c
index 11b29cb883e6..c085e58a94bf 100644
--- a/drivers/media/dvb/frontends/zl10039.c
+++ b/drivers/media/dvb/frontends/zl10039.c
@@ -287,7 +287,6 @@ struct dvb_frontend *zl10039_attach(struct dvb_frontend *fe,
                 break;
         default:
                 dprintk("Chip ID=%x does not match a known type\n", state->id);
-                break;
                 goto error;
         }