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Diffstat (limited to 'drivers/media/dvb/frontends/m88rs2000.c')
-rw-r--r--drivers/media/dvb/frontends/m88rs2000.c904
1 files changed, 904 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/m88rs2000.c b/drivers/media/dvb/frontends/m88rs2000.c
new file mode 100644
index 000000000000..045ee5a6f7ae
--- /dev/null
+++ b/drivers/media/dvb/frontends/m88rs2000.c
@@ -0,0 +1,904 @@
1/*
2 Driver for M88RS2000 demodulator and tuner
3
4 Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com)
5 Beta Driver
6
7 Include various calculation code from DS3000 driver.
8 Copyright (C) 2009 Konstantin Dimitrov.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23
24*/
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <linux/jiffies.h>
29#include <linux/string.h>
30#include <linux/slab.h>
31#include <linux/types.h>
32
33
34#include "dvb_frontend.h"
35#include "m88rs2000.h"
36
37struct m88rs2000_state {
38 struct i2c_adapter *i2c;
39 const struct m88rs2000_config *config;
40 struct dvb_frontend frontend;
41 u8 no_lock_count;
42 u32 tuner_frequency;
43 u32 symbol_rate;
44 fe_code_rate_t fec_inner;
45 u8 tuner_level;
46 int errmode;
47};
48
49static int m88rs2000_debug;
50
51module_param_named(debug, m88rs2000_debug, int, 0644);
52MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
53
54#define dprintk(level, args...) do { \
55 if (level & m88rs2000_debug) \
56 printk(KERN_DEBUG "m88rs2000-fe: " args); \
57} while (0)
58
59#define deb_info(args...) dprintk(0x01, args)
60#define info(format, arg...) \
61 printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
62
63static int m88rs2000_writereg(struct m88rs2000_state *state, u8 tuner,
64 u8 reg, u8 data)
65{
66 int ret;
67 u8 addr = (tuner == 0) ? state->config->tuner_addr :
68 state->config->demod_addr;
69 u8 buf[] = { reg, data };
70 struct i2c_msg msg = {
71 .addr = addr,
72 .flags = 0,
73 .buf = buf,
74 .len = 2
75 };
76
77 ret = i2c_transfer(state->i2c, &msg, 1);
78
79 if (ret != 1)
80 deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
81 "ret == %i)\n", __func__, reg, data, ret);
82
83 return (ret != 1) ? -EREMOTEIO : 0;
84}
85
86static int m88rs2000_demod_write(struct m88rs2000_state *state, u8 reg, u8 data)
87{
88 return m88rs2000_writereg(state, 1, reg, data);
89}
90
91static int m88rs2000_tuner_write(struct m88rs2000_state *state, u8 reg, u8 data)
92{
93 m88rs2000_demod_write(state, 0x81, 0x84);
94 udelay(10);
95 return m88rs2000_writereg(state, 0, reg, data);
96
97}
98
99static int m88rs2000_write(struct dvb_frontend *fe, const u8 buf[], int len)
100{
101 struct m88rs2000_state *state = fe->demodulator_priv;
102
103 if (len != 2)
104 return -EINVAL;
105
106 return m88rs2000_writereg(state, 1, buf[0], buf[1]);
107}
108
109static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 tuner, u8 reg)
110{
111 int ret;
112 u8 b0[] = { reg };
113 u8 b1[] = { 0 };
114 u8 addr = (tuner == 0) ? state->config->tuner_addr :
115 state->config->demod_addr;
116 struct i2c_msg msg[] = {
117 {
118 .addr = addr,
119 .flags = 0,
120 .buf = b0,
121 .len = 1
122 }, {
123 .addr = addr,
124 .flags = I2C_M_RD,
125 .buf = b1,
126 .len = 1
127 }
128 };
129
130 ret = i2c_transfer(state->i2c, msg, 2);
131
132 if (ret != 2)
133 deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
134 __func__, reg, ret);
135
136 return b1[0];
137}
138
139static u8 m88rs2000_demod_read(struct m88rs2000_state *state, u8 reg)
140{
141 return m88rs2000_readreg(state, 1, reg);
142}
143
144static u8 m88rs2000_tuner_read(struct m88rs2000_state *state, u8 reg)
145{
146 m88rs2000_demod_write(state, 0x81, 0x85);
147 udelay(10);
148 return m88rs2000_readreg(state, 0, reg);
149}
150
151static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
152{
153 struct m88rs2000_state *state = fe->demodulator_priv;
154 int ret;
155 u32 temp;
156 u8 b[3];
157
158 if ((srate < 1000000) || (srate > 45000000))
159 return -EINVAL;
160
161 temp = srate / 1000;
162 temp *= 11831;
163 temp /= 68;
164 temp -= 3;
165
166 b[0] = (u8) (temp >> 16) & 0xff;
167 b[1] = (u8) (temp >> 8) & 0xff;
168 b[2] = (u8) temp & 0xff;
169 ret = m88rs2000_demod_write(state, 0x93, b[2]);
170 ret |= m88rs2000_demod_write(state, 0x94, b[1]);
171 ret |= m88rs2000_demod_write(state, 0x95, b[0]);
172
173 deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
174 return ret;
175}
176
177static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
178 struct dvb_diseqc_master_cmd *m)
179{
180 struct m88rs2000_state *state = fe->demodulator_priv;
181
182 int i;
183 u8 reg;
184 deb_info("%s\n", __func__);
185 m88rs2000_demod_write(state, 0x9a, 0x30);
186 reg = m88rs2000_demod_read(state, 0xb2);
187 reg &= 0x3f;
188 m88rs2000_demod_write(state, 0xb2, reg);
189 for (i = 0; i < m->msg_len; i++)
190 m88rs2000_demod_write(state, 0xb3 + i, m->msg[i]);
191
192 reg = m88rs2000_demod_read(state, 0xb1);
193 reg &= 0x87;
194 reg |= ((m->msg_len - 1) << 3) | 0x07;
195 reg &= 0x7f;
196 m88rs2000_demod_write(state, 0xb1, reg);
197
198 for (i = 0; i < 15; i++) {
199 if ((m88rs2000_demod_read(state, 0xb1) & 0x40) == 0x0)
200 break;
201 msleep(20);
202 }
203
204 reg = m88rs2000_demod_read(state, 0xb1);
205 if ((reg & 0x40) > 0x0) {
206 reg &= 0x7f;
207 reg |= 0x40;
208 m88rs2000_demod_write(state, 0xb1, reg);
209 }
210
211 reg = m88rs2000_demod_read(state, 0xb2);
212 reg &= 0x3f;
213 reg |= 0x80;
214 m88rs2000_demod_write(state, 0xb2, reg);
215 m88rs2000_demod_write(state, 0x9a, 0xb0);
216
217
218 return 0;
219}
220
221static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
222 fe_sec_mini_cmd_t burst)
223{
224 struct m88rs2000_state *state = fe->demodulator_priv;
225 u8 reg0, reg1;
226 deb_info("%s\n", __func__);
227 m88rs2000_demod_write(state, 0x9a, 0x30);
228 msleep(50);
229 reg0 = m88rs2000_demod_read(state, 0xb1);
230 reg1 = m88rs2000_demod_read(state, 0xb2);
231 /* TODO complete this section */
232 m88rs2000_demod_write(state, 0xb2, reg1);
233 m88rs2000_demod_write(state, 0xb1, reg0);
234 m88rs2000_demod_write(state, 0x9a, 0xb0);
235
236 return 0;
237}
238
239static int m88rs2000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
240{
241 struct m88rs2000_state *state = fe->demodulator_priv;
242 u8 reg0, reg1;
243 m88rs2000_demod_write(state, 0x9a, 0x30);
244 reg0 = m88rs2000_demod_read(state, 0xb1);
245 reg1 = m88rs2000_demod_read(state, 0xb2);
246
247 reg1 &= 0x3f;
248
249 switch (tone) {
250 case SEC_TONE_ON:
251 reg0 |= 0x4;
252 reg0 &= 0xbc;
253 break;
254 case SEC_TONE_OFF:
255 reg1 |= 0x80;
256 break;
257 default:
258 break;
259 }
260 m88rs2000_demod_write(state, 0xb2, reg1);
261 m88rs2000_demod_write(state, 0xb1, reg0);
262 m88rs2000_demod_write(state, 0x9a, 0xb0);
263 return 0;
264}
265
266struct inittab {
267 u8 cmd;
268 u8 reg;
269 u8 val;
270};
271
272struct inittab m88rs2000_setup[] = {
273 {DEMOD_WRITE, 0x9a, 0x30},
274 {DEMOD_WRITE, 0x00, 0x01},
275 {WRITE_DELAY, 0x19, 0x00},
276 {DEMOD_WRITE, 0x00, 0x00},
277 {DEMOD_WRITE, 0x9a, 0xb0},
278 {DEMOD_WRITE, 0x81, 0xc1},
279 {TUNER_WRITE, 0x42, 0x73},
280 {TUNER_WRITE, 0x05, 0x07},
281 {TUNER_WRITE, 0x20, 0x27},
282 {TUNER_WRITE, 0x07, 0x02},
283 {TUNER_WRITE, 0x11, 0xff},
284 {TUNER_WRITE, 0x60, 0xf9},
285 {TUNER_WRITE, 0x08, 0x01},
286 {TUNER_WRITE, 0x00, 0x41},
287 {DEMOD_WRITE, 0x81, 0x81},
288 {DEMOD_WRITE, 0x86, 0xc6},
289 {DEMOD_WRITE, 0x9a, 0x30},
290 {DEMOD_WRITE, 0xf0, 0x22},
291 {DEMOD_WRITE, 0xf1, 0xbf},
292 {DEMOD_WRITE, 0xb0, 0x45},
293 {DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/
294 {DEMOD_WRITE, 0x9a, 0xb0},
295 {0xff, 0xaa, 0xff}
296};
297
298struct inittab m88rs2000_shutdown[] = {
299 {DEMOD_WRITE, 0x9a, 0x30},
300 {DEMOD_WRITE, 0xb0, 0x00},
301 {DEMOD_WRITE, 0xf1, 0x89},
302 {DEMOD_WRITE, 0x00, 0x01},
303 {DEMOD_WRITE, 0x9a, 0xb0},
304 {TUNER_WRITE, 0x00, 0x40},
305 {DEMOD_WRITE, 0x81, 0x81},
306 {0xff, 0xaa, 0xff}
307};
308
309struct inittab tuner_reset[] = {
310 {TUNER_WRITE, 0x42, 0x73},
311 {TUNER_WRITE, 0x05, 0x07},
312 {TUNER_WRITE, 0x20, 0x27},
313 {TUNER_WRITE, 0x07, 0x02},
314 {TUNER_WRITE, 0x11, 0xff},
315 {TUNER_WRITE, 0x60, 0xf9},
316 {TUNER_WRITE, 0x08, 0x01},
317 {TUNER_WRITE, 0x00, 0x41},
318 {0xff, 0xaa, 0xff}
319};
320
321struct inittab fe_reset[] = {
322 {DEMOD_WRITE, 0x00, 0x01},
323 {DEMOD_WRITE, 0xf1, 0xbf},
324 {DEMOD_WRITE, 0x00, 0x01},
325 {DEMOD_WRITE, 0x20, 0x81},
326 {DEMOD_WRITE, 0x21, 0x80},
327 {DEMOD_WRITE, 0x10, 0x33},
328 {DEMOD_WRITE, 0x11, 0x44},
329 {DEMOD_WRITE, 0x12, 0x07},
330 {DEMOD_WRITE, 0x18, 0x20},
331 {DEMOD_WRITE, 0x28, 0x04},
332 {DEMOD_WRITE, 0x29, 0x8e},
333 {DEMOD_WRITE, 0x3b, 0xff},
334 {DEMOD_WRITE, 0x32, 0x10},
335 {DEMOD_WRITE, 0x33, 0x02},
336 {DEMOD_WRITE, 0x34, 0x30},
337 {DEMOD_WRITE, 0x35, 0xff},
338 {DEMOD_WRITE, 0x38, 0x50},
339 {DEMOD_WRITE, 0x39, 0x68},
340 {DEMOD_WRITE, 0x3c, 0x7f},
341 {DEMOD_WRITE, 0x3d, 0x0f},
342 {DEMOD_WRITE, 0x45, 0x20},
343 {DEMOD_WRITE, 0x46, 0x24},
344 {DEMOD_WRITE, 0x47, 0x7c},
345 {DEMOD_WRITE, 0x48, 0x16},
346 {DEMOD_WRITE, 0x49, 0x04},
347 {DEMOD_WRITE, 0x4a, 0x01},
348 {DEMOD_WRITE, 0x4b, 0x78},
349 {DEMOD_WRITE, 0X4d, 0xd2},
350 {DEMOD_WRITE, 0x4e, 0x6d},
351 {DEMOD_WRITE, 0x50, 0x30},
352 {DEMOD_WRITE, 0x51, 0x30},
353 {DEMOD_WRITE, 0x54, 0x7b},
354 {DEMOD_WRITE, 0x56, 0x09},
355 {DEMOD_WRITE, 0x58, 0x59},
356 {DEMOD_WRITE, 0x59, 0x37},
357 {DEMOD_WRITE, 0x63, 0xfa},
358 {0xff, 0xaa, 0xff}
359};
360
361struct inittab fe_trigger[] = {
362 {DEMOD_WRITE, 0x97, 0x04},
363 {DEMOD_WRITE, 0x99, 0x77},
364 {DEMOD_WRITE, 0x9b, 0x64},
365 {DEMOD_WRITE, 0x9e, 0x00},
366 {DEMOD_WRITE, 0x9f, 0xf8},
367 {DEMOD_WRITE, 0xa0, 0x20},
368 {DEMOD_WRITE, 0xa1, 0xe0},
369 {DEMOD_WRITE, 0xa3, 0x38},
370 {DEMOD_WRITE, 0x98, 0xff},
371 {DEMOD_WRITE, 0xc0, 0x0f},
372 {DEMOD_WRITE, 0x89, 0x01},
373 {DEMOD_WRITE, 0x00, 0x00},
374 {WRITE_DELAY, 0x0a, 0x00},
375 {DEMOD_WRITE, 0x00, 0x01},
376 {DEMOD_WRITE, 0x00, 0x00},
377 {DEMOD_WRITE, 0x9a, 0xb0},
378 {0xff, 0xaa, 0xff}
379};
380
381static int m88rs2000_tab_set(struct m88rs2000_state *state,
382 struct inittab *tab)
383{
384 int ret = 0;
385 u8 i;
386 if (tab == NULL)
387 return -EINVAL;
388
389 for (i = 0; i < 255; i++) {
390 switch (tab[i].cmd) {
391 case 0x01:
392 ret = m88rs2000_demod_write(state, tab[i].reg,
393 tab[i].val);
394 break;
395 case 0x02:
396 ret = m88rs2000_tuner_write(state, tab[i].reg,
397 tab[i].val);
398 break;
399 case 0x10:
400 if (tab[i].reg > 0)
401 mdelay(tab[i].reg);
402 break;
403 case 0xff:
404 if (tab[i].reg == 0xaa && tab[i].val == 0xff)
405 return 0;
406 case 0x00:
407 break;
408 default:
409 return -EINVAL;
410 }
411 if (ret < 0)
412 return -ENODEV;
413 }
414 return 0;
415}
416
417static int m88rs2000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t volt)
418{
419 deb_info("%s: %s\n", __func__,
420 volt == SEC_VOLTAGE_13 ? "SEC_VOLTAGE_13" :
421 volt == SEC_VOLTAGE_18 ? "SEC_VOLTAGE_18" : "??");
422
423 return 0;
424}
425
426static int m88rs2000_startup(struct m88rs2000_state *state)
427{
428 int ret = 0;
429 u8 reg;
430
431 reg = m88rs2000_tuner_read(state, 0x00);
432 if ((reg & 0x40) == 0)
433 ret = -ENODEV;
434
435 return ret;
436}
437
438static int m88rs2000_init(struct dvb_frontend *fe)
439{
440 struct m88rs2000_state *state = fe->demodulator_priv;
441 int ret;
442
443 deb_info("m88rs2000: init chip\n");
444 /* Setup frontend from shutdown/cold */
445 ret = m88rs2000_tab_set(state, m88rs2000_setup);
446
447 return ret;
448}
449
450static int m88rs2000_sleep(struct dvb_frontend *fe)
451{
452 struct m88rs2000_state *state = fe->demodulator_priv;
453 int ret;
454 /* Shutdown the frondend */
455 ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
456 return ret;
457}
458
459static int m88rs2000_read_status(struct dvb_frontend *fe, fe_status_t *status)
460{
461 struct m88rs2000_state *state = fe->demodulator_priv;
462 u8 reg = m88rs2000_demod_read(state, 0x8c);
463
464 *status = 0;
465
466 if ((reg & 0x7) == 0x7) {
467 *status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI
468 | FE_HAS_LOCK;
469 if (state->config->set_ts_params)
470 state->config->set_ts_params(fe, CALL_IS_READ);
471 }
472 return 0;
473}
474
475/* Extact code for these unknown but lmedm04 driver uses interupt callbacks */
476
477static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber)
478{
479 deb_info("m88rs2000_read_ber %d\n", *ber);
480 *ber = 0;
481 return 0;
482}
483
484static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
485 u16 *strength)
486{
487 *strength = 0;
488 return 0;
489}
490
491static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr)
492{
493 deb_info("m88rs2000_read_snr %d\n", *snr);
494 *snr = 0;
495 return 0;
496}
497
498static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
499{
500 deb_info("m88rs2000_read_ber %d\n", *ucblocks);
501 *ucblocks = 0;
502 return 0;
503}
504
505static int m88rs2000_tuner_gate_ctrl(struct m88rs2000_state *state, u8 offset)
506{
507 int ret;
508 ret = m88rs2000_tuner_write(state, 0x51, 0x1f - offset);
509 ret |= m88rs2000_tuner_write(state, 0x51, 0x1f);
510 ret |= m88rs2000_tuner_write(state, 0x50, offset);
511 ret |= m88rs2000_tuner_write(state, 0x50, 0x00);
512 msleep(20);
513 return ret;
514}
515
516static int m88rs2000_set_tuner_rf(struct dvb_frontend *fe)
517{
518 struct m88rs2000_state *state = fe->demodulator_priv;
519 int reg;
520 reg = m88rs2000_tuner_read(state, 0x3d);
521 reg &= 0x7f;
522 if (reg < 0x16)
523 reg = 0xa1;
524 else if (reg == 0x16)
525 reg = 0x99;
526 else
527 reg = 0xf9;
528
529 m88rs2000_tuner_write(state, 0x60, reg);
530 reg = m88rs2000_tuner_gate_ctrl(state, 0x08);
531
532 if (fe->ops.i2c_gate_ctrl)
533 fe->ops.i2c_gate_ctrl(fe, 0);
534 return reg;
535}
536
537static int m88rs2000_set_tuner(struct dvb_frontend *fe, u16 *offset)
538{
539 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
540 struct m88rs2000_state *state = fe->demodulator_priv;
541 int ret;
542 u32 frequency = c->frequency;
543 s32 offset_khz;
544 s32 tmp;
545 u32 symbol_rate = (c->symbol_rate / 1000);
546 u32 f3db, gdiv28;
547 u16 value, ndiv, lpf_coeff;
548 u8 lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
549 u8 lo = 0x01, div4 = 0x0;
550
551 /* Reset Tuner */
552 ret = m88rs2000_tab_set(state, tuner_reset);
553
554 /* Calculate frequency divider */
555 if (frequency < 1060000) {
556 lo |= 0x10;
557 div4 = 0x1;
558 ndiv = (frequency * 14 * 4) / FE_CRYSTAL_KHZ;
559 } else
560 ndiv = (frequency * 14 * 2) / FE_CRYSTAL_KHZ;
561 ndiv = ndiv + ndiv % 2;
562 ndiv = ndiv - 1024;
563
564 ret = m88rs2000_tuner_write(state, 0x10, 0x80 | lo);
565
566 /* Set frequency divider */
567 ret |= m88rs2000_tuner_write(state, 0x01, (ndiv >> 8) & 0xf);
568 ret |= m88rs2000_tuner_write(state, 0x02, ndiv & 0xff);
569
570 ret |= m88rs2000_tuner_write(state, 0x03, 0x06);
571 ret |= m88rs2000_tuner_gate_ctrl(state, 0x10);
572 if (ret < 0)
573 return -ENODEV;
574
575 /* Tuner Frequency Range */
576 ret = m88rs2000_tuner_write(state, 0x10, lo);
577
578 ret |= m88rs2000_tuner_gate_ctrl(state, 0x08);
579
580 /* Tuner RF */
581 ret |= m88rs2000_set_tuner_rf(fe);
582
583 gdiv28 = (FE_CRYSTAL_KHZ / 1000 * 1694 + 500) / 1000;
584 ret |= m88rs2000_tuner_write(state, 0x04, gdiv28 & 0xff);
585 ret |= m88rs2000_tuner_gate_ctrl(state, 0x04);
586 if (ret < 0)
587 return -ENODEV;
588
589 value = m88rs2000_tuner_read(state, 0x26);
590
591 f3db = (symbol_rate * 135) / 200 + 2000;
592 f3db += FREQ_OFFSET_LOW_SYM_RATE;
593 if (f3db < 7000)
594 f3db = 7000;
595 if (f3db > 40000)
596 f3db = 40000;
597
598 gdiv28 = gdiv28 * 207 / (value * 2 + 151);
599 mlpf_max = gdiv28 * 135 / 100;
600 mlpf_min = gdiv28 * 78 / 100;
601 if (mlpf_max > 63)
602 mlpf_max = 63;
603
604 lpf_coeff = 2766;
605
606 nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
607 (FE_CRYSTAL_KHZ / 1000) + 1) / 2;
608 if (nlpf > 23)
609 nlpf = 23;
610 if (nlpf < 1)
611 nlpf = 1;
612
613 lpf_mxdiv = (nlpf * (FE_CRYSTAL_KHZ / 1000)
614 * lpf_coeff * 2 / f3db + 1) / 2;
615
616 if (lpf_mxdiv < mlpf_min) {
617 nlpf++;
618 lpf_mxdiv = (nlpf * (FE_CRYSTAL_KHZ / 1000)
619 * lpf_coeff * 2 / f3db + 1) / 2;
620 }
621
622 if (lpf_mxdiv > mlpf_max)
623 lpf_mxdiv = mlpf_max;
624
625 ret = m88rs2000_tuner_write(state, 0x04, lpf_mxdiv);
626 ret |= m88rs2000_tuner_write(state, 0x06, nlpf);
627
628 ret |= m88rs2000_tuner_gate_ctrl(state, 0x04);
629
630 ret |= m88rs2000_tuner_gate_ctrl(state, 0x01);
631
632 msleep(80);
633 /* calculate offset assuming 96000kHz*/
634 offset_khz = (ndiv - ndiv % 2 + 1024) * FE_CRYSTAL_KHZ
635 / 14 / (div4 + 1) / 2;
636
637 offset_khz -= frequency;
638
639 tmp = offset_khz;
640 tmp *= 65536;
641
642 tmp = (2 * tmp + 96000) / (2 * 96000);
643 if (tmp < 0)
644 tmp += 65536;
645
646 *offset = tmp & 0xffff;
647
648 if (fe->ops.i2c_gate_ctrl)
649 fe->ops.i2c_gate_ctrl(fe, 0);
650
651 return (ret < 0) ? -EINVAL : 0;
652}
653
654static int m88rs2000_set_fec(struct m88rs2000_state *state,
655 fe_code_rate_t fec)
656{
657 int ret;
658 u16 fec_set;
659 switch (fec) {
660 /* This is not confirmed kept for reference */
661/* case FEC_1_2:
662 fec_set = 0x88;
663 break;
664 case FEC_2_3:
665 fec_set = 0x68;
666 break;
667 case FEC_3_4:
668 fec_set = 0x48;
669 break;
670 case FEC_5_6:
671 fec_set = 0x28;
672 break;
673 case FEC_7_8:
674 fec_set = 0x18;
675 break; */
676 case FEC_AUTO:
677 default:
678 fec_set = 0x08;
679 }
680 ret = m88rs2000_demod_write(state, 0x76, fec_set);
681
682 return 0;
683}
684
685
686static fe_code_rate_t m88rs2000_get_fec(struct m88rs2000_state *state)
687{
688 u8 reg;
689 m88rs2000_demod_write(state, 0x9a, 0x30);
690 reg = m88rs2000_demod_read(state, 0x76);
691 m88rs2000_demod_write(state, 0x9a, 0xb0);
692
693 switch (reg) {
694 case 0x88:
695 return FEC_1_2;
696 case 0x68:
697 return FEC_2_3;
698 case 0x48:
699 return FEC_3_4;
700 case 0x28:
701 return FEC_5_6;
702 case 0x18:
703 return FEC_7_8;
704 case 0x08:
705 default:
706 break;
707 }
708
709 return FEC_AUTO;
710}
711
712static int m88rs2000_set_frontend(struct dvb_frontend *fe)
713{
714 struct m88rs2000_state *state = fe->demodulator_priv;
715 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
716 fe_status_t status;
717 int i, ret;
718 u16 offset = 0;
719 u8 reg;
720
721 state->no_lock_count = 0;
722
723 if (c->delivery_system != SYS_DVBS) {
724 deb_info("%s: unsupported delivery "
725 "system selected (%d)\n",
726 __func__, c->delivery_system);
727 return -EOPNOTSUPP;
728 }
729
730 /* Set Tuner */
731 ret = m88rs2000_set_tuner(fe, &offset);
732 if (ret < 0)
733 return -ENODEV;
734
735 ret = m88rs2000_demod_write(state, 0x9a, 0x30);
736 /* Unknown usually 0xc6 sometimes 0xc1 */
737 reg = m88rs2000_demod_read(state, 0x86);
738 ret |= m88rs2000_demod_write(state, 0x86, reg);
739 /* Offset lower nibble always 0 */
740 ret |= m88rs2000_demod_write(state, 0x9c, (offset >> 8));
741 ret |= m88rs2000_demod_write(state, 0x9d, offset & 0xf0);
742
743
744 /* Reset Demod */
745 ret = m88rs2000_tab_set(state, fe_reset);
746 if (ret < 0)
747 return -ENODEV;
748
749 /* Unknown */
750 reg = m88rs2000_demod_read(state, 0x70);
751 ret = m88rs2000_demod_write(state, 0x70, reg);
752
753 /* Set FEC */
754 ret |= m88rs2000_set_fec(state, c->fec_inner);
755 ret |= m88rs2000_demod_write(state, 0x85, 0x1);
756 ret |= m88rs2000_demod_write(state, 0x8a, 0xbf);
757 ret |= m88rs2000_demod_write(state, 0x8d, 0x1e);
758 ret |= m88rs2000_demod_write(state, 0x90, 0xf1);
759 ret |= m88rs2000_demod_write(state, 0x91, 0x08);
760
761 if (ret < 0)
762 return -ENODEV;
763
764 /* Set Symbol Rate */
765 ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
766 if (ret < 0)
767 return -ENODEV;
768
769 /* Set up Demod */
770 ret = m88rs2000_tab_set(state, fe_trigger);
771 if (ret < 0)
772 return -ENODEV;
773
774 for (i = 0; i < 25; i++) {
775 u8 reg = m88rs2000_demod_read(state, 0x8c);
776 if ((reg & 0x7) == 0x7) {
777 status = FE_HAS_LOCK;
778 break;
779 }
780 state->no_lock_count++;
781 if (state->no_lock_count > 15) {
782 reg = m88rs2000_demod_read(state, 0x70);
783 reg ^= 0x4;
784 m88rs2000_demod_write(state, 0x70, reg);
785 state->no_lock_count = 0;
786 }
787 if (state->no_lock_count == 20)
788 m88rs2000_set_tuner_rf(fe);
789 msleep(20);
790 }
791
792 if (status & FE_HAS_LOCK) {
793 state->fec_inner = m88rs2000_get_fec(state);
794 /* Uknown suspect SNR level */
795 reg = m88rs2000_demod_read(state, 0x65);
796 }
797
798 state->tuner_frequency = c->frequency;
799 state->symbol_rate = c->symbol_rate;
800 return 0;
801}
802
803static int m88rs2000_get_frontend(struct dvb_frontend *fe)
804{
805 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
806 struct m88rs2000_state *state = fe->demodulator_priv;
807 c->fec_inner = state->fec_inner;
808 c->frequency = state->tuner_frequency;
809 c->symbol_rate = state->symbol_rate;
810 return 0;
811}
812
813static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
814{
815 struct m88rs2000_state *state = fe->demodulator_priv;
816
817 if (enable)
818 m88rs2000_demod_write(state, 0x81, 0x84);
819 else
820 m88rs2000_demod_write(state, 0x81, 0x81);
821 udelay(10);
822 return 0;
823}
824
825static void m88rs2000_release(struct dvb_frontend *fe)
826{
827 struct m88rs2000_state *state = fe->demodulator_priv;
828 kfree(state);
829}
830
831static struct dvb_frontend_ops m88rs2000_ops = {
832 .delsys = { SYS_DVBS },
833 .info = {
834 .name = "M88RS2000 DVB-S",
835 .frequency_min = 950000,
836 .frequency_max = 2150000,
837 .frequency_stepsize = 1000, /* kHz for QPSK frontends */
838 .frequency_tolerance = 5000,
839 .symbol_rate_min = 1000000,
840 .symbol_rate_max = 45000000,
841 .symbol_rate_tolerance = 500, /* ppm */
842 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
843 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
844 FE_CAN_QPSK |
845 FE_CAN_FEC_AUTO
846 },
847
848 .release = m88rs2000_release,
849 .init = m88rs2000_init,
850 .sleep = m88rs2000_sleep,
851 .write = m88rs2000_write,
852 .i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
853 .read_status = m88rs2000_read_status,
854 .read_ber = m88rs2000_read_ber,
855 .read_signal_strength = m88rs2000_read_signal_strength,
856 .read_snr = m88rs2000_read_snr,
857 .read_ucblocks = m88rs2000_read_ucblocks,
858 .diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
859 .diseqc_send_burst = m88rs2000_send_diseqc_burst,
860 .set_tone = m88rs2000_set_tone,
861 .set_voltage = m88rs2000_set_voltage,
862
863 .set_frontend = m88rs2000_set_frontend,
864 .get_frontend = m88rs2000_get_frontend,
865};
866
867struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config,
868 struct i2c_adapter *i2c)
869{
870 struct m88rs2000_state *state = NULL;
871
872 /* allocate memory for the internal state */
873 state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
874 if (state == NULL)
875 goto error;
876
877 /* setup the state */
878 state->config = config;
879 state->i2c = i2c;
880 state->tuner_frequency = 0;
881 state->symbol_rate = 0;
882 state->fec_inner = 0;
883
884 if (m88rs2000_startup(state) < 0)
885 goto error;
886
887 /* create dvb_frontend */
888 memcpy(&state->frontend.ops, &m88rs2000_ops,
889 sizeof(struct dvb_frontend_ops));
890 state->frontend.demodulator_priv = state;
891 return &state->frontend;
892
893error:
894 kfree(state);
895
896 return NULL;
897}
898EXPORT_SYMBOL(m88rs2000_attach);
899
900MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
901MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
902MODULE_LICENSE("GPL");
903MODULE_VERSION("1.13");
904
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 12:27:26 -0500