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-rw-r--r--drivers/input/touchscreen/atmel_tsadcc.c41
1 files changed, 35 insertions, 6 deletions
diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c
index 5a2af5973cb4..3d9b5166ebe9 100644
--- a/drivers/input/touchscreen/atmel_tsadcc.c
+++ b/drivers/input/touchscreen/atmel_tsadcc.c
@@ -22,6 +22,8 @@
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <mach/board.h>
26#include <mach/cpu.h>
25 27
26/* Register definitions based on AT91SAM9RL64 preliminary draft datasheet */ 28/* Register definitions based on AT91SAM9RL64 preliminary draft datasheet */
27 29
@@ -36,7 +38,9 @@
36#define ATMEL_TSADCC_LOWRES (1 << 4) /* Resolution selection */ 38#define ATMEL_TSADCC_LOWRES (1 << 4) /* Resolution selection */
37#define ATMEL_TSADCC_SLEEP (1 << 5) /* Sleep mode */ 39#define ATMEL_TSADCC_SLEEP (1 << 5) /* Sleep mode */
38#define ATMEL_TSADCC_PENDET (1 << 6) /* Pen Detect selection */ 40#define ATMEL_TSADCC_PENDET (1 << 6) /* Pen Detect selection */
41#define ATMEL_TSADCC_PRES (1 << 7) /* Pressure Measurement Selection */
39#define ATMEL_TSADCC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */ 42#define ATMEL_TSADCC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */
43#define ATMEL_TSADCC_EPRESCAL (0xff << 8) /* Prescalar Rate Selection (Extended) */
40#define ATMEL_TSADCC_STARTUP (0x7f << 16) /* Start Up time */ 44#define ATMEL_TSADCC_STARTUP (0x7f << 16) /* Start Up time */
41#define ATMEL_TSADCC_SHTIM (0xf << 24) /* Sample & Hold time */ 45#define ATMEL_TSADCC_SHTIM (0xf << 24) /* Sample & Hold time */
42#define ATMEL_TSADCC_PENDBC (0xf << 28) /* Pen Detect debouncing time */ 46#define ATMEL_TSADCC_PENDBC (0xf << 28) /* Pen Detect debouncing time */
@@ -84,7 +88,13 @@
84#define ATMEL_TSADCC_CDR4 0x40 /* Channel Data 4 */ 88#define ATMEL_TSADCC_CDR4 0x40 /* Channel Data 4 */
85#define ATMEL_TSADCC_CDR5 0x44 /* Channel Data 5 */ 89#define ATMEL_TSADCC_CDR5 0x44 /* Channel Data 5 */
86 90
87#define ADC_CLOCK 1000000 91#define ATMEL_TSADCC_XPOS 0x50
92#define ATMEL_TSADCC_Z1DAT 0x54
93#define ATMEL_TSADCC_Z2DAT 0x58
94
95#define PRESCALER_VAL(x) ((x) >> 8)
96
97#define ADC_DEFAULT_CLOCK 100000
88 98
89struct atmel_tsadcc { 99struct atmel_tsadcc {
90 struct input_dev *input; 100 struct input_dev *input;
@@ -172,6 +182,7 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
172 struct atmel_tsadcc *ts_dev; 182 struct atmel_tsadcc *ts_dev;
173 struct input_dev *input_dev; 183 struct input_dev *input_dev;
174 struct resource *res; 184 struct resource *res;
185 struct at91_tsadcc_data *pdata = pdev->dev.platform_data;
175 int err = 0; 186 int err = 0;
176 unsigned int prsc; 187 unsigned int prsc;
177 unsigned int reg; 188 unsigned int reg;
@@ -254,19 +265,37 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
254 prsc = clk_get_rate(ts_dev->clk); 265 prsc = clk_get_rate(ts_dev->clk);
255 dev_info(&pdev->dev, "Master clock is set at: %d Hz\n", prsc); 266 dev_info(&pdev->dev, "Master clock is set at: %d Hz\n", prsc);
256 267
257 prsc = prsc / ADC_CLOCK / 2 - 1; 268 if (!pdata)
269 goto err_fail;
270
271 if (!pdata->adc_clock)
272 pdata->adc_clock = ADC_DEFAULT_CLOCK;
273
274 prsc = (prsc / (2 * pdata->adc_clock)) - 1;
275
276 /* saturate if this value is too high */
277 if (cpu_is_at91sam9rl()) {
278 if (prsc > PRESCALER_VAL(ATMEL_TSADCC_PRESCAL))
279 prsc = PRESCALER_VAL(ATMEL_TSADCC_PRESCAL);
280 } else {
281 if (prsc > PRESCALER_VAL(ATMEL_TSADCC_EPRESCAL))
282 prsc = PRESCALER_VAL(ATMEL_TSADCC_EPRESCAL);
283 }
284
285 dev_info(&pdev->dev, "Prescaler is set at: %d\n", prsc);
258 286
259 reg = ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE | 287 reg = ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE |
260 ((0x00 << 5) & ATMEL_TSADCC_SLEEP) | /* Normal Mode */ 288 ((0x00 << 5) & ATMEL_TSADCC_SLEEP) | /* Normal Mode */
261 ((0x01 << 6) & ATMEL_TSADCC_PENDET) | /* Enable Pen Detect */ 289 ((0x01 << 6) & ATMEL_TSADCC_PENDET) | /* Enable Pen Detect */
262 ((prsc << 8) & ATMEL_TSADCC_PRESCAL) | /* PRESCAL */ 290 (prsc << 8) |
263 ((0x13 << 16) & ATMEL_TSADCC_STARTUP) | /* STARTUP */ 291 ((0x26 << 16) & ATMEL_TSADCC_STARTUP) |
264 ((0x0F << 28) & ATMEL_TSADCC_PENDBC); /* PENDBC */ 292 ((pdata->pendet_debounce << 28) & ATMEL_TSADCC_PENDBC);
265 293
266 atmel_tsadcc_write(ATMEL_TSADCC_CR, ATMEL_TSADCC_SWRST); 294 atmel_tsadcc_write(ATMEL_TSADCC_CR, ATMEL_TSADCC_SWRST);
267 atmel_tsadcc_write(ATMEL_TSADCC_MR, reg); 295 atmel_tsadcc_write(ATMEL_TSADCC_MR, reg);
268 atmel_tsadcc_write(ATMEL_TSADCC_TRGR, ATMEL_TSADCC_TRGMOD_NONE); 296 atmel_tsadcc_write(ATMEL_TSADCC_TRGR, ATMEL_TSADCC_TRGMOD_NONE);
269 atmel_tsadcc_write(ATMEL_TSADCC_TSR, (0x3 << 24) & ATMEL_TSADCC_TSSHTIM); 297 atmel_tsadcc_write(ATMEL_TSADCC_TSR,
298 (pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TSSHTIM);
270 299
271 atmel_tsadcc_read(ATMEL_TSADCC_SR); 300 atmel_tsadcc_read(ATMEL_TSADCC_SR);
272 atmel_tsadcc_write(ATMEL_TSADCC_IER, ATMEL_TSADCC_PENCNT); 301 atmel_tsadcc_write(ATMEL_TSADCC_IER, ATMEL_TSADCC_PENCNT);