diff options
Diffstat (limited to 'drivers/input/serio/i8042.c')
-rw-r--r-- | drivers/input/serio/i8042.c | 101 |
1 files changed, 50 insertions, 51 deletions
diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c index f58513160480..d37a48e099d0 100644 --- a/drivers/input/serio/i8042.c +++ b/drivers/input/serio/i8042.c | |||
@@ -10,6 +10,8 @@ | |||
10 | * the Free Software Foundation. | 10 | * the Free Software Foundation. |
11 | */ | 11 | */ |
12 | 12 | ||
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
14 | |||
13 | #include <linux/types.h> | 15 | #include <linux/types.h> |
14 | #include <linux/delay.h> | 16 | #include <linux/delay.h> |
15 | #include <linux/module.h> | 17 | #include <linux/module.h> |
@@ -61,6 +63,10 @@ static bool i8042_noloop; | |||
61 | module_param_named(noloop, i8042_noloop, bool, 0); | 63 | module_param_named(noloop, i8042_noloop, bool, 0); |
62 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); | 64 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); |
63 | 65 | ||
66 | static bool i8042_notimeout; | ||
67 | module_param_named(notimeout, i8042_notimeout, bool, 0); | ||
68 | MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); | ||
69 | |||
64 | #ifdef CONFIG_X86 | 70 | #ifdef CONFIG_X86 |
65 | static bool i8042_dritek; | 71 | static bool i8042_dritek; |
66 | module_param_named(dritek, i8042_dritek, bool, 0); | 72 | module_param_named(dritek, i8042_dritek, bool, 0); |
@@ -225,8 +231,8 @@ static int i8042_flush(void) | |||
225 | udelay(50); | 231 | udelay(50); |
226 | data = i8042_read_data(); | 232 | data = i8042_read_data(); |
227 | i++; | 233 | i++; |
228 | dbg("%02x <- i8042 (flush, %s)", data, | 234 | dbg("%02x <- i8042 (flush, %s)\n", |
229 | str & I8042_STR_AUXDATA ? "aux" : "kbd"); | 235 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); |
230 | } | 236 | } |
231 | 237 | ||
232 | spin_unlock_irqrestore(&i8042_lock, flags); | 238 | spin_unlock_irqrestore(&i8042_lock, flags); |
@@ -253,32 +259,32 @@ static int __i8042_command(unsigned char *param, int command) | |||
253 | if (error) | 259 | if (error) |
254 | return error; | 260 | return error; |
255 | 261 | ||
256 | dbg("%02x -> i8042 (command)", command & 0xff); | 262 | dbg("%02x -> i8042 (command)\n", command & 0xff); |
257 | i8042_write_command(command & 0xff); | 263 | i8042_write_command(command & 0xff); |
258 | 264 | ||
259 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | 265 | for (i = 0; i < ((command >> 12) & 0xf); i++) { |
260 | error = i8042_wait_write(); | 266 | error = i8042_wait_write(); |
261 | if (error) | 267 | if (error) |
262 | return error; | 268 | return error; |
263 | dbg("%02x -> i8042 (parameter)", param[i]); | 269 | dbg("%02x -> i8042 (parameter)\n", param[i]); |
264 | i8042_write_data(param[i]); | 270 | i8042_write_data(param[i]); |
265 | } | 271 | } |
266 | 272 | ||
267 | for (i = 0; i < ((command >> 8) & 0xf); i++) { | 273 | for (i = 0; i < ((command >> 8) & 0xf); i++) { |
268 | error = i8042_wait_read(); | 274 | error = i8042_wait_read(); |
269 | if (error) { | 275 | if (error) { |
270 | dbg(" -- i8042 (timeout)"); | 276 | dbg(" -- i8042 (timeout)\n"); |
271 | return error; | 277 | return error; |
272 | } | 278 | } |
273 | 279 | ||
274 | if (command == I8042_CMD_AUX_LOOP && | 280 | if (command == I8042_CMD_AUX_LOOP && |
275 | !(i8042_read_status() & I8042_STR_AUXDATA)) { | 281 | !(i8042_read_status() & I8042_STR_AUXDATA)) { |
276 | dbg(" -- i8042 (auxerr)"); | 282 | dbg(" -- i8042 (auxerr)\n"); |
277 | return -1; | 283 | return -1; |
278 | } | 284 | } |
279 | 285 | ||
280 | param[i] = i8042_read_data(); | 286 | param[i] = i8042_read_data(); |
281 | dbg("%02x <- i8042 (return)", param[i]); | 287 | dbg("%02x <- i8042 (return)\n", param[i]); |
282 | } | 288 | } |
283 | 289 | ||
284 | return 0; | 290 | return 0; |
@@ -309,7 +315,7 @@ static int i8042_kbd_write(struct serio *port, unsigned char c) | |||
309 | spin_lock_irqsave(&i8042_lock, flags); | 315 | spin_lock_irqsave(&i8042_lock, flags); |
310 | 316 | ||
311 | if (!(retval = i8042_wait_write())) { | 317 | if (!(retval = i8042_wait_write())) { |
312 | dbg("%02x -> i8042 (kbd-data)", c); | 318 | dbg("%02x -> i8042 (kbd-data)\n", c); |
313 | i8042_write_data(c); | 319 | i8042_write_data(c); |
314 | } | 320 | } |
315 | 321 | ||
@@ -355,17 +361,14 @@ static void i8042_port_close(struct serio *serio) | |||
355 | 361 | ||
356 | i8042_ctr &= ~irq_bit; | 362 | i8042_ctr &= ~irq_bit; |
357 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | 363 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
358 | printk(KERN_WARNING | 364 | pr_warn("Can't write CTR while closing %s port\n", port_name); |
359 | "i8042.c: Can't write CTR while closing %s port.\n", | ||
360 | port_name); | ||
361 | 365 | ||
362 | udelay(50); | 366 | udelay(50); |
363 | 367 | ||
364 | i8042_ctr &= ~disable_bit; | 368 | i8042_ctr &= ~disable_bit; |
365 | i8042_ctr |= irq_bit; | 369 | i8042_ctr |= irq_bit; |
366 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | 370 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
367 | printk(KERN_ERR "i8042.c: Can't reactivate %s port.\n", | 371 | pr_err("Can't reactivate %s port\n", port_name); |
368 | port_name); | ||
369 | 372 | ||
370 | /* | 373 | /* |
371 | * See if there is any data appeared while we were messing with | 374 | * See if there is any data appeared while we were messing with |
@@ -456,7 +459,8 @@ static irqreturn_t i8042_interrupt(int irq, void *dev_id) | |||
456 | str = i8042_read_status(); | 459 | str = i8042_read_status(); |
457 | if (unlikely(~str & I8042_STR_OBF)) { | 460 | if (unlikely(~str & I8042_STR_OBF)) { |
458 | spin_unlock_irqrestore(&i8042_lock, flags); | 461 | spin_unlock_irqrestore(&i8042_lock, flags); |
459 | if (irq) dbg("Interrupt %d, without any data", irq); | 462 | if (irq) |
463 | dbg("Interrupt %d, without any data\n", irq); | ||
460 | ret = 0; | 464 | ret = 0; |
461 | goto out; | 465 | goto out; |
462 | } | 466 | } |
@@ -469,7 +473,8 @@ static irqreturn_t i8042_interrupt(int irq, void *dev_id) | |||
469 | 473 | ||
470 | dfl = 0; | 474 | dfl = 0; |
471 | if (str & I8042_STR_MUXERR) { | 475 | if (str & I8042_STR_MUXERR) { |
472 | dbg("MUX error, status is %02x, data is %02x", str, data); | 476 | dbg("MUX error, status is %02x, data is %02x\n", |
477 | str, data); | ||
473 | /* | 478 | /* |
474 | * When MUXERR condition is signalled the data register can only contain | 479 | * When MUXERR condition is signalled the data register can only contain |
475 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | 480 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately |
@@ -503,7 +508,7 @@ static irqreturn_t i8042_interrupt(int irq, void *dev_id) | |||
503 | } else { | 508 | } else { |
504 | 509 | ||
505 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | | 510 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | |
506 | ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); | 511 | ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0); |
507 | 512 | ||
508 | port_no = (str & I8042_STR_AUXDATA) ? | 513 | port_no = (str & I8042_STR_AUXDATA) ? |
509 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; | 514 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; |
@@ -512,7 +517,7 @@ static irqreturn_t i8042_interrupt(int irq, void *dev_id) | |||
512 | port = &i8042_ports[port_no]; | 517 | port = &i8042_ports[port_no]; |
513 | serio = port->exists ? port->serio : NULL; | 518 | serio = port->exists ? port->serio : NULL; |
514 | 519 | ||
515 | dbg("%02x <- i8042 (interrupt, %d, %d%s%s)", | 520 | dbg("%02x <- i8042 (interrupt, %d, %d%s%s)\n", |
516 | data, port_no, irq, | 521 | data, port_no, irq, |
517 | dfl & SERIO_PARITY ? ", bad parity" : "", | 522 | dfl & SERIO_PARITY ? ", bad parity" : "", |
518 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | 523 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); |
@@ -540,7 +545,7 @@ static int i8042_enable_kbd_port(void) | |||
540 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 545 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
541 | i8042_ctr &= ~I8042_CTR_KBDINT; | 546 | i8042_ctr &= ~I8042_CTR_KBDINT; |
542 | i8042_ctr |= I8042_CTR_KBDDIS; | 547 | i8042_ctr |= I8042_CTR_KBDDIS; |
543 | printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n"); | 548 | pr_err("Failed to enable KBD port\n"); |
544 | return -EIO; | 549 | return -EIO; |
545 | } | 550 | } |
546 | 551 | ||
@@ -559,7 +564,7 @@ static int i8042_enable_aux_port(void) | |||
559 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 564 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
560 | i8042_ctr &= ~I8042_CTR_AUXINT; | 565 | i8042_ctr &= ~I8042_CTR_AUXINT; |
561 | i8042_ctr |= I8042_CTR_AUXDIS; | 566 | i8042_ctr |= I8042_CTR_AUXDIS; |
562 | printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n"); | 567 | pr_err("Failed to enable AUX port\n"); |
563 | return -EIO; | 568 | return -EIO; |
564 | } | 569 | } |
565 | 570 | ||
@@ -641,7 +646,7 @@ static int __init i8042_check_mux(void) | |||
641 | if (i8042_set_mux_mode(true, &mux_version)) | 646 | if (i8042_set_mux_mode(true, &mux_version)) |
642 | return -1; | 647 | return -1; |
643 | 648 | ||
644 | printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", | 649 | pr_info("Detected active multiplexing controller, rev %d.%d\n", |
645 | (mux_version >> 4) & 0xf, mux_version & 0xf); | 650 | (mux_version >> 4) & 0xf, mux_version & 0xf); |
646 | 651 | ||
647 | /* | 652 | /* |
@@ -651,7 +656,7 @@ static int __init i8042_check_mux(void) | |||
651 | i8042_ctr &= ~I8042_CTR_AUXINT; | 656 | i8042_ctr &= ~I8042_CTR_AUXINT; |
652 | 657 | ||
653 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 658 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
654 | printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); | 659 | pr_err("Failed to disable AUX port, can't use MUX\n"); |
655 | return -EIO; | 660 | return -EIO; |
656 | } | 661 | } |
657 | 662 | ||
@@ -676,8 +681,8 @@ static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) | |||
676 | str = i8042_read_status(); | 681 | str = i8042_read_status(); |
677 | if (str & I8042_STR_OBF) { | 682 | if (str & I8042_STR_OBF) { |
678 | data = i8042_read_data(); | 683 | data = i8042_read_data(); |
679 | dbg("%02x <- i8042 (aux_test_irq, %s)", | 684 | dbg("%02x <- i8042 (aux_test_irq, %s)\n", |
680 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); | 685 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); |
681 | if (i8042_irq_being_tested && | 686 | if (i8042_irq_being_tested && |
682 | data == 0xa5 && (str & I8042_STR_AUXDATA)) | 687 | data == 0xa5 && (str & I8042_STR_AUXDATA)) |
683 | complete(&i8042_aux_irq_delivered); | 688 | complete(&i8042_aux_irq_delivered); |
@@ -770,8 +775,8 @@ static int __init i8042_check_aux(void) | |||
770 | */ | 775 | */ |
771 | 776 | ||
772 | if (i8042_toggle_aux(false)) { | 777 | if (i8042_toggle_aux(false)) { |
773 | printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); | 778 | pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); |
774 | printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); | 779 | pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); |
775 | } | 780 | } |
776 | 781 | ||
777 | if (i8042_toggle_aux(true)) | 782 | if (i8042_toggle_aux(true)) |
@@ -819,7 +824,7 @@ static int __init i8042_check_aux(void) | |||
819 | * AUX IRQ was never delivered so we need to flush the controller to | 824 | * AUX IRQ was never delivered so we need to flush the controller to |
820 | * get rid of the byte we put there; otherwise keyboard may not work. | 825 | * get rid of the byte we put there; otherwise keyboard may not work. |
821 | */ | 826 | */ |
822 | dbg(" -- i8042 (aux irq test timeout)"); | 827 | dbg(" -- i8042 (aux irq test timeout)\n"); |
823 | i8042_flush(); | 828 | i8042_flush(); |
824 | retval = -1; | 829 | retval = -1; |
825 | } | 830 | } |
@@ -845,7 +850,7 @@ static int __init i8042_check_aux(void) | |||
845 | static int i8042_controller_check(void) | 850 | static int i8042_controller_check(void) |
846 | { | 851 | { |
847 | if (i8042_flush() == I8042_BUFFER_SIZE) { | 852 | if (i8042_flush() == I8042_BUFFER_SIZE) { |
848 | printk(KERN_ERR "i8042.c: No controller found.\n"); | 853 | pr_err("No controller found\n"); |
849 | return -ENODEV; | 854 | return -ENODEV; |
850 | } | 855 | } |
851 | 856 | ||
@@ -864,15 +869,15 @@ static int i8042_controller_selftest(void) | |||
864 | do { | 869 | do { |
865 | 870 | ||
866 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | 871 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { |
867 | printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); | 872 | pr_err("i8042 controller selftest timeout\n"); |
868 | return -ENODEV; | 873 | return -ENODEV; |
869 | } | 874 | } |
870 | 875 | ||
871 | if (param == I8042_RET_CTL_TEST) | 876 | if (param == I8042_RET_CTL_TEST) |
872 | return 0; | 877 | return 0; |
873 | 878 | ||
874 | printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", | 879 | dbg("i8042 controller selftest: %#x != %#x\n", |
875 | param, I8042_RET_CTL_TEST); | 880 | param, I8042_RET_CTL_TEST); |
876 | msleep(50); | 881 | msleep(50); |
877 | } while (i++ < 5); | 882 | } while (i++ < 5); |
878 | 883 | ||
@@ -883,10 +888,10 @@ static int i8042_controller_selftest(void) | |||
883 | * and user will still get a working keyboard. This is especially | 888 | * and user will still get a working keyboard. This is especially |
884 | * important on netbooks. On other arches we trust hardware more. | 889 | * important on netbooks. On other arches we trust hardware more. |
885 | */ | 890 | */ |
886 | printk(KERN_INFO | 891 | pr_info("giving up on controller selftest, continuing anyway...\n"); |
887 | "i8042: giving up on controller selftest, continuing anyway...\n"); | ||
888 | return 0; | 892 | return 0; |
889 | #else | 893 | #else |
894 | pr_err("i8042 controller selftest failed\n"); | ||
890 | return -EIO; | 895 | return -EIO; |
891 | #endif | 896 | #endif |
892 | } | 897 | } |
@@ -909,8 +914,7 @@ static int i8042_controller_init(void) | |||
909 | 914 | ||
910 | do { | 915 | do { |
911 | if (n >= 10) { | 916 | if (n >= 10) { |
912 | printk(KERN_ERR | 917 | pr_err("Unable to get stable CTR read\n"); |
913 | "i8042.c: Unable to get stable CTR read.\n"); | ||
914 | return -EIO; | 918 | return -EIO; |
915 | } | 919 | } |
916 | 920 | ||
@@ -918,8 +922,7 @@ static int i8042_controller_init(void) | |||
918 | udelay(50); | 922 | udelay(50); |
919 | 923 | ||
920 | if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { | 924 | if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { |
921 | printk(KERN_ERR | 925 | pr_err("Can't read CTR while initializing i8042\n"); |
922 | "i8042.c: Can't read CTR while initializing i8042.\n"); | ||
923 | return -EIO; | 926 | return -EIO; |
924 | } | 927 | } |
925 | 928 | ||
@@ -943,7 +946,7 @@ static int i8042_controller_init(void) | |||
943 | if (i8042_unlock) | 946 | if (i8042_unlock) |
944 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | 947 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; |
945 | else | 948 | else |
946 | printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); | 949 | pr_warn("Warning: Keylock active\n"); |
947 | } | 950 | } |
948 | spin_unlock_irqrestore(&i8042_lock, flags); | 951 | spin_unlock_irqrestore(&i8042_lock, flags); |
949 | 952 | ||
@@ -970,7 +973,7 @@ static int i8042_controller_init(void) | |||
970 | */ | 973 | */ |
971 | 974 | ||
972 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 975 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
973 | printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); | 976 | pr_err("Can't write CTR while initializing i8042\n"); |
974 | return -EIO; | 977 | return -EIO; |
975 | } | 978 | } |
976 | 979 | ||
@@ -1000,7 +1003,7 @@ static void i8042_controller_reset(void) | |||
1000 | i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); | 1003 | i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); |
1001 | 1004 | ||
1002 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | 1005 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
1003 | printk(KERN_WARNING "i8042.c: Can't write CTR while resetting.\n"); | 1006 | pr_warn("Can't write CTR while resetting\n"); |
1004 | 1007 | ||
1005 | /* | 1008 | /* |
1006 | * Disable MUX mode if present. | 1009 | * Disable MUX mode if present. |
@@ -1021,7 +1024,7 @@ static void i8042_controller_reset(void) | |||
1021 | */ | 1024 | */ |
1022 | 1025 | ||
1023 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) | 1026 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) |
1024 | printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); | 1027 | pr_warn("Can't restore CTR\n"); |
1025 | } | 1028 | } |
1026 | 1029 | ||
1027 | 1030 | ||
@@ -1045,14 +1048,14 @@ static long i8042_panic_blink(int state) | |||
1045 | led = (state) ? 0x01 | 0x04 : 0; | 1048 | led = (state) ? 0x01 | 0x04 : 0; |
1046 | while (i8042_read_status() & I8042_STR_IBF) | 1049 | while (i8042_read_status() & I8042_STR_IBF) |
1047 | DELAY; | 1050 | DELAY; |
1048 | dbg("%02x -> i8042 (panic blink)", 0xed); | 1051 | dbg("%02x -> i8042 (panic blink)\n", 0xed); |
1049 | i8042_suppress_kbd_ack = 2; | 1052 | i8042_suppress_kbd_ack = 2; |
1050 | i8042_write_data(0xed); /* set leds */ | 1053 | i8042_write_data(0xed); /* set leds */ |
1051 | DELAY; | 1054 | DELAY; |
1052 | while (i8042_read_status() & I8042_STR_IBF) | 1055 | while (i8042_read_status() & I8042_STR_IBF) |
1053 | DELAY; | 1056 | DELAY; |
1054 | DELAY; | 1057 | DELAY; |
1055 | dbg("%02x -> i8042 (panic blink)", led); | 1058 | dbg("%02x -> i8042 (panic blink)\n", led); |
1056 | i8042_write_data(led); | 1059 | i8042_write_data(led); |
1057 | DELAY; | 1060 | DELAY; |
1058 | return delay; | 1061 | return delay; |
@@ -1063,14 +1066,12 @@ static long i8042_panic_blink(int state) | |||
1063 | #ifdef CONFIG_X86 | 1066 | #ifdef CONFIG_X86 |
1064 | static void i8042_dritek_enable(void) | 1067 | static void i8042_dritek_enable(void) |
1065 | { | 1068 | { |
1066 | char param = 0x90; | 1069 | unsigned char param = 0x90; |
1067 | int error; | 1070 | int error; |
1068 | 1071 | ||
1069 | error = i8042_command(¶m, 0x1059); | 1072 | error = i8042_command(¶m, 0x1059); |
1070 | if (error) | 1073 | if (error) |
1071 | printk(KERN_WARNING | 1074 | pr_warn("Failed to enable DRITEK extension: %d\n", error); |
1072 | "Failed to enable DRITEK extension: %d\n", | ||
1073 | error); | ||
1074 | } | 1075 | } |
1075 | #endif | 1076 | #endif |
1076 | 1077 | ||
@@ -1105,10 +1106,10 @@ static int i8042_controller_resume(bool force_reset) | |||
1105 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; | 1106 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; |
1106 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); | 1107 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); |
1107 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 1108 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
1108 | printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n"); | 1109 | pr_warn("Can't write CTR to resume, retrying...\n"); |
1109 | msleep(50); | 1110 | msleep(50); |
1110 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 1111 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
1111 | printk(KERN_ERR "i8042: CTR write retry failed\n"); | 1112 | pr_err("CTR write retry failed\n"); |
1112 | return -EIO; | 1113 | return -EIO; |
1113 | } | 1114 | } |
1114 | } | 1115 | } |
@@ -1121,9 +1122,7 @@ static int i8042_controller_resume(bool force_reset) | |||
1121 | 1122 | ||
1122 | if (i8042_mux_present) { | 1123 | if (i8042_mux_present) { |
1123 | if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) | 1124 | if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) |
1124 | printk(KERN_WARNING | 1125 | pr_warn("failed to resume active multiplexor, mouse won't work\n"); |
1125 | "i8042: failed to resume active multiplexor, " | ||
1126 | "mouse won't work.\n"); | ||
1127 | } else if (i8042_ports[I8042_AUX_PORT_NO].serio) | 1126 | } else if (i8042_ports[I8042_AUX_PORT_NO].serio) |
1128 | i8042_enable_aux_port(); | 1127 | i8042_enable_aux_port(); |
1129 | 1128 | ||