aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/infiniband/hw/qib/qib_iba7322.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/infiniband/hw/qib/qib_iba7322.c')
-rw-r--r--drivers/infiniband/hw/qib/qib_iba7322.c43
1 files changed, 36 insertions, 7 deletions
diff --git a/drivers/infiniband/hw/qib/qib_iba7322.c b/drivers/infiniband/hw/qib/qib_iba7322.c
index 503992d9c5ce..5eedf83e2c3b 100644
--- a/drivers/infiniband/hw/qib/qib_iba7322.c
+++ b/drivers/infiniband/hw/qib/qib_iba7322.c
@@ -543,7 +543,7 @@ struct vendor_txdds_ent {
543static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *); 543static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
544 544
545#define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */ 545#define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
546#define TXDDS_EXTRA_SZ 11 /* number of extra tx settings entries */ 546#define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */
547#define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */ 547#define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
548 548
549#define H1_FORCE_VAL 8 549#define H1_FORCE_VAL 8
@@ -1100,9 +1100,9 @@ static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1100 HWE_AUTO_P(SDmaMemReadErr, 1), 1100 HWE_AUTO_P(SDmaMemReadErr, 1),
1101 HWE_AUTO_P(SDmaMemReadErr, 0), 1101 HWE_AUTO_P(SDmaMemReadErr, 0),
1102 HWE_AUTO_P(IBCBusFromSPCParityErr, 1), 1102 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1103 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1103 HWE_AUTO_P(IBCBusFromSPCParityErr, 0), 1104 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1104 HWE_AUTO_P(statusValidNoEop, 1), 1105 HWE_AUTO(statusValidNoEop),
1105 HWE_AUTO_P(statusValidNoEop, 0),
1106 HWE_AUTO(LATriggered), 1106 HWE_AUTO(LATriggered),
1107 { .mask = 0 } 1107 { .mask = 0 }
1108}; 1108};
@@ -4763,6 +4763,8 @@ static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4763 SYM_MASK(IBPCSConfig_0, tx_rx_reset); 4763 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4764 4764
4765 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig); 4765 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
4766 qib_write_kreg(dd, kr_hwerrmask,
4767 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
4766 qib_write_kreg_port(ppd, krp_ibcctrl_a, 4768 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4767 ppd->cpspec->ibcctrl_a & 4769 ppd->cpspec->ibcctrl_a &
4768 ~SYM_MASK(IBCCtrlA_0, IBLinkEn)); 4770 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
@@ -4772,6 +4774,9 @@ static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4772 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits); 4774 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
4773 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 4775 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4774 qib_write_kreg(dd, kr_scratch, 0ULL); 4776 qib_write_kreg(dd, kr_scratch, 0ULL);
4777 qib_write_kreg(dd, kr_hwerrclear,
4778 SYM_MASK(HwErrClear, statusValidNoEopClear));
4779 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
4775} 4780}
4776 4781
4777/* 4782/*
@@ -5624,6 +5629,8 @@ static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
5624 if (ppd->port != port || !ppd->link_speed_supported) 5629 if (ppd->port != port || !ppd->link_speed_supported)
5625 continue; 5630 continue;
5626 ppd->cpspec->no_eep = val; 5631 ppd->cpspec->no_eep = val;
5632 if (seth1)
5633 ppd->cpspec->h1_val = h1;
5627 /* now change the IBC and serdes, overriding generic */ 5634 /* now change the IBC and serdes, overriding generic */
5628 init_txdds_table(ppd, 1); 5635 init_txdds_table(ppd, 1);
5629 any++; 5636 any++;
@@ -6064,9 +6071,9 @@ static int qib_init_7322_variables(struct qib_devdata *dd)
6064 * the "cable info" setup here. Can be overridden 6071 * the "cable info" setup here. Can be overridden
6065 * in adapter-specific routines. 6072 * in adapter-specific routines.
6066 */ 6073 */
6067 if (!(ppd->dd->flags & QIB_HAS_QSFP)) { 6074 if (!(dd->flags & QIB_HAS_QSFP)) {
6068 if (!IS_QMH(ppd->dd) && !IS_QME(ppd->dd)) 6075 if (!IS_QMH(dd) && !IS_QME(dd))
6069 qib_devinfo(ppd->dd->pcidev, "IB%u:%u: " 6076 qib_devinfo(dd->pcidev, "IB%u:%u: "
6070 "Unknown mezzanine card type\n", 6077 "Unknown mezzanine card type\n",
6071 dd->unit, ppd->port); 6078 dd->unit, ppd->port);
6072 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME; 6079 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
@@ -6119,9 +6126,25 @@ static int qib_init_7322_variables(struct qib_devdata *dd)
6119 qib_set_ctxtcnt(dd); 6126 qib_set_ctxtcnt(dd);
6120 6127
6121 if (qib_wc_pat) { 6128 if (qib_wc_pat) {
6122 ret = init_chip_wc_pat(dd, NUM_VL15_BUFS * dd->align4k); 6129 resource_size_t vl15off;
6130 /*
6131 * We do not set WC on the VL15 buffers to avoid
6132 * a rare problem with unaligned writes from
6133 * interrupt-flushed store buffers, so we need
6134 * to map those separately here. We can't solve
6135 * this for the rarely used mtrr case.
6136 */
6137 ret = init_chip_wc_pat(dd, 0);
6123 if (ret) 6138 if (ret)
6124 goto bail; 6139 goto bail;
6140
6141 /* vl15 buffers start just after the 4k buffers */
6142 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6143 dd->piobcnt4k * dd->align4k;
6144 dd->piovl15base = ioremap_nocache(vl15off,
6145 NUM_VL15_BUFS * dd->align4k);
6146 if (!dd->piovl15base)
6147 goto bail;
6125 } 6148 }
6126 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */ 6149 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6127 6150
@@ -6932,6 +6955,8 @@ static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
6932 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 6955 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
6933 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 6956 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
6934 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 6957 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
6958 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
6959 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
6935}; 6960};
6936 6961
6937static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = { 6962static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
@@ -6947,6 +6972,8 @@ static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
6947 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 6972 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
6948 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 6973 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
6949 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 6974 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
6975 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
6976 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
6950}; 6977};
6951 6978
6952static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = { 6979static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
@@ -6962,6 +6989,8 @@ static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
6962 { 0, 1, 12, 6 }, /* QME7342 backplane setting */ 6989 { 0, 1, 12, 6 }, /* QME7342 backplane setting */
6963 { 0, 1, 12, 7 }, /* QME7342 backplane setting */ 6990 { 0, 1, 12, 7 }, /* QME7342 backplane setting */
6964 { 0, 1, 12, 8 }, /* QME7342 backplane setting */ 6991 { 0, 1, 12, 8 }, /* QME7342 backplane setting */
6992 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
6993 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
6965}; 6994};
6966 6995
6967static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds, 6996static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,