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path: root/drivers/infiniband/hw/nes/nes_hw.h
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Diffstat (limited to 'drivers/infiniband/hw/nes/nes_hw.h')
-rw-r--r--drivers/infiniband/hw/nes/nes_hw.h91
1 files changed, 91 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/nes/nes_hw.h b/drivers/infiniband/hw/nes/nes_hw.h
index c3654c6383fe..4a0bfcd5a628 100644
--- a/drivers/infiniband/hw/nes/nes_hw.h
+++ b/drivers/infiniband/hw/nes/nes_hw.h
@@ -241,6 +241,7 @@ enum nes_cqp_stag_wqeword_idx {
241}; 241};
242 242
243#define NES_CQP_OP_IWARP_STATE_SHIFT 28 243#define NES_CQP_OP_IWARP_STATE_SHIFT 28
244#define NES_CQP_OP_TERMLEN_SHIFT 28
244 245
245enum nes_cqp_qp_bits { 246enum nes_cqp_qp_bits {
246 NES_CQP_QP_ARP_VALID = (1<<8), 247 NES_CQP_QP_ARP_VALID = (1<<8),
@@ -265,6 +266,8 @@ enum nes_cqp_qp_bits {
265 NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT), 266 NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT),
266 NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT), 267 NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT),
267 NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT), 268 NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT),
269 NES_CQP_QP_TERM_DONT_SEND_FIN = (1<<24),
270 NES_CQP_QP_TERM_DONT_SEND_TERM_MSG = (1<<25),
268 NES_CQP_QP_RESET = (1<<31), 271 NES_CQP_QP_RESET = (1<<31),
269}; 272};
270 273
@@ -633,11 +636,14 @@ enum nes_aeqe_bits {
633 NES_AEQE_INBOUND_RDMA = (1<<19), 636 NES_AEQE_INBOUND_RDMA = (1<<19),
634 NES_AEQE_IWARP_STATE_MASK = (7<<20), 637 NES_AEQE_IWARP_STATE_MASK = (7<<20),
635 NES_AEQE_TCP_STATE_MASK = (0xf<<24), 638 NES_AEQE_TCP_STATE_MASK = (0xf<<24),
639 NES_AEQE_Q2_DATA_WRITTEN = (0x3<<28),
636 NES_AEQE_VALID = (1<<31), 640 NES_AEQE_VALID = (1<<31),
637}; 641};
638 642
639#define NES_AEQE_IWARP_STATE_SHIFT 20 643#define NES_AEQE_IWARP_STATE_SHIFT 20
640#define NES_AEQE_TCP_STATE_SHIFT 24 644#define NES_AEQE_TCP_STATE_SHIFT 24
645#define NES_AEQE_Q2_DATA_ETHERNET (1<<28)
646#define NES_AEQE_Q2_DATA_MPA (1<<29)
641 647
642enum nes_aeqe_iwarp_state { 648enum nes_aeqe_iwarp_state {
643 NES_AEQE_IWARP_STATE_NON_EXISTANT = 0, 649 NES_AEQE_IWARP_STATE_NON_EXISTANT = 0,
@@ -1119,6 +1125,7 @@ struct nes_adapter {
1119 u8 netdev_max; /* from host nic address count in EEPROM */ 1125 u8 netdev_max; /* from host nic address count in EEPROM */
1120 u8 port_count; 1126 u8 port_count;
1121 u8 virtwq; 1127 u8 virtwq;
1128 u8 send_term_ok;
1122 u8 et_use_adaptive_rx_coalesce; 1129 u8 et_use_adaptive_rx_coalesce;
1123 u8 adapter_fcn_count; 1130 u8 adapter_fcn_count;
1124 u8 pft_mcast_map[NES_PFT_SIZE]; 1131 u8 pft_mcast_map[NES_PFT_SIZE];
@@ -1217,6 +1224,90 @@ struct nes_ib_device {
1217 u32 num_pd; 1224 u32 num_pd;
1218}; 1225};
1219 1226
1227enum nes_hdrct_flags {
1228 DDP_LEN_FLAG = 0x80,
1229 DDP_HDR_FLAG = 0x40,
1230 RDMA_HDR_FLAG = 0x20
1231};
1232
1233enum nes_term_layers {
1234 LAYER_RDMA = 0,
1235 LAYER_DDP = 1,
1236 LAYER_MPA = 2
1237};
1238
1239enum nes_term_error_types {
1240 RDMAP_CATASTROPHIC = 0,
1241 RDMAP_REMOTE_PROT = 1,
1242 RDMAP_REMOTE_OP = 2,
1243 DDP_CATASTROPHIC = 0,
1244 DDP_TAGGED_BUFFER = 1,
1245 DDP_UNTAGGED_BUFFER = 2,
1246 DDP_LLP = 3
1247};
1248
1249enum nes_term_rdma_errors {
1250 RDMAP_INV_STAG = 0x00,
1251 RDMAP_INV_BOUNDS = 0x01,
1252 RDMAP_ACCESS = 0x02,
1253 RDMAP_UNASSOC_STAG = 0x03,
1254 RDMAP_TO_WRAP = 0x04,
1255 RDMAP_INV_RDMAP_VER = 0x05,
1256 RDMAP_UNEXPECTED_OP = 0x06,
1257 RDMAP_CATASTROPHIC_LOCAL = 0x07,
1258 RDMAP_CATASTROPHIC_GLOBAL = 0x08,
1259 RDMAP_CANT_INV_STAG = 0x09,
1260 RDMAP_UNSPECIFIED = 0xff
1261};
1262
1263enum nes_term_ddp_errors {
1264 DDP_CATASTROPHIC_LOCAL = 0x00,
1265 DDP_TAGGED_INV_STAG = 0x00,
1266 DDP_TAGGED_BOUNDS = 0x01,
1267 DDP_TAGGED_UNASSOC_STAG = 0x02,
1268 DDP_TAGGED_TO_WRAP = 0x03,
1269 DDP_TAGGED_INV_DDP_VER = 0x04,
1270 DDP_UNTAGGED_INV_QN = 0x01,
1271 DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02,
1272 DDP_UNTAGGED_INV_MSN_RANGE = 0x03,
1273 DDP_UNTAGGED_INV_MO = 0x04,
1274 DDP_UNTAGGED_INV_TOO_LONG = 0x05,
1275 DDP_UNTAGGED_INV_DDP_VER = 0x06
1276};
1277
1278enum nes_term_mpa_errors {
1279 MPA_CLOSED = 0x01,
1280 MPA_CRC = 0x02,
1281 MPA_MARKER = 0x03,
1282 MPA_REQ_RSP = 0x04,
1283};
1284
1285struct nes_terminate_hdr {
1286 u8 layer_etype;
1287 u8 error_code;
1288 u8 hdrct;
1289 u8 rsvd;
1290};
1291
1292/* Used to determine how to fill in terminate error codes */
1293#define IWARP_OPCODE_WRITE 0
1294#define IWARP_OPCODE_READREQ 1
1295#define IWARP_OPCODE_READRSP 2
1296#define IWARP_OPCODE_SEND 3
1297#define IWARP_OPCODE_SEND_INV 4
1298#define IWARP_OPCODE_SEND_SE 5
1299#define IWARP_OPCODE_SEND_SE_INV 6
1300#define IWARP_OPCODE_TERM 7
1301
1302/* These values are used only during terminate processing */
1303#define TERM_DDP_LEN_TAGGED 14
1304#define TERM_DDP_LEN_UNTAGGED 18
1305#define TERM_RDMA_LEN 28
1306#define RDMA_OPCODE_MASK 0x0f
1307#define RDMA_READ_REQ_OPCODE 1
1308#define BAD_FRAME_OFFSET 64
1309#define CQE_MAJOR_DRV 0x8000
1310
1220#define nes_vlan_rx vlan_hwaccel_receive_skb 1311#define nes_vlan_rx vlan_hwaccel_receive_skb
1221#define nes_netif_rx netif_receive_skb 1312#define nes_netif_rx netif_receive_skb
1222 1313