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path: root/drivers/infiniband/hw/cxgb3/cxio_hal.c
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Diffstat (limited to 'drivers/infiniband/hw/cxgb3/cxio_hal.c')
-rw-r--r--drivers/infiniband/hw/cxgb3/cxio_hal.c27
1 files changed, 20 insertions, 7 deletions
diff --git a/drivers/infiniband/hw/cxgb3/cxio_hal.c b/drivers/infiniband/hw/cxgb3/cxio_hal.c
index 3f441fc57c17..f6d5747153a5 100644
--- a/drivers/infiniband/hw/cxgb3/cxio_hal.c
+++ b/drivers/infiniband/hw/cxgb3/cxio_hal.c
@@ -145,7 +145,9 @@ static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
145 } 145 }
146 wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe)); 146 wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
147 memset(wqe, 0, sizeof(*wqe)); 147 memset(wqe, 0, sizeof(*wqe));
148 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 3, 0, qpid, 7); 148 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD,
149 T3_COMPLETION_FLAG | T3_NOTIFY_FLAG, 0, qpid, 7,
150 T3_SOPEOP);
149 wqe->flags = cpu_to_be32(MODQP_WRITE_EC); 151 wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
150 sge_cmd = qpid << 8 | 3; 152 sge_cmd = qpid << 8 | 3;
151 wqe->sge_cmd = cpu_to_be64(sge_cmd); 153 wqe->sge_cmd = cpu_to_be64(sge_cmd);
@@ -276,7 +278,7 @@ int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
276 if (!wq->qpid) 278 if (!wq->qpid)
277 return -ENOMEM; 279 return -ENOMEM;
278 280
279 wq->rq = kzalloc(depth * sizeof(u64), GFP_KERNEL); 281 wq->rq = kzalloc(depth * sizeof(struct t3_swrq), GFP_KERNEL);
280 if (!wq->rq) 282 if (!wq->rq)
281 goto err1; 283 goto err1;
282 284
@@ -300,6 +302,7 @@ int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
300 if (!kernel_domain) 302 if (!kernel_domain)
301 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase + 303 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
302 (wq->qpid << rdev_p->qpshift); 304 (wq->qpid << rdev_p->qpshift);
305 wq->rdev = rdev_p;
303 PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __func__, 306 PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __func__,
304 wq->qpid, wq->doorbell, (unsigned long long) wq->udb); 307 wq->qpid, wq->doorbell, (unsigned long long) wq->udb);
305 return 0; 308 return 0;
@@ -558,7 +561,7 @@ static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
558 wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe)); 561 wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
559 memset(wqe, 0, sizeof(*wqe)); 562 memset(wqe, 0, sizeof(*wqe));
560 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0, 563 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0,
561 T3_CTL_QP_TID, 7); 564 T3_CTL_QP_TID, 7, T3_SOPEOP);
562 wqe->flags = cpu_to_be32(MODQP_WRITE_EC); 565 wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
563 sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3; 566 sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
564 wqe->sge_cmd = cpu_to_be64(sge_cmd); 567 wqe->sge_cmd = cpu_to_be64(sge_cmd);
@@ -674,7 +677,7 @@ static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
674 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag, 677 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
675 Q_GENBIT(rdev_p->ctrl_qp.wptr, 678 Q_GENBIT(rdev_p->ctrl_qp.wptr,
676 T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID, 679 T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
677 wr_len); 680 wr_len, T3_SOPEOP);
678 if (flag == T3_COMPLETION_FLAG) 681 if (flag == T3_COMPLETION_FLAG)
679 ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID); 682 ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
680 len -= 96; 683 len -= 96;
@@ -816,6 +819,13 @@ int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
816 0, 0); 819 0, 0);
817} 820}
818 821
822int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr)
823{
824 *stag = T3_STAG_UNSET;
825 return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
826 0, 0, 0ULL, 0, 0, pbl_size, pbl_addr);
827}
828
819int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr) 829int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
820{ 830{
821 struct t3_rdma_init_wr *wqe; 831 struct t3_rdma_init_wr *wqe;
@@ -1257,13 +1267,16 @@ proc_cqe:
1257 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe); 1267 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1258 PDBG("%s completing sq idx %ld\n", __func__, 1268 PDBG("%s completing sq idx %ld\n", __func__,
1259 Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)); 1269 Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1260 *cookie = (wq->sq + 1270 *cookie = wq->sq[Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)].wr_id;
1261 Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2))->wr_id;
1262 wq->sq_rptr++; 1271 wq->sq_rptr++;
1263 } else { 1272 } else {
1264 PDBG("%s completing rq idx %ld\n", __func__, 1273 PDBG("%s completing rq idx %ld\n", __func__,
1265 Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)); 1274 Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1266 *cookie = *(wq->rq + Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)); 1275 *cookie = wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].wr_id;
1276 if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr)
1277 cxio_hal_pblpool_free(wq->rdev,
1278 wq->rq[Q_PTR2IDX(wq->rq_rptr,
1279 wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE);
1267 wq->rq_rptr++; 1280 wq->rq_rptr++;
1268 } 1281 }
1269 1282