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-rw-r--r--drivers/ieee1394/dv1394.c2584
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diff --git a/drivers/ieee1394/dv1394.c b/drivers/ieee1394/dv1394.c
deleted file mode 100644
index c5a031b79d03..000000000000
--- a/drivers/ieee1394/dv1394.c
+++ /dev/null
@@ -1,2584 +0,0 @@
1/*
2 * dv1394.c - DV input/output over IEEE 1394 on OHCI chips
3 * Copyright (C)2001 Daniel Maas <dmaas@dcine.com>
4 * receive by Dan Dennedy <dan@dennedy.org>
5 *
6 * based on:
7 * video1394.c - video driver for OHCI 1394 boards
8 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software Foundation,
22 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 */
24
25/*
26 OVERVIEW
27
28 I designed dv1394 as a "pipe" that you can use to shoot DV onto a
29 FireWire bus. In transmission mode, dv1394 does the following:
30
31 1. accepts contiguous frames of DV data from user-space, via write()
32 or mmap() (see dv1394.h for the complete API)
33 2. wraps IEC 61883 packets around the DV data, inserting
34 empty synchronization packets as necessary
35 3. assigns accurate SYT timestamps to the outgoing packets
36 4. shoots them out using the OHCI card's IT DMA engine
37
38 Thanks to Dan Dennedy, we now have a receive mode that does the following:
39
40 1. accepts raw IEC 61883 packets from the OHCI card
41 2. re-assembles the DV data payloads into contiguous frames,
42 discarding empty packets
43 3. sends the DV data to user-space via read() or mmap()
44*/
45
46/*
47 TODO:
48
49 - tunable frame-drop behavior: either loop last frame, or halt transmission
50
51 - use a scatter/gather buffer for DMA programs (f->descriptor_pool)
52 so that we don't rely on allocating 64KB of contiguous kernel memory
53 via pci_alloc_consistent()
54
55 DONE:
56 - during reception, better handling of dropped frames and continuity errors
57 - during reception, prevent DMA from bypassing the irq tasklets
58 - reduce irq rate during reception (1/250 packets).
59 - add many more internal buffers during reception with scatter/gather dma.
60 - add dbc (continuity) checking on receive, increment status.dropped_frames
61 if not continuous.
62 - restart IT DMA after a bus reset
63 - safely obtain and release ISO Tx channels in cooperation with OHCI driver
64 - map received DIF blocks to their proper location in DV frame (ensure
65 recovery if dropped packet)
66 - handle bus resets gracefully (OHCI card seems to take care of this itself(!))
67 - do not allow resizing the user_buf once allocated; eliminate nuke_buffer_mappings
68 - eliminated #ifdef DV1394_DEBUG_LEVEL by inventing macros debug_printk and irq_printk
69 - added wmb() and mb() to places where PCI read/write ordering needs to be enforced
70 - set video->id correctly
71 - store video_cards in an array indexed by OHCI card ID, rather than a list
72 - implement DMA context allocation to cooperate with other users of the OHCI
73 - fix all XXX showstoppers
74 - disable IR/IT DMA interrupts on shutdown
75 - flush pci writes to the card by issuing a read
76 - character device dispatching
77 - switch over to the new kernel DMA API (pci_map_*()) (* needs testing on platforms with IOMMU!)
78 - keep all video_cards in a list (for open() via chardev), set file->private_data = video
79 - dv1394_poll should indicate POLLIN when receiving buffers are available
80 - add proc fs interface to set cip_n, cip_d, syt_offset, and video signal
81 - expose xmit and recv as separate devices (not exclusive)
82 - expose NTSC and PAL as separate devices (can be overridden)
83
84*/
85
86#include <linux/kernel.h>
87#include <linux/list.h>
88#include <linux/slab.h>
89#include <linux/interrupt.h>
90#include <linux/wait.h>
91#include <linux/errno.h>
92#include <linux/module.h>
93#include <linux/init.h>
94#include <linux/pci.h>
95#include <linux/fs.h>
96#include <linux/poll.h>
97#include <linux/mutex.h>
98#include <linux/bitops.h>
99#include <asm/byteorder.h>
100#include <asm/atomic.h>
101#include <asm/io.h>
102#include <asm/uaccess.h>
103#include <linux/delay.h>
104#include <asm/pgtable.h>
105#include <asm/page.h>
106#include <linux/sched.h>
107#include <linux/types.h>
108#include <linux/vmalloc.h>
109#include <linux/string.h>
110#include <linux/compat.h>
111#include <linux/cdev.h>
112
113#include "dv1394.h"
114#include "dv1394-private.h"
115#include "highlevel.h"
116#include "hosts.h"
117#include "ieee1394.h"
118#include "ieee1394_core.h"
119#include "ieee1394_hotplug.h"
120#include "ieee1394_types.h"
121#include "nodemgr.h"
122#include "ohci1394.h"
123
124/* DEBUG LEVELS:
125 0 - no debugging messages
126 1 - some debugging messages, but none during DMA frame transmission
127 2 - lots of messages, including during DMA frame transmission
128 (will cause underflows if your machine is too slow!)
129*/
130
131#define DV1394_DEBUG_LEVEL 0
132
133/* for debugging use ONLY: allow more than one open() of the device */
134/* #define DV1394_ALLOW_MORE_THAN_ONE_OPEN 1 */
135
136#if DV1394_DEBUG_LEVEL >= 2
137#define irq_printk( args... ) printk( args )
138#else
139#define irq_printk( args... ) do {} while (0)
140#endif
141
142#if DV1394_DEBUG_LEVEL >= 1
143#define debug_printk( args... ) printk( args)
144#else
145#define debug_printk( args... ) do {} while (0)
146#endif
147
148/* issue a dummy PCI read to force the preceding write
149 to be posted to the PCI bus immediately */
150
151static inline void flush_pci_write(struct ti_ohci *ohci)
152{
153 mb();
154 reg_read(ohci, OHCI1394_IsochronousCycleTimer);
155}
156
157static void it_tasklet_func(unsigned long data);
158static void ir_tasklet_func(unsigned long data);
159
160#ifdef CONFIG_COMPAT
161static long dv1394_compat_ioctl(struct file *file, unsigned int cmd,
162 unsigned long arg);
163#endif
164
165/* GLOBAL DATA */
166
167/* list of all video_cards */
168static LIST_HEAD(dv1394_cards);
169static DEFINE_SPINLOCK(dv1394_cards_lock);
170
171/* translate from a struct file* to the corresponding struct video_card* */
172
173static inline struct video_card* file_to_video_card(struct file *file)
174{
175 return file->private_data;
176}
177
178/*** FRAME METHODS *********************************************************/
179
180static void frame_reset(struct frame *f)
181{
182 f->state = FRAME_CLEAR;
183 f->done = 0;
184 f->n_packets = 0;
185 f->frame_begin_timestamp = NULL;
186 f->assigned_timestamp = 0;
187 f->cip_syt1 = NULL;
188 f->cip_syt2 = NULL;
189 f->mid_frame_timestamp = NULL;
190 f->frame_end_timestamp = NULL;
191 f->frame_end_branch = NULL;
192}
193
194static struct frame* frame_new(unsigned int frame_num, struct video_card *video)
195{
196 struct frame *f = kmalloc(sizeof(*f), GFP_KERNEL);
197 if (!f)
198 return NULL;
199
200 f->video = video;
201 f->frame_num = frame_num;
202
203 f->header_pool = pci_alloc_consistent(f->video->ohci->dev, PAGE_SIZE, &f->header_pool_dma);
204 if (!f->header_pool) {
205 printk(KERN_ERR "dv1394: failed to allocate CIP header pool\n");
206 kfree(f);
207 return NULL;
208 }
209
210 debug_printk("dv1394: frame_new: allocated CIP header pool at virt 0x%08lx (contig) dma 0x%08lx size %ld\n",
211 (unsigned long) f->header_pool, (unsigned long) f->header_pool_dma, PAGE_SIZE);
212
213 f->descriptor_pool_size = MAX_PACKETS * sizeof(struct DMA_descriptor_block);
214 /* make it an even # of pages */
215 f->descriptor_pool_size += PAGE_SIZE - (f->descriptor_pool_size%PAGE_SIZE);
216
217 f->descriptor_pool = pci_alloc_consistent(f->video->ohci->dev,
218 f->descriptor_pool_size,
219 &f->descriptor_pool_dma);
220 if (!f->descriptor_pool) {
221 pci_free_consistent(f->video->ohci->dev, PAGE_SIZE, f->header_pool, f->header_pool_dma);
222 kfree(f);
223 return NULL;
224 }
225
226 debug_printk("dv1394: frame_new: allocated DMA program memory at virt 0x%08lx (contig) dma 0x%08lx size %ld\n",
227 (unsigned long) f->descriptor_pool, (unsigned long) f->descriptor_pool_dma, f->descriptor_pool_size);
228
229 f->data = 0;
230 frame_reset(f);
231
232 return f;
233}
234
235static void frame_delete(struct frame *f)
236{
237 pci_free_consistent(f->video->ohci->dev, PAGE_SIZE, f->header_pool, f->header_pool_dma);
238 pci_free_consistent(f->video->ohci->dev, f->descriptor_pool_size, f->descriptor_pool, f->descriptor_pool_dma);
239 kfree(f);
240}
241
242
243
244
245/*
246 frame_prepare() - build the DMA program for transmitting
247
248 Frame_prepare() must be called OUTSIDE the video->spinlock.
249 However, frame_prepare() must still be serialized, so
250 it should be called WITH the video->mtx taken.
251 */
252
253static void frame_prepare(struct video_card *video, unsigned int this_frame)
254{
255 struct frame *f = video->frames[this_frame];
256 int last_frame;
257
258 struct DMA_descriptor_block *block;
259 dma_addr_t block_dma;
260 struct CIP_header *cip;
261 dma_addr_t cip_dma;
262
263 unsigned int n_descriptors, full_packets, packets_per_frame, payload_size;
264
265 /* these flags denote packets that need special attention */
266 int empty_packet, first_packet, last_packet, mid_packet;
267
268 __le32 *branch_address, *last_branch_address = NULL;
269 unsigned long data_p;
270 int first_packet_empty = 0;
271 u32 cycleTimer, ct_sec, ct_cyc, ct_off;
272 unsigned long irq_flags;
273
274 irq_printk("frame_prepare( %d ) ---------------------\n", this_frame);
275
276 full_packets = 0;
277
278
279
280 if (video->pal_or_ntsc == DV1394_PAL)
281 packets_per_frame = DV1394_PAL_PACKETS_PER_FRAME;
282 else
283 packets_per_frame = DV1394_NTSC_PACKETS_PER_FRAME;
284
285 while ( full_packets < packets_per_frame ) {
286 empty_packet = first_packet = last_packet = mid_packet = 0;
287
288 data_p = f->data + full_packets * 480;
289
290 /************************************************/
291 /* allocate a descriptor block and a CIP header */
292 /************************************************/
293
294 /* note: these should NOT cross a page boundary (DMA restriction) */
295
296 if (f->n_packets >= MAX_PACKETS) {
297 printk(KERN_ERR "dv1394: FATAL ERROR: max packet count exceeded\n");
298 return;
299 }
300
301 /* the block surely won't cross a page boundary,
302 since an even number of descriptor_blocks fit on a page */
303 block = &(f->descriptor_pool[f->n_packets]);
304
305 /* DMA address of the block = offset of block relative
306 to the kernel base address of the descriptor pool
307 + DMA base address of the descriptor pool */
308 block_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma;
309
310
311 /* the whole CIP pool fits on one page, so no worries about boundaries */
312 if ( ((unsigned long) &(f->header_pool[f->n_packets]) - (unsigned long) f->header_pool)
313 > PAGE_SIZE) {
314 printk(KERN_ERR "dv1394: FATAL ERROR: no room to allocate CIP header\n");
315 return;
316 }
317
318 cip = &(f->header_pool[f->n_packets]);
319
320 /* DMA address of the CIP header = offset of cip
321 relative to kernel base address of the header pool
322 + DMA base address of the header pool */
323 cip_dma = (unsigned long) cip % PAGE_SIZE + f->header_pool_dma;
324
325 /* is this an empty packet? */
326
327 if (video->cip_accum > (video->cip_d - video->cip_n)) {
328 empty_packet = 1;
329 payload_size = 8;
330 video->cip_accum -= (video->cip_d - video->cip_n);
331 } else {
332 payload_size = 488;
333 video->cip_accum += video->cip_n;
334 }
335
336 /* there are three important packets each frame:
337
338 the first packet in the frame - we ask the card to record the timestamp when
339 this packet is actually sent, so we can monitor
340 how accurate our timestamps are. Also, the first
341 packet serves as a semaphore to let us know that
342 it's OK to free the *previous* frame's DMA buffer
343
344 the last packet in the frame - this packet is used to detect buffer underflows.
345 if this is the last ready frame, the last DMA block
346 will have a branch back to the beginning of the frame
347 (so that the card will re-send the frame on underflow).
348 if this branch gets taken, we know that at least one
349 frame has been dropped. When the next frame is ready,
350 the branch is pointed to its first packet, and the
351 semaphore is disabled.
352
353 a "mid" packet slightly before the end of the frame - this packet should trigger
354 an interrupt so we can go and assign a timestamp to the first packet
355 in the next frame. We don't use the very last packet in the frame
356 for this purpose, because that would leave very little time to set
357 the timestamp before DMA starts on the next frame.
358 */
359
360 if (f->n_packets == 0) {
361 first_packet = 1;
362 } else if ( full_packets == (packets_per_frame-1) ) {
363 last_packet = 1;
364 } else if (f->n_packets == packets_per_frame) {
365 mid_packet = 1;
366 }
367
368
369 /********************/
370 /* setup CIP header */
371 /********************/
372
373 /* the timestamp will be written later from the
374 mid-frame interrupt handler. For now we just
375 store the address of the CIP header(s) that
376 need a timestamp. */
377
378 /* first packet in the frame needs a timestamp */
379 if (first_packet) {
380 f->cip_syt1 = cip;
381 if (empty_packet)
382 first_packet_empty = 1;
383
384 } else if (first_packet_empty && (f->n_packets == 1) ) {
385 /* if the first packet was empty, the second
386 packet's CIP header also needs a timestamp */
387 f->cip_syt2 = cip;
388 }
389
390 fill_cip_header(cip,
391 /* the node ID number of the OHCI card */
392 reg_read(video->ohci, OHCI1394_NodeID) & 0x3F,
393 video->continuity_counter,
394 video->pal_or_ntsc,
395 0xFFFF /* the timestamp is filled in later */);
396
397 /* advance counter, only for full packets */
398 if ( ! empty_packet )
399 video->continuity_counter++;
400
401 /******************************/
402 /* setup DMA descriptor block */
403 /******************************/
404
405 /* first descriptor - OUTPUT_MORE_IMMEDIATE, for the controller's IT header */
406 fill_output_more_immediate( &(block->u.out.omi), 1, video->channel, 0, payload_size);
407
408 if (empty_packet) {
409 /* second descriptor - OUTPUT_LAST for CIP header */
410 fill_output_last( &(block->u.out.u.empty.ol),
411
412 /* want completion status on all interesting packets */
413 (first_packet || mid_packet || last_packet) ? 1 : 0,
414
415 /* want interrupts on all interesting packets */
416 (first_packet || mid_packet || last_packet) ? 1 : 0,
417
418 sizeof(struct CIP_header), /* data size */
419 cip_dma);
420
421 if (first_packet)
422 f->frame_begin_timestamp = &(block->u.out.u.empty.ol.q[3]);
423 else if (mid_packet)
424 f->mid_frame_timestamp = &(block->u.out.u.empty.ol.q[3]);
425 else if (last_packet) {
426 f->frame_end_timestamp = &(block->u.out.u.empty.ol.q[3]);
427 f->frame_end_branch = &(block->u.out.u.empty.ol.q[2]);
428 }
429
430 branch_address = &(block->u.out.u.empty.ol.q[2]);
431 n_descriptors = 3;
432 if (first_packet)
433 f->first_n_descriptors = n_descriptors;
434
435 } else { /* full packet */
436
437 /* second descriptor - OUTPUT_MORE for CIP header */
438 fill_output_more( &(block->u.out.u.full.om),
439 sizeof(struct CIP_header), /* data size */
440 cip_dma);
441
442
443 /* third (and possibly fourth) descriptor - for DV data */
444 /* the 480-byte payload can cross a page boundary; if so,
445 we need to split it into two DMA descriptors */
446
447 /* does the 480-byte data payload cross a page boundary? */
448 if ( (PAGE_SIZE- ((unsigned long)data_p % PAGE_SIZE) ) < 480 ) {
449
450 /* page boundary crossed */
451
452 fill_output_more( &(block->u.out.u.full.u.cross.om),
453 /* data size - how much of data_p fits on the first page */
454 PAGE_SIZE - (data_p % PAGE_SIZE),
455
456 /* DMA address of data_p */
457 dma_region_offset_to_bus(&video->dv_buf,
458 data_p - (unsigned long) video->dv_buf.kvirt));
459
460 fill_output_last( &(block->u.out.u.full.u.cross.ol),
461
462 /* want completion status on all interesting packets */
463 (first_packet || mid_packet || last_packet) ? 1 : 0,
464
465 /* want interrupt on all interesting packets */
466 (first_packet || mid_packet || last_packet) ? 1 : 0,
467
468 /* data size - remaining portion of data_p */
469 480 - (PAGE_SIZE - (data_p % PAGE_SIZE)),
470
471 /* DMA address of data_p + PAGE_SIZE - (data_p % PAGE_SIZE) */
472 dma_region_offset_to_bus(&video->dv_buf,
473 data_p + PAGE_SIZE - (data_p % PAGE_SIZE) - (unsigned long) video->dv_buf.kvirt));
474
475 if (first_packet)
476 f->frame_begin_timestamp = &(block->u.out.u.full.u.cross.ol.q[3]);
477 else if (mid_packet)
478 f->mid_frame_timestamp = &(block->u.out.u.full.u.cross.ol.q[3]);
479 else if (last_packet) {
480 f->frame_end_timestamp = &(block->u.out.u.full.u.cross.ol.q[3]);
481 f->frame_end_branch = &(block->u.out.u.full.u.cross.ol.q[2]);
482 }
483
484 branch_address = &(block->u.out.u.full.u.cross.ol.q[2]);
485
486 n_descriptors = 5;
487 if (first_packet)
488 f->first_n_descriptors = n_descriptors;
489
490 full_packets++;
491
492 } else {
493 /* fits on one page */
494
495 fill_output_last( &(block->u.out.u.full.u.nocross.ol),
496
497 /* want completion status on all interesting packets */
498 (first_packet || mid_packet || last_packet) ? 1 : 0,
499
500 /* want interrupt on all interesting packets */
501 (first_packet || mid_packet || last_packet) ? 1 : 0,
502
503 480, /* data size (480 bytes of DV data) */
504
505
506 /* DMA address of data_p */
507 dma_region_offset_to_bus(&video->dv_buf,
508 data_p - (unsigned long) video->dv_buf.kvirt));
509
510 if (first_packet)
511 f->frame_begin_timestamp = &(block->u.out.u.full.u.nocross.ol.q[3]);
512 else if (mid_packet)
513 f->mid_frame_timestamp = &(block->u.out.u.full.u.nocross.ol.q[3]);
514 else if (last_packet) {
515 f->frame_end_timestamp = &(block->u.out.u.full.u.nocross.ol.q[3]);
516 f->frame_end_branch = &(block->u.out.u.full.u.nocross.ol.q[2]);
517 }
518
519 branch_address = &(block->u.out.u.full.u.nocross.ol.q[2]);
520
521 n_descriptors = 4;
522 if (first_packet)
523 f->first_n_descriptors = n_descriptors;
524
525 full_packets++;
526 }
527 }
528
529 /* link this descriptor block into the DMA program by filling in
530 the branch address of the previous block */
531
532 /* note: we are not linked into the active DMA chain yet */
533
534 if (last_branch_address) {
535 *(last_branch_address) = cpu_to_le32(block_dma | n_descriptors);
536 }
537
538 last_branch_address = branch_address;
539
540
541 f->n_packets++;
542
543 }
544
545 /* when we first assemble a new frame, set the final branch
546 to loop back up to the top */
547 *(f->frame_end_branch) = cpu_to_le32(f->descriptor_pool_dma | f->first_n_descriptors);
548
549 /* make the latest version of this frame visible to the PCI card */
550 dma_region_sync_for_device(&video->dv_buf, f->data - (unsigned long) video->dv_buf.kvirt, video->frame_size);
551
552 /* lock against DMA interrupt */
553 spin_lock_irqsave(&video->spinlock, irq_flags);
554
555 f->state = FRAME_READY;
556
557 video->n_clear_frames--;
558
559 last_frame = video->first_clear_frame - 1;
560 if (last_frame == -1)
561 last_frame = video->n_frames-1;
562
563 video->first_clear_frame = (video->first_clear_frame + 1) % video->n_frames;
564
565 irq_printk(" frame %d prepared, active_frame = %d, n_clear_frames = %d, first_clear_frame = %d\n last=%d\n",
566 this_frame, video->active_frame, video->n_clear_frames, video->first_clear_frame, last_frame);
567
568 irq_printk(" begin_ts %08lx mid_ts %08lx end_ts %08lx end_br %08lx\n",
569 (unsigned long) f->frame_begin_timestamp,
570 (unsigned long) f->mid_frame_timestamp,
571 (unsigned long) f->frame_end_timestamp,
572 (unsigned long) f->frame_end_branch);
573
574 if (video->active_frame != -1) {
575
576 /* if DMA is already active, we are almost done */
577 /* just link us onto the active DMA chain */
578 if (video->frames[last_frame]->frame_end_branch) {
579 u32 temp;
580
581 /* point the previous frame's tail to this frame's head */
582 *(video->frames[last_frame]->frame_end_branch) = cpu_to_le32(f->descriptor_pool_dma | f->first_n_descriptors);
583
584 /* this write MUST precede the next one, or we could silently drop frames */
585 wmb();
586
587 /* disable the want_status semaphore on the last packet */
588 temp = le32_to_cpu(*(video->frames[last_frame]->frame_end_branch - 2));
589 temp &= 0xF7CFFFFF;
590 *(video->frames[last_frame]->frame_end_branch - 2) = cpu_to_le32(temp);
591
592 /* flush these writes to memory ASAP */
593 flush_pci_write(video->ohci);
594
595 /* NOTE:
596 ideally the writes should be "atomic": if
597 the OHCI card reads the want_status flag in
598 between them, we'll falsely report a
599 dropped frame. Hopefully this window is too
600 small to really matter, and the consequence
601 is rather harmless. */
602
603
604 irq_printk(" new frame %d linked onto DMA chain\n", this_frame);
605
606 } else {
607 printk(KERN_ERR "dv1394: last frame not ready???\n");
608 }
609
610 } else {
611
612 u32 transmit_sec, transmit_cyc;
613 u32 ts_cyc;
614
615 /* DMA is stopped, so this is the very first frame */
616 video->active_frame = this_frame;
617
618 /* set CommandPtr to address and size of first descriptor block */
619 reg_write(video->ohci, video->ohci_IsoXmitCommandPtr,
620 video->frames[video->active_frame]->descriptor_pool_dma |
621 f->first_n_descriptors);
622
623 /* assign a timestamp based on the current cycle time...
624 We'll tell the card to begin DMA 100 cycles from now,
625 and assign a timestamp 103 cycles from now */
626
627 cycleTimer = reg_read(video->ohci, OHCI1394_IsochronousCycleTimer);
628
629 ct_sec = cycleTimer >> 25;
630 ct_cyc = (cycleTimer >> 12) & 0x1FFF;
631 ct_off = cycleTimer & 0xFFF;
632
633 transmit_sec = ct_sec;
634 transmit_cyc = ct_cyc + 100;
635
636 transmit_sec += transmit_cyc/8000;
637 transmit_cyc %= 8000;
638
639 ts_cyc = transmit_cyc + 3;
640 ts_cyc %= 8000;
641
642 f->assigned_timestamp = (ts_cyc&0xF) << 12;
643
644 /* now actually write the timestamp into the appropriate CIP headers */
645 if (f->cip_syt1) {
646 f->cip_syt1->b[6] = f->assigned_timestamp >> 8;
647 f->cip_syt1->b[7] = f->assigned_timestamp & 0xFF;
648 }
649 if (f->cip_syt2) {
650 f->cip_syt2->b[6] = f->assigned_timestamp >> 8;
651 f->cip_syt2->b[7] = f->assigned_timestamp & 0xFF;
652 }
653
654 /* --- start DMA --- */
655
656 /* clear all bits in ContextControl register */
657
658 reg_write(video->ohci, video->ohci_IsoXmitContextControlClear, 0xFFFFFFFF);
659 wmb();
660
661 /* the OHCI card has the ability to start ISO transmission on a
662 particular cycle (start-on-cycle). This way we can ensure that
663 the first DV frame will have an accurate timestamp.
664
665 However, start-on-cycle only appears to work if the OHCI card
666 is cycle master! Since the consequences of messing up the first
667 timestamp are minimal*, just disable start-on-cycle for now.
668
669 * my DV deck drops the first few frames before it "locks in;"
670 so the first frame having an incorrect timestamp is inconsequential.
671 */
672
673#if 0
674 reg_write(video->ohci, video->ohci_IsoXmitContextControlSet,
675 (1 << 31) /* enable start-on-cycle */
676 | ( (transmit_sec & 0x3) << 29)
677 | (transmit_cyc << 16));
678 wmb();
679#endif
680
681 video->dma_running = 1;
682
683 /* set the 'run' bit */
684 reg_write(video->ohci, video->ohci_IsoXmitContextControlSet, 0x8000);
685 flush_pci_write(video->ohci);
686
687 /* --- DMA should be running now --- */
688
689 debug_printk(" Cycle = %4u ContextControl = %08x CmdPtr = %08x\n",
690 (reg_read(video->ohci, OHCI1394_IsochronousCycleTimer) >> 12) & 0x1FFF,
691 reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
692 reg_read(video->ohci, video->ohci_IsoXmitCommandPtr));
693
694 debug_printk(" DMA start - current cycle %4u, transmit cycle %4u (%2u), assigning ts cycle %2u\n",
695 ct_cyc, transmit_cyc, transmit_cyc & 0xF, ts_cyc & 0xF);
696
697#if DV1394_DEBUG_LEVEL >= 2
698 {
699 /* check if DMA is really running */
700 int i = 0;
701 while (i < 20) {
702 mb();
703 mdelay(1);
704 if (reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) & (1 << 10)) {
705 printk("DMA ACTIVE after %d msec\n", i);
706 break;
707 }
708 i++;
709 }
710
711 printk("set = %08x, cmdPtr = %08x\n",
712 reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
713 reg_read(video->ohci, video->ohci_IsoXmitCommandPtr)
714 );
715
716 if ( ! (reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) & (1 << 10)) ) {
717 printk("DMA did NOT go active after 20ms, event = %x\n",
718 reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) & 0x1F);
719 } else
720 printk("DMA is RUNNING!\n");
721 }
722#endif
723
724 }
725
726
727 spin_unlock_irqrestore(&video->spinlock, irq_flags);
728}
729
730
731
732/*** RECEIVE FUNCTIONS *****************************************************/
733
734/*
735 frame method put_packet
736
737 map and copy the packet data to its location in the frame
738 based upon DIF section and sequence
739*/
740
741static void inline
742frame_put_packet (struct frame *f, struct packet *p)
743{
744 int section_type = p->data[0] >> 5; /* section type is in bits 5 - 7 */
745 int dif_sequence = p->data[1] >> 4; /* dif sequence number is in bits 4 - 7 */
746 int dif_block = p->data[2];
747
748 /* sanity check */
749 if (dif_sequence > 11 || dif_block > 149) return;
750
751 switch (section_type) {
752 case 0: /* 1 Header block */
753 memcpy( (void *) f->data + dif_sequence * 150 * 80, p->data, 480);
754 break;
755
756 case 1: /* 2 Subcode blocks */
757 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (1 + dif_block) * 80, p->data, 480);
758 break;
759
760 case 2: /* 3 VAUX blocks */
761 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (3 + dif_block) * 80, p->data, 480);
762 break;
763
764 case 3: /* 9 Audio blocks interleaved with video */
765 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (6 + dif_block * 16) * 80, p->data, 480);
766 break;
767
768 case 4: /* 135 Video blocks interleaved with audio */
769 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (7 + (dif_block / 15) + dif_block) * 80, p->data, 480);
770 break;
771
772 default: /* we can not handle any other data */
773 break;
774 }
775}
776
777
778static void start_dma_receive(struct video_card *video)
779{
780 if (video->first_run == 1) {
781 video->first_run = 0;
782
783 /* start DMA once all of the frames are READY */
784 video->n_clear_frames = 0;
785 video->first_clear_frame = -1;
786 video->current_packet = 0;
787 video->active_frame = 0;
788
789 /* reset iso recv control register */
790 reg_write(video->ohci, video->ohci_IsoRcvContextControlClear, 0xFFFFFFFF);
791 wmb();
792
793 /* clear bufferFill, set isochHeader and speed (0=100) */
794 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, 0x40000000);
795
796 /* match on all tags, listen on channel */
797 reg_write(video->ohci, video->ohci_IsoRcvContextMatch, 0xf0000000 | video->channel);
798
799 /* address and first descriptor block + Z=1 */
800 reg_write(video->ohci, video->ohci_IsoRcvCommandPtr,
801 video->frames[0]->descriptor_pool_dma | 1); /* Z=1 */
802 wmb();
803
804 video->dma_running = 1;
805
806 /* run */
807 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, 0x8000);
808 flush_pci_write(video->ohci);
809
810 debug_printk("dv1394: DMA started\n");
811
812#if DV1394_DEBUG_LEVEL >= 2
813 {
814 int i;
815
816 for (i = 0; i < 1000; ++i) {
817 mdelay(1);
818 if (reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & (1 << 10)) {
819 printk("DMA ACTIVE after %d msec\n", i);
820 break;
821 }
822 }
823 if ( reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & (1 << 11) ) {
824 printk("DEAD, event = %x\n",
825 reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & 0x1F);
826 } else
827 printk("RUNNING!\n");
828 }
829#endif
830 } else if ( reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & (1 << 11) ) {
831 debug_printk("DEAD, event = %x\n",
832 reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & 0x1F);
833
834 /* wake */
835 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 12));
836 }
837}
838
839
840/*
841 receive_packets() - build the DMA program for receiving
842*/
843
844static void receive_packets(struct video_card *video)
845{
846 struct DMA_descriptor_block *block = NULL;
847 dma_addr_t block_dma = 0;
848 struct packet *data = NULL;
849 dma_addr_t data_dma = 0;
850 __le32 *last_branch_address = NULL;
851 unsigned long irq_flags;
852 int want_interrupt = 0;
853 struct frame *f = NULL;
854 int i, j;
855
856 spin_lock_irqsave(&video->spinlock, irq_flags);
857
858 for (j = 0; j < video->n_frames; j++) {
859
860 /* connect frames */
861 if (j > 0 && f != NULL && f->frame_end_branch != NULL)
862 *(f->frame_end_branch) = cpu_to_le32(video->frames[j]->descriptor_pool_dma | 1); /* set Z=1 */
863
864 f = video->frames[j];
865
866 for (i = 0; i < MAX_PACKETS; i++) {
867 /* locate a descriptor block and packet from the buffer */
868 block = &(f->descriptor_pool[i]);
869 block_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma;
870
871 data = ((struct packet*)video->packet_buf.kvirt) + f->frame_num * MAX_PACKETS + i;
872 data_dma = dma_region_offset_to_bus( &video->packet_buf,
873 ((unsigned long) data - (unsigned long) video->packet_buf.kvirt) );
874
875 /* setup DMA descriptor block */
876 want_interrupt = ((i % (MAX_PACKETS/2)) == 0 || i == (MAX_PACKETS-1));
877 fill_input_last( &(block->u.in.il), want_interrupt, 512, data_dma);
878
879 /* link descriptors */
880 last_branch_address = f->frame_end_branch;
881
882 if (last_branch_address != NULL)
883 *(last_branch_address) = cpu_to_le32(block_dma | 1); /* set Z=1 */
884
885 f->frame_end_branch = &(block->u.in.il.q[2]);
886 }
887
888 } /* next j */
889
890 spin_unlock_irqrestore(&video->spinlock, irq_flags);
891
892}
893
894
895
896/*** MANAGEMENT FUNCTIONS **************************************************/
897
898static int do_dv1394_init(struct video_card *video, struct dv1394_init *init)
899{
900 unsigned long flags, new_buf_size;
901 int i;
902 u64 chan_mask;
903 int retval = -EINVAL;
904
905 debug_printk("dv1394: initialising %d\n", video->id);
906 if (init->api_version != DV1394_API_VERSION)
907 return -EINVAL;
908
909 /* first sanitize all the parameters */
910 if ( (init->n_frames < 2) || (init->n_frames > DV1394_MAX_FRAMES) )
911 return -EINVAL;
912
913 if ( (init->format != DV1394_NTSC) && (init->format != DV1394_PAL) )
914 return -EINVAL;
915
916 if ( (init->syt_offset == 0) || (init->syt_offset > 50) )
917 /* default SYT offset is 3 cycles */
918 init->syt_offset = 3;
919
920 if (init->channel > 63)
921 init->channel = 63;
922
923 chan_mask = (u64)1 << init->channel;
924
925 /* calculate what size DMA buffer is needed */
926 if (init->format == DV1394_NTSC)
927 new_buf_size = DV1394_NTSC_FRAME_SIZE * init->n_frames;
928 else
929 new_buf_size = DV1394_PAL_FRAME_SIZE * init->n_frames;
930
931 /* round up to PAGE_SIZE */
932 if (new_buf_size % PAGE_SIZE) new_buf_size += PAGE_SIZE - (new_buf_size % PAGE_SIZE);
933
934 /* don't allow the user to allocate the DMA buffer more than once */
935 if (video->dv_buf.kvirt && video->dv_buf_size != new_buf_size) {
936 printk("dv1394: re-sizing the DMA buffer is not allowed\n");
937 return -EINVAL;
938 }
939
940 /* shutdown the card if it's currently active */
941 /* (the card should not be reset if the parameters are screwy) */
942
943 do_dv1394_shutdown(video, 0);
944
945 /* try to claim the ISO channel */
946 spin_lock_irqsave(&video->ohci->IR_channel_lock, flags);
947 if (video->ohci->ISO_channel_usage & chan_mask) {
948 spin_unlock_irqrestore(&video->ohci->IR_channel_lock, flags);
949 retval = -EBUSY;
950 goto err;
951 }
952 video->ohci->ISO_channel_usage |= chan_mask;
953 spin_unlock_irqrestore(&video->ohci->IR_channel_lock, flags);
954
955 video->channel = init->channel;
956
957 /* initialize misc. fields of video */
958 video->n_frames = init->n_frames;
959 video->pal_or_ntsc = init->format;
960
961 video->cip_accum = 0;
962 video->continuity_counter = 0;
963
964 video->active_frame = -1;
965 video->first_clear_frame = 0;
966 video->n_clear_frames = video->n_frames;
967 video->dropped_frames = 0;
968
969 video->write_off = 0;
970
971 video->first_run = 1;
972 video->current_packet = -1;
973 video->first_frame = 0;
974
975 if (video->pal_or_ntsc == DV1394_NTSC) {
976 video->cip_n = init->cip_n != 0 ? init->cip_n : CIP_N_NTSC;
977 video->cip_d = init->cip_d != 0 ? init->cip_d : CIP_D_NTSC;
978 video->frame_size = DV1394_NTSC_FRAME_SIZE;
979 } else {
980 video->cip_n = init->cip_n != 0 ? init->cip_n : CIP_N_PAL;
981 video->cip_d = init->cip_d != 0 ? init->cip_d : CIP_D_PAL;
982 video->frame_size = DV1394_PAL_FRAME_SIZE;
983 }
984
985 video->syt_offset = init->syt_offset;
986
987 /* find and claim DMA contexts on the OHCI card */
988
989 if (video->ohci_it_ctx == -1) {
990 ohci1394_init_iso_tasklet(&video->it_tasklet, OHCI_ISO_TRANSMIT,
991 it_tasklet_func, (unsigned long) video);
992
993 if (ohci1394_register_iso_tasklet(video->ohci, &video->it_tasklet) < 0) {
994 printk(KERN_ERR "dv1394: could not find an available IT DMA context\n");
995 retval = -EBUSY;
996 goto err;
997 }
998
999 video->ohci_it_ctx = video->it_tasklet.context;
1000 debug_printk("dv1394: claimed IT DMA context %d\n", video->ohci_it_ctx);
1001 }
1002
1003 if (video->ohci_ir_ctx == -1) {
1004 ohci1394_init_iso_tasklet(&video->ir_tasklet, OHCI_ISO_RECEIVE,
1005 ir_tasklet_func, (unsigned long) video);
1006
1007 if (ohci1394_register_iso_tasklet(video->ohci, &video->ir_tasklet) < 0) {
1008 printk(KERN_ERR "dv1394: could not find an available IR DMA context\n");
1009 retval = -EBUSY;
1010 goto err;
1011 }
1012 video->ohci_ir_ctx = video->ir_tasklet.context;
1013 debug_printk("dv1394: claimed IR DMA context %d\n", video->ohci_ir_ctx);
1014 }
1015
1016 /* allocate struct frames */
1017 for (i = 0; i < init->n_frames; i++) {
1018 video->frames[i] = frame_new(i, video);
1019
1020 if (!video->frames[i]) {
1021 printk(KERN_ERR "dv1394: Cannot allocate frame structs\n");
1022 retval = -ENOMEM;
1023 goto err;
1024 }
1025 }
1026
1027 if (!video->dv_buf.kvirt) {
1028 /* allocate the ringbuffer */
1029 retval = dma_region_alloc(&video->dv_buf, new_buf_size, video->ohci->dev, PCI_DMA_TODEVICE);
1030 if (retval)
1031 goto err;
1032
1033 video->dv_buf_size = new_buf_size;
1034
1035 debug_printk("dv1394: Allocated %d frame buffers, total %u pages (%u DMA pages), %lu bytes\n",
1036 video->n_frames, video->dv_buf.n_pages,
1037 video->dv_buf.n_dma_pages, video->dv_buf_size);
1038 }
1039
1040 /* set up the frame->data pointers */
1041 for (i = 0; i < video->n_frames; i++)
1042 video->frames[i]->data = (unsigned long) video->dv_buf.kvirt + i * video->frame_size;
1043
1044 if (!video->packet_buf.kvirt) {
1045 /* allocate packet buffer */
1046 video->packet_buf_size = sizeof(struct packet) * video->n_frames * MAX_PACKETS;
1047 if (video->packet_buf_size % PAGE_SIZE)
1048 video->packet_buf_size += PAGE_SIZE - (video->packet_buf_size % PAGE_SIZE);
1049
1050 retval = dma_region_alloc(&video->packet_buf, video->packet_buf_size,
1051 video->ohci->dev, PCI_DMA_FROMDEVICE);
1052 if (retval)
1053 goto err;
1054
1055 debug_printk("dv1394: Allocated %d packets in buffer, total %u pages (%u DMA pages), %lu bytes\n",
1056 video->n_frames*MAX_PACKETS, video->packet_buf.n_pages,
1057 video->packet_buf.n_dma_pages, video->packet_buf_size);
1058 }
1059
1060 /* set up register offsets for IT context */
1061 /* IT DMA context registers are spaced 16 bytes apart */
1062 video->ohci_IsoXmitContextControlSet = OHCI1394_IsoXmitContextControlSet+16*video->ohci_it_ctx;
1063 video->ohci_IsoXmitContextControlClear = OHCI1394_IsoXmitContextControlClear+16*video->ohci_it_ctx;
1064 video->ohci_IsoXmitCommandPtr = OHCI1394_IsoXmitCommandPtr+16*video->ohci_it_ctx;
1065
1066 /* enable interrupts for IT context */
1067 reg_write(video->ohci, OHCI1394_IsoXmitIntMaskSet, (1 << video->ohci_it_ctx));
1068 debug_printk("dv1394: interrupts enabled for IT context %d\n", video->ohci_it_ctx);
1069
1070 /* set up register offsets for IR context */
1071 /* IR DMA context registers are spaced 32 bytes apart */
1072 video->ohci_IsoRcvContextControlSet = OHCI1394_IsoRcvContextControlSet+32*video->ohci_ir_ctx;
1073 video->ohci_IsoRcvContextControlClear = OHCI1394_IsoRcvContextControlClear+32*video->ohci_ir_ctx;
1074 video->ohci_IsoRcvCommandPtr = OHCI1394_IsoRcvCommandPtr+32*video->ohci_ir_ctx;
1075 video->ohci_IsoRcvContextMatch = OHCI1394_IsoRcvContextMatch+32*video->ohci_ir_ctx;
1076
1077 /* enable interrupts for IR context */
1078 reg_write(video->ohci, OHCI1394_IsoRecvIntMaskSet, (1 << video->ohci_ir_ctx) );
1079 debug_printk("dv1394: interrupts enabled for IR context %d\n", video->ohci_ir_ctx);
1080
1081 return 0;
1082
1083err:
1084 do_dv1394_shutdown(video, 1);
1085 return retval;
1086}
1087
1088/* if the user doesn't bother to call ioctl(INIT) before starting
1089 mmap() or read()/write(), just give him some default values */
1090
1091static int do_dv1394_init_default(struct video_card *video)
1092{
1093 struct dv1394_init init;
1094
1095 init.api_version = DV1394_API_VERSION;
1096 init.n_frames = DV1394_MAX_FRAMES / 4;
1097 init.channel = video->channel;
1098 init.format = video->pal_or_ntsc;
1099 init.cip_n = video->cip_n;
1100 init.cip_d = video->cip_d;
1101 init.syt_offset = video->syt_offset;
1102
1103 return do_dv1394_init(video, &init);
1104}
1105
1106/* do NOT call from interrupt context */
1107static void stop_dma(struct video_card *video)
1108{
1109 unsigned long flags;
1110 int i;
1111
1112 /* no interrupts */
1113 spin_lock_irqsave(&video->spinlock, flags);
1114
1115 video->dma_running = 0;
1116
1117 if ( (video->ohci_it_ctx == -1) && (video->ohci_ir_ctx == -1) )
1118 goto out;
1119
1120 /* stop DMA if in progress */
1121 if ( (video->active_frame != -1) ||
1122 (reg_read(video->ohci, video->ohci_IsoXmitContextControlClear) & (1 << 10)) ||
1123 (reg_read(video->ohci, video->ohci_IsoRcvContextControlClear) & (1 << 10)) ) {
1124
1125 /* clear the .run bits */
1126 reg_write(video->ohci, video->ohci_IsoXmitContextControlClear, (1 << 15));
1127 reg_write(video->ohci, video->ohci_IsoRcvContextControlClear, (1 << 15));
1128 flush_pci_write(video->ohci);
1129
1130 video->active_frame = -1;
1131 video->first_run = 1;
1132
1133 /* wait until DMA really stops */
1134 i = 0;
1135 while (i < 1000) {
1136
1137 /* wait 0.1 millisecond */
1138 udelay(100);
1139
1140 if ( (reg_read(video->ohci, video->ohci_IsoXmitContextControlClear) & (1 << 10)) ||
1141 (reg_read(video->ohci, video->ohci_IsoRcvContextControlClear) & (1 << 10)) ) {
1142 /* still active */
1143 debug_printk("dv1394: stop_dma: DMA not stopped yet\n" );
1144 mb();
1145 } else {
1146 debug_printk("dv1394: stop_dma: DMA stopped safely after %d ms\n", i/10);
1147 break;
1148 }
1149
1150 i++;
1151 }
1152
1153 if (i == 1000) {
1154 printk(KERN_ERR "dv1394: stop_dma: DMA still going after %d ms!\n", i/10);
1155 }
1156 }
1157 else
1158 debug_printk("dv1394: stop_dma: already stopped.\n");
1159
1160out:
1161 spin_unlock_irqrestore(&video->spinlock, flags);
1162}
1163
1164
1165
1166static void do_dv1394_shutdown(struct video_card *video, int free_dv_buf)
1167{
1168 int i;
1169
1170 debug_printk("dv1394: shutdown...\n");
1171
1172 /* stop DMA if in progress */
1173 stop_dma(video);
1174
1175 /* release the DMA contexts */
1176 if (video->ohci_it_ctx != -1) {
1177 video->ohci_IsoXmitContextControlSet = 0;
1178 video->ohci_IsoXmitContextControlClear = 0;
1179 video->ohci_IsoXmitCommandPtr = 0;
1180
1181 /* disable interrupts for IT context */
1182 reg_write(video->ohci, OHCI1394_IsoXmitIntMaskClear, (1 << video->ohci_it_ctx));
1183
1184 /* remove tasklet */
1185 ohci1394_unregister_iso_tasklet(video->ohci, &video->it_tasklet);
1186 debug_printk("dv1394: IT context %d released\n", video->ohci_it_ctx);
1187 video->ohci_it_ctx = -1;
1188 }
1189
1190 if (video->ohci_ir_ctx != -1) {
1191 video->ohci_IsoRcvContextControlSet = 0;
1192 video->ohci_IsoRcvContextControlClear = 0;
1193 video->ohci_IsoRcvCommandPtr = 0;
1194 video->ohci_IsoRcvContextMatch = 0;
1195
1196 /* disable interrupts for IR context */
1197 reg_write(video->ohci, OHCI1394_IsoRecvIntMaskClear, (1 << video->ohci_ir_ctx));
1198
1199 /* remove tasklet */
1200 ohci1394_unregister_iso_tasklet(video->ohci, &video->ir_tasklet);
1201 debug_printk("dv1394: IR context %d released\n", video->ohci_ir_ctx);
1202 video->ohci_ir_ctx = -1;
1203 }
1204
1205 /* release the ISO channel */
1206 if (video->channel != -1) {
1207 u64 chan_mask;
1208 unsigned long flags;
1209
1210 chan_mask = (u64)1 << video->channel;
1211
1212 spin_lock_irqsave(&video->ohci->IR_channel_lock, flags);
1213 video->ohci->ISO_channel_usage &= ~(chan_mask);
1214 spin_unlock_irqrestore(&video->ohci->IR_channel_lock, flags);
1215
1216 video->channel = -1;
1217 }
1218
1219 /* free the frame structs */
1220 for (i = 0; i < DV1394_MAX_FRAMES; i++) {
1221 if (video->frames[i])
1222 frame_delete(video->frames[i]);
1223 video->frames[i] = NULL;
1224 }
1225
1226 video->n_frames = 0;
1227
1228 /* we can't free the DMA buffer unless it is guaranteed that
1229 no more user-space mappings exist */
1230
1231 if (free_dv_buf) {
1232 dma_region_free(&video->dv_buf);
1233 video->dv_buf_size = 0;
1234 }
1235
1236 /* free packet buffer */
1237 dma_region_free(&video->packet_buf);
1238 video->packet_buf_size = 0;
1239
1240 debug_printk("dv1394: shutdown OK\n");
1241}
1242
1243/*
1244 **********************************
1245 *** MMAP() THEORY OF OPERATION ***
1246 **********************************
1247
1248 The ringbuffer cannot be re-allocated or freed while
1249 a user program maintains a mapping of it. (note that a mapping
1250 can persist even after the device fd is closed!)
1251
1252 So, only let the user process allocate the DMA buffer once.
1253 To resize or deallocate it, you must close the device file
1254 and open it again.
1255
1256 Previously Dan M. hacked out a scheme that allowed the DMA
1257 buffer to change by forcefully unmapping it from the user's
1258 address space. It was prone to error because it's very hard to
1259 track all the places the buffer could have been mapped (we
1260 would have had to walk the vma list of every process in the
1261 system to be sure we found all the mappings!). Instead, we
1262 force the user to choose one buffer size and stick with
1263 it. This small sacrifice is worth the huge reduction in
1264 error-prone code in dv1394.
1265*/
1266
1267static int dv1394_mmap(struct file *file, struct vm_area_struct *vma)
1268{
1269 struct video_card *video = file_to_video_card(file);
1270 int retval = -EINVAL;
1271
1272 /*
1273 * We cannot use the blocking variant mutex_lock here because .mmap
1274 * is called with mmap_sem held, while .ioctl, .read, .write acquire
1275 * video->mtx and subsequently call copy_to/from_user which will
1276 * grab mmap_sem in case of a page fault.
1277 */
1278 if (!mutex_trylock(&video->mtx))
1279 return -EAGAIN;
1280
1281 if ( ! video_card_initialized(video) ) {
1282 retval = do_dv1394_init_default(video);
1283 if (retval)
1284 goto out;
1285 }
1286
1287 retval = dma_region_mmap(&video->dv_buf, file, vma);
1288out:
1289 mutex_unlock(&video->mtx);
1290 return retval;
1291}
1292
1293/*** DEVICE FILE INTERFACE *************************************************/
1294
1295/* no need to serialize, multiple threads OK */
1296static unsigned int dv1394_poll(struct file *file, struct poll_table_struct *wait)
1297{
1298 struct video_card *video = file_to_video_card(file);
1299 unsigned int mask = 0;
1300 unsigned long flags;
1301
1302 poll_wait(file, &video->waitq, wait);
1303
1304 spin_lock_irqsave(&video->spinlock, flags);
1305 if ( video->n_frames == 0 ) {
1306
1307 } else if ( video->active_frame == -1 ) {
1308 /* nothing going on */
1309 mask |= POLLOUT;
1310 } else {
1311 /* any clear/ready buffers? */
1312 if (video->n_clear_frames >0)
1313 mask |= POLLOUT | POLLIN;
1314 }
1315 spin_unlock_irqrestore(&video->spinlock, flags);
1316
1317 return mask;
1318}
1319
1320static int dv1394_fasync(int fd, struct file *file, int on)
1321{
1322 /* I just copied this code verbatim from Alan Cox's mouse driver example
1323 (Documentation/DocBook/) */
1324
1325 struct video_card *video = file_to_video_card(file);
1326
1327 return fasync_helper(fd, file, on, &video->fasync);
1328}
1329
1330static ssize_t dv1394_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1331{
1332 struct video_card *video = file_to_video_card(file);
1333 DECLARE_WAITQUEUE(wait, current);
1334 ssize_t ret;
1335 size_t cnt;
1336 unsigned long flags;
1337 int target_frame;
1338
1339 /* serialize this to prevent multi-threaded mayhem */
1340 if (file->f_flags & O_NONBLOCK) {
1341 if (!mutex_trylock(&video->mtx))
1342 return -EAGAIN;
1343 } else {
1344 if (mutex_lock_interruptible(&video->mtx))
1345 return -ERESTARTSYS;
1346 }
1347
1348 if ( !video_card_initialized(video) ) {
1349 ret = do_dv1394_init_default(video);
1350 if (ret) {
1351 mutex_unlock(&video->mtx);
1352 return ret;
1353 }
1354 }
1355
1356 ret = 0;
1357 add_wait_queue(&video->waitq, &wait);
1358
1359 while (count > 0) {
1360
1361 /* must set TASK_INTERRUPTIBLE *before* checking for free
1362 buffers; otherwise we could miss a wakeup if the interrupt
1363 fires between the check and the schedule() */
1364
1365 set_current_state(TASK_INTERRUPTIBLE);
1366
1367 spin_lock_irqsave(&video->spinlock, flags);
1368
1369 target_frame = video->first_clear_frame;
1370
1371 spin_unlock_irqrestore(&video->spinlock, flags);
1372
1373 if (video->frames[target_frame]->state == FRAME_CLEAR) {
1374
1375 /* how much room is left in the target frame buffer */
1376 cnt = video->frame_size - (video->write_off - target_frame * video->frame_size);
1377
1378 } else {
1379 /* buffer is already used */
1380 cnt = 0;
1381 }
1382
1383 if (cnt > count)
1384 cnt = count;
1385
1386 if (cnt <= 0) {
1387 /* no room left, gotta wait */
1388 if (file->f_flags & O_NONBLOCK) {
1389 if (!ret)
1390 ret = -EAGAIN;
1391 break;
1392 }
1393 if (signal_pending(current)) {
1394 if (!ret)
1395 ret = -ERESTARTSYS;
1396 break;
1397 }
1398
1399 schedule();
1400
1401 continue; /* start over from 'while(count > 0)...' */
1402 }
1403
1404 if (copy_from_user(video->dv_buf.kvirt + video->write_off, buffer, cnt)) {
1405 if (!ret)
1406 ret = -EFAULT;
1407 break;
1408 }
1409
1410 video->write_off = (video->write_off + cnt) % (video->n_frames * video->frame_size);
1411
1412 count -= cnt;
1413 buffer += cnt;
1414 ret += cnt;
1415
1416 if (video->write_off == video->frame_size * ((target_frame + 1) % video->n_frames))
1417 frame_prepare(video, target_frame);
1418 }
1419
1420 remove_wait_queue(&video->waitq, &wait);
1421 set_current_state(TASK_RUNNING);
1422 mutex_unlock(&video->mtx);
1423 return ret;
1424}
1425
1426
1427static ssize_t dv1394_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1428{
1429 struct video_card *video = file_to_video_card(file);
1430 DECLARE_WAITQUEUE(wait, current);
1431 ssize_t ret;
1432 size_t cnt;
1433 unsigned long flags;
1434 int target_frame;
1435
1436 /* serialize this to prevent multi-threaded mayhem */
1437 if (file->f_flags & O_NONBLOCK) {
1438 if (!mutex_trylock(&video->mtx))
1439 return -EAGAIN;
1440 } else {
1441 if (mutex_lock_interruptible(&video->mtx))
1442 return -ERESTARTSYS;
1443 }
1444
1445 if ( !video_card_initialized(video) ) {
1446 ret = do_dv1394_init_default(video);
1447 if (ret) {
1448 mutex_unlock(&video->mtx);
1449 return ret;
1450 }
1451 video->continuity_counter = -1;
1452
1453 receive_packets(video);
1454
1455 start_dma_receive(video);
1456 }
1457
1458 ret = 0;
1459 add_wait_queue(&video->waitq, &wait);
1460
1461 while (count > 0) {
1462
1463 /* must set TASK_INTERRUPTIBLE *before* checking for free
1464 buffers; otherwise we could miss a wakeup if the interrupt
1465 fires between the check and the schedule() */
1466
1467 set_current_state(TASK_INTERRUPTIBLE);
1468
1469 spin_lock_irqsave(&video->spinlock, flags);
1470
1471 target_frame = video->first_clear_frame;
1472
1473 spin_unlock_irqrestore(&video->spinlock, flags);
1474
1475 if (target_frame >= 0 &&
1476 video->n_clear_frames > 0 &&
1477 video->frames[target_frame]->state == FRAME_CLEAR) {
1478
1479 /* how much room is left in the target frame buffer */
1480 cnt = video->frame_size - (video->write_off - target_frame * video->frame_size);
1481
1482 } else {
1483 /* buffer is already used */
1484 cnt = 0;
1485 }
1486
1487 if (cnt > count)
1488 cnt = count;
1489
1490 if (cnt <= 0) {
1491 /* no room left, gotta wait */
1492 if (file->f_flags & O_NONBLOCK) {
1493 if (!ret)
1494 ret = -EAGAIN;
1495 break;
1496 }
1497 if (signal_pending(current)) {
1498 if (!ret)
1499 ret = -ERESTARTSYS;
1500 break;
1501 }
1502
1503 schedule();
1504
1505 continue; /* start over from 'while(count > 0)...' */
1506 }
1507
1508 if (copy_to_user(buffer, video->dv_buf.kvirt + video->write_off, cnt)) {
1509 if (!ret)
1510 ret = -EFAULT;
1511 break;
1512 }
1513
1514 video->write_off = (video->write_off + cnt) % (video->n_frames * video->frame_size);
1515
1516 count -= cnt;
1517 buffer += cnt;
1518 ret += cnt;
1519
1520 if (video->write_off == video->frame_size * ((target_frame + 1) % video->n_frames)) {
1521 spin_lock_irqsave(&video->spinlock, flags);
1522 video->n_clear_frames--;
1523 video->first_clear_frame = (video->first_clear_frame + 1) % video->n_frames;
1524 spin_unlock_irqrestore(&video->spinlock, flags);
1525 }
1526 }
1527
1528 remove_wait_queue(&video->waitq, &wait);
1529 set_current_state(TASK_RUNNING);
1530 mutex_unlock(&video->mtx);
1531 return ret;
1532}
1533
1534
1535/*** DEVICE IOCTL INTERFACE ************************************************/
1536
1537static long dv1394_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1538{
1539 struct video_card *video = file_to_video_card(file);
1540 unsigned long flags;
1541 int ret = -EINVAL;
1542 void __user *argp = (void __user *)arg;
1543
1544 DECLARE_WAITQUEUE(wait, current);
1545
1546 /* serialize this to prevent multi-threaded mayhem */
1547 if (file->f_flags & O_NONBLOCK) {
1548 if (!mutex_trylock(&video->mtx))
1549 return -EAGAIN;
1550 } else {
1551 if (mutex_lock_interruptible(&video->mtx))
1552 return -ERESTARTSYS;
1553 }
1554
1555 switch(cmd)
1556 {
1557 case DV1394_IOC_SUBMIT_FRAMES: {
1558 unsigned int n_submit;
1559
1560 if ( !video_card_initialized(video) ) {
1561 ret = do_dv1394_init_default(video);
1562 if (ret)
1563 goto out;
1564 }
1565
1566 n_submit = (unsigned int) arg;
1567
1568 if (n_submit > video->n_frames) {
1569 ret = -EINVAL;
1570 goto out;
1571 }
1572
1573 while (n_submit > 0) {
1574
1575 add_wait_queue(&video->waitq, &wait);
1576 set_current_state(TASK_INTERRUPTIBLE);
1577
1578 spin_lock_irqsave(&video->spinlock, flags);
1579
1580 /* wait until video->first_clear_frame is really CLEAR */
1581 while (video->frames[video->first_clear_frame]->state != FRAME_CLEAR) {
1582
1583 spin_unlock_irqrestore(&video->spinlock, flags);
1584
1585 if (signal_pending(current)) {
1586 remove_wait_queue(&video->waitq, &wait);
1587 set_current_state(TASK_RUNNING);
1588 ret = -EINTR;
1589 goto out;
1590 }
1591
1592 schedule();
1593 set_current_state(TASK_INTERRUPTIBLE);
1594
1595 spin_lock_irqsave(&video->spinlock, flags);
1596 }
1597 spin_unlock_irqrestore(&video->spinlock, flags);
1598
1599 remove_wait_queue(&video->waitq, &wait);
1600 set_current_state(TASK_RUNNING);
1601
1602 frame_prepare(video, video->first_clear_frame);
1603
1604 n_submit--;
1605 }
1606
1607 ret = 0;
1608 break;
1609 }
1610
1611 case DV1394_IOC_WAIT_FRAMES: {
1612 unsigned int n_wait;
1613
1614 if ( !video_card_initialized(video) ) {
1615 ret = -EINVAL;
1616 goto out;
1617 }
1618
1619 n_wait = (unsigned int) arg;
1620
1621 /* since we re-run the last frame on underflow, we will
1622 never actually have n_frames clear frames; at most only
1623 n_frames - 1 */
1624
1625 if (n_wait > (video->n_frames-1) ) {
1626 ret = -EINVAL;
1627 goto out;
1628 }
1629
1630 add_wait_queue(&video->waitq, &wait);
1631 set_current_state(TASK_INTERRUPTIBLE);
1632
1633 spin_lock_irqsave(&video->spinlock, flags);
1634
1635 while (video->n_clear_frames < n_wait) {
1636
1637 spin_unlock_irqrestore(&video->spinlock, flags);
1638
1639 if (signal_pending(current)) {
1640 remove_wait_queue(&video->waitq, &wait);
1641 set_current_state(TASK_RUNNING);
1642 ret = -EINTR;
1643 goto out;
1644 }
1645
1646 schedule();
1647 set_current_state(TASK_INTERRUPTIBLE);
1648
1649 spin_lock_irqsave(&video->spinlock, flags);
1650 }
1651
1652 spin_unlock_irqrestore(&video->spinlock, flags);
1653
1654 remove_wait_queue(&video->waitq, &wait);
1655 set_current_state(TASK_RUNNING);
1656 ret = 0;
1657 break;
1658 }
1659
1660 case DV1394_IOC_RECEIVE_FRAMES: {
1661 unsigned int n_recv;
1662
1663 if ( !video_card_initialized(video) ) {
1664 ret = -EINVAL;
1665 goto out;
1666 }
1667
1668 n_recv = (unsigned int) arg;
1669
1670 /* at least one frame must be active */
1671 if (n_recv > (video->n_frames-1) ) {
1672 ret = -EINVAL;
1673 goto out;
1674 }
1675
1676 spin_lock_irqsave(&video->spinlock, flags);
1677
1678 /* release the clear frames */
1679 video->n_clear_frames -= n_recv;
1680
1681 /* advance the clear frame cursor */
1682 video->first_clear_frame = (video->first_clear_frame + n_recv) % video->n_frames;
1683
1684 /* reset dropped_frames */
1685 video->dropped_frames = 0;
1686
1687 spin_unlock_irqrestore(&video->spinlock, flags);
1688
1689 ret = 0;
1690 break;
1691 }
1692
1693 case DV1394_IOC_START_RECEIVE: {
1694 if ( !video_card_initialized(video) ) {
1695 ret = do_dv1394_init_default(video);
1696 if (ret)
1697 goto out;
1698 }
1699
1700 video->continuity_counter = -1;
1701
1702 receive_packets(video);
1703
1704 start_dma_receive(video);
1705
1706 ret = 0;
1707 break;
1708 }
1709
1710 case DV1394_IOC_INIT: {
1711 struct dv1394_init init;
1712 if (!argp) {
1713 ret = do_dv1394_init_default(video);
1714 } else {
1715 if (copy_from_user(&init, argp, sizeof(init))) {
1716 ret = -EFAULT;
1717 goto out;
1718 }
1719 ret = do_dv1394_init(video, &init);
1720 }
1721 break;
1722 }
1723
1724 case DV1394_IOC_SHUTDOWN:
1725 do_dv1394_shutdown(video, 0);
1726 ret = 0;
1727 break;
1728
1729
1730 case DV1394_IOC_GET_STATUS: {
1731 struct dv1394_status status;
1732
1733 if ( !video_card_initialized(video) ) {
1734 ret = -EINVAL;
1735 goto out;
1736 }
1737
1738 status.init.api_version = DV1394_API_VERSION;
1739 status.init.channel = video->channel;
1740 status.init.n_frames = video->n_frames;
1741 status.init.format = video->pal_or_ntsc;
1742 status.init.cip_n = video->cip_n;
1743 status.init.cip_d = video->cip_d;
1744 status.init.syt_offset = video->syt_offset;
1745
1746 status.first_clear_frame = video->first_clear_frame;
1747
1748 /* the rest of the fields need to be locked against the interrupt */
1749 spin_lock_irqsave(&video->spinlock, flags);
1750
1751 status.active_frame = video->active_frame;
1752 status.n_clear_frames = video->n_clear_frames;
1753
1754 status.dropped_frames = video->dropped_frames;
1755
1756 /* reset dropped_frames */
1757 video->dropped_frames = 0;
1758
1759 spin_unlock_irqrestore(&video->spinlock, flags);
1760
1761 if (copy_to_user(argp, &status, sizeof(status))) {
1762 ret = -EFAULT;
1763 goto out;
1764 }
1765
1766 ret = 0;
1767 break;
1768 }
1769
1770 default:
1771 break;
1772 }
1773
1774 out:
1775 mutex_unlock(&video->mtx);
1776 return ret;
1777}
1778
1779/*** DEVICE FILE INTERFACE CONTINUED ***************************************/
1780
1781static int dv1394_open(struct inode *inode, struct file *file)
1782{
1783 struct video_card *video = NULL;
1784
1785 if (file->private_data) {
1786 video = file->private_data;
1787
1788 } else {
1789 /* look up the card by ID */
1790 unsigned long flags;
1791 int idx = ieee1394_file_to_instance(file);
1792
1793 spin_lock_irqsave(&dv1394_cards_lock, flags);
1794 if (!list_empty(&dv1394_cards)) {
1795 struct video_card *p;
1796 list_for_each_entry(p, &dv1394_cards, list) {
1797 if ((p->id) == idx) {
1798 video = p;
1799 break;
1800 }
1801 }
1802 }
1803 spin_unlock_irqrestore(&dv1394_cards_lock, flags);
1804
1805 if (!video) {
1806 debug_printk("dv1394: OHCI card %d not found", idx);
1807 return -ENODEV;
1808 }
1809
1810 file->private_data = (void*) video;
1811 }
1812
1813#ifndef DV1394_ALLOW_MORE_THAN_ONE_OPEN
1814
1815 if ( test_and_set_bit(0, &video->open) ) {
1816 /* video is already open by someone else */
1817 return -EBUSY;
1818 }
1819
1820#endif
1821
1822 printk(KERN_INFO "%s: NOTE, the dv1394 interface is unsupported "
1823 "and will not be available in the new firewire driver stack. "
1824 "Try libraw1394 based programs instead.\n", current->comm);
1825
1826 return nonseekable_open(inode, file);
1827}
1828
1829
1830static int dv1394_release(struct inode *inode, struct file *file)
1831{
1832 struct video_card *video = file_to_video_card(file);
1833
1834 /* OK to free the DMA buffer, no more mappings can exist */
1835 do_dv1394_shutdown(video, 1);
1836
1837 /* give someone else a turn */
1838 clear_bit(0, &video->open);
1839
1840 return 0;
1841}
1842
1843
1844/*** DEVICE DRIVER HANDLERS ************************************************/
1845
1846static void it_tasklet_func(unsigned long data)
1847{
1848 int wake = 0;
1849 struct video_card *video = (struct video_card*) data;
1850
1851 spin_lock(&video->spinlock);
1852
1853 if (!video->dma_running)
1854 goto out;
1855
1856 irq_printk("ContextControl = %08x, CommandPtr = %08x\n",
1857 reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
1858 reg_read(video->ohci, video->ohci_IsoXmitCommandPtr)
1859 );
1860
1861
1862 if ( (video->ohci_it_ctx != -1) &&
1863 (reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) & (1 << 10)) ) {
1864
1865 struct frame *f;
1866 unsigned int frame, i;
1867
1868
1869 if (video->active_frame == -1)
1870 frame = 0;
1871 else
1872 frame = video->active_frame;
1873
1874 /* check all the DMA-able frames */
1875 for (i = 0; i < video->n_frames; i++, frame = (frame+1) % video->n_frames) {
1876
1877 irq_printk("IRQ checking frame %d...", frame);
1878 f = video->frames[frame];
1879 if (f->state != FRAME_READY) {
1880 irq_printk("clear, skipping\n");
1881 /* we don't own this frame */
1882 continue;
1883 }
1884
1885 irq_printk("DMA\n");
1886
1887 /* check the frame begin semaphore to see if we can free the previous frame */
1888 if ( *(f->frame_begin_timestamp) ) {
1889 int prev_frame;
1890 struct frame *prev_f;
1891
1892
1893
1894 /* don't reset, need this later *(f->frame_begin_timestamp) = 0; */
1895 irq_printk(" BEGIN\n");
1896
1897 prev_frame = frame - 1;
1898 if (prev_frame == -1)
1899 prev_frame += video->n_frames;
1900 prev_f = video->frames[prev_frame];
1901
1902 /* make sure we can actually garbage collect
1903 this frame */
1904 if ( (prev_f->state == FRAME_READY) &&
1905 prev_f->done && (!f->done) )
1906 {
1907 frame_reset(prev_f);
1908 video->n_clear_frames++;
1909 wake = 1;
1910 video->active_frame = frame;
1911
1912 irq_printk(" BEGIN - freeing previous frame %d, new active frame is %d\n", prev_frame, frame);
1913 } else {
1914 irq_printk(" BEGIN - can't free yet\n");
1915 }
1916
1917 f->done = 1;
1918 }
1919
1920
1921 /* see if we need to set the timestamp for the next frame */
1922 if ( *(f->mid_frame_timestamp) ) {
1923 struct frame *next_frame;
1924 u32 begin_ts, ts_cyc, ts_off;
1925
1926 *(f->mid_frame_timestamp) = 0;
1927
1928 begin_ts = le32_to_cpu(*(f->frame_begin_timestamp));
1929
1930 irq_printk(" MIDDLE - first packet was sent at cycle %4u (%2u), assigned timestamp was (%2u) %4u\n",
1931 begin_ts & 0x1FFF, begin_ts & 0xF,
1932 f->assigned_timestamp >> 12, f->assigned_timestamp & 0xFFF);
1933
1934 /* prepare next frame and assign timestamp */
1935 next_frame = video->frames[ (frame+1) % video->n_frames ];
1936
1937 if (next_frame->state == FRAME_READY) {
1938 irq_printk(" MIDDLE - next frame is ready, good\n");
1939 } else {
1940 debug_printk("dv1394: Underflow! At least one frame has been dropped.\n");
1941 next_frame = f;
1942 }
1943
1944 /* set the timestamp to the timestamp of the last frame sent,
1945 plus the length of the last frame sent, plus the syt latency */
1946 ts_cyc = begin_ts & 0xF;
1947 /* advance one frame, plus syt latency (typically 2-3) */
1948 ts_cyc += f->n_packets + video->syt_offset ;
1949
1950 ts_off = 0;
1951
1952 ts_cyc += ts_off/3072;
1953 ts_off %= 3072;
1954
1955 next_frame->assigned_timestamp = ((ts_cyc&0xF) << 12) + ts_off;
1956 if (next_frame->cip_syt1) {
1957 next_frame->cip_syt1->b[6] = next_frame->assigned_timestamp >> 8;
1958 next_frame->cip_syt1->b[7] = next_frame->assigned_timestamp & 0xFF;
1959 }
1960 if (next_frame->cip_syt2) {
1961 next_frame->cip_syt2->b[6] = next_frame->assigned_timestamp >> 8;
1962 next_frame->cip_syt2->b[7] = next_frame->assigned_timestamp & 0xFF;
1963 }
1964
1965 }
1966
1967 /* see if the frame looped */
1968 if ( *(f->frame_end_timestamp) ) {
1969
1970 *(f->frame_end_timestamp) = 0;
1971
1972 debug_printk(" END - the frame looped at least once\n");
1973
1974 video->dropped_frames++;
1975 }
1976
1977 } /* for (each frame) */
1978 }
1979
1980 if (wake) {
1981 kill_fasync(&video->fasync, SIGIO, POLL_OUT);
1982
1983 /* wake readers/writers/ioctl'ers */
1984 wake_up_interruptible(&video->waitq);
1985 }
1986
1987out:
1988 spin_unlock(&video->spinlock);
1989}
1990
1991static void ir_tasklet_func(unsigned long data)
1992{
1993 int wake = 0;
1994 struct video_card *video = (struct video_card*) data;
1995
1996 spin_lock(&video->spinlock);
1997
1998 if (!video->dma_running)
1999 goto out;
2000
2001 if ( (video->ohci_ir_ctx != -1) &&
2002 (reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & (1 << 10)) ) {
2003
2004 int sof=0; /* start-of-frame flag */
2005 struct frame *f;
2006 u16 packet_length;
2007 int i, dbc=0;
2008 struct DMA_descriptor_block *block = NULL;
2009 u16 xferstatus;
2010
2011 int next_i, prev_i;
2012 struct DMA_descriptor_block *next = NULL;
2013 dma_addr_t next_dma = 0;
2014 struct DMA_descriptor_block *prev = NULL;
2015
2016 /* loop over all descriptors in all frames */
2017 for (i = 0; i < video->n_frames*MAX_PACKETS; i++) {
2018 struct packet *p = dma_region_i(&video->packet_buf, struct packet, video->current_packet);
2019
2020 /* make sure we are seeing the latest changes to p */
2021 dma_region_sync_for_cpu(&video->packet_buf,
2022 (unsigned long) p - (unsigned long) video->packet_buf.kvirt,
2023 sizeof(struct packet));
2024
2025 packet_length = le16_to_cpu(p->data_length);
2026
2027 /* get the descriptor based on packet_buffer cursor */
2028 f = video->frames[video->current_packet / MAX_PACKETS];
2029 block = &(f->descriptor_pool[video->current_packet % MAX_PACKETS]);
2030 xferstatus = le32_to_cpu(block->u.in.il.q[3]) >> 16;
2031 xferstatus &= 0x1F;
2032 irq_printk("ir_tasklet_func: xferStatus/resCount [%d] = 0x%08x\n", i, le32_to_cpu(block->u.in.il.q[3]) );
2033
2034 /* get the current frame */
2035 f = video->frames[video->active_frame];
2036
2037 /* exclude empty packet */
2038 if (packet_length > 8 && xferstatus == 0x11) {
2039 /* check for start of frame */
2040 /* DRD> Changed to check section type ([0]>>5==0)
2041 and dif sequence ([1]>>4==0) */
2042 sof = ( (p->data[0] >> 5) == 0 && (p->data[1] >> 4) == 0);
2043
2044 dbc = (int) (p->cip_h1 >> 24);
2045 if ( video->continuity_counter != -1 && dbc > ((video->continuity_counter + 1) % 256) )
2046 {
2047 printk(KERN_WARNING "dv1394: discontinuity detected, dropping all frames\n" );
2048 video->dropped_frames += video->n_clear_frames + 1;
2049 video->first_frame = 0;
2050 video->n_clear_frames = 0;
2051 video->first_clear_frame = -1;
2052 }
2053 video->continuity_counter = dbc;
2054
2055 if (!video->first_frame) {
2056 if (sof) {
2057 video->first_frame = 1;
2058 }
2059
2060 } else if (sof) {
2061 /* close current frame */
2062 frame_reset(f); /* f->state = STATE_CLEAR */
2063 video->n_clear_frames++;
2064 if (video->n_clear_frames > video->n_frames) {
2065 video->dropped_frames++;
2066 printk(KERN_WARNING "dv1394: dropped a frame during reception\n" );
2067 video->n_clear_frames = video->n_frames-1;
2068 video->first_clear_frame = (video->first_clear_frame + 1) % video->n_frames;
2069 }
2070 if (video->first_clear_frame == -1)
2071 video->first_clear_frame = video->active_frame;
2072
2073 /* get the next frame */
2074 video->active_frame = (video->active_frame + 1) % video->n_frames;
2075 f = video->frames[video->active_frame];
2076 irq_printk(" frame received, active_frame = %d, n_clear_frames = %d, first_clear_frame = %d\n",
2077 video->active_frame, video->n_clear_frames, video->first_clear_frame);
2078 }
2079 if (video->first_frame) {
2080 if (sof) {
2081 /* open next frame */
2082 f->state = FRAME_READY;
2083 }
2084
2085 /* copy to buffer */
2086 if (f->n_packets > (video->frame_size / 480)) {
2087 printk(KERN_ERR "frame buffer overflow during receive\n");
2088 }
2089
2090 frame_put_packet(f, p);
2091
2092 } /* first_frame */
2093 }
2094
2095 /* stop, end of ready packets */
2096 else if (xferstatus == 0) {
2097 break;
2098 }
2099
2100 /* reset xferStatus & resCount */
2101 block->u.in.il.q[3] = cpu_to_le32(512);
2102
2103 /* terminate dma chain at this (next) packet */
2104 next_i = video->current_packet;
2105 f = video->frames[next_i / MAX_PACKETS];
2106 next = &(f->descriptor_pool[next_i % MAX_PACKETS]);
2107 next_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma;
2108 next->u.in.il.q[0] |= cpu_to_le32(3 << 20); /* enable interrupt */
2109 next->u.in.il.q[2] = cpu_to_le32(0); /* disable branch */
2110
2111 /* link previous to next */
2112 prev_i = (next_i == 0) ? (MAX_PACKETS * video->n_frames - 1) : (next_i - 1);
2113 f = video->frames[prev_i / MAX_PACKETS];
2114 prev = &(f->descriptor_pool[prev_i % MAX_PACKETS]);
2115 if (prev_i % (MAX_PACKETS/2)) {
2116 prev->u.in.il.q[0] &= ~cpu_to_le32(3 << 20); /* no interrupt */
2117 } else {
2118 prev->u.in.il.q[0] |= cpu_to_le32(3 << 20); /* enable interrupt */
2119 }
2120 prev->u.in.il.q[2] = cpu_to_le32(next_dma | 1); /* set Z=1 */
2121 wmb();
2122
2123 /* wake up DMA in case it fell asleep */
2124 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 12));
2125
2126 /* advance packet_buffer cursor */
2127 video->current_packet = (video->current_packet + 1) % (MAX_PACKETS * video->n_frames);
2128
2129 } /* for all packets */
2130
2131 wake = 1; /* why the hell not? */
2132
2133 } /* receive interrupt */
2134
2135 if (wake) {
2136 kill_fasync(&video->fasync, SIGIO, POLL_IN);
2137
2138 /* wake readers/writers/ioctl'ers */
2139 wake_up_interruptible(&video->waitq);
2140 }
2141
2142out:
2143 spin_unlock(&video->spinlock);
2144}
2145
2146static struct cdev dv1394_cdev;
2147static const struct file_operations dv1394_fops=
2148{
2149 .owner = THIS_MODULE,
2150 .poll = dv1394_poll,
2151 .unlocked_ioctl = dv1394_ioctl,
2152#ifdef CONFIG_COMPAT
2153 .compat_ioctl = dv1394_compat_ioctl,
2154#endif
2155 .mmap = dv1394_mmap,
2156 .open = dv1394_open,
2157 .write = dv1394_write,
2158 .read = dv1394_read,
2159 .release = dv1394_release,
2160 .fasync = dv1394_fasync,
2161 .llseek = no_llseek,
2162};
2163
2164
2165/*** HOTPLUG STUFF **********************************************************/
2166/*
2167 * Export information about protocols/devices supported by this driver.
2168 */
2169#ifdef MODULE
2170static const struct ieee1394_device_id dv1394_id_table[] = {
2171 {
2172 .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
2173 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY & 0xffffff,
2174 .version = AVC_SW_VERSION_ENTRY & 0xffffff
2175 },
2176 { }
2177};
2178
2179MODULE_DEVICE_TABLE(ieee1394, dv1394_id_table);
2180#endif /* MODULE */
2181
2182static struct hpsb_protocol_driver dv1394_driver = {
2183 .name = "dv1394",
2184};
2185
2186
2187/*** IEEE1394 HPSB CALLBACKS ***********************************************/
2188
2189static int dv1394_init(struct ti_ohci *ohci, enum pal_or_ntsc format, enum modes mode)
2190{
2191 struct video_card *video;
2192 unsigned long flags;
2193 int i;
2194
2195 video = kzalloc(sizeof(*video), GFP_KERNEL);
2196 if (!video) {
2197 printk(KERN_ERR "dv1394: cannot allocate video_card\n");
2198 return -1;
2199 }
2200
2201 video->ohci = ohci;
2202 /* lower 2 bits of id indicate which of four "plugs"
2203 per host */
2204 video->id = ohci->host->id << 2;
2205 if (format == DV1394_NTSC)
2206 video->id |= mode;
2207 else
2208 video->id |= 2 + mode;
2209
2210 video->ohci_it_ctx = -1;
2211 video->ohci_ir_ctx = -1;
2212
2213 video->ohci_IsoXmitContextControlSet = 0;
2214 video->ohci_IsoXmitContextControlClear = 0;
2215 video->ohci_IsoXmitCommandPtr = 0;
2216
2217 video->ohci_IsoRcvContextControlSet = 0;
2218 video->ohci_IsoRcvContextControlClear = 0;
2219 video->ohci_IsoRcvCommandPtr = 0;
2220 video->ohci_IsoRcvContextMatch = 0;
2221
2222 video->n_frames = 0; /* flag that video is not initialized */
2223 video->channel = 63; /* default to broadcast channel */
2224 video->active_frame = -1;
2225
2226 /* initialize the following */
2227 video->pal_or_ntsc = format;
2228 video->cip_n = 0; /* 0 = use builtin default */
2229 video->cip_d = 0;
2230 video->syt_offset = 0;
2231 video->mode = mode;
2232
2233 for (i = 0; i < DV1394_MAX_FRAMES; i++)
2234 video->frames[i] = NULL;
2235
2236 dma_region_init(&video->dv_buf);
2237 video->dv_buf_size = 0;
2238 dma_region_init(&video->packet_buf);
2239 video->packet_buf_size = 0;
2240
2241 clear_bit(0, &video->open);
2242 spin_lock_init(&video->spinlock);
2243 video->dma_running = 0;
2244 mutex_init(&video->mtx);
2245 init_waitqueue_head(&video->waitq);
2246 video->fasync = NULL;
2247
2248 spin_lock_irqsave(&dv1394_cards_lock, flags);
2249 INIT_LIST_HEAD(&video->list);
2250 list_add_tail(&video->list, &dv1394_cards);
2251 spin_unlock_irqrestore(&dv1394_cards_lock, flags);
2252
2253 debug_printk("dv1394: dv1394_init() OK on ID %d\n", video->id);
2254 return 0;
2255}
2256
2257static void dv1394_remove_host(struct hpsb_host *host)
2258{
2259 struct video_card *video, *tmp_video;
2260 unsigned long flags;
2261 int found_ohci_card = 0;
2262
2263 do {
2264 video = NULL;
2265 spin_lock_irqsave(&dv1394_cards_lock, flags);
2266 list_for_each_entry(tmp_video, &dv1394_cards, list) {
2267 if ((tmp_video->id >> 2) == host->id) {
2268 list_del(&tmp_video->list);
2269 video = tmp_video;
2270 found_ohci_card = 1;
2271 break;
2272 }
2273 }
2274 spin_unlock_irqrestore(&dv1394_cards_lock, flags);
2275
2276 if (video) {
2277 do_dv1394_shutdown(video, 1);
2278 kfree(video);
2279 }
2280 } while (video);
2281
2282 if (found_ohci_card)
2283 device_destroy(hpsb_protocol_class, MKDEV(IEEE1394_MAJOR,
2284 IEEE1394_MINOR_BLOCK_DV1394 * 16 + (host->id << 2)));
2285}
2286
2287static void dv1394_add_host(struct hpsb_host *host)
2288{
2289 struct ti_ohci *ohci;
2290 int id = host->id;
2291
2292 /* We only work with the OHCI-1394 driver */
2293 if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
2294 return;
2295
2296 ohci = (struct ti_ohci *)host->hostdata;
2297
2298 device_create(hpsb_protocol_class, NULL,
2299 MKDEV(IEEE1394_MAJOR,
2300 IEEE1394_MINOR_BLOCK_DV1394 * 16 + (id<<2)),
2301 NULL, "dv1394-%d", id);
2302
2303 dv1394_init(ohci, DV1394_NTSC, MODE_RECEIVE);
2304 dv1394_init(ohci, DV1394_NTSC, MODE_TRANSMIT);
2305 dv1394_init(ohci, DV1394_PAL, MODE_RECEIVE);
2306 dv1394_init(ohci, DV1394_PAL, MODE_TRANSMIT);
2307}
2308
2309
2310/* Bus reset handler. In the event of a bus reset, we may need to
2311 re-start the DMA contexts - otherwise the user program would
2312 end up waiting forever.
2313*/
2314
2315static void dv1394_host_reset(struct hpsb_host *host)
2316{
2317 struct video_card *video = NULL, *tmp_vid;
2318 unsigned long flags;
2319
2320 /* We only work with the OHCI-1394 driver */
2321 if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
2322 return;
2323
2324 /* find the corresponding video_cards */
2325 spin_lock_irqsave(&dv1394_cards_lock, flags);
2326 list_for_each_entry(tmp_vid, &dv1394_cards, list) {
2327 if ((tmp_vid->id >> 2) == host->id) {
2328 video = tmp_vid;
2329 break;
2330 }
2331 }
2332 spin_unlock_irqrestore(&dv1394_cards_lock, flags);
2333
2334 if (!video)
2335 return;
2336
2337
2338 spin_lock_irqsave(&video->spinlock, flags);
2339
2340 if (!video->dma_running)
2341 goto out;
2342
2343 /* check IT context */
2344 if (video->ohci_it_ctx != -1) {
2345 u32 ctx;
2346
2347 ctx = reg_read(video->ohci, video->ohci_IsoXmitContextControlSet);
2348
2349 /* if (RUN but not ACTIVE) */
2350 if ( (ctx & (1<<15)) &&
2351 !(ctx & (1<<10)) ) {
2352
2353 debug_printk("dv1394: IT context stopped due to bus reset; waking it up\n");
2354
2355 /* to be safe, assume a frame has been dropped. User-space programs
2356 should handle this condition like an underflow. */
2357 video->dropped_frames++;
2358
2359 /* for some reason you must clear, then re-set the RUN bit to restart DMA */
2360
2361 /* clear RUN */
2362 reg_write(video->ohci, video->ohci_IsoXmitContextControlClear, (1 << 15));
2363 flush_pci_write(video->ohci);
2364
2365 /* set RUN */
2366 reg_write(video->ohci, video->ohci_IsoXmitContextControlSet, (1 << 15));
2367 flush_pci_write(video->ohci);
2368
2369 /* set the WAKE bit (just in case; this isn't strictly necessary) */
2370 reg_write(video->ohci, video->ohci_IsoXmitContextControlSet, (1 << 12));
2371 flush_pci_write(video->ohci);
2372
2373 irq_printk("dv1394: AFTER IT restart ctx 0x%08x ptr 0x%08x\n",
2374 reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
2375 reg_read(video->ohci, video->ohci_IsoXmitCommandPtr));
2376 }
2377 }
2378
2379 /* check IR context */
2380 if (video->ohci_ir_ctx != -1) {
2381 u32 ctx;
2382
2383 ctx = reg_read(video->ohci, video->ohci_IsoRcvContextControlSet);
2384
2385 /* if (RUN but not ACTIVE) */
2386 if ( (ctx & (1<<15)) &&
2387 !(ctx & (1<<10)) ) {
2388
2389 debug_printk("dv1394: IR context stopped due to bus reset; waking it up\n");
2390
2391 /* to be safe, assume a frame has been dropped. User-space programs
2392 should handle this condition like an overflow. */
2393 video->dropped_frames++;
2394
2395 /* for some reason you must clear, then re-set the RUN bit to restart DMA */
2396 /* XXX this doesn't work for me, I can't get IR DMA to restart :[ */
2397
2398 /* clear RUN */
2399 reg_write(video->ohci, video->ohci_IsoRcvContextControlClear, (1 << 15));
2400 flush_pci_write(video->ohci);
2401
2402 /* set RUN */
2403 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 15));
2404 flush_pci_write(video->ohci);
2405
2406 /* set the WAKE bit (just in case; this isn't strictly necessary) */
2407 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 12));
2408 flush_pci_write(video->ohci);
2409
2410 irq_printk("dv1394: AFTER IR restart ctx 0x%08x ptr 0x%08x\n",
2411 reg_read(video->ohci, video->ohci_IsoRcvContextControlSet),
2412 reg_read(video->ohci, video->ohci_IsoRcvCommandPtr));
2413 }
2414 }
2415
2416out:
2417 spin_unlock_irqrestore(&video->spinlock, flags);
2418
2419 /* wake readers/writers/ioctl'ers */
2420 wake_up_interruptible(&video->waitq);
2421}
2422
2423static struct hpsb_highlevel dv1394_highlevel = {
2424 .name = "dv1394",
2425 .add_host = dv1394_add_host,
2426 .remove_host = dv1394_remove_host,
2427 .host_reset = dv1394_host_reset,
2428};
2429
2430#ifdef CONFIG_COMPAT
2431
2432#define DV1394_IOC32_INIT _IOW('#', 0x06, struct dv1394_init32)
2433#define DV1394_IOC32_GET_STATUS _IOR('#', 0x0c, struct dv1394_status32)
2434
2435struct dv1394_init32 {
2436 u32 api_version;
2437 u32 channel;
2438 u32 n_frames;
2439 u32 format;
2440 u32 cip_n;
2441 u32 cip_d;
2442 u32 syt_offset;
2443};
2444
2445struct dv1394_status32 {
2446 struct dv1394_init32 init;
2447 s32 active_frame;
2448 u32 first_clear_frame;
2449 u32 n_clear_frames;
2450 u32 dropped_frames;
2451};
2452
2453/* RED-PEN: this should use compat_alloc_userspace instead */
2454
2455static int handle_dv1394_init(struct file *file, unsigned int cmd, unsigned long arg)
2456{
2457 struct dv1394_init32 dv32;
2458 struct dv1394_init dv;
2459 mm_segment_t old_fs;
2460 int ret;
2461
2462 if (file->f_op->unlocked_ioctl != dv1394_ioctl)
2463 return -EFAULT;
2464
2465 if (copy_from_user(&dv32, (void __user *)arg, sizeof(dv32)))
2466 return -EFAULT;
2467
2468 dv.api_version = dv32.api_version;
2469 dv.channel = dv32.channel;
2470 dv.n_frames = dv32.n_frames;
2471 dv.format = dv32.format;
2472 dv.cip_n = (unsigned long)dv32.cip_n;
2473 dv.cip_d = (unsigned long)dv32.cip_d;
2474 dv.syt_offset = dv32.syt_offset;
2475
2476 old_fs = get_fs();
2477 set_fs(KERNEL_DS);
2478 ret = dv1394_ioctl(file, DV1394_IOC_INIT, (unsigned long)&dv);
2479 set_fs(old_fs);
2480
2481 return ret;
2482}
2483
2484static int handle_dv1394_get_status(struct file *file, unsigned int cmd, unsigned long arg)
2485{
2486 struct dv1394_status32 dv32;
2487 struct dv1394_status dv;
2488 mm_segment_t old_fs;
2489 int ret;
2490
2491 if (file->f_op->unlocked_ioctl != dv1394_ioctl)
2492 return -EFAULT;
2493
2494 old_fs = get_fs();
2495 set_fs(KERNEL_DS);
2496 ret = dv1394_ioctl(file, DV1394_IOC_GET_STATUS, (unsigned long)&dv);
2497 set_fs(old_fs);
2498
2499 if (!ret) {
2500 dv32.init.api_version = dv.init.api_version;
2501 dv32.init.channel = dv.init.channel;
2502 dv32.init.n_frames = dv.init.n_frames;
2503 dv32.init.format = dv.init.format;
2504 dv32.init.cip_n = (u32)dv.init.cip_n;
2505 dv32.init.cip_d = (u32)dv.init.cip_d;
2506 dv32.init.syt_offset = dv.init.syt_offset;
2507 dv32.active_frame = dv.active_frame;
2508 dv32.first_clear_frame = dv.first_clear_frame;
2509 dv32.n_clear_frames = dv.n_clear_frames;
2510 dv32.dropped_frames = dv.dropped_frames;
2511
2512 if (copy_to_user((struct dv1394_status32 __user *)arg, &dv32, sizeof(dv32)))
2513 ret = -EFAULT;
2514 }
2515
2516 return ret;
2517}
2518
2519
2520
2521static long dv1394_compat_ioctl(struct file *file, unsigned int cmd,
2522 unsigned long arg)
2523{
2524 switch (cmd) {
2525 case DV1394_IOC_SHUTDOWN:
2526 case DV1394_IOC_SUBMIT_FRAMES:
2527 case DV1394_IOC_WAIT_FRAMES:
2528 case DV1394_IOC_RECEIVE_FRAMES:
2529 case DV1394_IOC_START_RECEIVE:
2530 return dv1394_ioctl(file, cmd, arg);
2531
2532 case DV1394_IOC32_INIT:
2533 return handle_dv1394_init(file, cmd, arg);
2534 case DV1394_IOC32_GET_STATUS:
2535 return handle_dv1394_get_status(file, cmd, arg);
2536 default:
2537 return -ENOIOCTLCMD;
2538 }
2539}
2540
2541#endif /* CONFIG_COMPAT */
2542
2543
2544/*** KERNEL MODULE HANDLERS ************************************************/
2545
2546MODULE_AUTHOR("Dan Maas <dmaas@dcine.com>, Dan Dennedy <dan@dennedy.org>");
2547MODULE_DESCRIPTION("driver for DV input/output on OHCI board");
2548MODULE_SUPPORTED_DEVICE("dv1394");
2549MODULE_LICENSE("GPL");
2550
2551static void __exit dv1394_exit_module(void)
2552{
2553 hpsb_unregister_protocol(&dv1394_driver);
2554 hpsb_unregister_highlevel(&dv1394_highlevel);
2555 cdev_del(&dv1394_cdev);
2556}
2557
2558static int __init dv1394_init_module(void)
2559{
2560 int ret;
2561
2562 cdev_init(&dv1394_cdev, &dv1394_fops);
2563 dv1394_cdev.owner = THIS_MODULE;
2564 ret = cdev_add(&dv1394_cdev, IEEE1394_DV1394_DEV, 16);
2565 if (ret) {
2566 printk(KERN_ERR "dv1394: unable to register character device\n");
2567 return ret;
2568 }
2569
2570 hpsb_register_highlevel(&dv1394_highlevel);
2571
2572 ret = hpsb_register_protocol(&dv1394_driver);
2573 if (ret) {
2574 printk(KERN_ERR "dv1394: failed to register protocol\n");
2575 hpsb_unregister_highlevel(&dv1394_highlevel);
2576 cdev_del(&dv1394_cdev);
2577 return ret;
2578 }
2579
2580 return 0;
2581}
2582
2583module_init(dv1394_init_module);
2584module_exit(dv1394_exit_module);
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 22:15:42 -0500