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-rw-r--r--drivers/ide/Kconfig34
-rw-r--r--drivers/ide/Makefile2
-rw-r--r--drivers/ide/arm/icside.c2
-rw-r--r--drivers/ide/arm/palm_bk3710.c1
-rw-r--r--drivers/ide/arm/rapide.c1
-rw-r--r--drivers/ide/cris/Makefile3
-rw-r--r--drivers/ide/cris/ide-cris.c1086
-rw-r--r--drivers/ide/h8300/ide-h8300.c108
-rw-r--r--drivers/ide/ide-cd.c32
-rw-r--r--drivers/ide/ide-dma.c11
-rw-r--r--drivers/ide/ide-floppy.c27
-rw-r--r--drivers/ide/ide-io.c68
-rw-r--r--drivers/ide/ide-iops.c344
-rw-r--r--drivers/ide/ide-lib.c2
-rw-r--r--drivers/ide/ide-probe.c8
-rw-r--r--drivers/ide/ide-tape.c19
-rw-r--r--drivers/ide/ide-taskfile.c70
-rw-r--r--drivers/ide/legacy/falconide.c26
-rw-r--r--drivers/ide/legacy/ide_platform.c4
-rw-r--r--drivers/ide/legacy/q40ide.c24
-rw-r--r--drivers/ide/mips/au1xxx-ide.c17
-rw-r--r--drivers/ide/mips/swarm.c1
-rw-r--r--drivers/ide/pci/ns87415.c44
-rw-r--r--drivers/ide/pci/pdc202xx_new.c8
-rw-r--r--drivers/ide/pci/piix.c1
-rw-r--r--drivers/ide/pci/scc_pata.c196
-rw-r--r--drivers/ide/pci/sgiioc4.c1
-rw-r--r--drivers/ide/pci/siimage.c539
-rw-r--r--drivers/ide/ppc/pmac.c1
29 files changed, 927 insertions, 1753 deletions
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 3f9e10001e19..f702f9152ce6 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -862,40 +862,6 @@ config BLK_DEV_IDE_BAST
862 Say Y here if you want to support the onboard IDE channels on the 862 Say Y here if you want to support the onboard IDE channels on the
863 Simtec BAST or the Thorcom VR1000 863 Simtec BAST or the Thorcom VR1000
864 864
865config ETRAX_IDE
866 tristate "ETRAX IDE support"
867 depends on CRIS && BROKEN
868 select BLK_DEV_IDEDMA
869 help
870 Enables the ETRAX IDE driver.
871
872 You can't use parallel ports or SCSI ports at the same time.
873
874config ETRAX_IDE_DELAY
875 int "Delay for drives to regain consciousness"
876 depends on ETRAX_IDE && ETRAX_ARCH_V10
877 default 15
878 help
879 Number of seconds to wait for IDE drives to spin up after an IDE
880 reset.
881
882choice
883 prompt "IDE reset pin"
884 depends on ETRAX_IDE && ETRAX_ARCH_V10
885 default ETRAX_IDE_PB7_RESET
886
887config ETRAX_IDE_PB7_RESET
888 bool "Port_PB_Bit_7"
889 help
890 IDE reset on pin 7 on port B
891
892config ETRAX_IDE_G27_RESET
893 bool "Port_G_Bit_27"
894 help
895 IDE reset on pin 27 on port G
896
897endchoice
898
899config IDE_H8300 865config IDE_H8300
900 tristate "H8300 IDE support" 866 tristate "H8300 IDE support"
901 depends on H8300 867 depends on H8300
diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile
index 571544c37bb2..f94b679b611e 100644
--- a/drivers/ide/Makefile
+++ b/drivers/ide/Makefile
@@ -35,7 +35,7 @@ ifeq ($(CONFIG_BLK_DEV_CMD640), y)
35 obj-y += cmd640-core.o 35 obj-y += cmd640-core.o
36endif 36endif
37 37
38obj-$(CONFIG_BLK_DEV_IDE) += cris/ ppc/ 38obj-$(CONFIG_BLK_DEV_IDE) += ppc/
39obj-$(CONFIG_IDE_H8300) += h8300/ 39obj-$(CONFIG_IDE_H8300) += h8300/
40obj-$(CONFIG_IDE_GENERIC) += ide-generic.o 40obj-$(CONFIG_IDE_GENERIC) += ide-generic.o
41obj-$(CONFIG_BLK_DEV_IDEPNP) += ide-pnp.o 41obj-$(CONFIG_BLK_DEV_IDEPNP) += ide-pnp.o
diff --git a/drivers/ide/arm/icside.c b/drivers/ide/arm/icside.c
index 65038ca35e10..061456914ca3 100644
--- a/drivers/ide/arm/icside.c
+++ b/drivers/ide/arm/icside.c
@@ -483,7 +483,7 @@ static const struct ide_port_info icside_v6_port_info __initdata = {
483 .init_dma = icside_dma_off_init, 483 .init_dma = icside_dma_off_init,
484 .port_ops = &icside_v6_no_dma_port_ops, 484 .port_ops = &icside_v6_no_dma_port_ops,
485 .dma_ops = &icside_v6_dma_ops, 485 .dma_ops = &icside_v6_dma_ops,
486 .host_flags = IDE_HFLAG_SERIALIZE, 486 .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
487 .mwdma_mask = ATA_MWDMA2, 487 .mwdma_mask = ATA_MWDMA2,
488 .swdma_mask = ATA_SWDMA2, 488 .swdma_mask = ATA_SWDMA2,
489}; 489};
diff --git a/drivers/ide/arm/palm_bk3710.c b/drivers/ide/arm/palm_bk3710.c
index aaf32541622d..96378ebfb31f 100644
--- a/drivers/ide/arm/palm_bk3710.c
+++ b/drivers/ide/arm/palm_bk3710.c
@@ -342,6 +342,7 @@ static const struct ide_port_ops palm_bk3710_ports_ops = {
342static const struct ide_port_info __devinitdata palm_bk3710_port_info = { 342static const struct ide_port_info __devinitdata palm_bk3710_port_info = {
343 .init_dma = palm_bk3710_init_dma, 343 .init_dma = palm_bk3710_init_dma,
344 .port_ops = &palm_bk3710_ports_ops, 344 .port_ops = &palm_bk3710_ports_ops,
345 .host_flags = IDE_HFLAG_MMIO,
345 .pio_mask = ATA_PIO4, 346 .pio_mask = ATA_PIO4,
346 .udma_mask = ATA_UDMA4, /* (input clk 99MHz) */ 347 .udma_mask = ATA_UDMA4, /* (input clk 99MHz) */
347 .mwdma_mask = ATA_MWDMA2, 348 .mwdma_mask = ATA_MWDMA2,
diff --git a/drivers/ide/arm/rapide.c b/drivers/ide/arm/rapide.c
index babc1a5e128d..1747b2358775 100644
--- a/drivers/ide/arm/rapide.c
+++ b/drivers/ide/arm/rapide.c
@@ -53,6 +53,7 @@ rapide_probe(struct expansion_card *ec, const struct ecard_id *id)
53 53
54 ide_init_port_hw(hwif, &hw); 54 ide_init_port_hw(hwif, &hw);
55 55
56 hwif->host_flags = IDE_HFLAG_MMIO;
56 default_hwif_mmiops(hwif); 57 default_hwif_mmiops(hwif);
57 58
58 idx[0] = hwif->index; 59 idx[0] = hwif->index;
diff --git a/drivers/ide/cris/Makefile b/drivers/ide/cris/Makefile
deleted file mode 100644
index 20b95960531f..000000000000
--- a/drivers/ide/cris/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
1EXTRA_CFLAGS += -Idrivers/ide
2
3obj-$(CONFIG_IDE_ETRAX) += ide-cris.o
diff --git a/drivers/ide/cris/ide-cris.c b/drivers/ide/cris/ide-cris.c
deleted file mode 100644
index 9df26855bc05..000000000000
--- a/drivers/ide/cris/ide-cris.c
+++ /dev/null
@@ -1,1086 +0,0 @@
1/*
2 * Etrax specific IDE functions, like init and PIO-mode setting etc.
3 * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
4 * Copyright (c) 2000-2005 Axis Communications AB
5 *
6 * Authors: Bjorn Wesen (initial version)
7 * Mikael Starvik (crisv32 port)
8 */
9
10/* Regarding DMA:
11 *
12 * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
13 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
14 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
15 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
16 * device can't do DMA handshaking for some stupid reason. We don't need to do that.
17 */
18
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/timer.h>
22#include <linux/mm.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/blkdev.h>
26#include <linux/hdreg.h>
27#include <linux/ide.h>
28#include <linux/init.h>
29
30#include <asm/io.h>
31#include <asm/dma.h>
32
33/* number of DMA descriptors */
34#define MAX_DMA_DESCRS 64
35
36/* number of times to retry busy-flags when reading/writing IDE-registers
37 * this can't be too high because a hung harddisk might cause the watchdog
38 * to trigger (sometimes INB and OUTB are called with irq's disabled)
39 */
40
41#define IDE_REGISTER_TIMEOUT 300
42
43#define LOWDB(x)
44#define D(x)
45
46enum /* Transfer types */
47{
48 TYPE_PIO,
49 TYPE_DMA,
50 TYPE_UDMA
51};
52
53/* CRISv32 specifics */
54#ifdef CONFIG_ETRAX_ARCH_V32
55#include <asm/arch/hwregs/ata_defs.h>
56#include <asm/arch/hwregs/dma_defs.h>
57#include <asm/arch/hwregs/dma.h>
58#include <asm/arch/pinmux.h>
59
60#define ATA_UDMA2_CYC 2
61#define ATA_UDMA2_DVS 3
62#define ATA_UDMA1_CYC 2
63#define ATA_UDMA1_DVS 4
64#define ATA_UDMA0_CYC 4
65#define ATA_UDMA0_DVS 6
66#define ATA_DMA2_STROBE 7
67#define ATA_DMA2_HOLD 1
68#define ATA_DMA1_STROBE 8
69#define ATA_DMA1_HOLD 3
70#define ATA_DMA0_STROBE 25
71#define ATA_DMA0_HOLD 19
72#define ATA_PIO4_SETUP 3
73#define ATA_PIO4_STROBE 7
74#define ATA_PIO4_HOLD 1
75#define ATA_PIO3_SETUP 3
76#define ATA_PIO3_STROBE 9
77#define ATA_PIO3_HOLD 3
78#define ATA_PIO2_SETUP 3
79#define ATA_PIO2_STROBE 13
80#define ATA_PIO2_HOLD 5
81#define ATA_PIO1_SETUP 5
82#define ATA_PIO1_STROBE 23
83#define ATA_PIO1_HOLD 9
84#define ATA_PIO0_SETUP 9
85#define ATA_PIO0_STROBE 39
86#define ATA_PIO0_HOLD 9
87
88int
89cris_ide_ack_intr(ide_hwif_t* hwif)
90{
91 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
92 hwif->io_ports.data_addr);
93 REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
94 return 1;
95}
96
97static inline int
98cris_ide_busy(void)
99{
100 reg_ata_rs_stat_data stat_data;
101 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
102 return stat_data.busy;
103}
104
105static inline int
106cris_ide_ready(void)
107{
108 return !cris_ide_busy();
109}
110
111static inline int
112cris_ide_data_available(unsigned short* data)
113{
114 reg_ata_rs_stat_data stat_data;
115 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
116 *data = stat_data.data;
117 return stat_data.dav;
118}
119
120static void
121cris_ide_write_command(unsigned long command)
122{
123 REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */
124}
125
126static void
127cris_ide_set_speed(int type, int setup, int strobe, int hold)
128{
129 reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0);
130 reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1);
131
132 if (type == TYPE_PIO) {
133 ctrl0.pio_setup = setup;
134 ctrl0.pio_strb = strobe;
135 ctrl0.pio_hold = hold;
136 } else if (type == TYPE_DMA) {
137 ctrl0.dma_strb = strobe;
138 ctrl0.dma_hold = hold;
139 } else if (type == TYPE_UDMA) {
140 ctrl1.udma_tcyc = setup;
141 ctrl1.udma_tdvs = strobe;
142 }
143 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
144 REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
145}
146
147static unsigned long
148cris_ide_base_address(int bus)
149{
150 reg_ata_rw_ctrl2 ctrl2 = {0};
151 ctrl2.sel = bus;
152 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
153}
154
155static unsigned long
156cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
157{
158 reg_ata_rw_ctrl2 ctrl2 = {0};
159 ctrl2.addr = addr;
160 ctrl2.cs1 = cs1;
161 ctrl2.cs0 = cs0;
162 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
163}
164
165static __init void
166cris_ide_reset(unsigned val)
167{
168 reg_ata_rw_ctrl0 ctrl0 = {0};
169 ctrl0.rst = val ? regk_ata_active : regk_ata_inactive;
170 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
171}
172
173static __init void
174cris_ide_init(void)
175{
176 reg_ata_rw_ctrl0 ctrl0 = {0};
177 reg_ata_rw_intr_mask intr_mask = {0};
178
179 ctrl0.en = regk_ata_yes;
180 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
181
182 intr_mask.bus0 = regk_ata_yes;
183 intr_mask.bus1 = regk_ata_yes;
184 intr_mask.bus2 = regk_ata_yes;
185 intr_mask.bus3 = regk_ata_yes;
186
187 REG_WR(ata, regi_ata, rw_intr_mask, intr_mask);
188
189 crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
190 crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
191
192 crisv32_pinmux_alloc_fixed(pinmux_ata);
193 crisv32_pinmux_alloc_fixed(pinmux_ata0);
194 crisv32_pinmux_alloc_fixed(pinmux_ata1);
195 crisv32_pinmux_alloc_fixed(pinmux_ata2);
196 crisv32_pinmux_alloc_fixed(pinmux_ata3);
197
198 DMA_RESET(regi_dma2);
199 DMA_ENABLE(regi_dma2);
200 DMA_RESET(regi_dma3);
201 DMA_ENABLE(regi_dma3);
202
203 DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2);
204 DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2);
205}
206
207static dma_descr_context mycontext __attribute__ ((__aligned__(32)));
208
209#define cris_dma_descr_type dma_descr_data
210#define cris_pio_read regk_ata_rd
211#define cris_ultra_mask 0x7
212#define MAX_DESCR_SIZE 0xffffffffUL
213
214static unsigned long
215cris_ide_get_reg(unsigned long reg)
216{
217 return (reg & 0x0e000000) >> 25;
218}
219
220static void
221cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
222{
223 d->buf = (char*)virt_to_phys(buf);
224 d->after = d->buf + len;
225 d->eol = last;
226}
227
228static void
229cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len)
230{
231 ide_hwif_t *hwif = drive->hwif;
232
233 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
234 hwif->io_ports.data_addr);
235 reg_ata_rw_trf_cnt trf_cnt = {0};
236
237 mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
238 mycontext.saved_data_buf = d->buf;
239 /* start the dma channel */
240 DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext));
241
242 /* initiate a multi word dma read using PIO handshaking */
243 trf_cnt.cnt = len >> 1;
244 /* Due to a "feature" the transfer count has to be one extra word for UDMA. */
245 if (type == TYPE_UDMA)
246 trf_cnt.cnt++;
247 REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
248
249 ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr;
250 ctrl2.trf_mode = regk_ata_dma;
251 ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio :
252 type == TYPE_DMA ? regk_ata_dma : regk_ata_udma;
253 ctrl2.multi = regk_ata_yes;
254 ctrl2.dma_size = regk_ata_word;
255 REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
256}
257
258static void
259cris_ide_wait_dma(int dir)
260{
261 reg_dma_rw_stat status;
262 do
263 {
264 status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat);
265 } while(status.list_state != regk_dma_data_at_eol);
266}
267
268static int cris_dma_test_irq(ide_drive_t *drive)
269{
270 ide_hwif_t *hwif = drive->hwif;
271 int intr = REG_RD_INT(ata, regi_ata, r_intr);
272
273 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
274 hwif->io_ports.data_addr);
275
276 return intr & (1 << ctrl2.sel) ? 1 : 0;
277}
278
279static void cris_ide_initialize_dma(int dir)
280{
281}
282
283#else
284/* CRISv10 specifics */
285#include <asm/arch/svinto.h>
286#include <asm/arch/io_interface_mux.h>
287
288/* PIO timing (in R_ATA_CONFIG)
289 *
290 * _____________________________
291 * ADDRESS : ________/
292 *
293 * _______________
294 * DIOR : ____________/ \__________
295 *
296 * _______________
297 * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX
298 *
299 *
300 * DIOR is unbuffered while address and data is buffered.
301 * This creates two problems:
302 * 1. The DIOR pulse is to early (because it is unbuffered)
303 * 2. The rise time of DIOR is long
304 *
305 * There are at least three different plausible solutions
306 * 1. Use a pad capable of larger currents in Etrax
307 * 2. Use an external buffer
308 * 3. Make the strobe pulse longer
309 *
310 * Some of the strobe timings below are modified to compensate
311 * for this. This implies a slight performance decrease.
312 *
313 * THIS SHOULD NEVER BE CHANGED!
314 *
315 * TODO: Is this true for the latest LX boards still ?
316 */
317
318#define ATA_UDMA2_CYC 0 /* No UDMA supported, just to make it compile. */
319#define ATA_UDMA2_DVS 0
320#define ATA_UDMA1_CYC 0
321#define ATA_UDMA1_DVS 0
322#define ATA_UDMA0_CYC 0
323#define ATA_UDMA0_DVS 0
324#define ATA_DMA2_STROBE 4
325#define ATA_DMA2_HOLD 0
326#define ATA_DMA1_STROBE 4
327#define ATA_DMA1_HOLD 1
328#define ATA_DMA0_STROBE 12
329#define ATA_DMA0_HOLD 9
330#define ATA_PIO4_SETUP 1
331#define ATA_PIO4_STROBE 5
332#define ATA_PIO4_HOLD 0
333#define ATA_PIO3_SETUP 1
334#define ATA_PIO3_STROBE 5
335#define ATA_PIO3_HOLD 1
336#define ATA_PIO2_SETUP 1
337#define ATA_PIO2_STROBE 6
338#define ATA_PIO2_HOLD 2
339#define ATA_PIO1_SETUP 2
340#define ATA_PIO1_STROBE 11
341#define ATA_PIO1_HOLD 4
342#define ATA_PIO0_SETUP 4
343#define ATA_PIO0_STROBE 19
344#define ATA_PIO0_HOLD 4
345
346int
347cris_ide_ack_intr(ide_hwif_t* hwif)
348{
349 return 1;
350}
351
352static inline int
353cris_ide_busy(void)
354{
355 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ;
356}
357
358static inline int
359cris_ide_ready(void)
360{
361 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy) ;
362}
363
364static inline int
365cris_ide_data_available(unsigned short* data)
366{
367 unsigned long status = *R_ATA_STATUS_DATA;
368 *data = (unsigned short)status;
369 return status & IO_MASK(R_ATA_STATUS_DATA, dav);
370}
371
372static void
373cris_ide_write_command(unsigned long command)
374{
375 *R_ATA_CTRL_DATA = command;
376}
377
378static void
379cris_ide_set_speed(int type, int setup, int strobe, int hold)
380{
381 static int pio_setup = ATA_PIO4_SETUP;
382 static int pio_strobe = ATA_PIO4_STROBE;
383 static int pio_hold = ATA_PIO4_HOLD;
384 static int dma_strobe = ATA_DMA2_STROBE;
385 static int dma_hold = ATA_DMA2_HOLD;
386
387 if (type == TYPE_PIO) {
388 pio_setup = setup;
389 pio_strobe = strobe;
390 pio_hold = hold;
391 } else if (type == TYPE_DMA) {
392 dma_strobe = strobe;
393 dma_hold = hold;
394 }
395 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
396 IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) |
397 IO_FIELD( R_ATA_CONFIG, dma_hold, dma_hold ) |
398 IO_FIELD( R_ATA_CONFIG, pio_setup, pio_setup ) |
399 IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) |
400 IO_FIELD( R_ATA_CONFIG, pio_hold, pio_hold ) );
401}
402
403static unsigned long
404cris_ide_base_address(int bus)
405{
406 return IO_FIELD(R_ATA_CTRL_DATA, sel, bus);
407}
408
409static unsigned long
410cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
411{
412 return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) |
413 IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) |
414 IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1);
415}
416
417static __init void
418cris_ide_reset(unsigned val)
419{
420#ifdef CONFIG_ETRAX_IDE_G27_RESET
421 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val);
422#endif
423#ifdef CONFIG_ETRAX_IDE_PB7_RESET
424 port_pb_dir_shadow = port_pb_dir_shadow |
425 IO_STATE(R_PORT_PB_DIR, dir7, output);
426 *R_PORT_PB_DIR = port_pb_dir_shadow;
427 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val);
428#endif
429}
430
431static __init void
432cris_ide_init(void)
433{
434 volatile unsigned int dummy;
435
436 *R_ATA_CTRL_DATA = 0;
437 *R_ATA_TRANSFER_CNT = 0;
438 *R_ATA_CONFIG = 0;
439
440 if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) {
441 printk(KERN_CRIT "ide: Failed to get IO interface\n");
442 return;
443 } else if (cris_request_dma(ATA_TX_DMA_NBR,
444 "ETRAX100LX IDE TX",
445 DMA_VERBOSE_ON_ERROR,
446 dma_ata)) {
447 cris_free_io_interface(if_ata);
448 printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n");
449 return;
450 } else if (cris_request_dma(ATA_RX_DMA_NBR,
451 "ETRAX100LX IDE RX",
452 DMA_VERBOSE_ON_ERROR,
453 dma_ata)) {
454 cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx");
455 cris_free_io_interface(if_ata);
456 printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n");
457 return;
458 }
459
460 /* make a dummy read to set the ata controller in a proper state */
461 dummy = *R_ATA_STATUS_DATA;
462
463 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ));
464 *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) |
465 IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) );
466
467 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
468
469 *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
470 IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
471 IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
472 IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
473
474 /* reset the dma channels we will use */
475
476 RESET_DMA(ATA_TX_DMA_NBR);
477 RESET_DMA(ATA_RX_DMA_NBR);
478 WAIT_DMA(ATA_TX_DMA_NBR);
479 WAIT_DMA(ATA_RX_DMA_NBR);
480}
481
482#define cris_dma_descr_type etrax_dma_descr
483#define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read)
484#define cris_ultra_mask 0x0
485#define MAX_DESCR_SIZE 0x10000UL
486
487static unsigned long
488cris_ide_get_reg(unsigned long reg)
489{
490 return (reg & 0x0e000000) >> 25;
491}
492
493static void
494cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
495{
496 d->buf = virt_to_phys(buf);
497 d->sw_len = len == MAX_DESCR_SIZE ? 0 : len;
498 if (last)
499 d->ctrl |= d_eol;
500}
501
502static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len)
503{
504 unsigned long cmd;
505
506 if (dir) {
507 /* need to do this before RX DMA due to a chip bug
508 * it is enough to just flush the part of the cache that
509 * corresponds to the buffers we start, but since HD transfers
510 * usually are more than 8 kB, it is easier to optimize for the
511 * normal case and just flush the entire cache. its the only
512 * way to be sure! (OB movie quote)
513 */
514 flush_etrax_cache();
515 *R_DMA_CH3_FIRST = virt_to_phys(d);
516 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
517
518 } else {
519 *R_DMA_CH2_FIRST = virt_to_phys(d);
520 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
521 }
522
523 /* initiate a multi word dma read using DMA handshaking */
524
525 *R_ATA_TRANSFER_CNT =
526 IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1);
527
528 cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write);
529 cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) :
530 IO_STATE(R_ATA_CTRL_DATA, handsh, dma);
531 *R_ATA_CTRL_DATA =
532 cmd |
533 IO_FIELD(R_ATA_CTRL_DATA, data,
534 drive->hwif->io_ports.data_addr) |
535 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
536 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
537 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
538}
539
540static void
541cris_ide_wait_dma(int dir)
542{
543 if (dir)
544 WAIT_DMA(ATA_RX_DMA_NBR);
545 else
546 WAIT_DMA(ATA_TX_DMA_NBR);
547}
548
549static int cris_dma_test_irq(ide_drive_t *drive)
550{
551 int intr = *R_IRQ_MASK0_RD;
552 int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel,
553 drive->hwif->io_ports.data_addr);
554
555 return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
556}
557
558
559static void cris_ide_initialize_dma(int dir)
560{
561 if (dir)
562 {
563 RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
564 WAIT_DMA(ATA_RX_DMA_NBR);
565 }
566 else
567 {
568 RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
569 WAIT_DMA(ATA_TX_DMA_NBR);
570 }
571}
572
573#endif
574
575void
576cris_ide_outw(unsigned short data, unsigned long reg) {
577 int timeleft;
578
579 LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
580
581 /* note the lack of handling any timeouts. we stop waiting, but we don't
582 * really notify anybody.
583 */
584
585 timeleft = IDE_REGISTER_TIMEOUT;
586 /* wait for busy flag */
587 do {
588 timeleft--;
589 } while(timeleft && cris_ide_busy());
590
591 /*
592 * Fall through at a timeout, so the ongoing command will be
593 * aborted by the write below, which is expected to be a dummy
594 * command to the command register. This happens when a faulty
595 * drive times out on a command. See comment on timeout in
596 * INB.
597 */
598 if(!timeleft)
599 printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
600
601 cris_ide_write_command(reg|data); /* write data to the drive's register */
602
603 timeleft = IDE_REGISTER_TIMEOUT;
604 /* wait for transmitter ready */
605 do {
606 timeleft--;
607 } while(timeleft && !cris_ide_ready());
608}
609
610void
611cris_ide_outb(unsigned char data, unsigned long reg)
612{
613 cris_ide_outw(data, reg);
614}
615
616void
617cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
618{
619 cris_ide_outw(addr, port);
620}
621
622unsigned short
623cris_ide_inw(unsigned long reg) {
624 int timeleft;
625 unsigned short val;
626
627 timeleft = IDE_REGISTER_TIMEOUT;
628 /* wait for busy flag */
629 do {
630 timeleft--;
631 } while(timeleft && cris_ide_busy());
632
633 if(!timeleft) {
634 /*
635 * If we're asked to read the status register, like for
636 * example when a command does not complete for an
637 * extended time, but the ATA interface is stuck in a
638 * busy state at the *ETRAX* ATA interface level (as has
639 * happened repeatedly with at least one bad disk), then
640 * the best thing to do is to pretend that we read
641 * "busy" in the status register, so the IDE driver will
642 * time-out, abort the ongoing command and perform a
643 * reset sequence. Note that the subsequent OUT_BYTE
644 * call will also timeout on busy, but as long as the
645 * write is still performed, everything will be fine.
646 */
647 if (cris_ide_get_reg(reg) == 7)
648 return BUSY_STAT;
649 else
650 /* For other rare cases we assume 0 is good enough. */
651 return 0;
652 }
653
654 cris_ide_write_command(reg | cris_pio_read);
655
656 timeleft = IDE_REGISTER_TIMEOUT;
657 /* wait for available */
658 do {
659 timeleft--;
660 } while(timeleft && !cris_ide_data_available(&val));
661
662 if(!timeleft)
663 return 0;
664
665 LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg));
666
667 return val;
668}
669
670unsigned char
671cris_ide_inb(unsigned long reg)
672{
673 return (unsigned char)cris_ide_inw(reg);
674}
675
676static void cris_ide_input_data (ide_drive_t *drive, void *, unsigned int);
677static void cris_ide_output_data (ide_drive_t *drive, void *, unsigned int);
678static void cris_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
679static void cris_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
680
681static void cris_dma_host_set(ide_drive_t *drive, int on)
682{
683}
684
685static void cris_set_pio_mode(ide_drive_t *drive, const u8 pio)
686{
687 int setup, strobe, hold;
688
689 switch(pio)
690 {
691 case 0:
692 setup = ATA_PIO0_SETUP;
693 strobe = ATA_PIO0_STROBE;
694 hold = ATA_PIO0_HOLD;
695 break;
696 case 1:
697 setup = ATA_PIO1_SETUP;
698 strobe = ATA_PIO1_STROBE;
699 hold = ATA_PIO1_HOLD;
700 break;
701 case 2:
702 setup = ATA_PIO2_SETUP;
703 strobe = ATA_PIO2_STROBE;
704 hold = ATA_PIO2_HOLD;
705 break;
706 case 3:
707 setup = ATA_PIO3_SETUP;
708 strobe = ATA_PIO3_STROBE;
709 hold = ATA_PIO3_HOLD;
710 break;
711 case 4:
712 setup = ATA_PIO4_SETUP;
713 strobe = ATA_PIO4_STROBE;
714 hold = ATA_PIO4_HOLD;
715 break;
716 default:
717 return;
718 }
719
720 cris_ide_set_speed(TYPE_PIO, setup, strobe, hold);
721}
722
723static void cris_set_dma_mode(ide_drive_t *drive, const u8 speed)
724{
725 int cyc = 0, dvs = 0, strobe = 0, hold = 0;
726
727 switch(speed)
728 {
729 case XFER_UDMA_0:
730 cyc = ATA_UDMA0_CYC;
731 dvs = ATA_UDMA0_DVS;
732 break;
733 case XFER_UDMA_1:
734 cyc = ATA_UDMA1_CYC;
735 dvs = ATA_UDMA1_DVS;
736 break;
737 case XFER_UDMA_2:
738 cyc = ATA_UDMA2_CYC;
739 dvs = ATA_UDMA2_DVS;
740 break;
741 case XFER_MW_DMA_0:
742 strobe = ATA_DMA0_STROBE;
743 hold = ATA_DMA0_HOLD;
744 break;
745 case XFER_MW_DMA_1:
746 strobe = ATA_DMA1_STROBE;
747 hold = ATA_DMA1_HOLD;
748 break;
749 case XFER_MW_DMA_2:
750 strobe = ATA_DMA2_STROBE;
751 hold = ATA_DMA2_HOLD;
752 break;
753 }
754
755 if (speed >= XFER_UDMA_0)
756 cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0);
757 else
758 cris_ide_set_speed(TYPE_DMA, 0, strobe, hold);
759}
760
761static void __init cris_setup_ports(hw_regs_t *hw, unsigned long base)
762{
763 int i;
764
765 memset(hw, 0, sizeof(*hw));
766
767 for (i = 0; i <= 7; i++)
768 hw->io_ports_array[i] = base + cris_ide_reg_addr(i, 0, 1);
769
770 /*
771 * the IDE control register is at ATA address 6,
772 * with CS1 active instead of CS0
773 */
774 hw->io_ports.ctl_addr = base + cris_ide_reg_addr(6, 1, 0);
775
776 hw->irq = ide_default_irq(0);
777 hw->ack_intr = cris_ide_ack_intr;
778}
779
780static const struct ide_port_ops cris_port_ops = {
781 .set_pio_mode = cris_set_pio_mode,
782 .set_dma_mode = cris_set_dma_mode,
783};
784
785static const struct ide_dma_ops cris_dma_ops;
786
787static const struct ide_port_info cris_port_info __initdata = {
788 .chipset = ide_etrax100,
789 .port_ops = &cris_port_ops,
790 .dma_ops = &cris_dma_ops,
791 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
792 IDE_HFLAG_NO_DMA, /* no SFF-style DMA */
793 .pio_mask = ATA_PIO4,
794 .udma_mask = cris_ultra_mask,
795 .mwdma_mask = ATA_MWDMA2,
796};
797
798static int __init init_e100_ide(void)
799{
800 hw_regs_t hw;
801 int h;
802 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
803
804 printk("ide: ETRAX FS built-in ATA DMA controller\n");
805
806 for (h = 0; h < 4; h++) {
807 ide_hwif_t *hwif = NULL;
808
809 cris_setup_ports(&hw, cris_ide_base_address(h));
810
811 hwif = ide_find_port();
812 if (hwif == NULL)
813 continue;
814 ide_init_port_data(hwif, hwif->index);
815 ide_init_port_hw(hwif, &hw);
816
817 hwif->ata_input_data = &cris_ide_input_data;
818 hwif->ata_output_data = &cris_ide_output_data;
819 hwif->atapi_input_bytes = &cris_atapi_input_bytes;
820 hwif->atapi_output_bytes = &cris_atapi_output_bytes;
821 hwif->OUTB = &cris_ide_outb;
822 hwif->OUTW = &cris_ide_outw;
823 hwif->OUTBSYNC = &cris_ide_outbsync;
824 hwif->INB = &cris_ide_inb;
825 hwif->INW = &cris_ide_inw;
826 hwif->cbl = ATA_CBL_PATA40;
827
828 idx[h] = hwif->index;
829 }
830
831 /* Reset pulse */
832 cris_ide_reset(0);
833 udelay(25);
834 cris_ide_reset(1);
835
836 cris_ide_init();
837
838 cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD);
839 cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD);
840 cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0);
841
842 ide_device_add(idx, &cris_port_info);
843
844 return 0;
845}
846
847static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16)));
848
849/*
850 * The following routines are mainly used by the ATAPI drivers.
851 *
852 * These routines will round up any request for an odd number of bytes,
853 * so if an odd bytecount is specified, be sure that there's at least one
854 * extra byte allocated for the buffer.
855 */
856static void
857cris_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
858{
859 D(printk("atapi_input_bytes, buffer 0x%x, count %d\n",
860 buffer, bytecount));
861
862 if(bytecount & 1) {
863 printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
864 bytecount++; /* to round off */
865 }
866
867 /* setup DMA and start transfer */
868
869 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
870 cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount);
871
872 /* wait for completion */
873 LED_DISK_READ(1);
874 cris_ide_wait_dma(1);
875 LED_DISK_READ(0);
876}
877
878static void
879cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
880{
881 D(printk("atapi_output_bytes, buffer 0x%x, count %d\n",
882 buffer, bytecount));
883
884 if(bytecount & 1) {
885 printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
886 bytecount++;
887 }
888
889 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
890 cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount);
891
892 /* wait for completion */
893
894 LED_DISK_WRITE(1);
895 LED_DISK_READ(1);
896 cris_ide_wait_dma(0);
897 LED_DISK_WRITE(0);
898}
899
900/*
901 * This is used for most PIO data transfers *from* the IDE interface
902 */
903static void
904cris_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
905{
906 cris_atapi_input_bytes(drive, buffer, wcount << 2);
907}
908
909/*
910 * This is used for most PIO data transfers *to* the IDE interface
911 */
912static void
913cris_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
914{
915 cris_atapi_output_bytes(drive, buffer, wcount << 2);
916}
917
918/* we only have one DMA channel on the chip for ATA, so we can keep these statically */
919static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16)));
920static unsigned int ata_tot_size;
921
922/*
923 * cris_ide_build_dmatable() prepares a dma request.
924 * Returns 0 if all went okay, returns 1 otherwise.
925 */
926static int cris_ide_build_dmatable (ide_drive_t *drive)
927{
928 ide_hwif_t *hwif = drive->hwif;
929 struct scatterlist* sg;
930 struct request *rq = drive->hwif->hwgroup->rq;
931 unsigned long size, addr;
932 unsigned int count = 0;
933 int i = 0;
934
935 sg = hwif->sg_table;
936
937 ata_tot_size = 0;
938
939 ide_map_sg(drive, rq);
940 i = hwif->sg_nents;
941
942 while(i) {
943 /*
944 * Determine addr and size of next buffer area. We assume that
945 * individual virtual buffers are always composed linearly in
946 * physical memory. For example, we assume that any 8kB buffer
947 * is always composed of two adjacent physical 4kB pages rather
948 * than two possibly non-adjacent physical 4kB pages.
949 */
950 /* group sequential buffers into one large buffer */
951 addr = sg_phys(sg);
952 size = sg_dma_len(sg);
953 while (--i) {
954 sg = sg_next(sg);
955 if ((addr + size) != sg_phys(sg))
956 break;
957 size += sg_dma_len(sg);
958 }
959
960 /* did we run out of descriptors? */
961
962 if(count >= MAX_DMA_DESCRS) {
963 printk("%s: too few DMA descriptors\n", drive->name);
964 return 1;
965 }
966
967 /* however, this case is more difficult - rw_trf_cnt cannot be more
968 than 65536 words per transfer, so in that case we need to either
969 1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with
970 the descriptors, or
971 2) simply do the request here, and get dma_intr to only ide_end_request on
972 those blocks that were actually set-up for transfer.
973 */
974
975 if(ata_tot_size + size > 131072) {
976 printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
977 return 1;
978 }
979
980 /* If size > MAX_DESCR_SIZE it has to be splitted into new descriptors. Since we
981 don't handle size > 131072 only one split is necessary */
982
983 if(size > MAX_DESCR_SIZE) {
984 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, MAX_DESCR_SIZE, 0);
985 count++;
986 ata_tot_size += MAX_DESCR_SIZE;
987 size -= MAX_DESCR_SIZE;
988 addr += MAX_DESCR_SIZE;
989 }
990
991 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1);
992 count++;
993 ata_tot_size += size;
994 }
995
996 if (count) {
997 /* return and say all is ok */
998 return 0;
999 }
1000
1001 printk("%s: empty DMA table?\n", drive->name);
1002 return 1; /* let the PIO routines handle this weirdness */
1003}
1004
1005/*
1006 * cris_dma_intr() is the handler for disk read/write DMA interrupts
1007 */
1008static ide_startstop_t cris_dma_intr (ide_drive_t *drive)
1009{
1010 LED_DISK_READ(0);
1011 LED_DISK_WRITE(0);
1012
1013 return ide_dma_intr(drive);
1014}
1015
1016/*
1017 * Functions below initiates/aborts DMA read/write operations on a drive.
1018 *
1019 * The caller is assumed to have selected the drive and programmed the drive's
1020 * sector address using CHS or LBA. All that remains is to prepare for DMA
1021 * and then issue the actual read/write DMA/PIO command to the drive.
1022 *
1023 * For ATAPI devices, we just prepare for DMA and return. The caller should
1024 * then issue the packet command to the drive and call us again with
1025 * cris_dma_start afterwards.
1026 *
1027 * Returns 0 if all went well.
1028 * Returns 1 if DMA read/write could not be started, in which case
1029 * the caller should revert to PIO for the current request.
1030 */
1031
1032static int cris_dma_end(ide_drive_t *drive)
1033{
1034 drive->waiting_for_dma = 0;
1035 return 0;
1036}
1037
1038static int cris_dma_setup(ide_drive_t *drive)
1039{
1040 struct request *rq = drive->hwif->hwgroup->rq;
1041
1042 cris_ide_initialize_dma(!rq_data_dir(rq));
1043 if (cris_ide_build_dmatable (drive)) {
1044 ide_map_sg(drive, rq);
1045 return 1;
1046 }
1047
1048 drive->waiting_for_dma = 1;
1049 return 0;
1050}
1051
1052static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command)
1053{
1054 ide_execute_command(drive, command, &cris_dma_intr, WAIT_CMD, NULL);
1055}
1056
1057static void cris_dma_start(ide_drive_t *drive)
1058{
1059 struct request *rq = drive->hwif->hwgroup->rq;
1060 int writing = rq_data_dir(rq);
1061 int type = TYPE_DMA;
1062
1063 if (drive->current_speed >= XFER_UDMA_0)
1064 type = TYPE_UDMA;
1065
1066 cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size);
1067
1068 if (writing) {
1069 LED_DISK_WRITE(1);
1070 } else {
1071 LED_DISK_READ(1);
1072 }
1073}
1074
1075static const struct ide_dma_ops cris_dma_ops = {
1076 .dma_host_set = cris_dma_host_set,
1077 .dma_setup = cris_dma_setup,
1078 .dma_exec_cmd = cris_dma_exec_cmd,
1079 .dma_start = cris_dma_start,
1080 .dma_end = cris_dma_end,
1081 .dma_test_irq = cris_dma_test_irq,
1082};
1083
1084module_init(init_e100_ide);
1085
1086MODULE_LICENSE("GPL");
diff --git a/drivers/ide/h8300/ide-h8300.c b/drivers/ide/h8300/ide-h8300.c
index fd23f12e17aa..ecf53bb0d2aa 100644
--- a/drivers/ide/h8300/ide-h8300.c
+++ b/drivers/ide/h8300/ide-h8300.c
@@ -42,6 +42,91 @@ static u16 mm_inw(unsigned long a)
42 return r; 42 return r;
43} 43}
44 44
45static void h8300_tf_load(ide_drive_t *drive, ide_task_t *task)
46{
47 ide_hwif_t *hwif = drive->hwif;
48 struct ide_io_ports *io_ports = &hwif->io_ports;
49 struct ide_taskfile *tf = &task->tf;
50 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
51
52 if (task->tf_flags & IDE_TFLAG_FLAGGED)
53 HIHI = 0xFF;
54
55 ide_set_irq(drive, 1);
56
57 if (task->tf_flags & IDE_TFLAG_OUT_DATA)
58 mm_outw((tf->hob_data << 8) | tf->data, io_ports->data_addr);
59
60 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
61 outb(tf->hob_feature, io_ports->feature_addr);
62 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
63 outb(tf->hob_nsect, io_ports->nsect_addr);
64 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
65 outb(tf->hob_lbal, io_ports->lbal_addr);
66 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
67 outb(tf->hob_lbam, io_ports->lbam_addr);
68 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
69 outb(tf->hob_lbah, io_ports->lbah_addr);
70
71 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
72 outb(tf->feature, io_ports->feature_addr);
73 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
74 outb(tf->nsect, io_ports->nsect_addr);
75 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
76 outb(tf->lbal, io_ports->lbal_addr);
77 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
78 outb(tf->lbam, io_ports->lbam_addr);
79 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
80 outb(tf->lbah, io_ports->lbah_addr);
81
82 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
83 outb((tf->device & HIHI) | drive->select.all,
84 io_ports->device_addr);
85}
86
87static void h8300_tf_read(ide_drive_t *drive, ide_task_t *task)
88{
89 ide_hwif_t *hwif = drive->hwif;
90 struct ide_io_ports *io_ports = &hwif->io_ports;
91 struct ide_taskfile *tf = &task->tf;
92
93 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
94 u16 data = mm_inw(io_ports->data_addr);
95
96 tf->data = data & 0xff;
97 tf->hob_data = (data >> 8) & 0xff;
98 }
99
100 /* be sure we're looking at the low order bits */
101 outb(drive->ctl & ~0x80, io_ports->ctl_addr);
102
103 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
104 tf->nsect = inb(io_ports->nsect_addr);
105 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
106 tf->lbal = inb(io_ports->lbal_addr);
107 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
108 tf->lbam = inb(io_ports->lbam_addr);
109 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
110 tf->lbah = inb(io_ports->lbah_addr);
111 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
112 tf->device = inb(io_ports->device_addr);
113
114 if (task->tf_flags & IDE_TFLAG_LBA48) {
115 outb(drive->ctl | 0x80, io_ports->ctl_addr);
116
117 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
118 tf->hob_feature = inb(io_ports->feature_addr);
119 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
120 tf->hob_nsect = inb(io_ports->nsect_addr);
121 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
122 tf->hob_lbal = inb(io_ports->lbal_addr);
123 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
124 tf->hob_lbam = inb(io_ports->lbam_addr);
125 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
126 tf->hob_lbah = inb(io_ports->lbah_addr);
127 }
128}
129
45static void mm_outsw(unsigned long addr, void *buf, u32 len) 130static void mm_outsw(unsigned long addr, void *buf, u32 len)
46{ 131{
47 unsigned short *bp = (unsigned short *)buf; 132 unsigned short *bp = (unsigned short *)buf;
@@ -56,6 +141,18 @@ static void mm_insw(unsigned long addr, void *buf, u32 len)
56 *bp = bswap(*(volatile u16 *)addr); 141 *bp = bswap(*(volatile u16 *)addr);
57} 142}
58 143
144static void h8300_input_data(ide_drive_t *drive, struct request *rq,
145 void *buf, unsigned int len)
146{
147 mm_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
148}
149
150static void h8300_output_data(ide_drive_t *drive, struct request *rq,
151 void *buf, unsigned int len)
152{
153 mm_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
154}
155
59#define H8300_IDE_GAP (2) 156#define H8300_IDE_GAP (2)
60 157
61static inline void hw_setup(hw_regs_t *hw) 158static inline void hw_setup(hw_regs_t *hw)
@@ -74,12 +171,11 @@ static inline void hwif_setup(ide_hwif_t *hwif)
74{ 171{
75 default_hwif_iops(hwif); 172 default_hwif_iops(hwif);
76 173
77 hwif->OUTW = mm_outw; 174 hwif->tf_load = h8300_tf_load;
78 hwif->OUTSW = mm_outsw; 175 hwif->tf_read = h8300_tf_read;
79 hwif->INW = mm_inw; 176
80 hwif->INSW = mm_insw; 177 hwif->input_data = h8300_input_data;
81 hwif->OUTSL = NULL; 178 hwif->output_data = h8300_output_data;
82 hwif->INSL = NULL;
83} 179}
84 180
85static int __init h8300_ide_init(void) 181static int __init h8300_ide_init(void)
diff --git a/drivers/ide/ide-cd.c b/drivers/ide/ide-cd.c
index b34fd2bde96f..fe9df38f62cc 100644
--- a/drivers/ide/ide-cd.c
+++ b/drivers/ide/ide-cd.c
@@ -142,7 +142,6 @@ static void cdrom_analyze_sense_data(ide_drive_t *drive,
142{ 142{
143 unsigned long sector; 143 unsigned long sector;
144 unsigned long bio_sectors; 144 unsigned long bio_sectors;
145 unsigned long valid;
146 struct cdrom_info *info = drive->driver_data; 145 struct cdrom_info *info = drive->driver_data;
147 146
148 if (!cdrom_log_sense(drive, failed_command, sense)) 147 if (!cdrom_log_sense(drive, failed_command, sense))
@@ -173,17 +172,13 @@ static void cdrom_analyze_sense_data(ide_drive_t *drive,
173 (sense->information[2] << 8) | 172 (sense->information[2] << 8) |
174 (sense->information[3]); 173 (sense->information[3]);
175 174
176 bio_sectors = bio_sectors(failed_command->bio);
177 if (bio_sectors < 4)
178 bio_sectors = 4;
179 if (drive->queue->hardsect_size == 2048) 175 if (drive->queue->hardsect_size == 2048)
180 /* device sector size is 2K */ 176 /* device sector size is 2K */
181 sector <<= 2; 177 sector <<= 2;
178
179 bio_sectors = max(bio_sectors(failed_command->bio), 4U);
182 sector &= ~(bio_sectors - 1); 180 sector &= ~(bio_sectors - 1);
183 valid = (sector - failed_command->sector) << 9;
184 181
185 if (valid < 0)
186 valid = 0;
187 if (sector < get_capacity(info->disk) && 182 if (sector < get_capacity(info->disk) &&
188 drive->probed_capacity - sector < 4 * 75) 183 drive->probed_capacity - sector < 4 * 75)
189 set_capacity(info->disk, sector); 184 set_capacity(info->disk, sector);
@@ -555,14 +550,7 @@ static ide_startstop_t cdrom_start_packet_command(ide_drive_t *drive,
555 ATAPI_WAIT_PC, cdrom_timer_expiry); 550 ATAPI_WAIT_PC, cdrom_timer_expiry);
556 return ide_started; 551 return ide_started;
557 } else { 552 } else {
558 unsigned long flags; 553 ide_execute_pkt_cmd(drive);
559
560 /* packet command */
561 spin_lock_irqsave(&ide_lock, flags);
562 hwif->OUTBSYNC(drive, WIN_PACKETCMD,
563 hwif->io_ports.command_addr);
564 ndelay(400);
565 spin_unlock_irqrestore(&ide_lock, flags);
566 554
567 return (*handler) (drive); 555 return (*handler) (drive);
568 } 556 }
@@ -613,7 +601,7 @@ static ide_startstop_t cdrom_transfer_packet_command(ide_drive_t *drive,
613 cmd_len = ATAPI_MIN_CDB_BYTES; 601 cmd_len = ATAPI_MIN_CDB_BYTES;
614 602
615 /* send the command to the device */ 603 /* send the command to the device */
616 HWIF(drive)->atapi_output_bytes(drive, rq->cmd, cmd_len); 604 hwif->output_data(drive, NULL, rq->cmd, cmd_len);
617 605
618 /* start the DMA if need be */ 606 /* start the DMA if need be */
619 if (info->dma) 607 if (info->dma)
@@ -629,7 +617,7 @@ static void ide_cd_pad_transfer(ide_drive_t *drive, xfer_func_t *xf, int len)
629{ 617{
630 while (len > 0) { 618 while (len > 0) {
631 int dum = 0; 619 int dum = 0;
632 xf(drive, &dum, sizeof(dum)); 620 xf(drive, NULL, &dum, sizeof(dum));
633 len -= sizeof(dum); 621 len -= sizeof(dum);
634 } 622 }
635} 623}
@@ -639,7 +627,7 @@ static void ide_cd_drain_data(ide_drive_t *drive, int nsects)
639 while (nsects > 0) { 627 while (nsects > 0) {
640 static char dum[SECTOR_SIZE]; 628 static char dum[SECTOR_SIZE];
641 629
642 drive->hwif->atapi_input_bytes(drive, dum, sizeof(dum)); 630 drive->hwif->input_data(drive, NULL, dum, sizeof(dum));
643 nsects--; 631 nsects--;
644 } 632 }
645} 633}
@@ -666,7 +654,7 @@ static int ide_cd_check_ireason(ide_drive_t *drive, struct request *rq,
666 printk(KERN_ERR "%s: %s: wrong transfer direction!\n", 654 printk(KERN_ERR "%s: %s: wrong transfer direction!\n",
667 drive->name, __func__); 655 drive->name, __func__);
668 656
669 xf = rw ? hwif->atapi_output_bytes : hwif->atapi_input_bytes; 657 xf = rw ? hwif->output_data : hwif->input_data;
670 ide_cd_pad_transfer(drive, xf, len); 658 ide_cd_pad_transfer(drive, xf, len);
671 } else if (rw == 0 && ireason == 1) { 659 } else if (rw == 0 && ireason == 1) {
672 /* 660 /*
@@ -1019,10 +1007,10 @@ static ide_startstop_t cdrom_newpc_intr(ide_drive_t *drive)
1019 1007
1020 if (ireason == 0) { 1008 if (ireason == 0) {
1021 write = 1; 1009 write = 1;
1022 xferfunc = HWIF(drive)->atapi_output_bytes; 1010 xferfunc = hwif->output_data;
1023 } else { 1011 } else {
1024 write = 0; 1012 write = 0;
1025 xferfunc = HWIF(drive)->atapi_input_bytes; 1013 xferfunc = hwif->input_data;
1026 } 1014 }
1027 1015
1028 /* transfer data */ 1016 /* transfer data */
@@ -1061,7 +1049,7 @@ static ide_startstop_t cdrom_newpc_intr(ide_drive_t *drive)
1061 if (blen > thislen) 1049 if (blen > thislen)
1062 blen = thislen; 1050 blen = thislen;
1063 1051
1064 xferfunc(drive, ptr, blen); 1052 xferfunc(drive, NULL, ptr, blen);
1065 1053
1066 thislen -= blen; 1054 thislen -= blen;
1067 len -= blen; 1055 len -= blen;
diff --git a/drivers/ide/ide-dma.c b/drivers/ide/ide-dma.c
index c352cf27b6e7..653b1ade13d3 100644
--- a/drivers/ide/ide-dma.c
+++ b/drivers/ide/ide-dma.c
@@ -464,9 +464,10 @@ int ide_dma_setup(ide_drive_t *drive)
464 464
465 /* PRD table */ 465 /* PRD table */
466 if (hwif->mmio) 466 if (hwif->mmio)
467 writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable); 467 writel(hwif->dmatable_dma,
468 (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS));
468 else 469 else
469 outl(hwif->dmatable_dma, hwif->dma_prdtable); 470 outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS);
470 471
471 /* specify r/w */ 472 /* specify r/w */
472 hwif->OUTB(reading, hwif->dma_command); 473 hwif->OUTB(reading, hwif->dma_command);
@@ -858,14 +859,8 @@ void ide_setup_dma(ide_hwif_t *hwif, unsigned long base)
858 859
859 if (!hwif->dma_command) 860 if (!hwif->dma_command)
860 hwif->dma_command = hwif->dma_base + 0; 861 hwif->dma_command = hwif->dma_base + 0;
861 if (!hwif->dma_vendor1)
862 hwif->dma_vendor1 = hwif->dma_base + 1;
863 if (!hwif->dma_status) 862 if (!hwif->dma_status)
864 hwif->dma_status = hwif->dma_base + 2; 863 hwif->dma_status = hwif->dma_base + 2;
865 if (!hwif->dma_vendor3)
866 hwif->dma_vendor3 = hwif->dma_base + 3;
867 if (!hwif->dma_prdtable)
868 hwif->dma_prdtable = hwif->dma_base + 4;
869 864
870 hwif->dma_ops = &sff_dma_ops; 865 hwif->dma_ops = &sff_dma_ops;
871} 866}
diff --git a/drivers/ide/ide-floppy.c b/drivers/ide/ide-floppy.c
index 489079b8ed03..f05fbc2bd7a8 100644
--- a/drivers/ide/ide-floppy.c
+++ b/drivers/ide/ide-floppy.c
@@ -231,6 +231,7 @@ static int idefloppy_end_request(ide_drive_t *drive, int uptodate, int nsecs)
231static void ide_floppy_io_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc, 231static void ide_floppy_io_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc,
232 unsigned int bcount, int direction) 232 unsigned int bcount, int direction)
233{ 233{
234 ide_hwif_t *hwif = drive->hwif;
234 struct request *rq = pc->rq; 235 struct request *rq = pc->rq;
235 struct req_iterator iter; 236 struct req_iterator iter;
236 struct bio_vec *bvec; 237 struct bio_vec *bvec;
@@ -246,9 +247,9 @@ static void ide_floppy_io_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc,
246 247
247 data = bvec_kmap_irq(bvec, &flags); 248 data = bvec_kmap_irq(bvec, &flags);
248 if (direction) 249 if (direction)
249 drive->hwif->atapi_output_bytes(drive, data, count); 250 hwif->output_data(drive, NULL, data, count);
250 else 251 else
251 drive->hwif->atapi_input_bytes(drive, data, count); 252 hwif->input_data(drive, NULL, data, count);
252 bvec_kunmap_irq(data, &flags); 253 bvec_kunmap_irq(data, &flags);
253 254
254 bcount -= count; 255 bcount -= count;
@@ -261,10 +262,7 @@ static void ide_floppy_io_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc,
261 if (bcount) { 262 if (bcount) {
262 printk(KERN_ERR "%s: leftover data in %s, bcount == %d\n", 263 printk(KERN_ERR "%s: leftover data in %s, bcount == %d\n",
263 drive->name, __func__, bcount); 264 drive->name, __func__, bcount);
264 if (direction) 265 ide_pad_transfer(drive, direction, bcount);
265 ide_atapi_write_zeros(drive, bcount);
266 else
267 ide_atapi_discard_data(drive, bcount);
268 } 266 }
269} 267}
270 268
@@ -490,7 +488,7 @@ static ide_startstop_t idefloppy_pc_intr(ide_drive_t *drive)
490 printk(KERN_ERR "ide-floppy: The floppy wants " 488 printk(KERN_ERR "ide-floppy: The floppy wants "
491 "to send us more data than expected " 489 "to send us more data than expected "
492 "- discarding data\n"); 490 "- discarding data\n");
493 ide_atapi_discard_data(drive, bcount); 491 ide_pad_transfer(drive, 0, bcount);
494 492
495 ide_set_handler(drive, 493 ide_set_handler(drive,
496 &idefloppy_pc_intr, 494 &idefloppy_pc_intr,
@@ -503,12 +501,12 @@ static ide_startstop_t idefloppy_pc_intr(ide_drive_t *drive)
503 } 501 }
504 } 502 }
505 if (pc->flags & PC_FLAG_WRITING) 503 if (pc->flags & PC_FLAG_WRITING)
506 xferfunc = hwif->atapi_output_bytes; 504 xferfunc = hwif->output_data;
507 else 505 else
508 xferfunc = hwif->atapi_input_bytes; 506 xferfunc = hwif->input_data;
509 507
510 if (pc->buf) 508 if (pc->buf)
511 xferfunc(drive, pc->cur_pos, bcount); 509 xferfunc(drive, NULL, pc->cur_pos, bcount);
512 else 510 else
513 ide_floppy_io_buffers(drive, pc, bcount, 511 ide_floppy_io_buffers(drive, pc, bcount,
514 !!(pc->flags & PC_FLAG_WRITING)); 512 !!(pc->flags & PC_FLAG_WRITING));
@@ -548,8 +546,10 @@ static ide_startstop_t idefloppy_transfer_pc(ide_drive_t *drive)
548 546
549 /* Set the interrupt routine */ 547 /* Set the interrupt routine */
550 ide_set_handler(drive, &idefloppy_pc_intr, IDEFLOPPY_WAIT_CMD, NULL); 548 ide_set_handler(drive, &idefloppy_pc_intr, IDEFLOPPY_WAIT_CMD, NULL);
549
551 /* Send the actual packet */ 550 /* Send the actual packet */
552 HWIF(drive)->atapi_output_bytes(drive, floppy->pc->c, 12); 551 hwif->output_data(drive, NULL, floppy->pc->c, 12);
552
553 return ide_started; 553 return ide_started;
554} 554}
555 555
@@ -569,7 +569,8 @@ static int idefloppy_transfer_pc2(ide_drive_t *drive)
569 idefloppy_floppy_t *floppy = drive->driver_data; 569 idefloppy_floppy_t *floppy = drive->driver_data;
570 570
571 /* Send the actual packet */ 571 /* Send the actual packet */
572 HWIF(drive)->atapi_output_bytes(drive, floppy->pc->c, 12); 572 drive->hwif->output_data(drive, NULL, floppy->pc->c, 12);
573
573 /* Timeout for the packet command */ 574 /* Timeout for the packet command */
574 return IDEFLOPPY_WAIT_CMD; 575 return IDEFLOPPY_WAIT_CMD;
575} 576}
@@ -692,7 +693,7 @@ static ide_startstop_t idefloppy_issue_pc(ide_drive_t *drive,
692 return ide_started; 693 return ide_started;
693 } else { 694 } else {
694 /* Issue the packet command */ 695 /* Issue the packet command */
695 hwif->OUTB(WIN_PACKETCMD, hwif->io_ports.command_addr); 696 ide_execute_pkt_cmd(drive);
696 return (*pkt_xfer_routine) (drive); 697 return (*pkt_xfer_routine) (drive);
697 } 698 }
698} 699}
diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c
index 3a2d8930d17f..788783da9025 100644
--- a/drivers/ide/ide-io.c
+++ b/drivers/ide/ide-io.c
@@ -295,49 +295,6 @@ static void ide_complete_pm_request (ide_drive_t *drive, struct request *rq)
295 spin_unlock_irqrestore(&ide_lock, flags); 295 spin_unlock_irqrestore(&ide_lock, flags);
296} 296}
297 297
298void ide_tf_read(ide_drive_t *drive, ide_task_t *task)
299{
300 ide_hwif_t *hwif = drive->hwif;
301 struct ide_io_ports *io_ports = &hwif->io_ports;
302 struct ide_taskfile *tf = &task->tf;
303
304 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
305 u16 data = hwif->INW(io_ports->data_addr);
306
307 tf->data = data & 0xff;
308 tf->hob_data = (data >> 8) & 0xff;
309 }
310
311 /* be sure we're looking at the low order bits */
312 hwif->OUTB(drive->ctl & ~0x80, io_ports->ctl_addr);
313
314 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
315 tf->nsect = hwif->INB(io_ports->nsect_addr);
316 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
317 tf->lbal = hwif->INB(io_ports->lbal_addr);
318 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
319 tf->lbam = hwif->INB(io_ports->lbam_addr);
320 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
321 tf->lbah = hwif->INB(io_ports->lbah_addr);
322 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
323 tf->device = hwif->INB(io_ports->device_addr);
324
325 if (task->tf_flags & IDE_TFLAG_LBA48) {
326 hwif->OUTB(drive->ctl | 0x80, io_ports->ctl_addr);
327
328 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
329 tf->hob_feature = hwif->INB(io_ports->feature_addr);
330 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
331 tf->hob_nsect = hwif->INB(io_ports->nsect_addr);
332 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
333 tf->hob_lbal = hwif->INB(io_ports->lbal_addr);
334 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
335 tf->hob_lbam = hwif->INB(io_ports->lbam_addr);
336 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
337 tf->hob_lbah = hwif->INB(io_ports->lbah_addr);
338 }
339}
340
341/** 298/**
342 * ide_end_drive_cmd - end an explicit drive command 299 * ide_end_drive_cmd - end an explicit drive command
343 * @drive: command 300 * @drive: command
@@ -373,7 +330,7 @@ void ide_end_drive_cmd (ide_drive_t *drive, u8 stat, u8 err)
373 tf->error = err; 330 tf->error = err;
374 tf->status = stat; 331 tf->status = stat;
375 332
376 ide_tf_read(drive, task); 333 drive->hwif->tf_read(drive, task);
377 334
378 if (task->tf_flags & IDE_TFLAG_DYN) 335 if (task->tf_flags & IDE_TFLAG_DYN)
379 kfree(task); 336 kfree(task);
@@ -422,7 +379,7 @@ static void try_to_flush_leftover_data (ide_drive_t *drive)
422 u32 wcount = (i > 16) ? 16 : i; 379 u32 wcount = (i > 16) ? 16 : i;
423 380
424 i -= wcount; 381 i -= wcount;
425 HWIF(drive)->ata_input_data(drive, buffer, wcount); 382 drive->hwif->input_data(drive, NULL, buffer, wcount * 4);
426 } 383 }
427} 384}
428 385
@@ -502,7 +459,8 @@ static ide_startstop_t ide_atapi_error(ide_drive_t *drive, struct request *rq, u
502 459
503 if (ide_read_status(drive) & (BUSY_STAT | DRQ_STAT)) 460 if (ide_read_status(drive) & (BUSY_STAT | DRQ_STAT))
504 /* force an abort */ 461 /* force an abort */
505 hwif->OUTB(WIN_IDLEIMMEDIATE, hwif->io_ports.command_addr); 462 hwif->OUTBSYNC(drive, WIN_IDLEIMMEDIATE,
463 hwif->io_ports.command_addr);
506 464
507 if (rq->errors >= ERROR_MAX) { 465 if (rq->errors >= ERROR_MAX) {
508 ide_kill_rq(drive, rq); 466 ide_kill_rq(drive, rq);
@@ -1679,7 +1637,23 @@ void ide_pktcmd_tf_load(ide_drive_t *drive, u32 tf_flags, u16 bcount, u8 dma)
1679 task.tf.lbam = bcount & 0xff; 1637 task.tf.lbam = bcount & 0xff;
1680 task.tf.lbah = (bcount >> 8) & 0xff; 1638 task.tf.lbah = (bcount >> 8) & 0xff;
1681 1639
1682 ide_tf_load(drive, &task); 1640 ide_tf_dump(drive->name, &task.tf);
1641 drive->hwif->tf_load(drive, &task);
1683} 1642}
1684 1643
1685EXPORT_SYMBOL_GPL(ide_pktcmd_tf_load); 1644EXPORT_SYMBOL_GPL(ide_pktcmd_tf_load);
1645
1646void ide_pad_transfer(ide_drive_t *drive, int write, int len)
1647{
1648 ide_hwif_t *hwif = drive->hwif;
1649 u8 buf[4] = { 0 };
1650
1651 while (len > 0) {
1652 if (write)
1653 hwif->output_data(drive, NULL, buf, min(4, len));
1654 else
1655 hwif->input_data(drive, NULL, buf, min(4, len));
1656 len -= 4;
1657 }
1658}
1659EXPORT_SYMBOL_GPL(ide_pad_transfer);
diff --git a/drivers/ide/ide-iops.c b/drivers/ide/ide-iops.c
index 5425d3038ec2..57d9a9a79a6f 100644
--- a/drivers/ide/ide-iops.c
+++ b/drivers/ide/ide-iops.c
@@ -37,21 +37,6 @@ static u8 ide_inb (unsigned long port)
37 return (u8) inb(port); 37 return (u8) inb(port);
38} 38}
39 39
40static u16 ide_inw (unsigned long port)
41{
42 return (u16) inw(port);
43}
44
45static void ide_insw (unsigned long port, void *addr, u32 count)
46{
47 insw(port, addr, count);
48}
49
50static void ide_insl (unsigned long port, void *addr, u32 count)
51{
52 insl(port, addr, count);
53}
54
55static void ide_outb (u8 val, unsigned long port) 40static void ide_outb (u8 val, unsigned long port)
56{ 41{
57 outb(val, port); 42 outb(val, port);
@@ -62,32 +47,11 @@ static void ide_outbsync (ide_drive_t *drive, u8 addr, unsigned long port)
62 outb(addr, port); 47 outb(addr, port);
63} 48}
64 49
65static void ide_outw (u16 val, unsigned long port)
66{
67 outw(val, port);
68}
69
70static void ide_outsw (unsigned long port, void *addr, u32 count)
71{
72 outsw(port, addr, count);
73}
74
75static void ide_outsl (unsigned long port, void *addr, u32 count)
76{
77 outsl(port, addr, count);
78}
79
80void default_hwif_iops (ide_hwif_t *hwif) 50void default_hwif_iops (ide_hwif_t *hwif)
81{ 51{
82 hwif->OUTB = ide_outb; 52 hwif->OUTB = ide_outb;
83 hwif->OUTBSYNC = ide_outbsync; 53 hwif->OUTBSYNC = ide_outbsync;
84 hwif->OUTW = ide_outw;
85 hwif->OUTSW = ide_outsw;
86 hwif->OUTSL = ide_outsl;
87 hwif->INB = ide_inb; 54 hwif->INB = ide_inb;
88 hwif->INW = ide_inw;
89 hwif->INSW = ide_insw;
90 hwif->INSL = ide_insl;
91} 55}
92 56
93/* 57/*
@@ -99,21 +63,6 @@ static u8 ide_mm_inb (unsigned long port)
99 return (u8) readb((void __iomem *) port); 63 return (u8) readb((void __iomem *) port);
100} 64}
101 65
102static u16 ide_mm_inw (unsigned long port)
103{
104 return (u16) readw((void __iomem *) port);
105}
106
107static void ide_mm_insw (unsigned long port, void *addr, u32 count)
108{
109 __ide_mm_insw((void __iomem *) port, addr, count);
110}
111
112static void ide_mm_insl (unsigned long port, void *addr, u32 count)
113{
114 __ide_mm_insl((void __iomem *) port, addr, count);
115}
116
117static void ide_mm_outb (u8 value, unsigned long port) 66static void ide_mm_outb (u8 value, unsigned long port)
118{ 67{
119 writeb(value, (void __iomem *) port); 68 writeb(value, (void __iomem *) port);
@@ -124,34 +73,13 @@ static void ide_mm_outbsync (ide_drive_t *drive, u8 value, unsigned long port)
124 writeb(value, (void __iomem *) port); 73 writeb(value, (void __iomem *) port);
125} 74}
126 75
127static void ide_mm_outw (u16 value, unsigned long port)
128{
129 writew(value, (void __iomem *) port);
130}
131
132static void ide_mm_outsw (unsigned long port, void *addr, u32 count)
133{
134 __ide_mm_outsw((void __iomem *) port, addr, count);
135}
136
137static void ide_mm_outsl (unsigned long port, void *addr, u32 count)
138{
139 __ide_mm_outsl((void __iomem *) port, addr, count);
140}
141
142void default_hwif_mmiops (ide_hwif_t *hwif) 76void default_hwif_mmiops (ide_hwif_t *hwif)
143{ 77{
144 hwif->OUTB = ide_mm_outb; 78 hwif->OUTB = ide_mm_outb;
145 /* Most systems will need to override OUTBSYNC, alas however 79 /* Most systems will need to override OUTBSYNC, alas however
146 this one is controller specific! */ 80 this one is controller specific! */
147 hwif->OUTBSYNC = ide_mm_outbsync; 81 hwif->OUTBSYNC = ide_mm_outbsync;
148 hwif->OUTW = ide_mm_outw;
149 hwif->OUTSW = ide_mm_outsw;
150 hwif->OUTSL = ide_mm_outsl;
151 hwif->INB = ide_mm_inb; 82 hwif->INB = ide_mm_inb;
152 hwif->INW = ide_mm_inw;
153 hwif->INSW = ide_mm_insw;
154 hwif->INSL = ide_mm_insl;
155} 83}
156 84
157EXPORT_SYMBOL(default_hwif_mmiops); 85EXPORT_SYMBOL(default_hwif_mmiops);
@@ -175,6 +103,123 @@ void SELECT_MASK (ide_drive_t *drive, int mask)
175 port_ops->maskproc(drive, mask); 103 port_ops->maskproc(drive, mask);
176} 104}
177 105
106static void ide_tf_load(ide_drive_t *drive, ide_task_t *task)
107{
108 ide_hwif_t *hwif = drive->hwif;
109 struct ide_io_ports *io_ports = &hwif->io_ports;
110 struct ide_taskfile *tf = &task->tf;
111 void (*tf_outb)(u8 addr, unsigned long port);
112 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
113 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
114
115 if (mmio)
116 tf_outb = ide_mm_outb;
117 else
118 tf_outb = ide_outb;
119
120 if (task->tf_flags & IDE_TFLAG_FLAGGED)
121 HIHI = 0xFF;
122
123 ide_set_irq(drive, 1);
124
125 if ((task->tf_flags & IDE_TFLAG_NO_SELECT_MASK) == 0)
126 SELECT_MASK(drive, 0);
127
128 if (task->tf_flags & IDE_TFLAG_OUT_DATA) {
129 u16 data = (tf->hob_data << 8) | tf->data;
130
131 if (mmio)
132 writew(data, (void __iomem *)io_ports->data_addr);
133 else
134 outw(data, io_ports->data_addr);
135 }
136
137 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
138 tf_outb(tf->hob_feature, io_ports->feature_addr);
139 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
140 tf_outb(tf->hob_nsect, io_ports->nsect_addr);
141 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
142 tf_outb(tf->hob_lbal, io_ports->lbal_addr);
143 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
144 tf_outb(tf->hob_lbam, io_ports->lbam_addr);
145 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
146 tf_outb(tf->hob_lbah, io_ports->lbah_addr);
147
148 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
149 tf_outb(tf->feature, io_ports->feature_addr);
150 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
151 tf_outb(tf->nsect, io_ports->nsect_addr);
152 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
153 tf_outb(tf->lbal, io_ports->lbal_addr);
154 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
155 tf_outb(tf->lbam, io_ports->lbam_addr);
156 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
157 tf_outb(tf->lbah, io_ports->lbah_addr);
158
159 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
160 tf_outb((tf->device & HIHI) | drive->select.all,
161 io_ports->device_addr);
162}
163
164static void ide_tf_read(ide_drive_t *drive, ide_task_t *task)
165{
166 ide_hwif_t *hwif = drive->hwif;
167 struct ide_io_ports *io_ports = &hwif->io_ports;
168 struct ide_taskfile *tf = &task->tf;
169 void (*tf_outb)(u8 addr, unsigned long port);
170 u8 (*tf_inb)(unsigned long port);
171 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
172
173 if (mmio) {
174 tf_outb = ide_mm_outb;
175 tf_inb = ide_mm_inb;
176 } else {
177 tf_outb = ide_outb;
178 tf_inb = ide_inb;
179 }
180
181 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
182 u16 data;
183
184 if (mmio)
185 data = readw((void __iomem *)io_ports->data_addr);
186 else
187 data = inw(io_ports->data_addr);
188
189 tf->data = data & 0xff;
190 tf->hob_data = (data >> 8) & 0xff;
191 }
192
193 /* be sure we're looking at the low order bits */
194 tf_outb(drive->ctl & ~0x80, io_ports->ctl_addr);
195
196 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
197 tf->nsect = tf_inb(io_ports->nsect_addr);
198 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
199 tf->lbal = tf_inb(io_ports->lbal_addr);
200 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
201 tf->lbam = tf_inb(io_ports->lbam_addr);
202 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
203 tf->lbah = tf_inb(io_ports->lbah_addr);
204 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
205 tf->device = tf_inb(io_ports->device_addr);
206
207 if (task->tf_flags & IDE_TFLAG_LBA48) {
208 tf_outb(drive->ctl | 0x80, io_ports->ctl_addr);
209
210 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
211 tf->hob_feature = tf_inb(io_ports->feature_addr);
212 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
213 tf->hob_nsect = tf_inb(io_ports->nsect_addr);
214 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
215 tf->hob_lbal = tf_inb(io_ports->lbal_addr);
216 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
217 tf->hob_lbam = tf_inb(io_ports->lbam_addr);
218 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
219 tf->hob_lbah = tf_inb(io_ports->lbah_addr);
220 }
221}
222
178/* 223/*
179 * Some localbus EIDE interfaces require a special access sequence 224 * Some localbus EIDE interfaces require a special access sequence
180 * when using 32-bit I/O instructions to transfer data. We call this 225 * when using 32-bit I/O instructions to transfer data. We call this
@@ -182,109 +227,112 @@ void SELECT_MASK (ide_drive_t *drive, int mask)
182 * of the sector count register location, with interrupts disabled 227 * of the sector count register location, with interrupts disabled
183 * to ensure that the reads all happen together. 228 * to ensure that the reads all happen together.
184 */ 229 */
185static void ata_vlb_sync(ide_drive_t *drive, unsigned long port) 230static void ata_vlb_sync(unsigned long port)
186{ 231{
187 (void) HWIF(drive)->INB(port); 232 (void)inb(port);
188 (void) HWIF(drive)->INB(port); 233 (void)inb(port);
189 (void) HWIF(drive)->INB(port); 234 (void)inb(port);
190} 235}
191 236
192/* 237/*
193 * This is used for most PIO data transfers *from* the IDE interface 238 * This is used for most PIO data transfers *from* the IDE interface
239 *
240 * These routines will round up any request for an odd number of bytes,
241 * so if an odd len is specified, be sure that there's at least one
242 * extra byte allocated for the buffer.
194 */ 243 */
195static void ata_input_data(ide_drive_t *drive, void *buffer, u32 wcount) 244static void ata_input_data(ide_drive_t *drive, struct request *rq,
245 void *buf, unsigned int len)
196{ 246{
197 ide_hwif_t *hwif = drive->hwif; 247 ide_hwif_t *hwif = drive->hwif;
198 struct ide_io_ports *io_ports = &hwif->io_ports; 248 struct ide_io_ports *io_ports = &hwif->io_ports;
249 unsigned long data_addr = io_ports->data_addr;
199 u8 io_32bit = drive->io_32bit; 250 u8 io_32bit = drive->io_32bit;
251 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
252
253 len++;
200 254
201 if (io_32bit) { 255 if (io_32bit) {
202 if (io_32bit & 2) { 256 unsigned long uninitialized_var(flags);
203 unsigned long flags;
204 257
258 if ((io_32bit & 2) && !mmio) {
205 local_irq_save(flags); 259 local_irq_save(flags);
206 ata_vlb_sync(drive, io_ports->nsect_addr); 260 ata_vlb_sync(io_ports->nsect_addr);
207 hwif->INSL(io_ports->data_addr, buffer, wcount); 261 }
262
263 if (mmio)
264 __ide_mm_insl((void __iomem *)data_addr, buf, len / 4);
265 else
266 insl(data_addr, buf, len / 4);
267
268 if ((io_32bit & 2) && !mmio)
208 local_irq_restore(flags); 269 local_irq_restore(flags);
209 } else 270
210 hwif->INSL(io_ports->data_addr, buffer, wcount); 271 if ((len & 3) >= 2) {
211 } else 272 if (mmio)
212 hwif->INSW(io_ports->data_addr, buffer, wcount << 1); 273 __ide_mm_insw((void __iomem *)data_addr,
274 (u8 *)buf + (len & ~3), 1);
275 else
276 insw(data_addr, (u8 *)buf + (len & ~3), 1);
277 }
278 } else {
279 if (mmio)
280 __ide_mm_insw((void __iomem *)data_addr, buf, len / 2);
281 else
282 insw(data_addr, buf, len / 2);
283 }
213} 284}
214 285
215/* 286/*
216 * This is used for most PIO data transfers *to* the IDE interface 287 * This is used for most PIO data transfers *to* the IDE interface
217 */ 288 */
218static void ata_output_data(ide_drive_t *drive, void *buffer, u32 wcount) 289static void ata_output_data(ide_drive_t *drive, struct request *rq,
290 void *buf, unsigned int len)
219{ 291{
220 ide_hwif_t *hwif = drive->hwif; 292 ide_hwif_t *hwif = drive->hwif;
221 struct ide_io_ports *io_ports = &hwif->io_ports; 293 struct ide_io_ports *io_ports = &hwif->io_ports;
294 unsigned long data_addr = io_ports->data_addr;
222 u8 io_32bit = drive->io_32bit; 295 u8 io_32bit = drive->io_32bit;
296 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
223 297
224 if (io_32bit) { 298 if (io_32bit) {
225 if (io_32bit & 2) { 299 unsigned long uninitialized_var(flags);
226 unsigned long flags;
227 300
301 if ((io_32bit & 2) && !mmio) {
228 local_irq_save(flags); 302 local_irq_save(flags);
229 ata_vlb_sync(drive, io_ports->nsect_addr); 303 ata_vlb_sync(io_ports->nsect_addr);
230 hwif->OUTSL(io_ports->data_addr, buffer, wcount); 304 }
231 local_irq_restore(flags);
232 } else
233 hwif->OUTSL(io_ports->data_addr, buffer, wcount);
234 } else
235 hwif->OUTSW(io_ports->data_addr, buffer, wcount << 1);
236}
237
238/*
239 * The following routines are mainly used by the ATAPI drivers.
240 *
241 * These routines will round up any request for an odd number of bytes,
242 * so if an odd bytecount is specified, be sure that there's at least one
243 * extra byte allocated for the buffer.
244 */
245
246static void atapi_input_bytes(ide_drive_t *drive, void *buffer, u32 bytecount)
247{
248 ide_hwif_t *hwif = HWIF(drive);
249 305
250 ++bytecount; 306 if (mmio)
251#if defined(CONFIG_ATARI) || defined(CONFIG_Q40) 307 __ide_mm_outsl((void __iomem *)data_addr, buf, len / 4);
252 if (MACH_IS_ATARI || MACH_IS_Q40) { 308 else
253 /* Atari has a byte-swapped IDE interface */ 309 outsl(data_addr, buf, len / 4);
254 insw_swapw(hwif->io_ports.data_addr, buffer, bytecount / 2);
255 return;
256 }
257#endif /* CONFIG_ATARI || CONFIG_Q40 */
258 hwif->ata_input_data(drive, buffer, bytecount / 4);
259 if ((bytecount & 0x03) >= 2)
260 hwif->INSW(hwif->io_ports.data_addr,
261 (u8 *)buffer + (bytecount & ~0x03), 1);
262}
263 310
264static void atapi_output_bytes(ide_drive_t *drive, void *buffer, u32 bytecount) 311 if ((io_32bit & 2) && !mmio)
265{ 312 local_irq_restore(flags);
266 ide_hwif_t *hwif = HWIF(drive);
267 313
268 ++bytecount; 314 if ((len & 3) >= 2) {
269#if defined(CONFIG_ATARI) || defined(CONFIG_Q40) 315 if (mmio)
270 if (MACH_IS_ATARI || MACH_IS_Q40) { 316 __ide_mm_outsw((void __iomem *)data_addr,
271 /* Atari has a byte-swapped IDE interface */ 317 (u8 *)buf + (len & ~3), 1);
272 outsw_swapw(hwif->io_ports.data_addr, buffer, bytecount / 2); 318 else
273 return; 319 outsw(data_addr, (u8 *)buf + (len & ~3), 1);
320 }
321 } else {
322 if (mmio)
323 __ide_mm_outsw((void __iomem *)data_addr, buf, len / 2);
324 else
325 outsw(data_addr, buf, len / 2);
274 } 326 }
275#endif /* CONFIG_ATARI || CONFIG_Q40 */
276 hwif->ata_output_data(drive, buffer, bytecount / 4);
277 if ((bytecount & 0x03) >= 2)
278 hwif->OUTSW(hwif->io_ports.data_addr,
279 (u8 *)buffer + (bytecount & ~0x03), 1);
280} 327}
281 328
282void default_hwif_transport(ide_hwif_t *hwif) 329void default_hwif_transport(ide_hwif_t *hwif)
283{ 330{
284 hwif->ata_input_data = ata_input_data; 331 hwif->tf_load = ide_tf_load;
285 hwif->ata_output_data = ata_output_data; 332 hwif->tf_read = ide_tf_read;
286 hwif->atapi_input_bytes = atapi_input_bytes; 333
287 hwif->atapi_output_bytes = atapi_output_bytes; 334 hwif->input_data = ata_input_data;
335 hwif->output_data = ata_output_data;
288} 336}
289 337
290void ide_fix_driveid (struct hd_driveid *id) 338void ide_fix_driveid (struct hd_driveid *id)
@@ -577,6 +625,8 @@ static const struct drive_list_entry ivb_list[] = {
577 { "TSSTcorp CDDVDW SH-S202J" , "SB01" }, 625 { "TSSTcorp CDDVDW SH-S202J" , "SB01" },
578 { "TSSTcorp CDDVDW SH-S202N" , "SB00" }, 626 { "TSSTcorp CDDVDW SH-S202N" , "SB00" },
579 { "TSSTcorp CDDVDW SH-S202N" , "SB01" }, 627 { "TSSTcorp CDDVDW SH-S202N" , "SB01" },
628 { "TSSTcorp CDDVDW SH-S202H" , "SB00" },
629 { "TSSTcorp CDDVDW SH-S202H" , "SB01" },
580 { NULL , NULL } 630 { NULL , NULL }
581}; 631};
582 632
@@ -641,7 +691,7 @@ int ide_driveid_update(ide_drive_t *drive)
641 SELECT_MASK(drive, 1); 691 SELECT_MASK(drive, 1);
642 ide_set_irq(drive, 1); 692 ide_set_irq(drive, 1);
643 msleep(50); 693 msleep(50);
644 hwif->OUTB(WIN_IDENTIFY, hwif->io_ports.command_addr); 694 hwif->OUTBSYNC(drive, WIN_IDENTIFY, hwif->io_ports.command_addr);
645 timeout = jiffies + WAIT_WORSTCASE; 695 timeout = jiffies + WAIT_WORSTCASE;
646 do { 696 do {
647 if (time_after(jiffies, timeout)) { 697 if (time_after(jiffies, timeout)) {
@@ -668,7 +718,7 @@ int ide_driveid_update(ide_drive_t *drive)
668 local_irq_restore(flags); 718 local_irq_restore(flags);
669 return 0; 719 return 0;
670 } 720 }
671 hwif->ata_input_data(drive, id, SECTOR_WORDS); 721 hwif->input_data(drive, NULL, id, SECTOR_SIZE);
672 (void)ide_read_status(drive); /* clear drive IRQ */ 722 (void)ide_read_status(drive); /* clear drive IRQ */
673 local_irq_enable(); 723 local_irq_enable();
674 local_irq_restore(flags); 724 local_irq_restore(flags);
@@ -849,9 +899,19 @@ void ide_execute_command(ide_drive_t *drive, u8 cmd, ide_handler_t *handler,
849 ndelay(400); 899 ndelay(400);
850 spin_unlock_irqrestore(&ide_lock, flags); 900 spin_unlock_irqrestore(&ide_lock, flags);
851} 901}
852
853EXPORT_SYMBOL(ide_execute_command); 902EXPORT_SYMBOL(ide_execute_command);
854 903
904void ide_execute_pkt_cmd(ide_drive_t *drive)
905{
906 ide_hwif_t *hwif = drive->hwif;
907 unsigned long flags;
908
909 spin_lock_irqsave(&ide_lock, flags);
910 hwif->OUTBSYNC(drive, WIN_PACKETCMD, hwif->io_ports.command_addr);
911 ndelay(400);
912 spin_unlock_irqrestore(&ide_lock, flags);
913}
914EXPORT_SYMBOL_GPL(ide_execute_pkt_cmd);
855 915
856/* needed below */ 916/* needed below */
857static ide_startstop_t do_reset1 (ide_drive_t *, int); 917static ide_startstop_t do_reset1 (ide_drive_t *, int);
diff --git a/drivers/ide/ide-lib.c b/drivers/ide/ide-lib.c
index 6f04ea3e93a8..47af80df6872 100644
--- a/drivers/ide/ide-lib.c
+++ b/drivers/ide/ide-lib.c
@@ -487,7 +487,7 @@ static void ide_dump_sector(ide_drive_t *drive)
487 else 487 else
488 task.tf_flags = IDE_TFLAG_IN_LBA | IDE_TFLAG_IN_DEVICE; 488 task.tf_flags = IDE_TFLAG_IN_LBA | IDE_TFLAG_IN_DEVICE;
489 489
490 ide_tf_read(drive, &task); 490 drive->hwif->tf_read(drive, &task);
491 491
492 if (lba48 || (tf->device & ATA_LBA)) 492 if (lba48 || (tf->device & ATA_LBA))
493 printk(", LBAsect=%llu", 493 printk(", LBAsect=%llu",
diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c
index 862f02603f9b..099a0fe1745b 100644
--- a/drivers/ide/ide-probe.c
+++ b/drivers/ide/ide-probe.c
@@ -124,7 +124,7 @@ static inline void do_identify (ide_drive_t *drive, u8 cmd)
124 124
125 id = drive->id; 125 id = drive->id;
126 /* read 512 bytes of id info */ 126 /* read 512 bytes of id info */
127 hwif->ata_input_data(drive, id, SECTOR_WORDS); 127 hwif->input_data(drive, NULL, id, SECTOR_SIZE);
128 128
129 drive->id_read = 1; 129 drive->id_read = 1;
130 local_irq_enable(); 130 local_irq_enable();
@@ -293,7 +293,7 @@ static int actual_try_to_identify (ide_drive_t *drive, u8 cmd)
293 hwif->OUTB(0, io_ports->feature_addr); 293 hwif->OUTB(0, io_ports->feature_addr);
294 294
295 /* ask drive for ID */ 295 /* ask drive for ID */
296 hwif->OUTB(cmd, io_ports->command_addr); 296 hwif->OUTBSYNC(drive, cmd, io_ports->command_addr);
297 297
298 timeout = ((cmd == WIN_IDENTIFY) ? WAIT_WORSTCASE : WAIT_PIDENTIFY) / 2; 298 timeout = ((cmd == WIN_IDENTIFY) ? WAIT_WORSTCASE : WAIT_PIDENTIFY) / 2;
299 timeout += jiffies; 299 timeout += jiffies;
@@ -480,7 +480,7 @@ static int do_probe (ide_drive_t *drive, u8 cmd)
480 msleep(50); 480 msleep(50);
481 hwif->OUTB(drive->select.all, io_ports->device_addr); 481 hwif->OUTB(drive->select.all, io_ports->device_addr);
482 msleep(50); 482 msleep(50);
483 hwif->OUTB(WIN_SRST, io_ports->command_addr); 483 hwif->OUTBSYNC(drive, WIN_SRST, io_ports->command_addr);
484 (void)ide_busy_sleep(hwif); 484 (void)ide_busy_sleep(hwif);
485 rc = try_to_identify(drive, cmd); 485 rc = try_to_identify(drive, cmd);
486 } 486 }
@@ -516,7 +516,7 @@ static void enable_nest (ide_drive_t *drive)
516 printk("%s: enabling %s -- ", hwif->name, drive->id->model); 516 printk("%s: enabling %s -- ", hwif->name, drive->id->model);
517 SELECT_DRIVE(drive); 517 SELECT_DRIVE(drive);
518 msleep(50); 518 msleep(50);
519 hwif->OUTB(EXABYTE_ENABLE_NEST, hwif->io_ports.command_addr); 519 hwif->OUTBSYNC(drive, EXABYTE_ENABLE_NEST, hwif->io_ports.command_addr);
520 520
521 if (ide_busy_sleep(hwif)) { 521 if (ide_busy_sleep(hwif)) {
522 printk(KERN_CONT "failed (timeout)\n"); 522 printk(KERN_CONT "failed (timeout)\n");
diff --git a/drivers/ide/ide-tape.c b/drivers/ide/ide-tape.c
index 29870c415110..54a43b044608 100644
--- a/drivers/ide/ide-tape.c
+++ b/drivers/ide/ide-tape.c
@@ -395,13 +395,13 @@ static void idetape_input_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc,
395 if (bh == NULL) { 395 if (bh == NULL) {
396 printk(KERN_ERR "ide-tape: bh == NULL in " 396 printk(KERN_ERR "ide-tape: bh == NULL in "
397 "idetape_input_buffers\n"); 397 "idetape_input_buffers\n");
398 ide_atapi_discard_data(drive, bcount); 398 ide_pad_transfer(drive, 0, bcount);
399 return; 399 return;
400 } 400 }
401 count = min( 401 count = min(
402 (unsigned int)(bh->b_size - atomic_read(&bh->b_count)), 402 (unsigned int)(bh->b_size - atomic_read(&bh->b_count)),
403 bcount); 403 bcount);
404 HWIF(drive)->atapi_input_bytes(drive, bh->b_data + 404 drive->hwif->input_data(drive, NULL, bh->b_data +
405 atomic_read(&bh->b_count), count); 405 atomic_read(&bh->b_count), count);
406 bcount -= count; 406 bcount -= count;
407 atomic_add(count, &bh->b_count); 407 atomic_add(count, &bh->b_count);
@@ -427,7 +427,7 @@ static void idetape_output_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc,
427 return; 427 return;
428 } 428 }
429 count = min((unsigned int)pc->b_count, (unsigned int)bcount); 429 count = min((unsigned int)pc->b_count, (unsigned int)bcount);
430 HWIF(drive)->atapi_output_bytes(drive, pc->b_data, count); 430 drive->hwif->output_data(drive, NULL, pc->b_data, count);
431 bcount -= count; 431 bcount -= count;
432 pc->b_data += count; 432 pc->b_data += count;
433 pc->b_count -= count; 433 pc->b_count -= count;
@@ -871,7 +871,7 @@ static ide_startstop_t idetape_pc_intr(ide_drive_t *drive)
871 printk(KERN_ERR "ide-tape: The tape wants to " 871 printk(KERN_ERR "ide-tape: The tape wants to "
872 "send us more data than expected " 872 "send us more data than expected "
873 "- discarding data\n"); 873 "- discarding data\n");
874 ide_atapi_discard_data(drive, bcount); 874 ide_pad_transfer(drive, 0, bcount);
875 ide_set_handler(drive, &idetape_pc_intr, 875 ide_set_handler(drive, &idetape_pc_intr,
876 IDETAPE_WAIT_CMD, NULL); 876 IDETAPE_WAIT_CMD, NULL);
877 return ide_started; 877 return ide_started;
@@ -880,16 +880,16 @@ static ide_startstop_t idetape_pc_intr(ide_drive_t *drive)
880 "data than expected - allowing transfer\n"); 880 "data than expected - allowing transfer\n");
881 } 881 }
882 iobuf = &idetape_input_buffers; 882 iobuf = &idetape_input_buffers;
883 xferfunc = hwif->atapi_input_bytes; 883 xferfunc = hwif->input_data;
884 } else { 884 } else {
885 iobuf = &idetape_output_buffers; 885 iobuf = &idetape_output_buffers;
886 xferfunc = hwif->atapi_output_bytes; 886 xferfunc = hwif->output_data;
887 } 887 }
888 888
889 if (pc->bh) 889 if (pc->bh)
890 iobuf(drive, pc, bcount); 890 iobuf(drive, pc, bcount);
891 else 891 else
892 xferfunc(drive, pc->cur_pos, bcount); 892 xferfunc(drive, NULL, pc->cur_pos, bcount);
893 893
894 /* Update the current position */ 894 /* Update the current position */
895 pc->xferred += bcount; 895 pc->xferred += bcount;
@@ -979,7 +979,8 @@ static ide_startstop_t idetape_transfer_pc(ide_drive_t *drive)
979 hwif->dma_ops->dma_start(drive); 979 hwif->dma_ops->dma_start(drive);
980#endif 980#endif
981 /* Send the actual packet */ 981 /* Send the actual packet */
982 HWIF(drive)->atapi_output_bytes(drive, pc->c, 12); 982 hwif->output_data(drive, NULL, pc->c, 12);
983
983 return ide_started; 984 return ide_started;
984} 985}
985 986
@@ -1055,7 +1056,7 @@ static ide_startstop_t idetape_issue_pc(ide_drive_t *drive,
1055 IDETAPE_WAIT_CMD, NULL); 1056 IDETAPE_WAIT_CMD, NULL);
1056 return ide_started; 1057 return ide_started;
1057 } else { 1058 } else {
1058 hwif->OUTB(WIN_PACKETCMD, hwif->io_ports.command_addr); 1059 ide_execute_pkt_cmd(drive);
1059 return idetape_transfer_pc(drive); 1060 return idetape_transfer_pc(drive);
1060 } 1061 }
1061} 1062}
diff --git a/drivers/ide/ide-taskfile.c b/drivers/ide/ide-taskfile.c
index 9f9ad9fb6b89..9a846a0cd5a4 100644
--- a/drivers/ide/ide-taskfile.c
+++ b/drivers/ide/ide-taskfile.c
@@ -33,60 +33,18 @@
33#include <asm/uaccess.h> 33#include <asm/uaccess.h>
34#include <asm/io.h> 34#include <asm/io.h>
35 35
36void ide_tf_load(ide_drive_t *drive, ide_task_t *task) 36void ide_tf_dump(const char *s, struct ide_taskfile *tf)
37{ 37{
38 ide_hwif_t *hwif = drive->hwif;
39 struct ide_io_ports *io_ports = &hwif->io_ports;
40 struct ide_taskfile *tf = &task->tf;
41 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
42
43 if (task->tf_flags & IDE_TFLAG_FLAGGED)
44 HIHI = 0xFF;
45
46#ifdef DEBUG 38#ifdef DEBUG
47 printk("%s: tf: feat 0x%02x nsect 0x%02x lbal 0x%02x " 39 printk("%s: tf: feat 0x%02x nsect 0x%02x lbal 0x%02x "
48 "lbam 0x%02x lbah 0x%02x dev 0x%02x cmd 0x%02x\n", 40 "lbam 0x%02x lbah 0x%02x dev 0x%02x cmd 0x%02x\n",
49 drive->name, tf->feature, tf->nsect, tf->lbal, 41 s, tf->feature, tf->nsect, tf->lbal,
50 tf->lbam, tf->lbah, tf->device, tf->command); 42 tf->lbam, tf->lbah, tf->device, tf->command);
51 printk("%s: hob: nsect 0x%02x lbal 0x%02x " 43 printk("%s: hob: nsect 0x%02x lbal 0x%02x "
52 "lbam 0x%02x lbah 0x%02x\n", 44 "lbam 0x%02x lbah 0x%02x\n",
53 drive->name, tf->hob_nsect, tf->hob_lbal, 45 s, tf->hob_nsect, tf->hob_lbal,
54 tf->hob_lbam, tf->hob_lbah); 46 tf->hob_lbam, tf->hob_lbah);
55#endif 47#endif
56
57 ide_set_irq(drive, 1);
58
59 if ((task->tf_flags & IDE_TFLAG_NO_SELECT_MASK) == 0)
60 SELECT_MASK(drive, 0);
61
62 if (task->tf_flags & IDE_TFLAG_OUT_DATA)
63 hwif->OUTW((tf->hob_data << 8) | tf->data, io_ports->data_addr);
64
65 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
66 hwif->OUTB(tf->hob_feature, io_ports->feature_addr);
67 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
68 hwif->OUTB(tf->hob_nsect, io_ports->nsect_addr);
69 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
70 hwif->OUTB(tf->hob_lbal, io_ports->lbal_addr);
71 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
72 hwif->OUTB(tf->hob_lbam, io_ports->lbam_addr);
73 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
74 hwif->OUTB(tf->hob_lbah, io_ports->lbah_addr);
75
76 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
77 hwif->OUTB(tf->feature, io_ports->feature_addr);
78 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
79 hwif->OUTB(tf->nsect, io_ports->nsect_addr);
80 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
81 hwif->OUTB(tf->lbal, io_ports->lbal_addr);
82 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
83 hwif->OUTB(tf->lbam, io_ports->lbam_addr);
84 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
85 hwif->OUTB(tf->lbah, io_ports->lbah_addr);
86
87 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
88 hwif->OUTB((tf->device & HIHI) | drive->select.all,
89 io_ports->device_addr);
90} 48}
91 49
92int taskfile_lib_get_identify (ide_drive_t *drive, u8 *buf) 50int taskfile_lib_get_identify (ide_drive_t *drive, u8 *buf)
@@ -149,8 +107,10 @@ ide_startstop_t do_rw_taskfile (ide_drive_t *drive, ide_task_t *task)
149 if (task->tf_flags & IDE_TFLAG_FLAGGED) 107 if (task->tf_flags & IDE_TFLAG_FLAGGED)
150 task->tf_flags |= IDE_TFLAG_FLAGGED_SET_IN_FLAGS; 108 task->tf_flags |= IDE_TFLAG_FLAGGED_SET_IN_FLAGS;
151 109
152 if ((task->tf_flags & IDE_TFLAG_DMA_PIO_FALLBACK) == 0) 110 if ((task->tf_flags & IDE_TFLAG_DMA_PIO_FALLBACK) == 0) {
153 ide_tf_load(drive, task); 111 ide_tf_dump(drive->name, tf);
112 hwif->tf_load(drive, task);
113 }
154 114
155 switch (task->data_phase) { 115 switch (task->data_phase) {
156 case TASKFILE_MULTI_OUT: 116 case TASKFILE_MULTI_OUT:
@@ -283,7 +243,8 @@ static u8 wait_drive_not_busy(ide_drive_t *drive)
283 return stat; 243 return stat;
284} 244}
285 245
286static void ide_pio_sector(ide_drive_t *drive, unsigned int write) 246static void ide_pio_sector(ide_drive_t *drive, struct request *rq,
247 unsigned int write)
287{ 248{
288 ide_hwif_t *hwif = drive->hwif; 249 ide_hwif_t *hwif = drive->hwif;
289 struct scatterlist *sg = hwif->sg_table; 250 struct scatterlist *sg = hwif->sg_table;
@@ -323,9 +284,9 @@ static void ide_pio_sector(ide_drive_t *drive, unsigned int write)
323 284
324 /* do the actual data transfer */ 285 /* do the actual data transfer */
325 if (write) 286 if (write)
326 hwif->ata_output_data(drive, buf, SECTOR_WORDS); 287 hwif->output_data(drive, rq, buf, SECTOR_SIZE);
327 else 288 else
328 hwif->ata_input_data(drive, buf, SECTOR_WORDS); 289 hwif->input_data(drive, rq, buf, SECTOR_SIZE);
329 290
330 kunmap_atomic(buf, KM_BIO_SRC_IRQ); 291 kunmap_atomic(buf, KM_BIO_SRC_IRQ);
331#ifdef CONFIG_HIGHMEM 292#ifdef CONFIG_HIGHMEM
@@ -333,13 +294,14 @@ static void ide_pio_sector(ide_drive_t *drive, unsigned int write)
333#endif 294#endif
334} 295}
335 296
336static void ide_pio_multi(ide_drive_t *drive, unsigned int write) 297static void ide_pio_multi(ide_drive_t *drive, struct request *rq,
298 unsigned int write)
337{ 299{
338 unsigned int nsect; 300 unsigned int nsect;
339 301
340 nsect = min_t(unsigned int, drive->hwif->nleft, drive->mult_count); 302 nsect = min_t(unsigned int, drive->hwif->nleft, drive->mult_count);
341 while (nsect--) 303 while (nsect--)
342 ide_pio_sector(drive, write); 304 ide_pio_sector(drive, rq, write);
343} 305}
344 306
345static void ide_pio_datablock(ide_drive_t *drive, struct request *rq, 307static void ide_pio_datablock(ide_drive_t *drive, struct request *rq,
@@ -362,10 +324,10 @@ static void ide_pio_datablock(ide_drive_t *drive, struct request *rq,
362 switch (drive->hwif->data_phase) { 324 switch (drive->hwif->data_phase) {
363 case TASKFILE_MULTI_IN: 325 case TASKFILE_MULTI_IN:
364 case TASKFILE_MULTI_OUT: 326 case TASKFILE_MULTI_OUT:
365 ide_pio_multi(drive, write); 327 ide_pio_multi(drive, rq, write);
366 break; 328 break;
367 default: 329 default:
368 ide_pio_sector(drive, write); 330 ide_pio_sector(drive, rq, write);
369 break; 331 break;
370 } 332 }
371 333
diff --git a/drivers/ide/legacy/falconide.c b/drivers/ide/legacy/falconide.c
index 56cdaa0eeea5..83555ca513b5 100644
--- a/drivers/ide/legacy/falconide.c
+++ b/drivers/ide/legacy/falconide.c
@@ -44,6 +44,28 @@
44int falconide_intr_lock; 44int falconide_intr_lock;
45EXPORT_SYMBOL(falconide_intr_lock); 45EXPORT_SYMBOL(falconide_intr_lock);
46 46
47static void falconide_input_data(ide_drive_t *drive, struct request *rq,
48 void *buf, unsigned int len)
49{
50 unsigned long data_addr = drive->hwif->io_ports.data_addr;
51
52 if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
53 return insw(data_addr, buf, (len + 1) / 2);
54
55 insw_swapw(data_addr, buf, (len + 1) / 2);
56}
57
58static void falconide_output_data(ide_drive_t *drive, struct request *rq,
59 void *buf, unsigned int len)
60{
61 unsigned long data_addr = drive->hwif->io_ports.data_addr;
62
63 if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
64 return outsw(data_adr, buf, (len + 1) / 2);
65
66 outsw_swapw(data_addr, buf, (len + 1) / 2);
67}
68
47static void __init falconide_setup_ports(hw_regs_t *hw) 69static void __init falconide_setup_ports(hw_regs_t *hw)
48{ 70{
49 int i; 71 int i;
@@ -90,6 +112,10 @@ static int __init falconide_init(void)
90 ide_init_port_data(hwif, index); 112 ide_init_port_data(hwif, index);
91 ide_init_port_hw(hwif, &hw); 113 ide_init_port_hw(hwif, &hw);
92 114
115 /* Atari has a byte-swapped IDE interface */
116 hwif->input_data = falconide_input_data;
117 hwif->output_data = falconide_output_data;
118
93 ide_get_lock(NULL, NULL); 119 ide_get_lock(NULL, NULL);
94 ide_device_add(idx, NULL); 120 ide_device_add(idx, NULL);
95 ide_release_lock(); 121 ide_release_lock();
diff --git a/drivers/ide/legacy/ide_platform.c b/drivers/ide/legacy/ide_platform.c
index 8279dc7ca4c0..d3bc3f24e05d 100644
--- a/drivers/ide/legacy/ide_platform.c
+++ b/drivers/ide/legacy/ide_platform.c
@@ -101,8 +101,10 @@ static int __devinit plat_ide_probe(struct platform_device *pdev)
101 101
102 ide_init_port_hw(hwif, &hw); 102 ide_init_port_hw(hwif, &hw);
103 103
104 if (mmio) 104 if (mmio) {
105 hwif->host_flags = IDE_HFLAG_MMIO;
105 default_hwif_mmiops(hwif); 106 default_hwif_mmiops(hwif);
107 }
106 108
107 idx[0] = hwif->index; 109 idx[0] = hwif->index;
108 110
diff --git a/drivers/ide/legacy/q40ide.c b/drivers/ide/legacy/q40ide.c
index f9210458aea0..6f535d00e638 100644
--- a/drivers/ide/legacy/q40ide.c
+++ b/drivers/ide/legacy/q40ide.c
@@ -72,7 +72,27 @@ static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
72 hw->ack_intr = ack_intr; 72 hw->ack_intr = ack_intr;
73} 73}
74 74
75static void q40ide_input_data(ide_drive_t *drive, struct request *rq,
76 void *buf, unsigned int len)
77{
78 unsigned long data_addr = drive->hwif->io_ports.data_addr;
79
80 if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
81 return insw(data_addr, buf, (len + 1) / 2);
75 82
83 insw_swapw(data_addr, buf, (len + 1) / 2);
84}
85
86static void q40ide_output_data(ide_drive_t *drive, struct request *rq,
87 void *buf, unsigned int len)
88{
89 unsigned long data_addr = drive->hwif->io_ports.data_addr;
90
91 if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
92 return outsw(data_addr, buf, (len + 1) / 2);
93
94 outsw_swapw(data_addr, buf, (len + 1) / 2);
95}
76 96
77/* 97/*
78 * the static array is needed to have the name reported in /proc/ioports, 98 * the static array is needed to have the name reported in /proc/ioports,
@@ -123,6 +143,10 @@ static int __init q40ide_init(void)
123 ide_init_port_data(hwif, hwif->index); 143 ide_init_port_data(hwif, hwif->index);
124 ide_init_port_hw(hwif, &hw); 144 ide_init_port_hw(hwif, &hw);
125 145
146 /* Q40 has a byte-swapped IDE interface */
147 hwif->input_data = q40ide_input_data;
148 hwif->output_data = q40ide_output_data;
149
126 idx[i] = hwif->index; 150 idx[i] = hwif->index;
127 } 151 }
128 } 152 }
diff --git a/drivers/ide/mips/au1xxx-ide.c b/drivers/ide/mips/au1xxx-ide.c
index e0cf5e2dbab7..1a6c27b32498 100644
--- a/drivers/ide/mips/au1xxx-ide.c
+++ b/drivers/ide/mips/au1xxx-ide.c
@@ -48,8 +48,6 @@
48 48
49static _auide_hwif auide_hwif; 49static _auide_hwif auide_hwif;
50 50
51static int auide_ddma_init(_auide_hwif *auide);
52
53#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) 51#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
54 52
55void auide_insw(unsigned long port, void *addr, u32 count) 53void auide_insw(unsigned long port, void *addr, u32 count)
@@ -88,6 +86,17 @@ void auide_outsw(unsigned long port, void *addr, u32 count)
88 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); 86 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
89} 87}
90 88
89static void au1xxx_input_data(ide_drive_t *drive, struct request *rq,
90 void *buf, unsigned int len)
91{
92 auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
93}
94
95static void au1xxx_output_data(ide_drive_t *drive, struct request *rq,
96 void *buf, unsigned int len)
97{
98 auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
99}
91#endif 100#endif
92 101
93static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio) 102static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
@@ -598,8 +607,8 @@ static int au_ide_probe(struct device *dev)
598 */ 607 */
599 608
600#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA 609#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
601 hwif->INSW = auide_insw; 610 hwif->input_data = au1xxx_input_data;
602 hwif->OUTSW = auide_outsw; 611 hwif->output_data = au1xxx_output_data;
603#endif 612#endif
604 hwif->select_data = 0; /* no chipset-specific code */ 613 hwif->select_data = 0; /* no chipset-specific code */
605 hwif->config_data = 0; /* no chipset-specific code */ 614 hwif->config_data = 0; /* no chipset-specific code */
diff --git a/drivers/ide/mips/swarm.c b/drivers/ide/mips/swarm.c
index 68947626e4aa..712d17bdd470 100644
--- a/drivers/ide/mips/swarm.c
+++ b/drivers/ide/mips/swarm.c
@@ -109,6 +109,7 @@ static int __devinit swarm_ide_probe(struct device *dev)
109 base = ioremap(offset, size); 109 base = ioremap(offset, size);
110 110
111 /* Setup MMIO ops. */ 111 /* Setup MMIO ops. */
112 hwif->host_flags = IDE_HFLAG_MMIO;
112 default_hwif_mmiops(hwif); 113 default_hwif_mmiops(hwif);
113 114
114 hwif->chipset = ide_generic; 115 hwif->chipset = ide_generic;
diff --git a/drivers/ide/pci/ns87415.c b/drivers/ide/pci/ns87415.c
index c13e299077ec..fec4955f449b 100644
--- a/drivers/ide/pci/ns87415.c
+++ b/drivers/ide/pci/ns87415.c
@@ -63,6 +63,48 @@ static u8 superio_ide_inb (unsigned long port)
63 return inb(port); 63 return inb(port);
64} 64}
65 65
66static void superio_tf_read(ide_drive_t *drive, ide_task_t *task)
67{
68 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
69 struct ide_taskfile *tf = &task->tf;
70
71 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
72 u16 data = inw(io_ports->data_addr);
73
74 tf->data = data & 0xff;
75 tf->hob_data = (data >> 8) & 0xff;
76 }
77
78 /* be sure we're looking at the low order bits */
79 outb(drive->ctl & ~0x80, io_ports->ctl_addr);
80
81 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
82 tf->nsect = inb(io_ports->nsect_addr);
83 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
84 tf->lbal = inb(io_ports->lbal_addr);
85 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
86 tf->lbam = inb(io_ports->lbam_addr);
87 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
88 tf->lbah = inb(io_ports->lbah_addr);
89 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
90 tf->device = superio_ide_inb(io_ports->device_addr);
91
92 if (task->tf_flags & IDE_TFLAG_LBA48) {
93 outb(drive->ctl | 0x80, io_ports->ctl_addr);
94
95 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
96 tf->hob_feature = inb(io_ports->feature_addr);
97 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
98 tf->hob_nsect = inb(io_ports->nsect_addr);
99 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
100 tf->hob_lbal = inb(io_ports->lbal_addr);
101 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
102 tf->hob_lbam = inb(io_ports->lbam_addr);
103 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
104 tf->hob_lbah = inb(io_ports->lbah_addr);
105 }
106}
107
66static void __devinit superio_ide_init_iops (struct hwif_s *hwif) 108static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
67{ 109{
68 struct pci_dev *pdev = to_pci_dev(hwif->dev); 110 struct pci_dev *pdev = to_pci_dev(hwif->dev);
@@ -80,6 +122,8 @@ static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
80 tmp = superio_ide_inb(superio_ide_dma_status[port]); 122 tmp = superio_ide_inb(superio_ide_dma_status[port]);
81 outb(tmp | 0x66, superio_ide_dma_status[port]); 123 outb(tmp | 0x66, superio_ide_dma_status[port]);
82 124
125 hwif->tf_read = superio_tf_read;
126
83 /* We need to override inb to workaround a SuperIO errata */ 127 /* We need to override inb to workaround a SuperIO errata */
84 hwif->INB = superio_ide_inb; 128 hwif->INB = superio_ide_inb;
85} 129}
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index ec9bd7b352fc..070df8ab3b21 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -83,8 +83,8 @@ static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
83{ 83{
84 u8 value; 84 u8 value;
85 85
86 outb(index, hwif->dma_vendor1); 86 outb(index, hwif->dma_base + 1);
87 value = inb(hwif->dma_vendor3); 87 value = inb(hwif->dma_base + 3);
88 88
89 DBG("index[%02X] value[%02X]\n", index, value); 89 DBG("index[%02X] value[%02X]\n", index, value);
90 return value; 90 return value;
@@ -97,8 +97,8 @@ static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
97 */ 97 */
98static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value) 98static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
99{ 99{
100 outb(index, hwif->dma_vendor1); 100 outb(index, hwif->dma_base + 1);
101 outb(value, hwif->dma_vendor3); 101 outb(value, hwif->dma_base + 3);
102 DBG("index[%02X] value[%02X]\n", index, value); 102 DBG("index[%02X] value[%02X]\n", index, value);
103} 103}
104 104
diff --git a/drivers/ide/pci/piix.c b/drivers/ide/pci/piix.c
index 21c5dd23f928..f04738d14a6f 100644
--- a/drivers/ide/pci/piix.c
+++ b/drivers/ide/pci/piix.c
@@ -250,6 +250,7 @@ static const struct ich_laptop ich_laptop[] = {
250 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 250 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
251 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 251 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
252 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */ 252 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
253 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
253 /* end marker */ 254 /* end marker */
254 { 0, } 255 { 0, }
255}; 256};
diff --git a/drivers/ide/pci/scc_pata.c b/drivers/ide/pci/scc_pata.c
index ad7cdf9060ca..910fb00deb71 100644
--- a/drivers/ide/pci/scc_pata.c
+++ b/drivers/ide/pci/scc_pata.c
@@ -126,12 +126,6 @@ static u8 scc_ide_inb(unsigned long port)
126 return (u8)data; 126 return (u8)data;
127} 127}
128 128
129static u16 scc_ide_inw(unsigned long port)
130{
131 u32 data = in_be32((void*)port);
132 return (u16)data;
133}
134
135static void scc_ide_insw(unsigned long port, void *addr, u32 count) 129static void scc_ide_insw(unsigned long port, void *addr, u32 count)
136{ 130{
137 u16 *ptr = (u16 *)addr; 131 u16 *ptr = (u16 *)addr;
@@ -154,11 +148,6 @@ static void scc_ide_outb(u8 addr, unsigned long port)
154 out_be32((void*)port, addr); 148 out_be32((void*)port, addr);
155} 149}
156 150
157static void scc_ide_outw(u16 addr, unsigned long port)
158{
159 out_be32((void*)port, addr);
160}
161
162static void 151static void
163scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port) 152scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
164{ 153{
@@ -271,6 +260,20 @@ static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
271 out_be32((void __iomem *)udenvt_port, reg); 260 out_be32((void __iomem *)udenvt_port, reg);
272} 261}
273 262
263static void scc_dma_host_set(ide_drive_t *drive, int on)
264{
265 ide_hwif_t *hwif = drive->hwif;
266 u8 unit = (drive->select.b.unit & 0x01);
267 u8 dma_stat = scc_ide_inb(hwif->dma_status);
268
269 if (on)
270 dma_stat |= (1 << (5 + unit));
271 else
272 dma_stat &= ~(1 << (5 + unit));
273
274 scc_ide_outb(dma_stat, hwif->dma_status);
275}
276
274/** 277/**
275 * scc_ide_dma_setup - begin a DMA phase 278 * scc_ide_dma_setup - begin a DMA phase
276 * @drive: target device 279 * @drive: target device
@@ -301,7 +304,7 @@ static int scc_dma_setup(ide_drive_t *drive)
301 } 304 }
302 305
303 /* PRD table */ 306 /* PRD table */
304 out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma); 307 out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
305 308
306 /* specify r/w */ 309 /* specify r/w */
307 out_be32((void __iomem *)hwif->dma_command, reading); 310 out_be32((void __iomem *)hwif->dma_command, reading);
@@ -315,13 +318,45 @@ static int scc_dma_setup(ide_drive_t *drive)
315 return 0; 318 return 0;
316} 319}
317 320
321static void scc_dma_start(ide_drive_t *drive)
322{
323 ide_hwif_t *hwif = drive->hwif;
324 u8 dma_cmd = scc_ide_inb(hwif->dma_command);
325
326 /* start DMA */
327 scc_ide_outb(dma_cmd | 1, hwif->dma_command);
328 hwif->dma = 1;
329 wmb();
330}
331
332static int __scc_dma_end(ide_drive_t *drive)
333{
334 ide_hwif_t *hwif = drive->hwif;
335 u8 dma_stat, dma_cmd;
336
337 drive->waiting_for_dma = 0;
338 /* get DMA command mode */
339 dma_cmd = scc_ide_inb(hwif->dma_command);
340 /* stop DMA */
341 scc_ide_outb(dma_cmd & ~1, hwif->dma_command);
342 /* get DMA status */
343 dma_stat = scc_ide_inb(hwif->dma_status);
344 /* clear the INTR & ERROR bits */
345 scc_ide_outb(dma_stat | 6, hwif->dma_status);
346 /* purge DMA mappings */
347 ide_destroy_dmatable(drive);
348 /* verify good DMA status */
349 hwif->dma = 0;
350 wmb();
351 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
352}
318 353
319/** 354/**
320 * scc_dma_end - Stop DMA 355 * scc_dma_end - Stop DMA
321 * @drive: IDE drive 356 * @drive: IDE drive
322 * 357 *
323 * Check and clear INT Status register. 358 * Check and clear INT Status register.
324 * Then call __ide_dma_end(). 359 * Then call __scc_dma_end().
325 */ 360 */
326 361
327static int scc_dma_end(ide_drive_t *drive) 362static int scc_dma_end(ide_drive_t *drive)
@@ -425,7 +460,7 @@ static int scc_dma_end(ide_drive_t *drive)
425 break; 460 break;
426 } 461 }
427 462
428 dma_stat = __ide_dma_end(drive); 463 dma_stat = __scc_dma_end(drive);
429 if (data_loss) 464 if (data_loss)
430 dma_stat |= 2; /* emulate DMA error (to retry command) */ 465 dma_stat |= 2; /* emulate DMA error (to retry command) */
431 return dma_stat; 466 return dma_stat;
@@ -618,6 +653,122 @@ static int __devinit init_setup_scc(struct pci_dev *dev,
618 return rc; 653 return rc;
619} 654}
620 655
656static void scc_tf_load(ide_drive_t *drive, ide_task_t *task)
657{
658 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
659 struct ide_taskfile *tf = &task->tf;
660 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
661
662 if (task->tf_flags & IDE_TFLAG_FLAGGED)
663 HIHI = 0xFF;
664
665 ide_set_irq(drive, 1);
666
667 if (task->tf_flags & IDE_TFLAG_OUT_DATA)
668 out_be32((void *)io_ports->data_addr,
669 (tf->hob_data << 8) | tf->data);
670
671 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
672 scc_ide_outb(tf->hob_feature, io_ports->feature_addr);
673 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
674 scc_ide_outb(tf->hob_nsect, io_ports->nsect_addr);
675 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
676 scc_ide_outb(tf->hob_lbal, io_ports->lbal_addr);
677 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
678 scc_ide_outb(tf->hob_lbam, io_ports->lbam_addr);
679 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
680 scc_ide_outb(tf->hob_lbah, io_ports->lbah_addr);
681
682 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
683 scc_ide_outb(tf->feature, io_ports->feature_addr);
684 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
685 scc_ide_outb(tf->nsect, io_ports->nsect_addr);
686 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
687 scc_ide_outb(tf->lbal, io_ports->lbal_addr);
688 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
689 scc_ide_outb(tf->lbam, io_ports->lbam_addr);
690 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
691 scc_ide_outb(tf->lbah, io_ports->lbah_addr);
692
693 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
694 scc_ide_outb((tf->device & HIHI) | drive->select.all,
695 io_ports->device_addr);
696}
697
698static void scc_tf_read(ide_drive_t *drive, ide_task_t *task)
699{
700 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
701 struct ide_taskfile *tf = &task->tf;
702
703 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
704 u16 data = (u16)in_be32((void *)io_ports->data_addr);
705
706 tf->data = data & 0xff;
707 tf->hob_data = (data >> 8) & 0xff;
708 }
709
710 /* be sure we're looking at the low order bits */
711 scc_ide_outb(drive->ctl & ~0x80, io_ports->ctl_addr);
712
713 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
714 tf->nsect = scc_ide_inb(io_ports->nsect_addr);
715 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
716 tf->lbal = scc_ide_inb(io_ports->lbal_addr);
717 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
718 tf->lbam = scc_ide_inb(io_ports->lbam_addr);
719 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
720 tf->lbah = scc_ide_inb(io_ports->lbah_addr);
721 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
722 tf->device = scc_ide_inb(io_ports->device_addr);
723
724 if (task->tf_flags & IDE_TFLAG_LBA48) {
725 scc_ide_outb(drive->ctl | 0x80, io_ports->ctl_addr);
726
727 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
728 tf->hob_feature = scc_ide_inb(io_ports->feature_addr);
729 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
730 tf->hob_nsect = scc_ide_inb(io_ports->nsect_addr);
731 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
732 tf->hob_lbal = scc_ide_inb(io_ports->lbal_addr);
733 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
734 tf->hob_lbam = scc_ide_inb(io_ports->lbam_addr);
735 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
736 tf->hob_lbah = scc_ide_inb(io_ports->lbah_addr);
737 }
738}
739
740static void scc_input_data(ide_drive_t *drive, struct request *rq,
741 void *buf, unsigned int len)
742{
743 unsigned long data_addr = drive->hwif->io_ports.data_addr;
744
745 len++;
746
747 if (drive->io_32bit) {
748 scc_ide_insl(data_addr, buf, len / 4);
749
750 if ((len & 3) >= 2)
751 scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
752 } else
753 scc_ide_insw(data_addr, buf, len / 2);
754}
755
756static void scc_output_data(ide_drive_t *drive, struct request *rq,
757 void *buf, unsigned int len)
758{
759 unsigned long data_addr = drive->hwif->io_ports.data_addr;
760
761 len++;
762
763 if (drive->io_32bit) {
764 scc_ide_outsl(data_addr, buf, len / 4);
765
766 if ((len & 3) >= 2)
767 scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
768 } else
769 scc_ide_outsw(data_addr, buf, len / 2);
770}
771
621/** 772/**
622 * init_mmio_iops_scc - set up the iops for MMIO 773 * init_mmio_iops_scc - set up the iops for MMIO
623 * @hwif: interface to set up 774 * @hwif: interface to set up
@@ -632,15 +783,15 @@ static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
632 783
633 ide_set_hwifdata(hwif, ports); 784 ide_set_hwifdata(hwif, ports);
634 785
786 hwif->tf_load = scc_tf_load;
787 hwif->tf_read = scc_tf_read;
788
789 hwif->input_data = scc_input_data;
790 hwif->output_data = scc_output_data;
791
635 hwif->INB = scc_ide_inb; 792 hwif->INB = scc_ide_inb;
636 hwif->INW = scc_ide_inw;
637 hwif->INSW = scc_ide_insw;
638 hwif->INSL = scc_ide_insl;
639 hwif->OUTB = scc_ide_outb; 793 hwif->OUTB = scc_ide_outb;
640 hwif->OUTBSYNC = scc_ide_outbsync; 794 hwif->OUTBSYNC = scc_ide_outbsync;
641 hwif->OUTW = scc_ide_outw;
642 hwif->OUTSW = scc_ide_outsw;
643 hwif->OUTSL = scc_ide_outsl;
644 795
645 hwif->dma_base = dma_base; 796 hwif->dma_base = dma_base;
646 hwif->config_data = ports->ctl; 797 hwif->config_data = ports->ctl;
@@ -687,7 +838,6 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif)
687 838
688 hwif->dma_command = hwif->dma_base; 839 hwif->dma_command = hwif->dma_base;
689 hwif->dma_status = hwif->dma_base + 0x04; 840 hwif->dma_status = hwif->dma_base + 0x04;
690 hwif->dma_prdtable = hwif->dma_base + 0x08;
691 841
692 /* PTERADD */ 842 /* PTERADD */
693 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma); 843 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
@@ -706,10 +856,10 @@ static const struct ide_port_ops scc_port_ops = {
706}; 856};
707 857
708static const struct ide_dma_ops scc_dma_ops = { 858static const struct ide_dma_ops scc_dma_ops = {
709 .dma_host_set = ide_dma_host_set, 859 .dma_host_set = scc_dma_host_set,
710 .dma_setup = scc_dma_setup, 860 .dma_setup = scc_dma_setup,
711 .dma_exec_cmd = ide_dma_exec_cmd, 861 .dma_exec_cmd = ide_dma_exec_cmd,
712 .dma_start = ide_dma_start, 862 .dma_start = scc_dma_start,
713 .dma_end = scc_dma_end, 863 .dma_end = scc_dma_end,
714 .dma_test_irq = scc_dma_test_irq, 864 .dma_test_irq = scc_dma_test_irq,
715 .dma_lost_irq = ide_dma_lost_irq, 865 .dma_lost_irq = ide_dma_lost_irq,
diff --git a/drivers/ide/pci/sgiioc4.c b/drivers/ide/pci/sgiioc4.c
index 63e28f4e6d3b..16a0bce17d69 100644
--- a/drivers/ide/pci/sgiioc4.c
+++ b/drivers/ide/pci/sgiioc4.c
@@ -573,6 +573,7 @@ static const struct ide_port_info sgiioc4_port_info __devinitdata = {
573 .init_dma = ide_dma_sgiioc4, 573 .init_dma = ide_dma_sgiioc4,
574 .port_ops = &sgiioc4_port_ops, 574 .port_ops = &sgiioc4_port_ops,
575 .dma_ops = &sgiioc4_dma_ops, 575 .dma_ops = &sgiioc4_dma_ops,
576 .host_flags = IDE_HFLAG_MMIO,
576 .mwdma_mask = ATA_MWDMA2_ONLY, 577 .mwdma_mask = ATA_MWDMA2_ONLY,
577}; 578};
578 579
diff --git a/drivers/ide/pci/siimage.c b/drivers/ide/pci/siimage.c
index c2040a017f47..4cf8fc54aa2a 100644
--- a/drivers/ide/pci/siimage.c
+++ b/drivers/ide/pci/siimage.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> 2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2003 Red Hat <alan@redhat.com> 3 * Copyright (C) 2003 Red Hat <alan@redhat.com>
4 * Copyright (C) 2007 MontaVista Software, Inc. 4 * Copyright (C) 2007-2008 MontaVista Software, Inc.
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz 5 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
6 * 6 *
7 * May be copied or modified under the terms of the GNU General Public License 7 * May be copied or modified under the terms of the GNU General Public License
8 * 8 *
@@ -17,10 +17,10 @@
17 * 17 *
18 * FAQ Items: 18 * FAQ Items:
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives 19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5 not UDMA6. 20 * ensure the system is set up for ATA100/UDMA5, not UDMA6.
21 * 21 *
22 * If you are using WD drives with SATA bridges you must set the 22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang 23 * drive to "Single". "Master" will hang.
24 * 24 *
25 * If you have strange problems with nVidia chipset systems please 25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS 26 * see the SI support documentation and update your system BIOS
@@ -42,25 +42,24 @@
42#include <linux/hdreg.h> 42#include <linux/hdreg.h>
43#include <linux/ide.h> 43#include <linux/ide.h>
44#include <linux/init.h> 44#include <linux/init.h>
45 45#include <linux/io.h>
46#include <asm/io.h>
47 46
48/** 47/**
49 * pdev_is_sata - check if device is SATA 48 * pdev_is_sata - check if device is SATA
50 * @pdev: PCI device to check 49 * @pdev: PCI device to check
51 * 50 *
52 * Returns true if this is a SATA controller 51 * Returns true if this is a SATA controller
53 */ 52 */
54 53
55static int pdev_is_sata(struct pci_dev *pdev) 54static int pdev_is_sata(struct pci_dev *pdev)
56{ 55{
57#ifdef CONFIG_BLK_DEV_IDE_SATA 56#ifdef CONFIG_BLK_DEV_IDE_SATA
58 switch(pdev->device) { 57 switch (pdev->device) {
59 case PCI_DEVICE_ID_SII_3112: 58 case PCI_DEVICE_ID_SII_3112:
60 case PCI_DEVICE_ID_SII_1210SA: 59 case PCI_DEVICE_ID_SII_1210SA:
61 return 1; 60 return 1;
62 case PCI_DEVICE_ID_SII_680: 61 case PCI_DEVICE_ID_SII_680:
63 return 0; 62 return 0;
64 } 63 }
65 BUG(); 64 BUG();
66#endif 65#endif
@@ -70,10 +69,10 @@ static int pdev_is_sata(struct pci_dev *pdev)
70/** 69/**
71 * is_sata - check if hwif is SATA 70 * is_sata - check if hwif is SATA
72 * @hwif: interface to check 71 * @hwif: interface to check
73 * 72 *
74 * Returns true if this is a SATA controller 73 * Returns true if this is a SATA controller
75 */ 74 */
76 75
77static inline int is_sata(ide_hwif_t *hwif) 76static inline int is_sata(ide_hwif_t *hwif)
78{ 77{
79 return pdev_is_sata(to_pci_dev(hwif->dev)); 78 return pdev_is_sata(to_pci_dev(hwif->dev));
@@ -86,21 +85,22 @@ static inline int is_sata(ide_hwif_t *hwif)
86 * 85 *
87 * Turn a config register offset into the right address in either 86 * Turn a config register offset into the right address in either
88 * PCI space or MMIO space to access the control register in question 87 * PCI space or MMIO space to access the control register in question
89 * Thankfully this is a configuration operation so isnt performance 88 * Thankfully this is a configuration operation, so isn't performance
90 * criticial. 89 * critical.
91 */ 90 */
92 91
93static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) 92static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
94{ 93{
95 unsigned long base = (unsigned long)hwif->hwif_data; 94 unsigned long base = (unsigned long)hwif->hwif_data;
95
96 base += 0xA0 + r; 96 base += 0xA0 + r;
97 if(hwif->mmio) 97 if (hwif->mmio)
98 base += (hwif->channel << 6); 98 base += hwif->channel << 6;
99 else 99 else
100 base += (hwif->channel << 4); 100 base += hwif->channel << 4;
101 return base; 101 return base;
102} 102}
103 103
104/** 104/**
105 * siimage_seldev - return register base 105 * siimage_seldev - return register base
106 * @hwif: interface 106 * @hwif: interface
@@ -110,20 +110,69 @@ static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
110 * PCI space or MMIO space to access the control register in question 110 * PCI space or MMIO space to access the control register in question
111 * including accounting for the unit shift. 111 * including accounting for the unit shift.
112 */ 112 */
113 113
114static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) 114static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
115{ 115{
116 ide_hwif_t *hwif = HWIF(drive); 116 ide_hwif_t *hwif = HWIF(drive);
117 unsigned long base = (unsigned long)hwif->hwif_data; 117 unsigned long base = (unsigned long)hwif->hwif_data;
118
118 base += 0xA0 + r; 119 base += 0xA0 + r;
119 if(hwif->mmio) 120 if (hwif->mmio)
120 base += (hwif->channel << 6); 121 base += hwif->channel << 6;
121 else 122 else
122 base += (hwif->channel << 4); 123 base += hwif->channel << 4;
123 base |= drive->select.b.unit << drive->select.b.unit; 124 base |= drive->select.b.unit << drive->select.b.unit;
124 return base; 125 return base;
125} 126}
126 127
128static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
129{
130 u8 tmp = 0;
131
132 if (pci_get_drvdata(dev))
133 tmp = readb((void __iomem *)addr);
134 else
135 pci_read_config_byte(dev, addr, &tmp);
136
137 return tmp;
138}
139
140static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
141{
142 u16 tmp = 0;
143
144 if (pci_get_drvdata(dev))
145 tmp = readw((void __iomem *)addr);
146 else
147 pci_read_config_word(dev, addr, &tmp);
148
149 return tmp;
150}
151
152static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
153{
154 if (pci_get_drvdata(dev))
155 writeb(val, (void __iomem *)addr);
156 else
157 pci_write_config_byte(dev, addr, val);
158}
159
160static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
161{
162 if (pci_get_drvdata(dev))
163 writew(val, (void __iomem *)addr);
164 else
165 pci_write_config_word(dev, addr, val);
166}
167
168static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
169{
170 if (pci_get_drvdata(dev))
171 writel(val, (void __iomem *)addr);
172 else
173 pci_write_config_dword(dev, addr, val);
174}
175
127/** 176/**
128 * sil_udma_filter - compute UDMA mask 177 * sil_udma_filter - compute UDMA mask
129 * @drive: IDE device 178 * @drive: IDE device
@@ -136,24 +185,26 @@ static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
136 185
137static u8 sil_pata_udma_filter(ide_drive_t *drive) 186static u8 sil_pata_udma_filter(ide_drive_t *drive)
138{ 187{
139 ide_hwif_t *hwif = drive->hwif; 188 ide_hwif_t *hwif = drive->hwif;
140 struct pci_dev *dev = to_pci_dev(hwif->dev); 189 struct pci_dev *dev = to_pci_dev(hwif->dev);
141 unsigned long base = (unsigned long) hwif->hwif_data; 190 unsigned long base = (unsigned long)hwif->hwif_data;
142 u8 mask = 0, scsc = 0; 191 u8 scsc, mask = 0;
143 192
144 if (hwif->mmio) 193 scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
145 scsc = hwif->INB(base + 0x4A);
146 else
147 pci_read_config_byte(dev, 0x8A, &scsc);
148 194
149 if ((scsc & 0x30) == 0x10) /* 133 */ 195 switch (scsc & 0x30) {
196 case 0x10: /* 133 */
150 mask = ATA_UDMA6; 197 mask = ATA_UDMA6;
151 else if ((scsc & 0x30) == 0x20) /* 2xPCI */ 198 break;
199 case 0x20: /* 2xPCI */
152 mask = ATA_UDMA6; 200 mask = ATA_UDMA6;
153 else if ((scsc & 0x30) == 0x00) /* 100 */ 201 break;
202 case 0x00: /* 100 */
154 mask = ATA_UDMA5; 203 mask = ATA_UDMA5;
155 else /* Disabled ? */ 204 break;
205 default: /* Disabled ? */
156 BUG(); 206 BUG();
207 }
157 208
158 return mask; 209 return mask;
159} 210}
@@ -175,15 +226,16 @@ static u8 sil_sata_udma_filter(ide_drive_t *drive)
175 226
176static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) 227static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
177{ 228{
178 const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; 229 static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
179 const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 230 static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
180 231
181 ide_hwif_t *hwif = HWIF(drive); 232 ide_hwif_t *hwif = HWIF(drive);
233 struct pci_dev *dev = to_pci_dev(hwif->dev);
182 ide_drive_t *pair = ide_get_paired_drive(drive); 234 ide_drive_t *pair = ide_get_paired_drive(drive);
183 u32 speedt = 0; 235 u32 speedt = 0;
184 u16 speedp = 0; 236 u16 speedp = 0;
185 unsigned long addr = siimage_seldev(drive, 0x04); 237 unsigned long addr = siimage_seldev(drive, 0x04);
186 unsigned long tfaddr = siimage_selreg(hwif, 0x02); 238 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
187 unsigned long base = (unsigned long)hwif->hwif_data; 239 unsigned long base = (unsigned long)hwif->hwif_data;
188 u8 tf_pio = pio; 240 u8 tf_pio = pio;
189 u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84) 241 u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84)
@@ -203,36 +255,20 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
203 speedp = data_speed[pio]; 255 speedp = data_speed[pio];
204 speedt = tf_speed[tf_pio]; 256 speedt = tf_speed[tf_pio];
205 257
206 if (hwif->mmio) { 258 sil_iowrite16(dev, speedp, addr);
207 hwif->OUTW(speedp, addr); 259 sil_iowrite16(dev, speedt, tfaddr);
208 hwif->OUTW(speedt, tfaddr); 260
209 /* Now set up IORDY */ 261 /* now set up IORDY */
210 if (pio > 2) 262 speedp = sil_ioread16(dev, tfaddr - 2);
211 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2); 263 speedp &= ~0x200;
212 else 264 if (pio > 2)
213 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2); 265 speedp |= 0x200;
214 266 sil_iowrite16(dev, speedp, tfaddr - 2);
215 mode = hwif->INB(base + addr_mask); 267
216 mode &= ~(unit ? 0x30 : 0x03); 268 mode = sil_ioread8(dev, base + addr_mask);
217 mode |= (unit ? 0x10 : 0x01); 269 mode &= ~(unit ? 0x30 : 0x03);
218 hwif->OUTB(mode, base + addr_mask); 270 mode |= unit ? 0x10 : 0x01;
219 } else { 271 sil_iowrite8(dev, mode, base + addr_mask);
220 struct pci_dev *dev = to_pci_dev(hwif->dev);
221
222 pci_write_config_word(dev, addr, speedp);
223 pci_write_config_word(dev, tfaddr, speedt);
224 pci_read_config_word(dev, tfaddr - 2, &speedp);
225 speedp &= ~0x200;
226 /* Set IORDY for mode 3 or 4 */
227 if (pio > 2)
228 speedp |= 0x200;
229 pci_write_config_word(dev, tfaddr - 2, speedp);
230
231 pci_read_config_byte(dev, addr_mask, &mode);
232 mode &= ~(unit ? 0x30 : 0x03);
233 mode |= (unit ? 0x10 : 0x01);
234 pci_write_config_byte(dev, addr_mask, mode);
235 }
236} 272}
237 273
238/** 274/**
@@ -245,59 +281,45 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
245 281
246static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) 282static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
247{ 283{
248 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; 284 static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
249 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; 285 static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
250 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; 286 static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
251 287
252 ide_hwif_t *hwif = HWIF(drive); 288 ide_hwif_t *hwif = HWIF(drive);
253 struct pci_dev *dev = to_pci_dev(hwif->dev); 289 struct pci_dev *dev = to_pci_dev(hwif->dev);
254 u16 ultra = 0, multi = 0; 290 u16 ultra = 0, multi = 0;
255 u8 mode = 0, unit = drive->select.b.unit; 291 u8 mode = 0, unit = drive->select.b.unit;
256 unsigned long base = (unsigned long)hwif->hwif_data; 292 unsigned long base = (unsigned long)hwif->hwif_data;
257 u8 scsc = 0, addr_mask = ((hwif->channel) ? 293 u8 scsc = 0, addr_mask = hwif->channel ?
258 ((hwif->mmio) ? 0xF4 : 0x84) : 294 (hwif->mmio ? 0xF4 : 0x84) :
259 ((hwif->mmio) ? 0xB4 : 0x80)); 295 (hwif->mmio ? 0xB4 : 0x80);
260
261 unsigned long ma = siimage_seldev(drive, 0x08); 296 unsigned long ma = siimage_seldev(drive, 0x08);
262 unsigned long ua = siimage_seldev(drive, 0x0C); 297 unsigned long ua = siimage_seldev(drive, 0x0C);
263 298
264 if (hwif->mmio) { 299 scsc = sil_ioread8 (dev, base + (hwif->mmio ? 0x4A : 0x8A));
265 scsc = hwif->INB(base + 0x4A); 300 mode = sil_ioread8 (dev, base + addr_mask);
266 mode = hwif->INB(base + addr_mask); 301 multi = sil_ioread16(dev, ma);
267 multi = hwif->INW(ma); 302 ultra = sil_ioread16(dev, ua);
268 ultra = hwif->INW(ua);
269 } else {
270 pci_read_config_byte(dev, 0x8A, &scsc);
271 pci_read_config_byte(dev, addr_mask, &mode);
272 pci_read_config_word(dev, ma, &multi);
273 pci_read_config_word(dev, ua, &ultra);
274 }
275 303
276 mode &= ~((unit) ? 0x30 : 0x03); 304 mode &= ~(unit ? 0x30 : 0x03);
277 ultra &= ~0x3F; 305 ultra &= ~0x3F;
278 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; 306 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
279 307
280 scsc = is_sata(hwif) ? 1 : scsc; 308 scsc = is_sata(hwif) ? 1 : scsc;
281 309
282 if (speed >= XFER_UDMA_0) { 310 if (speed >= XFER_UDMA_0) {
283 multi = dma[2]; 311 multi = dma[2];
284 ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] : 312 ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
285 ultra5[speed - XFER_UDMA_0]); 313 ultra5[speed - XFER_UDMA_0];
286 mode |= (unit ? 0x30 : 0x03); 314 mode |= unit ? 0x30 : 0x03;
287 } else { 315 } else {
288 multi = dma[speed - XFER_MW_DMA_0]; 316 multi = dma[speed - XFER_MW_DMA_0];
289 mode |= (unit ? 0x20 : 0x02); 317 mode |= unit ? 0x20 : 0x02;
290 } 318 }
291 319
292 if (hwif->mmio) { 320 sil_iowrite8 (dev, mode, base + addr_mask);
293 hwif->OUTB(mode, base + addr_mask); 321 sil_iowrite16(dev, multi, ma);
294 hwif->OUTW(multi, ma); 322 sil_iowrite16(dev, ultra, ua);
295 hwif->OUTW(ultra, ua);
296 } else {
297 pci_write_config_byte(dev, addr_mask, mode);
298 pci_write_config_word(dev, ma, multi);
299 pci_write_config_word(dev, ua, ultra);
300 }
301} 323}
302 324
303/* returns 1 if dma irq issued, 0 otherwise */ 325/* returns 1 if dma irq issued, 0 otherwise */
@@ -309,13 +331,14 @@ static int siimage_io_dma_test_irq(ide_drive_t *drive)
309 unsigned long addr = siimage_selreg(hwif, 1); 331 unsigned long addr = siimage_selreg(hwif, 1);
310 332
311 /* return 1 if INTR asserted */ 333 /* return 1 if INTR asserted */
312 if ((hwif->INB(hwif->dma_status) & 4) == 4) 334 if (hwif->INB(hwif->dma_status) & 4)
313 return 1; 335 return 1;
314 336
315 /* return 1 if Device INTR asserted */ 337 /* return 1 if Device INTR asserted */
316 pci_read_config_byte(dev, addr, &dma_altstat); 338 pci_read_config_byte(dev, addr, &dma_altstat);
317 if (dma_altstat & 8) 339 if (dma_altstat & 8)
318 return 0; //return 1; 340 return 0; /* return 1; */
341
319 return 0; 342 return 0;
320} 343}
321 344
@@ -335,9 +358,9 @@ static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
335 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET]; 358 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
336 359
337 if (sata_error_addr) { 360 if (sata_error_addr) {
338 unsigned long base = (unsigned long)hwif->hwif_data; 361 unsigned long base = (unsigned long)hwif->hwif_data;
339 u32 ext_stat = readl((void __iomem *)(base + 0x10)); 362 u32 ext_stat = readl((void __iomem *)(base + 0x10));
340 u8 watchdog = 0; 363 u8 watchdog = 0;
341 364
342 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { 365 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
343 u32 sata_error = readl(sata_error_addr); 366 u32 sata_error = readl(sata_error_addr);
@@ -346,25 +369,22 @@ static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
346 watchdog = (sata_error & 0x00680000) ? 1 : 0; 369 watchdog = (sata_error & 0x00680000) ? 1 : 0;
347 printk(KERN_WARNING "%s: sata_error = 0x%08x, " 370 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
348 "watchdog = %d, %s\n", 371 "watchdog = %d, %s\n",
349 drive->name, sata_error, watchdog, 372 drive->name, sata_error, watchdog, __func__);
350 __func__); 373 } else
351
352 } else {
353 watchdog = (ext_stat & 0x8000) ? 1 : 0; 374 watchdog = (ext_stat & 0x8000) ? 1 : 0;
354 }
355 ext_stat >>= 16;
356 375
376 ext_stat >>= 16;
357 if (!(ext_stat & 0x0404) && !watchdog) 377 if (!(ext_stat & 0x0404) && !watchdog)
358 return 0; 378 return 0;
359 } 379 }
360 380
361 /* return 1 if INTR asserted */ 381 /* return 1 if INTR asserted */
362 if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) 382 if (readb((void __iomem *)hwif->dma_status) & 0x04)
363 return 1; 383 return 1;
364 384
365 /* return 1 if Device INTR asserted */ 385 /* return 1 if Device INTR asserted */
366 if ((readb((void __iomem *)addr) & 8) == 8) 386 if (readb((void __iomem *)addr) & 8)
367 return 0; //return 1; 387 return 0; /* return 1; */
368 388
369 return 0; 389 return 0;
370} 390}
@@ -423,63 +443,33 @@ static void sil_sata_pre_reset(ide_drive_t *drive)
423} 443}
424 444
425/** 445/**
426 * proc_reports_siimage - add siimage controller to proc 446 * setup_mmio_siimage - switch controller into MMIO mode
427 * @dev: PCI device
428 * @clocking: SCSC value
429 * @name: controller name
430 *
431 * Report the clocking mode of the controller and add it to
432 * the /proc interface layer
433 */
434
435static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
436{
437 if (!pdev_is_sata(dev)) {
438 printk(KERN_INFO "%s: BASE CLOCK ", name);
439 clocking &= 0x03;
440 switch (clocking) {
441 case 0x03: printk("DISABLED!\n"); break;
442 case 0x02: printk("== 2X PCI\n"); break;
443 case 0x01: printk("== 133\n"); break;
444 case 0x00: printk("== 100\n"); break;
445 }
446 }
447}
448
449/**
450 * setup_mmio_siimage - switch an SI controller into MMIO
451 * @dev: PCI device we are configuring 447 * @dev: PCI device we are configuring
452 * @name: device name 448 * @name: device name
453 * 449 *
454 * Attempt to put the device into mmio mode. There are some slight 450 * Attempt to put the device into MMIO mode. There are some slight
455 * complications here with certain systems where the mmio bar isnt 451 * complications here with certain systems where the MMIO BAR isn't
456 * mapped so we have to be sure we can fall back to I/O. 452 * mapped, so we have to be sure that we can fall back to I/O.
457 */ 453 */
458 454
459static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name) 455static unsigned int setup_mmio_siimage(struct pci_dev *dev, const char *name)
460{ 456{
461 resource_size_t bar5 = pci_resource_start(dev, 5); 457 resource_size_t bar5 = pci_resource_start(dev, 5);
462 unsigned long barsize = pci_resource_len(dev, 5); 458 unsigned long barsize = pci_resource_len(dev, 5);
463 u8 tmpbyte = 0;
464 void __iomem *ioaddr; 459 void __iomem *ioaddr;
465 u32 tmp, irq_mask;
466 460
467 /* 461 /*
468 * Drop back to PIO if we can't map the mmio. Some 462 * Drop back to PIO if we can't map the MMIO. Some systems
469 * systems seem to get terminally confused in the PCI 463 * seem to get terminally confused in the PCI spaces.
470 * spaces.
471 */ 464 */
472 465 if (!request_mem_region(bar5, barsize, name)) {
473 if(!request_mem_region(bar5, barsize, name)) 466 printk(KERN_WARNING "siimage: IDE controller MMIO ports not "
474 { 467 "available.\n");
475 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
476 return 0; 468 return 0;
477 } 469 }
478
479 ioaddr = ioremap(bar5, barsize);
480 470
481 if (ioaddr == NULL) 471 ioaddr = ioremap(bar5, barsize);
482 { 472 if (ioaddr == NULL) {
483 release_mem_region(bar5, barsize); 473 release_mem_region(bar5, barsize);
484 return 0; 474 return 0;
485 } 475 }
@@ -487,62 +477,6 @@ static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
487 pci_set_master(dev); 477 pci_set_master(dev);
488 pci_set_drvdata(dev, (void *) ioaddr); 478 pci_set_drvdata(dev, (void *) ioaddr);
489 479
490 if (pdev_is_sata(dev)) {
491 /* make sure IDE0/1 interrupts are not masked */
492 irq_mask = (1 << 22) | (1 << 23);
493 tmp = readl(ioaddr + 0x48);
494 if (tmp & irq_mask) {
495 tmp &= ~irq_mask;
496 writel(tmp, ioaddr + 0x48);
497 readl(ioaddr + 0x48); /* flush */
498 }
499 writel(0, ioaddr + 0x148);
500 writel(0, ioaddr + 0x1C8);
501 }
502
503 writeb(0, ioaddr + 0xB4);
504 writeb(0, ioaddr + 0xF4);
505 tmpbyte = readb(ioaddr + 0x4A);
506
507 switch(tmpbyte & 0x30) {
508 case 0x00:
509 /* In 100 MHz clocking, try and switch to 133 */
510 writeb(tmpbyte|0x10, ioaddr + 0x4A);
511 break;
512 case 0x10:
513 /* On 133Mhz clocking */
514 break;
515 case 0x20:
516 /* On PCIx2 clocking */
517 break;
518 case 0x30:
519 /* Clocking is disabled */
520 /* 133 clock attempt to force it on */
521 writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
522 break;
523 }
524
525 writeb( 0x72, ioaddr + 0xA1);
526 writew( 0x328A, ioaddr + 0xA2);
527 writel(0x62DD62DD, ioaddr + 0xA4);
528 writel(0x43924392, ioaddr + 0xA8);
529 writel(0x40094009, ioaddr + 0xAC);
530 writeb( 0x72, ioaddr + 0xE1);
531 writew( 0x328A, ioaddr + 0xE2);
532 writel(0x62DD62DD, ioaddr + 0xE4);
533 writel(0x43924392, ioaddr + 0xE8);
534 writel(0x40094009, ioaddr + 0xEC);
535
536 if (pdev_is_sata(dev)) {
537 writel(0xFFFF0000, ioaddr + 0x108);
538 writel(0xFFFF0000, ioaddr + 0x188);
539 writel(0x00680000, ioaddr + 0x148);
540 writel(0x00680000, ioaddr + 0x1C8);
541 }
542
543 tmpbyte = readb(ioaddr + 0x4A);
544
545 proc_reports_siimage(dev, (tmpbyte>>4), name);
546 return 1; 480 return 1;
547} 481}
548 482
@@ -552,55 +486,92 @@ static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
552 * @name: device name 486 * @name: device name
553 * 487 *
554 * Perform the initial PCI set up for this device. Attempt to switch 488 * Perform the initial PCI set up for this device. Attempt to switch
555 * to 133MHz clocking if the system isn't already set up to do it. 489 * to 133 MHz clocking if the system isn't already set up to do it.
556 */ 490 */
557 491
558static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) 492static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev,
493 const char *name)
559{ 494{
560 u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0; 495 unsigned long base, scsc_addr;
496 void __iomem *ioaddr = NULL;
497 u8 rev = dev->revision, tmp, BA5_EN;
561 498
562 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); 499 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
563 500
564 pci_read_config_byte(dev, 0x8A, &BA5_EN); 501 pci_read_config_byte(dev, 0x8A, &BA5_EN);
565 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) { 502
566 if (setup_mmio_siimage(dev, name)) { 503 if ((BA5_EN & 0x01) || pci_resource_start(dev, 5))
567 return 0; 504 if (setup_mmio_siimage(dev, name))
505 ioaddr = pci_get_drvdata(dev);
506
507 base = (unsigned long)ioaddr;
508
509 if (ioaddr && pdev_is_sata(dev)) {
510 u32 tmp32, irq_mask;
511
512 /* make sure IDE0/1 interrupts are not masked */
513 irq_mask = (1 << 22) | (1 << 23);
514 tmp32 = readl(ioaddr + 0x48);
515 if (tmp32 & irq_mask) {
516 tmp32 &= ~irq_mask;
517 writel(tmp32, ioaddr + 0x48);
518 readl(ioaddr + 0x48); /* flush */
568 } 519 }
520 writel(0, ioaddr + 0x148);
521 writel(0, ioaddr + 0x1C8);
522 }
523
524 sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
525 sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
526
527 scsc_addr = base ? (base + 0x4A) : 0x8A;
528 tmp = sil_ioread8(dev, scsc_addr);
529
530 switch (tmp & 0x30) {
531 case 0x00:
532 /* On 100 MHz clocking, try and switch to 133 MHz */
533 sil_iowrite8(dev, tmp | 0x10, scsc_addr);
534 break;
535 case 0x30:
536 /* Clocking is disabled, attempt to force 133MHz clocking. */
537 sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
538 case 0x10:
539 /* On 133Mhz clocking. */
540 break;
541 case 0x20:
542 /* On PCIx2 clocking. */
543 break;
569 } 544 }
570 545
571 pci_write_config_byte(dev, 0x80, 0x00); 546 tmp = sil_ioread8(dev, scsc_addr);
572 pci_write_config_byte(dev, 0x84, 0x00); 547
573 pci_read_config_byte(dev, 0x8A, &tmpbyte); 548 sil_iowrite8 (dev, 0x72, base + 0xA1);
574 switch(tmpbyte & 0x30) { 549 sil_iowrite16(dev, 0x328A, base + 0xA2);
575 case 0x00: 550 sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
576 /* 133 clock attempt to force it on */ 551 sil_iowrite32(dev, 0x43924392, base + 0xA8);
577 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10); 552 sil_iowrite32(dev, 0x40094009, base + 0xAC);
578 case 0x30: 553 sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
579 /* if clocking is disabled */ 554 sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
580 /* 133 clock attempt to force it on */ 555 sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
581 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20); 556 sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
582 case 0x10: 557 sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
583 /* 133 already */ 558
584 break; 559 if (base && pdev_is_sata(dev)) {
585 case 0x20: 560 writel(0xFFFF0000, ioaddr + 0x108);
586 /* BIOS set PCI x2 clocking */ 561 writel(0xFFFF0000, ioaddr + 0x188);
587 break; 562 writel(0x00680000, ioaddr + 0x148);
563 writel(0x00680000, ioaddr + 0x1C8);
588 } 564 }
589 565
590 pci_read_config_byte(dev, 0x8A, &tmpbyte); 566 /* report the clocking mode of the controller */
567 if (!pdev_is_sata(dev)) {
568 static const char *clk_str[] =
569 { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
591 570
592 pci_write_config_byte(dev, 0xA1, 0x72); 571 tmp >>= 4;
593 pci_write_config_word(dev, 0xA2, 0x328A); 572 printk(KERN_INFO "%s: BASE CLOCK %s\n", name, clk_str[tmp & 3]);
594 pci_write_config_dword(dev, 0xA4, 0x62DD62DD); 573 }
595 pci_write_config_dword(dev, 0xA8, 0x43924392);
596 pci_write_config_dword(dev, 0xAC, 0x40094009);
597 pci_write_config_byte(dev, 0xB1, 0x72);
598 pci_write_config_word(dev, 0xB2, 0x328A);
599 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
600 pci_write_config_dword(dev, 0xB8, 0x43924392);
601 pci_write_config_dword(dev, 0xBC, 0x40094009);
602 574
603 proc_reports_siimage(dev, (tmpbyte>>4), name);
604 return 0; 575 return 0;
605} 576}
606 577
@@ -610,8 +581,7 @@ static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const ch
610 * 581 *
611 * The basic setup here is fairly simple, we can use standard MMIO 582 * The basic setup here is fairly simple, we can use standard MMIO
612 * operations. However we do have to set the taskfile register offsets 583 * operations. However we do have to set the taskfile register offsets
613 * by hand as there isnt a standard defined layout for them this 584 * by hand as there isn't a standard defined layout for them this time.
614 * time.
615 * 585 *
616 * The hardware supports buffered taskfiles and also some rather nice 586 * The hardware supports buffered taskfiles and also some rather nice
617 * extended PRD tables. For better SI3112 support use the libata driver 587 * extended PRD tables. For better SI3112 support use the libata driver
@@ -622,23 +592,20 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
622 struct pci_dev *dev = to_pci_dev(hwif->dev); 592 struct pci_dev *dev = to_pci_dev(hwif->dev);
623 void *addr = pci_get_drvdata(dev); 593 void *addr = pci_get_drvdata(dev);
624 u8 ch = hwif->channel; 594 u8 ch = hwif->channel;
625 unsigned long base;
626
627 struct ide_io_ports *io_ports = &hwif->io_ports; 595 struct ide_io_ports *io_ports = &hwif->io_ports;
596 unsigned long base;
628 597
629 /* 598 /*
630 * Fill in the basic HWIF bits 599 * Fill in the basic hwif bits
631 */ 600 */
632 601 hwif->host_flags |= IDE_HFLAG_MMIO;
633 default_hwif_mmiops(hwif); 602 default_hwif_mmiops(hwif);
634 hwif->hwif_data = addr; 603 hwif->hwif_data = addr;
635 604
636 /* 605 /*
637 * Now set up the hw. We have to do this ourselves as 606 * Now set up the hw. We have to do this ourselves as the
638 * the MMIO layout isnt the same as the standard port 607 * MMIO layout isn't the same as the standard port based I/O.
639 * based I/O
640 */ 608 */
641
642 memset(io_ports, 0, sizeof(*io_ports)); 609 memset(io_ports, 0, sizeof(*io_ports));
643 610
644 base = (unsigned long)addr; 611 base = (unsigned long)addr;
@@ -648,10 +615,9 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
648 base += 0x80; 615 base += 0x80;
649 616
650 /* 617 /*
651 * The buffered task file doesn't have status/control 618 * The buffered task file doesn't have status/control, so we
652 * so we can't currently use it sanely since we want to 619 * can't currently use it sanely since we want to use LBA48 mode.
653 * use LBA48 mode. 620 */
654 */
655 io_ports->data_addr = base; 621 io_ports->data_addr = base;
656 io_ports->error_addr = base + 1; 622 io_ports->error_addr = base + 1;
657 io_ports->nsect_addr = base + 2; 623 io_ports->nsect_addr = base + 2;
@@ -680,19 +646,17 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
680 646
681static int is_dev_seagate_sata(ide_drive_t *drive) 647static int is_dev_seagate_sata(ide_drive_t *drive)
682{ 648{
683 const char *s = &drive->id->model[0]; 649 const char *s = &drive->id->model[0];
684 unsigned len; 650 unsigned len = strnlen(s, sizeof(drive->id->model));
685
686 len = strnlen(s, sizeof(drive->id->model));
687 651
688 if ((len > 4) && (!memcmp(s, "ST", 2))) { 652 if ((len > 4) && (!memcmp(s, "ST", 2)))
689 if ((!memcmp(s + len - 2, "AS", 2)) || 653 if ((!memcmp(s + len - 2, "AS", 2)) ||
690 (!memcmp(s + len - 3, "ASL", 3))) { 654 (!memcmp(s + len - 3, "ASL", 3))) {
691 printk(KERN_INFO "%s: applying pessimistic Seagate " 655 printk(KERN_INFO "%s: applying pessimistic Seagate "
692 "errata fix\n", drive->name); 656 "errata fix\n", drive->name);
693 return 1; 657 return 1;
694 } 658 }
695 } 659
696 return 0; 660 return 0;
697} 661}
698 662
@@ -709,7 +673,7 @@ static void __devinit sil_quirkproc(ide_drive_t *drive)
709{ 673{
710 ide_hwif_t *hwif = drive->hwif; 674 ide_hwif_t *hwif = drive->hwif;
711 675
712 /* Try and raise the rqsize */ 676 /* Try and rise the rqsize */
713 if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) 677 if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
714 hwif->rqsize = 128; 678 hwif->rqsize = 128;
715} 679}
@@ -743,20 +707,14 @@ static void __devinit init_iops_siimage(ide_hwif_t *hwif)
743 * sil_cable_detect - cable detection 707 * sil_cable_detect - cable detection
744 * @hwif: interface to check 708 * @hwif: interface to check
745 * 709 *
746 * Check for the presence of an ATA66 capable cable on the 710 * Check for the presence of an ATA66 capable cable on the interface.
747 * interface.
748 */ 711 */
749 712
750static u8 __devinit sil_cable_detect(ide_hwif_t *hwif) 713static u8 __devinit sil_cable_detect(ide_hwif_t *hwif)
751{ 714{
752 struct pci_dev *dev = to_pci_dev(hwif->dev); 715 struct pci_dev *dev = to_pci_dev(hwif->dev);
753 unsigned long addr = siimage_selreg(hwif, 0); 716 unsigned long addr = siimage_selreg(hwif, 0);
754 u8 ata66 = 0; 717 u8 ata66 = sil_ioread8(dev, addr);
755
756 if (pci_get_drvdata(dev) == NULL)
757 pci_read_config_byte(dev, addr, &ata66);
758 else
759 ata66 = hwif->INB(addr);
760 718
761 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; 719 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
762} 720}
@@ -802,15 +760,16 @@ static const struct ide_port_info siimage_chipsets[] __devinitdata = {
802}; 760};
803 761
804/** 762/**
805 * siimage_init_one - pci layer discovery entry 763 * siimage_init_one - PCI layer discovery entry
806 * @dev: PCI device 764 * @dev: PCI device
807 * @id: ident table entry 765 * @id: ident table entry
808 * 766 *
809 * Called by the PCI code when it finds an SI680 or SI3112 controller. 767 * Called by the PCI code when it finds an SiI680 or SiI3112 controller.
810 * We then use the IDE PCI generic helper to do most of the work. 768 * We then use the IDE PCI generic helper to do most of the work.
811 */ 769 */
812 770
813static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) 771static int __devinit siimage_init_one(struct pci_dev *dev,
772 const struct pci_device_id *id)
814{ 773{
815 struct ide_port_info d; 774 struct ide_port_info d;
816 u8 idx = id->driver_data; 775 u8 idx = id->driver_data;
diff --git a/drivers/ide/ppc/pmac.c b/drivers/ide/ppc/pmac.c
index 3cac6b2790dd..48aa019127bc 100644
--- a/drivers/ide/ppc/pmac.c
+++ b/drivers/ide/ppc/pmac.c
@@ -941,6 +941,7 @@ static const struct ide_port_info pmac_port_info = {
941 .port_ops = &pmac_ide_port_ops, 941 .port_ops = &pmac_ide_port_ops,
942 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA | 942 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
943 IDE_HFLAG_POST_SET_MODE | 943 IDE_HFLAG_POST_SET_MODE |
944 IDE_HFLAG_MMIO |
944 IDE_HFLAG_UNMASK_IRQS, 945 IDE_HFLAG_UNMASK_IRQS,
945 .pio_mask = ATA_PIO4, 946 .pio_mask = ATA_PIO4,
946 .mwdma_mask = ATA_MWDMA2, 947 .mwdma_mask = ATA_MWDMA2,
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 04:19:33 -0500