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path: root/drivers/ide/sl82c105.c
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Diffstat (limited to 'drivers/ide/sl82c105.c')
-rw-r--r--drivers/ide/sl82c105.c32
1 files changed, 6 insertions, 26 deletions
diff --git a/drivers/ide/sl82c105.c b/drivers/ide/sl82c105.c
index d698da470d6f..f21dc2ad7682 100644
--- a/drivers/ide/sl82c105.c
+++ b/drivers/ide/sl82c105.c
@@ -24,13 +24,6 @@
24 24
25#define DRV_NAME "sl82c105" 25#define DRV_NAME "sl82c105"
26 26
27#undef DEBUG
28
29#ifdef DEBUG
30#define DBG(arg) printk arg
31#else
32#define DBG(fmt,...)
33#endif
34/* 27/*
35 * SL82C105 PCI config register 0x40 bits. 28 * SL82C105 PCI config register 0x40 bits.
36 */ 29 */
@@ -70,12 +63,13 @@ static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
70/* 63/*
71 * Configure the chipset for PIO mode. 64 * Configure the chipset for PIO mode.
72 */ 65 */
73static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio) 66static void sl82c105_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
74{ 67{
75 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 68 struct pci_dev *dev = to_pci_dev(hwif->dev);
76 unsigned long timings = (unsigned long)ide_get_drivedata(drive); 69 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
77 int reg = 0x44 + drive->dn * 4; 70 int reg = 0x44 + drive->dn * 4;
78 u16 drv_ctrl; 71 u16 drv_ctrl;
72 const u8 pio = drive->pio_mode - XFER_PIO_0;
79 73
80 drv_ctrl = get_pio_timings(drive, pio); 74 drv_ctrl = get_pio_timings(drive, pio);
81 75
@@ -98,14 +92,12 @@ static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
98/* 92/*
99 * Configure the chipset for DMA mode. 93 * Configure the chipset for DMA mode.
100 */ 94 */
101static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed) 95static void sl82c105_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
102{ 96{
103 static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; 97 static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
104 unsigned long timings = (unsigned long)ide_get_drivedata(drive); 98 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
105 u16 drv_ctrl; 99 u16 drv_ctrl;
106 100 const u8 speed = drive->dma_mode;
107 DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
108 drive->name, ide_xfer_verbose(speed)));
109 101
110 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; 102 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
111 103
@@ -196,8 +188,6 @@ static void sl82c105_dma_start(ide_drive_t *drive)
196 struct pci_dev *dev = to_pci_dev(hwif->dev); 188 struct pci_dev *dev = to_pci_dev(hwif->dev);
197 int reg = 0x44 + drive->dn * 4; 189 int reg = 0x44 + drive->dn * 4;
198 190
199 DBG(("%s(drive:%s)\n", __func__, drive->name));
200
201 pci_write_config_word(dev, reg, 191 pci_write_config_word(dev, reg,
202 (unsigned long)ide_get_drivedata(drive) >> 16); 192 (unsigned long)ide_get_drivedata(drive) >> 16);
203 193
@@ -209,8 +199,6 @@ static void sl82c105_dma_clear(ide_drive_t *drive)
209{ 199{
210 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 200 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
211 201
212 DBG(("sl82c105_dma_clear(drive:%s)\n", drive->name));
213
214 sl82c105_reset_host(dev); 202 sl82c105_reset_host(dev);
215} 203}
216 204
@@ -218,11 +206,7 @@ static int sl82c105_dma_end(ide_drive_t *drive)
218{ 206{
219 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 207 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
220 int reg = 0x44 + drive->dn * 4; 208 int reg = 0x44 + drive->dn * 4;
221 int ret; 209 int ret = ide_dma_end(drive);
222
223 DBG(("%s(drive:%s)\n", __func__, drive->name));
224
225 ret = ide_dma_end(drive);
226 210
227 pci_write_config_word(dev, reg, 211 pci_write_config_word(dev, reg,
228 (unsigned long)ide_get_drivedata(drive)); 212 (unsigned long)ide_get_drivedata(drive));
@@ -239,8 +223,6 @@ static void sl82c105_resetproc(ide_drive_t *drive)
239 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 223 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
240 u32 val; 224 u32 val;
241 225
242 DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
243
244 pci_read_config_dword(dev, 0x40, &val); 226 pci_read_config_dword(dev, 0x40, &val);
245 val |= (CTRL_P1F16 | CTRL_P0F16); 227 val |= (CTRL_P1F16 | CTRL_P0F16);
246 pci_write_config_dword(dev, 0x40, val); 228 pci_write_config_dword(dev, 0x40, val);
@@ -291,8 +273,6 @@ static int init_chipset_sl82c105(struct pci_dev *dev)
291{ 273{
292 u32 val; 274 u32 val;
293 275
294 DBG(("init_chipset_sl82c105()\n"));
295
296 pci_read_config_dword(dev, 0x40, &val); 276 pci_read_config_dword(dev, 0x40, &val);
297 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; 277 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
298 pci_write_config_dword(dev, 0x40, val); 278 pci_write_config_dword(dev, 0x40, val);