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-rw-r--r--drivers/ide/pci/cmd640.c2
-rw-r--r--drivers/ide/pci/delkin_cb.c28
-rw-r--r--drivers/ide/pci/opti621.c221
-rw-r--r--drivers/ide/pci/sis5513.c5
4 files changed, 57 insertions, 199 deletions
diff --git a/drivers/ide/pci/cmd640.c b/drivers/ide/pci/cmd640.c
index aaf38109eaec..b38a1980dcd5 100644
--- a/drivers/ide/pci/cmd640.c
+++ b/drivers/ide/pci/cmd640.c
@@ -747,9 +747,11 @@ static int __init cmd640x_init(void)
747 747
748 ide_std_init_ports(&hw[0], 0x1f0, 0x3f6); 748 ide_std_init_ports(&hw[0], 0x1f0, 0x3f6);
749 hw[0].irq = 14; 749 hw[0].irq = 14;
750 hw[0].chipset = ide_cmd640;
750 751
751 ide_std_init_ports(&hw[1], 0x170, 0x376); 752 ide_std_init_ports(&hw[1], 0x170, 0x376);
752 hw[1].irq = 15; 753 hw[1].irq = 15;
754 hw[1].chipset = ide_cmd640;
753 755
754 printk(KERN_INFO "cmd640: buggy cmd640%c interface on %s, config=0x%02x" 756 printk(KERN_INFO "cmd640: buggy cmd640%c interface on %s, config=0x%02x"
755 "\n", 'a' + cmd640_chip_version - 1, bus_type, cfr); 757 "\n", 'a' + cmd640_chip_version - 1, bus_type, cfr);
diff --git a/drivers/ide/pci/delkin_cb.c b/drivers/ide/pci/delkin_cb.c
index b9e457996d0e..af0f30051d5a 100644
--- a/drivers/ide/pci/delkin_cb.c
+++ b/drivers/ide/pci/delkin_cb.c
@@ -47,13 +47,18 @@ static const struct ide_port_ops delkin_cb_port_ops = {
47 .quirkproc = ide_undecoded_slave, 47 .quirkproc = ide_undecoded_slave,
48}; 48};
49 49
50static const struct ide_port_info delkin_cb_port_info = {
51 .port_ops = &delkin_cb_port_ops,
52 .host_flags = IDE_HFLAG_IO_32BIT | IDE_HFLAG_UNMASK_IRQS |
53 IDE_HFLAG_NO_DMA,
54};
55
50static int __devinit 56static int __devinit
51delkin_cb_probe (struct pci_dev *dev, const struct pci_device_id *id) 57delkin_cb_probe (struct pci_dev *dev, const struct pci_device_id *id)
52{ 58{
53 unsigned long base; 59 unsigned long base;
54 hw_regs_t hw; 60 hw_regs_t hw;
55 ide_hwif_t *hwif = NULL; 61 ide_hwif_t *hwif = NULL;
56 ide_drive_t *drive;
57 int i, rc; 62 int i, rc;
58 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; 63 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
59 64
@@ -79,6 +84,7 @@ delkin_cb_probe (struct pci_dev *dev, const struct pci_device_id *id)
79 memset(&hw, 0, sizeof(hw)); 84 memset(&hw, 0, sizeof(hw));
80 ide_std_init_ports(&hw, base + 0x10, base + 0x1e); 85 ide_std_init_ports(&hw, base + 0x10, base + 0x1e);
81 hw.irq = dev->irq; 86 hw.irq = dev->irq;
87 hw.dev = &dev->dev;
82 hw.chipset = ide_pci; /* this enables IRQ sharing */ 88 hw.chipset = ide_pci; /* this enables IRQ sharing */
83 89
84 hwif = ide_find_port(); 90 hwif = ide_find_port();
@@ -89,26 +95,16 @@ delkin_cb_probe (struct pci_dev *dev, const struct pci_device_id *id)
89 95
90 ide_init_port_data(hwif, i); 96 ide_init_port_data(hwif, i);
91 ide_init_port_hw(hwif, &hw); 97 ide_init_port_hw(hwif, &hw);
92 hwif->port_ops = &delkin_cb_port_ops;
93 98
94 idx[0] = i; 99 idx[0] = i;
95 100
96 ide_device_add(idx, NULL); 101 ide_device_add(idx, &delkin_cb_port_info);
97
98 if (!hwif->present)
99 goto out_disable;
100 102
101 pci_set_drvdata(dev, hwif); 103 pci_set_drvdata(dev, hwif);
102 hwif->dev = &dev->dev; 104
103 drive = &hwif->drives[0];
104 if (drive->present) {
105 drive->io_32bit = 1;
106 drive->unmask = 1;
107 }
108 return 0; 105 return 0;
109 106
110out_disable: 107out_disable:
111 printk(KERN_ERR "delkin_cb: no IDE devices found\n");
112 pci_release_regions(dev); 108 pci_release_regions(dev);
113 pci_disable_device(dev); 109 pci_disable_device(dev);
114 return -ENODEV; 110 return -ENODEV;
@@ -139,14 +135,12 @@ static struct pci_driver driver = {
139 .remove = delkin_cb_remove, 135 .remove = delkin_cb_remove,
140}; 136};
141 137
142static int 138static int __init delkin_cb_init(void)
143delkin_cb_init (void)
144{ 139{
145 return pci_register_driver(&driver); 140 return pci_register_driver(&driver);
146} 141}
147 142
148static void 143static void __exit delkin_cb_exit(void)
149delkin_cb_exit (void)
150{ 144{
151 pci_unregister_driver(&driver); 145 pci_unregister_driver(&driver);
152} 146}
diff --git a/drivers/ide/pci/opti621.c b/drivers/ide/pci/opti621.c
index 6e99080497bf..725c80508d90 100644
--- a/drivers/ide/pci/opti621.c
+++ b/drivers/ide/pci/opti621.c
@@ -81,8 +81,6 @@
81 * 0.5 doesn't work. 81 * 0.5 doesn't work.
82 */ 82 */
83 83
84#define OPTI621_DEBUG /* define for debug messages */
85
86#include <linux/types.h> 84#include <linux/types.h>
87#include <linux/module.h> 85#include <linux/module.h>
88#include <linux/kernel.h> 86#include <linux/kernel.h>
@@ -92,28 +90,6 @@
92 90
93#include <asm/io.h> 91#include <asm/io.h>
94 92
95//#define OPTI621_MAX_PIO 3
96/* In fact, I do not have any PIO 4 drive
97 * (address: 25 ns, data: 70 ns, recovery: 35 ns),
98 * but OPTi 82C621 is programmable and it can do (minimal values):
99 * on 40MHz PCI bus (pulse 25 ns):
100 * address: 25 ns, data: 25 ns, recovery: 50 ns;
101 * on 20MHz PCI bus (pulse 50 ns):
102 * address: 50 ns, data: 50 ns, recovery: 100 ns.
103 */
104
105/* #define READ_PREFETCH 0 */
106/* Uncomment for disable read prefetch.
107 * There is some readprefetch capatibility in hdparm,
108 * but when I type hdparm -P 1 /dev/hda, I got errors
109 * and till reset drive is inaccessible.
110 * This (hw) read prefetch is safe on my drive.
111 */
112
113#ifndef READ_PREFETCH
114#define READ_PREFETCH 0x40 /* read prefetch is enabled */
115#endif /* else read prefetch is disabled */
116
117#define READ_REG 0 /* index of Read cycle timing register */ 93#define READ_REG 0 /* index of Read cycle timing register */
118#define WRITE_REG 1 /* index of Write cycle timing register */ 94#define WRITE_REG 1 /* index of Write cycle timing register */
119#define CNTRL_REG 3 /* index of Control register */ 95#define CNTRL_REG 3 /* index of Control register */
@@ -122,51 +98,8 @@
122 98
123static int reg_base; 99static int reg_base;
124 100
125#define PIO_NOT_EXIST 254
126#define PIO_DONT_KNOW 255
127
128static DEFINE_SPINLOCK(opti621_lock); 101static DEFINE_SPINLOCK(opti621_lock);
129 102
130/* there are stored pio numbers from other calls of opti621_set_pio_mode */
131static void compute_pios(ide_drive_t *drive, const u8 pio)
132/* Store values into drive->drive_data
133 * second_contr - 0 for primary controller, 1 for secondary
134 * slave_drive - 0 -> pio is for master, 1 -> pio is for slave
135 * pio - PIO mode for selected drive (for other we don't know)
136 */
137{
138 int d;
139 ide_hwif_t *hwif = HWIF(drive);
140
141 drive->drive_data = pio;
142
143 for (d = 0; d < 2; ++d) {
144 drive = &hwif->drives[d];
145 if (drive->present) {
146 if (drive->drive_data == PIO_DONT_KNOW)
147 drive->drive_data = ide_get_best_pio_mode(drive, 255, 3);
148#ifdef OPTI621_DEBUG
149 printk("%s: Selected PIO mode %d\n",
150 drive->name, drive->drive_data);
151#endif
152 } else {
153 drive->drive_data = PIO_NOT_EXIST;
154 }
155 }
156}
157
158static int cmpt_clk(int time, int bus_speed)
159/* Returns (rounded up) time in clocks for time in ns,
160 * with bus_speed in MHz.
161 * Example: bus_speed = 40 MHz, time = 80 ns
162 * 1000/40 = 25 ns (clk value),
163 * 80/25 = 3.2, rounded up to 4 (I hope ;-)).
164 * Use idebus=xx to select right frequency.
165 */
166{
167 return ((time*bus_speed+999)/1000);
168}
169
170/* Write value to register reg, base of register 103/* Write value to register reg, base of register
171 * is at reg_base (0x1f0 primary, 0x170 secondary, 104 * is at reg_base (0x1f0 primary, 0x170 secondary,
172 * if not changed by PCI configuration). 105 * if not changed by PCI configuration).
@@ -199,83 +132,29 @@ static u8 read_reg(int reg)
199 return ret; 132 return ret;
200} 133}
201 134
202typedef struct pio_clocks_s {
203 int address_time; /* Address setup (clocks) */
204 int data_time; /* Active/data pulse (clocks) */
205 int recovery_time; /* Recovery time (clocks) */
206} pio_clocks_t;
207
208static void compute_clocks(int pio, pio_clocks_t *clks)
209{
210 if (pio != PIO_NOT_EXIST) {
211 int adr_setup, data_pls;
212 int bus_speed = ide_pci_clk ? ide_pci_clk : system_bus_clock();
213
214 adr_setup = ide_pio_timings[pio].setup_time;
215 data_pls = ide_pio_timings[pio].active_time;
216 clks->address_time = cmpt_clk(adr_setup, bus_speed);
217 clks->data_time = cmpt_clk(data_pls, bus_speed);
218 clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
219 - adr_setup-data_pls, bus_speed);
220 if (clks->address_time < 1)
221 clks->address_time = 1;
222 if (clks->address_time > 4)
223 clks->address_time = 4;
224 if (clks->data_time < 1)
225 clks->data_time = 1;
226 if (clks->data_time > 16)
227 clks->data_time = 16;
228 if (clks->recovery_time < 2)
229 clks->recovery_time = 2;
230 if (clks->recovery_time > 17)
231 clks->recovery_time = 17;
232 } else {
233 clks->address_time = 1;
234 clks->data_time = 1;
235 clks->recovery_time = 2;
236 /* minimal values */
237 }
238}
239
240static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio) 135static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
241{ 136{
242 /* primary and secondary drives share some registers, 137 ide_hwif_t *hwif = drive->hwif;
243 * so we have to program both drives 138 ide_drive_t *pair = ide_get_paired_drive(drive);
244 */
245 unsigned long flags; 139 unsigned long flags;
246 u8 pio1 = 0, pio2 = 0; 140 u8 tim, misc, addr_pio = pio, clk;
247 pio_clocks_t first, second; 141
248 int ax, drdy; 142 /* DRDY is default 2 (by OPTi Databook) */
249 u8 cycle1, cycle2, misc; 143 static const u8 addr_timings[2][5] = {
250 ide_hwif_t *hwif = HWIF(drive); 144 { 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */
251 145 { 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */
252 /* sets drive->drive_data for both drives */ 146 };
253 compute_pios(drive, pio); 147 static const u8 data_rec_timings[2][5] = {
254 pio1 = hwif->drives[0].drive_data; 148 { 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */
255 pio2 = hwif->drives[1].drive_data; 149 { 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */
256 150 };
257 compute_clocks(pio1, &first); 151
258 compute_clocks(pio2, &second); 152 drive->drive_data = XFER_PIO_0 + pio;
259 153
260 /* ax = max(a1,a2) */ 154 if (pair->present) {
261 ax = (first.address_time < second.address_time) ? second.address_time : first.address_time; 155 if (pair->drive_data && pair->drive_data < drive->drive_data)
262 156 addr_pio = pair->drive_data - XFER_PIO_0;
263 drdy = 2; /* DRDY is default 2 (by OPTi Databook) */ 157 }
264
265 cycle1 = ((first.data_time-1)<<4) | (first.recovery_time-2);
266 cycle2 = ((second.data_time-1)<<4) | (second.recovery_time-2);
267 misc = READ_PREFETCH | ((ax-1)<<4) | ((drdy-2)<<1);
268
269#ifdef OPTI621_DEBUG
270 printk("%s: master: address: %d, data: %d, "
271 "recovery: %d, drdy: %d [clk]\n",
272 hwif->name, ax, first.data_time,
273 first.recovery_time, drdy);
274 printk("%s: slave: address: %d, data: %d, "
275 "recovery: %d, drdy: %d [clk]\n",
276 hwif->name, ax, second.data_time,
277 second.recovery_time, drdy);
278#endif
279 158
280 spin_lock_irqsave(&opti621_lock, flags); 159 spin_lock_irqsave(&opti621_lock, flags);
281 160
@@ -289,24 +168,21 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
289 (void)inb(reg_base + CNTRL_REG); 168 (void)inb(reg_base + CNTRL_REG);
290 /* if reads 0xc0, no interface exist? */ 169 /* if reads 0xc0, no interface exist? */
291 read_reg(CNTRL_REG); 170 read_reg(CNTRL_REG);
292 /* read version, probably 0 */
293 read_reg(STRAP_REG);
294 171
295 /* program primary drive */ 172 /* check CLK speed */
296 /* select Index-0 for Register-A */ 173 clk = read_reg(STRAP_REG) & 1;
297 write_reg(0, MISC_REG); 174
298 /* set read cycle timings */ 175 printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);
299 write_reg(cycle1, READ_REG);
300 /* set write cycle timings */
301 write_reg(cycle1, WRITE_REG);
302 176
303 /* program secondary drive */ 177 tim = data_rec_timings[clk][pio];
304 /* select Index-1 for Register-B */ 178 misc = addr_timings[clk][addr_pio];
305 write_reg(1, MISC_REG); 179
180 /* select Index-0/1 for Register-A/B */
181 write_reg(drive->select.b.unit, MISC_REG);
306 /* set read cycle timings */ 182 /* set read cycle timings */
307 write_reg(cycle2, READ_REG); 183 write_reg(tim, READ_REG);
308 /* set write cycle timings */ 184 /* set write cycle timings */
309 write_reg(cycle2, WRITE_REG); 185 write_reg(tim, WRITE_REG);
310 186
311 /* use Register-A for drive 0 */ 187 /* use Register-A for drive 0 */
312 /* use Register-B for drive 1 */ 188 /* use Register-B for drive 1 */
@@ -319,45 +195,26 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
319 spin_unlock_irqrestore(&opti621_lock, flags); 195 spin_unlock_irqrestore(&opti621_lock, flags);
320} 196}
321 197
322static void __devinit opti621_port_init_devs(ide_hwif_t *hwif)
323{
324 hwif->drives[0].drive_data = PIO_DONT_KNOW;
325 hwif->drives[1].drive_data = PIO_DONT_KNOW;
326}
327
328static const struct ide_port_ops opti621_port_ops = { 198static const struct ide_port_ops opti621_port_ops = {
329 .port_init_devs = opti621_port_init_devs,
330 .set_pio_mode = opti621_set_pio_mode, 199 .set_pio_mode = opti621_set_pio_mode,
331}; 200};
332 201
333static const struct ide_port_info opti621_chipsets[] __devinitdata = { 202static const struct ide_port_info opti621_chipset __devinitdata = {
334 { /* 0 */ 203 .name = "OPTI621/X",
335 .name = "OPTI621", 204 .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
336 .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} }, 205 .port_ops = &opti621_port_ops,
337 .port_ops = &opti621_port_ops, 206 .host_flags = IDE_HFLAG_NO_DMA,
338 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 207 .pio_mask = ATA_PIO4,
339 .pio_mask = ATA_PIO3,
340 .swdma_mask = ATA_SWDMA2,
341 .mwdma_mask = ATA_MWDMA2,
342 }, { /* 1 */
343 .name = "OPTI621X",
344 .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
345 .port_ops = &opti621_port_ops,
346 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
347 .pio_mask = ATA_PIO3,
348 .swdma_mask = ATA_SWDMA2,
349 .mwdma_mask = ATA_MWDMA2,
350 }
351}; 208};
352 209
353static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id) 210static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
354{ 211{
355 return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]); 212 return ide_setup_pci_device(dev, &opti621_chipset);
356} 213}
357 214
358static const struct pci_device_id opti621_pci_tbl[] = { 215static const struct pci_device_id opti621_pci_tbl[] = {
359 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 }, 216 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
360 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 }, 217 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 },
361 { 0, }, 218 { 0, },
362}; 219};
363MODULE_DEVICE_TABLE(pci, opti621_pci_tbl); 220MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
diff --git a/drivers/ide/pci/sis5513.c b/drivers/ide/pci/sis5513.c
index 4b0b85d8faf5..e127eb25ab63 100644
--- a/drivers/ide/pci/sis5513.c
+++ b/drivers/ide/pci/sis5513.c
@@ -569,6 +569,11 @@ static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_devi
569{ 569{
570 struct ide_port_info d = sis5513_chipset; 570 struct ide_port_info d = sis5513_chipset;
571 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f }; 571 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
572 int rc;
573
574 rc = pci_enable_device(dev);
575 if (rc)
576 return rc;
572 577
573 if (sis_find_family(dev) == 0) 578 if (sis_find_family(dev) == 0)
574 return -ENOTSUPP; 579 return -ENOTSUPP;