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path: root/drivers/ide/pci/piix.c
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Diffstat (limited to 'drivers/ide/pci/piix.c')
-rw-r--r--drivers/ide/pci/piix.c163
1 files changed, 33 insertions, 130 deletions
diff --git a/drivers/ide/pci/piix.c b/drivers/ide/pci/piix.c
index 061d300ab8be..8b219dd63024 100644
--- a/drivers/ide/pci/piix.c
+++ b/drivers/ide/pci/piix.c
@@ -106,68 +106,6 @@
106static int no_piix_dma; 106static int no_piix_dma;
107 107
108/** 108/**
109 * piix_ratemask - compute rate mask for PIIX IDE
110 * @drive: IDE drive to compute for
111 *
112 * Returns the available modes for the PIIX IDE controller.
113 */
114
115static u8 piix_ratemask (ide_drive_t *drive)
116{
117 struct pci_dev *dev = HWIF(drive)->pci_dev;
118 u8 mode;
119
120 switch(dev->device) {
121 case PCI_DEVICE_ID_INTEL_82801EB_1:
122 mode = 3;
123 break;
124 /* UDMA 100 capable */
125 case PCI_DEVICE_ID_INTEL_82801BA_8:
126 case PCI_DEVICE_ID_INTEL_82801BA_9:
127 case PCI_DEVICE_ID_INTEL_82801CA_10:
128 case PCI_DEVICE_ID_INTEL_82801CA_11:
129 case PCI_DEVICE_ID_INTEL_82801E_11:
130 case PCI_DEVICE_ID_INTEL_82801DB_1:
131 case PCI_DEVICE_ID_INTEL_82801DB_10:
132 case PCI_DEVICE_ID_INTEL_82801DB_11:
133 case PCI_DEVICE_ID_INTEL_82801EB_11:
134 case PCI_DEVICE_ID_INTEL_ESB_2:
135 case PCI_DEVICE_ID_INTEL_ICH6_19:
136 case PCI_DEVICE_ID_INTEL_ICH7_21:
137 case PCI_DEVICE_ID_INTEL_ESB2_18:
138 case PCI_DEVICE_ID_INTEL_ICH8_6:
139 mode = 3;
140 break;
141 /* UDMA 66 capable */
142 case PCI_DEVICE_ID_INTEL_82801AA_1:
143 case PCI_DEVICE_ID_INTEL_82372FB_1:
144 mode = 2;
145 break;
146 /* UDMA 33 capable */
147 case PCI_DEVICE_ID_INTEL_82371AB:
148 case PCI_DEVICE_ID_INTEL_82443MX_1:
149 case PCI_DEVICE_ID_INTEL_82451NX:
150 case PCI_DEVICE_ID_INTEL_82801AB_1:
151 return 1;
152 /* Non UDMA capable (MWDMA2) */
153 case PCI_DEVICE_ID_INTEL_82371SB_1:
154 case PCI_DEVICE_ID_INTEL_82371FB_1:
155 case PCI_DEVICE_ID_INTEL_82371FB_0:
156 case PCI_DEVICE_ID_INTEL_82371MX:
157 default:
158 return 0;
159 }
160
161 /*
162 * If we are UDMA66 capable fall back to UDMA33
163 * if the drive cannot see an 80pin cable.
164 */
165 if (!eighty_ninty_three(drive))
166 mode = min_t(u8, mode, 1);
167 return mode;
168}
169
170/**
171 * piix_dma_2_pio - return the PIO mode matching DMA 109 * piix_dma_2_pio - return the PIO mode matching DMA
172 * @xfer_rate: transfer speed 110 * @xfer_rate: transfer speed
173 * 111 *
@@ -301,7 +239,7 @@ static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
301 ide_hwif_t *hwif = HWIF(drive); 239 ide_hwif_t *hwif = HWIF(drive);
302 struct pci_dev *dev = hwif->pci_dev; 240 struct pci_dev *dev = hwif->pci_dev;
303 u8 maslave = hwif->channel ? 0x42 : 0x40; 241 u8 maslave = hwif->channel ? 0x42 : 0x40;
304 u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed); 242 u8 speed = ide_rate_filter(drive, xferspeed);
305 int a_speed = 3 << (drive->dn * 4); 243 int a_speed = 3 << (drive->dn * 4);
306 int u_flag = 1 << drive->dn; 244 int u_flag = 1 << drive->dn;
307 int v_flag = 0x01 << drive->dn; 245 int v_flag = 0x01 << drive->dn;
@@ -366,30 +304,6 @@ static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
366} 304}
367 305
368/** 306/**
369 * piix_config_drive_for_dma - configure drive for DMA
370 * @drive: IDE drive to configure
371 *
372 * Set up a PIIX interface channel for the best available speed.
373 * We prefer UDMA if it is available and then MWDMA. If DMA is
374 * not available we switch to PIO and return 0.
375 */
376
377static int piix_config_drive_for_dma (ide_drive_t *drive)
378{
379 u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
380
381 /*
382 * If no DMA speed was available or the chipset has DMA bugs
383 * then disable DMA and use PIO
384 */
385 if (!speed)
386 return 0;
387
388 (void) piix_tune_chipset(drive, speed);
389 return ide_dma_enable(drive);
390}
391
392/**
393 * piix_config_drive_xfer_rate - set up an IDE device 307 * piix_config_drive_xfer_rate - set up an IDE device
394 * @drive: IDE drive to configure 308 * @drive: IDE drive to configure
395 * 309 *
@@ -401,7 +315,7 @@ static int piix_config_drive_xfer_rate (ide_drive_t *drive)
401{ 315{
402 drive->init_speed = 0; 316 drive->init_speed = 0;
403 317
404 if (ide_use_dma(drive) && piix_config_drive_for_dma(drive)) 318 if (ide_tune_dma(drive))
405 return 0; 319 return 0;
406 320
407 if (ide_use_fast_pio(drive)) 321 if (ide_use_fast_pio(drive))
@@ -524,26 +438,14 @@ static void __devinit init_hwif_piix(ide_hwif_t *hwif)
524 hwif->ide_dma_clear_irq = &piix_dma_clear_irq; 438 hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
525 439
526 hwif->atapi_dma = 1; 440 hwif->atapi_dma = 1;
527 hwif->ultra_mask = 0x3f; 441
442 hwif->ultra_mask = hwif->cds->udma_mask;
528 hwif->mwdma_mask = 0x06; 443 hwif->mwdma_mask = 0x06;
529 hwif->swdma_mask = 0x04; 444 hwif->swdma_mask = 0x04;
530 445
531 switch(hwif->pci_dev->device) { 446 if (hwif->ultra_mask & 0x78) {
532 case PCI_DEVICE_ID_INTEL_82371FB_0: 447 if (!hwif->udma_four)
533 case PCI_DEVICE_ID_INTEL_82371FB_1: 448 hwif->udma_four = piix_cable_detect(hwif);
534 case PCI_DEVICE_ID_INTEL_82371SB_1:
535 hwif->ultra_mask = 0x80;
536 break;
537 case PCI_DEVICE_ID_INTEL_82371AB:
538 case PCI_DEVICE_ID_INTEL_82443MX_1:
539 case PCI_DEVICE_ID_INTEL_82451NX:
540 case PCI_DEVICE_ID_INTEL_82801AB_1:
541 hwif->ultra_mask = 0x07;
542 break;
543 default:
544 if (!hwif->udma_four)
545 hwif->udma_four = piix_cable_detect(hwif);
546 break;
547 } 449 }
548 450
549 if (no_piix_dma) 451 if (no_piix_dma)
@@ -557,7 +459,7 @@ static void __devinit init_hwif_piix(ide_hwif_t *hwif)
557 hwif->drives[0].autodma = hwif->autodma; 459 hwif->drives[0].autodma = hwif->autodma;
558} 460}
559 461
560#define DECLARE_PIIX_DEV(name_str) \ 462#define DECLARE_PIIX_DEV(name_str, udma) \
561 { \ 463 { \
562 .name = name_str, \ 464 .name = name_str, \
563 .init_chipset = init_chipset_piix, \ 465 .init_chipset = init_chipset_piix, \
@@ -566,11 +468,12 @@ static void __devinit init_hwif_piix(ide_hwif_t *hwif)
566 .autodma = AUTODMA, \ 468 .autodma = AUTODMA, \
567 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ 469 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
568 .bootable = ON_BOARD, \ 470 .bootable = ON_BOARD, \
471 .udma_mask = udma, \
569 } 472 }
570 473
571static ide_pci_device_t piix_pci_info[] __devinitdata = { 474static ide_pci_device_t piix_pci_info[] __devinitdata = {
572 /* 0 */ DECLARE_PIIX_DEV("PIIXa"), 475 /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */
573 /* 1 */ DECLARE_PIIX_DEV("PIIXb"), 476 /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */
574 477
575 /* 2 */ 478 /* 2 */
576 { /* 479 { /*
@@ -587,28 +490,28 @@ static ide_pci_device_t piix_pci_info[] __devinitdata = {
587 .flags = IDEPCI_FLAG_ISA_PORTS 490 .flags = IDEPCI_FLAG_ISA_PORTS
588 }, 491 },
589 492
590 /* 3 */ DECLARE_PIIX_DEV("PIIX3"), 493 /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */
591 /* 4 */ DECLARE_PIIX_DEV("PIIX4"), 494 /* 4 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
592 /* 5 */ DECLARE_PIIX_DEV("ICH0"), 495 /* 5 */ DECLARE_PIIX_DEV("ICH0", 0x07), /* udma0-2 */
593 /* 6 */ DECLARE_PIIX_DEV("PIIX4"), 496 /* 6 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
594 /* 7 */ DECLARE_PIIX_DEV("ICH"), 497 /* 7 */ DECLARE_PIIX_DEV("ICH", 0x1f), /* udma0-4 */
595 /* 8 */ DECLARE_PIIX_DEV("PIIX4"), 498 /* 8 */ DECLARE_PIIX_DEV("PIIX4", 0x1f), /* udma0-4 */
596 /* 9 */ DECLARE_PIIX_DEV("PIIX4"), 499 /* 9 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
597 /* 10 */ DECLARE_PIIX_DEV("ICH2"), 500 /* 10 */ DECLARE_PIIX_DEV("ICH2", 0x3f), /* udma0-5 */
598 /* 11 */ DECLARE_PIIX_DEV("ICH2M"), 501 /* 11 */ DECLARE_PIIX_DEV("ICH2M", 0x3f), /* udma0-5 */
599 /* 12 */ DECLARE_PIIX_DEV("ICH3M"), 502 /* 12 */ DECLARE_PIIX_DEV("ICH3M", 0x3f), /* udma0-5 */
600 /* 13 */ DECLARE_PIIX_DEV("ICH3"), 503 /* 13 */ DECLARE_PIIX_DEV("ICH3", 0x3f), /* udma0-5 */
601 /* 14 */ DECLARE_PIIX_DEV("ICH4"), 504 /* 14 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
602 /* 15 */ DECLARE_PIIX_DEV("ICH5"), 505 /* 15 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
603 /* 16 */ DECLARE_PIIX_DEV("C-ICH"), 506 /* 16 */ DECLARE_PIIX_DEV("C-ICH", 0x3f), /* udma0-5 */
604 /* 17 */ DECLARE_PIIX_DEV("ICH4"), 507 /* 17 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
605 /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"), 508 /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA", 0x3f), /* udma0-5 */
606 /* 19 */ DECLARE_PIIX_DEV("ICH5"), 509 /* 19 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
607 /* 20 */ DECLARE_PIIX_DEV("ICH6"), 510 /* 20 */ DECLARE_PIIX_DEV("ICH6", 0x3f), /* udma0-5 */
608 /* 21 */ DECLARE_PIIX_DEV("ICH7"), 511 /* 21 */ DECLARE_PIIX_DEV("ICH7", 0x3f), /* udma0-5 */
609 /* 22 */ DECLARE_PIIX_DEV("ICH4"), 512 /* 22 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
610 /* 23 */ DECLARE_PIIX_DEV("ESB2"), 513 /* 23 */ DECLARE_PIIX_DEV("ESB2", 0x3f), /* udma0-5 */
611 /* 24 */ DECLARE_PIIX_DEV("ICH8M"), 514 /* 24 */ DECLARE_PIIX_DEV("ICH8M", 0x3f), /* udma0-5 */
612}; 515};
613 516
614/** 517/**