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path: root/drivers/ide/pci/it8172.c
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Diffstat (limited to 'drivers/ide/pci/it8172.c')
-rw-r--r--drivers/ide/pci/it8172.c307
1 files changed, 0 insertions, 307 deletions
diff --git a/drivers/ide/pci/it8172.c b/drivers/ide/pci/it8172.c
deleted file mode 100644
index 0fc89fafad65..000000000000
--- a/drivers/ide/pci/it8172.c
+++ /dev/null
@@ -1,307 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 IDE controller support
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * stevel@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/kernel.h>
34#include <linux/ioport.h>
35#include <linux/pci.h>
36#include <linux/hdreg.h>
37#include <linux/ide.h>
38#include <linux/delay.h>
39#include <linux/init.h>
40
41#include <asm/io.h>
42#include <asm/it8172/it8172_int.h>
43
44/*
45 * Prototypes
46 */
47static u8 it8172_ratemask (ide_drive_t *drive)
48{
49 return 1;
50}
51
52static void it8172_tune_drive (ide_drive_t *drive, u8 pio)
53{
54 ide_hwif_t *hwif = HWIF(drive);
55 struct pci_dev *dev = hwif->pci_dev;
56 int is_slave = (&hwif->drives[1] == drive);
57 unsigned long flags;
58 u16 drive_enables;
59 u32 drive_timing;
60
61 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
62 spin_lock_irqsave(&ide_lock, flags);
63 pci_read_config_word(dev, 0x40, &drive_enables);
64 pci_read_config_dword(dev, 0x44, &drive_timing);
65
66 /*
67 * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
68 * are being left at the default values of 8 PCI clocks (242 nsec
69 * for a 33 MHz clock). These can be safely shortened at higher
70 * PIO modes. The DIOR/DIOW pulse width and recovery times only
71 * apply to PIO modes, not to the DMA modes.
72 */
73
74 /*
75 * Enable port 0x44. The IT8172G spec is confused; it calls
76 * this register the "Slave IDE Timing Register", but in fact,
77 * it controls timing for both master and slave drives.
78 */
79 drive_enables |= 0x4000;
80
81 if (is_slave) {
82 drive_enables &= 0xc006;
83 if (pio > 1)
84 /* enable prefetch and IORDY sample-point */
85 drive_enables |= 0x0060;
86 } else {
87 drive_enables &= 0xc060;
88 if (pio > 1)
89 /* enable prefetch and IORDY sample-point */
90 drive_enables |= 0x0006;
91 }
92
93 pci_write_config_word(dev, 0x40, drive_enables);
94 spin_unlock_irqrestore(&ide_lock, flags);
95}
96
97static u8 it8172_dma_2_pio (u8 xfer_rate)
98{
99 switch(xfer_rate) {
100 case XFER_UDMA_5:
101 case XFER_UDMA_4:
102 case XFER_UDMA_3:
103 case XFER_UDMA_2:
104 case XFER_UDMA_1:
105 case XFER_UDMA_0:
106 case XFER_MW_DMA_2:
107 case XFER_PIO_4:
108 return 4;
109 case XFER_MW_DMA_1:
110 case XFER_PIO_3:
111 return 3;
112 case XFER_SW_DMA_2:
113 case XFER_PIO_2:
114 return 2;
115 case XFER_MW_DMA_0:
116 case XFER_SW_DMA_1:
117 case XFER_SW_DMA_0:
118 case XFER_PIO_1:
119 case XFER_PIO_0:
120 case XFER_PIO_SLOW:
121 default:
122 return 0;
123 }
124}
125
126static int it8172_tune_chipset (ide_drive_t *drive, u8 xferspeed)
127{
128 ide_hwif_t *hwif = HWIF(drive);
129 struct pci_dev *dev = hwif->pci_dev;
130 u8 speed = ide_rate_filter(it8172_ratemask(drive), xferspeed);
131 int a_speed = 3 << (drive->dn * 4);
132 int u_flag = 1 << drive->dn;
133 int u_speed = 0;
134 u8 reg48, reg4a;
135
136 pci_read_config_byte(dev, 0x48, &reg48);
137 pci_read_config_byte(dev, 0x4a, &reg4a);
138
139 /*
140 * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
141 * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
142 * transfers on some drives, even though both numbers meet the minimum
143 * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
144 * So the faster times are just commented out here. The good news is
145 * that the slower cycle time has very little affect on transfer
146 * performance.
147 */
148
149 switch(speed) {
150 case XFER_UDMA_4:
151 case XFER_UDMA_2: //u_speed = 2 << (drive->dn * 4); break;
152 case XFER_UDMA_5:
153 case XFER_UDMA_3:
154 case XFER_UDMA_1: //u_speed = 1 << (drive->dn * 4); break;
155 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
156 case XFER_MW_DMA_2:
157 case XFER_MW_DMA_1:
158 case XFER_MW_DMA_0:
159 case XFER_SW_DMA_2: break;
160 case XFER_PIO_4:
161 case XFER_PIO_3:
162 case XFER_PIO_2:
163 case XFER_PIO_0: break;
164 default: return -1;
165 }
166
167 if (speed >= XFER_UDMA_0) {
168 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
169 reg4a &= ~a_speed;
170 pci_write_config_byte(dev, 0x4a, reg4a | u_speed);
171 } else {
172 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
173 pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);
174 }
175
176 it8172_tune_drive(drive, it8172_dma_2_pio(speed));
177 return (ide_config_drive_speed(drive, speed));
178}
179
180static int it8172_config_chipset_for_dma (ide_drive_t *drive)
181{
182 u8 speed = ide_dma_speed(drive, it8172_ratemask(drive));
183
184 if (!(speed)) {
185 u8 tspeed = ide_get_best_pio_mode(drive, 255, 4, NULL);
186 speed = it8172_dma_2_pio(XFER_PIO_0 + tspeed);
187 }
188
189 (void) it8172_tune_chipset(drive, speed);
190 return ide_dma_enable(drive);
191}
192
193static int it8172_config_drive_xfer_rate (ide_drive_t *drive)
194{
195 ide_hwif_t *hwif = HWIF(drive);
196 struct hd_driveid *id = drive->id;
197
198 drive->init_speed = 0;
199
200 if (id && (id->capability & 1) && drive->autodma) {
201
202 if (ide_use_dma(drive)) {
203 if (it8172_config_chipset_for_dma(drive))
204 return hwif->ide_dma_on(drive);
205 }
206
207 goto fast_ata_pio;
208
209 } else if ((id->capability & 8) || (id->field_valid & 2)) {
210fast_ata_pio:
211 it8172_tune_drive(drive, 5);
212 return hwif->ide_dma_off_quietly(drive);
213 }
214 /* IORDY not supported */
215 return 0;
216}
217
218static unsigned int __devinit init_chipset_it8172 (struct pci_dev *dev, const char *name)
219{
220 unsigned char progif;
221
222 /*
223 * Place both IDE interfaces into PCI "native" mode
224 */
225 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
226 pci_write_config_byte(dev, PCI_CLASS_PROG, progif | 0x05);
227
228 return IT8172_IDE_IRQ;
229}
230
231
232static void __devinit init_hwif_it8172 (ide_hwif_t *hwif)
233{
234 struct pci_dev* dev = hwif->pci_dev;
235 unsigned long cmdBase, ctrlBase;
236
237 hwif->autodma = 0;
238 hwif->tuneproc = &it8172_tune_drive;
239 hwif->speedproc = &it8172_tune_chipset;
240
241 cmdBase = dev->resource[0].start;
242 ctrlBase = dev->resource[1].start;
243
244 ide_init_hwif_ports(&hwif->hw, cmdBase, ctrlBase | 2, NULL);
245 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
246 hwif->noprobe = 0;
247
248 if (!hwif->dma_base) {
249 hwif->drives[0].autotune = 1;
250 hwif->drives[1].autotune = 1;
251 return;
252 }
253
254 hwif->atapi_dma = 1;
255 hwif->ultra_mask = 0x07;
256 hwif->mwdma_mask = 0x06;
257 hwif->swdma_mask = 0x04;
258
259 hwif->ide_dma_check = &it8172_config_drive_xfer_rate;
260 if (!noautodma)
261 hwif->autodma = 1;
262 hwif->drives[0].autodma = hwif->autodma;
263 hwif->drives[1].autodma = hwif->autodma;
264}
265
266static ide_pci_device_t it8172_chipsets[] __devinitdata = {
267 { /* 0 */
268 .name = "IT8172G",
269 .init_chipset = init_chipset_it8172,
270 .init_hwif = init_hwif_it8172,
271 .channels = 2,
272 .autodma = AUTODMA,
273 .enablebits = {{0x00,0x00,0x00}, {0x40,0x00,0x01}},
274 .bootable = ON_BOARD,
275 }
276};
277
278static int __devinit it8172_init_one(struct pci_dev *dev, const struct pci_device_id *id)
279{
280 if ((!(PCI_FUNC(dev->devfn) & 1) ||
281 (!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))
282 return -ENODEV; /* IT8172 is more than an IDE controller */
283 return ide_setup_pci_device(dev, &it8172_chipsets[id->driver_data]);
284}
285
286static struct pci_device_id it8172_pci_tbl[] = {
287 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
288 { 0, },
289};
290MODULE_DEVICE_TABLE(pci, it8172_pci_tbl);
291
292static struct pci_driver driver = {
293 .name = "IT8172_IDE",
294 .id_table = it8172_pci_tbl,
295 .probe = it8172_init_one,
296};
297
298static int it8172_ide_init(void)
299{
300 return ide_pci_register_driver(&driver);
301}
302
303module_init(it8172_ide_init);
304
305MODULE_AUTHOR("SteveL@mvista.com");
306MODULE_DESCRIPTION("PCI driver module for ITE 8172 IDE");
307MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 03:26:47 -0500