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path: root/drivers/ide/pci/hpt366.c
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Diffstat (limited to 'drivers/ide/pci/hpt366.c')
-rw-r--r--drivers/ide/pci/hpt366.c61
1 files changed, 1 insertions, 60 deletions
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index 6357bb6269ab..82d0e318a1fe 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -760,7 +760,7 @@ static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
760 } 760 }
761 } else 761 } else
762 outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), 762 outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
763 IDE_CONTROL_REG); 763 hwif->io_ports[IDE_CONTROL_OFFSET]);
764} 764}
765 765
766/* 766/*
@@ -929,64 +929,6 @@ static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
929 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21); 929 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
930} 930}
931 931
932/*
933 * Set/get power state for a drive.
934 * NOTE: affects both drives on each channel.
935 *
936 * When we turn the power back on, we need to re-initialize things.
937 */
938#define TRISTATE_BIT 0x8000
939
940static int hpt3xx_busproc(ide_drive_t *drive, int state)
941{
942 ide_hwif_t *hwif = HWIF(drive);
943 struct pci_dev *dev = to_pci_dev(hwif->dev);
944 u8 mcr_addr = hwif->select_data + 2;
945 u8 resetmask = hwif->channel ? 0x80 : 0x40;
946 u8 bsr2 = 0;
947 u16 mcr = 0;
948
949 hwif->bus_state = state;
950
951 /* Grab the status. */
952 pci_read_config_word(dev, mcr_addr, &mcr);
953 pci_read_config_byte(dev, 0x59, &bsr2);
954
955 /*
956 * Set the state. We don't set it if we don't need to do so.
957 * Make sure that the drive knows that it has failed if it's off.
958 */
959 switch (state) {
960 case BUSSTATE_ON:
961 if (!(bsr2 & resetmask))
962 return 0;
963 hwif->drives[0].failures = hwif->drives[1].failures = 0;
964
965 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
966 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
967 return 0;
968 case BUSSTATE_OFF:
969 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
970 return 0;
971 mcr &= ~TRISTATE_BIT;
972 break;
973 case BUSSTATE_TRISTATE:
974 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
975 return 0;
976 mcr |= TRISTATE_BIT;
977 break;
978 default:
979 return -EINVAL;
980 }
981
982 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
983 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
984
985 pci_write_config_word(dev, mcr_addr, mcr);
986 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
987 return 0;
988}
989
990/** 932/**
991 * hpt37x_calibrate_dpll - calibrate the DPLL 933 * hpt37x_calibrate_dpll - calibrate the DPLL
992 * @dev: PCI device 934 * @dev: PCI device
@@ -1334,7 +1276,6 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1334 1276
1335 hwif->quirkproc = &hpt3xx_quirkproc; 1277 hwif->quirkproc = &hpt3xx_quirkproc;
1336 hwif->maskproc = &hpt3xx_maskproc; 1278 hwif->maskproc = &hpt3xx_maskproc;
1337 hwif->busproc = &hpt3xx_busproc;
1338 1279
1339 hwif->udma_filter = &hpt3xx_udma_filter; 1280 hwif->udma_filter = &hpt3xx_udma_filter;
1340 hwif->mdma_filter = &hpt3xx_mdma_filter; 1281 hwif->mdma_filter = &hpt3xx_mdma_filter;