diff options
Diffstat (limited to 'drivers/i2c/busses/i2c-rcar.c')
| -rw-r--r-- | drivers/i2c/busses/i2c-rcar.c | 266 |
1 files changed, 59 insertions, 207 deletions
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c index d4fa8eba6e9d..899405923678 100644 --- a/drivers/i2c/busses/i2c-rcar.c +++ b/drivers/i2c/busses/i2c-rcar.c | |||
| @@ -1,7 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * drivers/i2c/busses/i2c-rcar.c | 2 | * Driver for the Renesas RCar I2C unit |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2012 Renesas Solutions Corp. | 4 | * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com> |
| 5 | * | ||
| 6 | * Copyright (C) 2012-14 Renesas Solutions Corp. | ||
| 5 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 7 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
| 6 | * | 8 | * |
| 7 | * This file is based on the drivers/i2c/busses/i2c-sh7760.c | 9 | * This file is based on the drivers/i2c/busses/i2c-sh7760.c |
| @@ -12,16 +14,12 @@ | |||
| 12 | * | 14 | * |
| 13 | * This program is free software; you can redistribute it and/or modify | 15 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License as published by | 16 | * it under the terms of the GNU General Public License as published by |
| 15 | * the Free Software Foundation; either version 2 of the License | 17 | * the Free Software Foundation; version 2 of the License. |
| 16 | * | 18 | * |
| 17 | * This program is distributed in the hope that it will be useful, | 19 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. | 22 | * GNU General Public License for more details. |
| 21 | * | ||
| 22 | * You should have received a copy of the GNU General Public License | ||
| 23 | * along with this program; if not, write to the Free Software | ||
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 25 | */ | 23 | */ |
| 26 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
| 27 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
| @@ -36,7 +34,6 @@ | |||
| 36 | #include <linux/platform_device.h> | 34 | #include <linux/platform_device.h> |
| 37 | #include <linux/pm_runtime.h> | 35 | #include <linux/pm_runtime.h> |
| 38 | #include <linux/slab.h> | 36 | #include <linux/slab.h> |
| 39 | #include <linux/spinlock.h> | ||
| 40 | 37 | ||
| 41 | /* register offsets */ | 38 | /* register offsets */ |
| 42 | #define ICSCR 0x00 /* slave ctrl */ | 39 | #define ICSCR 0x00 /* slave ctrl */ |
| @@ -60,7 +57,7 @@ | |||
| 60 | #define FSB (1 << 1) /* force stop bit */ | 57 | #define FSB (1 << 1) /* force stop bit */ |
| 61 | #define ESG (1 << 0) /* en startbit gen */ | 58 | #define ESG (1 << 0) /* en startbit gen */ |
| 62 | 59 | ||
| 63 | /* ICMSR */ | 60 | /* ICMSR (also for ICMIE) */ |
| 64 | #define MNR (1 << 6) /* nack received */ | 61 | #define MNR (1 << 6) /* nack received */ |
| 65 | #define MAL (1 << 5) /* arbitration lost */ | 62 | #define MAL (1 << 5) /* arbitration lost */ |
| 66 | #define MST (1 << 4) /* sent a stop */ | 63 | #define MST (1 << 4) /* sent a stop */ |
| @@ -69,32 +66,18 @@ | |||
| 69 | #define MDR (1 << 1) | 66 | #define MDR (1 << 1) |
| 70 | #define MAT (1 << 0) /* slave addr xfer done */ | 67 | #define MAT (1 << 0) /* slave addr xfer done */ |
| 71 | 68 | ||
| 72 | /* ICMIE */ | ||
| 73 | #define MNRE (1 << 6) /* nack irq en */ | ||
| 74 | #define MALE (1 << 5) /* arblos irq en */ | ||
| 75 | #define MSTE (1 << 4) /* stop irq en */ | ||
| 76 | #define MDEE (1 << 3) | ||
| 77 | #define MDTE (1 << 2) | ||
| 78 | #define MDRE (1 << 1) | ||
| 79 | #define MATE (1 << 0) /* address sent irq en */ | ||
| 80 | 69 | ||
| 70 | #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) | ||
| 71 | #define RCAR_BUS_PHASE_DATA (MDBS | MIE) | ||
| 72 | #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) | ||
| 81 | 73 | ||
| 82 | enum { | 74 | #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) |
| 83 | RCAR_BUS_PHASE_ADDR, | 75 | #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) |
| 84 | RCAR_BUS_PHASE_DATA, | 76 | #define RCAR_IRQ_STOP (MST) |
| 85 | RCAR_BUS_PHASE_STOP, | ||
| 86 | }; | ||
| 87 | 77 | ||
| 88 | enum { | 78 | #define RCAR_IRQ_ACK_SEND (~(MAT | MDE)) |
| 89 | RCAR_IRQ_CLOSE, | 79 | #define RCAR_IRQ_ACK_RECV (~(MAT | MDR)) |
| 90 | RCAR_IRQ_OPEN_FOR_SEND, | ||
| 91 | RCAR_IRQ_OPEN_FOR_RECV, | ||
| 92 | RCAR_IRQ_OPEN_FOR_STOP, | ||
| 93 | }; | ||
| 94 | 80 | ||
| 95 | /* | ||
| 96 | * flags | ||
| 97 | */ | ||
| 98 | #define ID_LAST_MSG (1 << 0) | 81 | #define ID_LAST_MSG (1 << 0) |
| 99 | #define ID_IOERROR (1 << 1) | 82 | #define ID_IOERROR (1 << 1) |
| 100 | #define ID_DONE (1 << 2) | 83 | #define ID_DONE (1 << 2) |
| @@ -112,14 +95,12 @@ struct rcar_i2c_priv { | |||
| 112 | struct i2c_msg *msg; | 95 | struct i2c_msg *msg; |
| 113 | struct clk *clk; | 96 | struct clk *clk; |
| 114 | 97 | ||
| 115 | spinlock_t lock; | ||
| 116 | wait_queue_head_t wait; | 98 | wait_queue_head_t wait; |
| 117 | 99 | ||
| 118 | int pos; | 100 | int pos; |
| 119 | int irq; | ||
| 120 | u32 icccr; | 101 | u32 icccr; |
| 121 | u32 flags; | 102 | u32 flags; |
| 122 | enum rcar_i2c_type devtype; | 103 | enum rcar_i2c_type devtype; |
| 123 | }; | 104 | }; |
| 124 | 105 | ||
| 125 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) | 106 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) |
| @@ -130,9 +111,7 @@ struct rcar_i2c_priv { | |||
| 130 | 111 | ||
| 131 | #define LOOP_TIMEOUT 1024 | 112 | #define LOOP_TIMEOUT 1024 |
| 132 | 113 | ||
| 133 | /* | 114 | |
| 134 | * basic functions | ||
| 135 | */ | ||
| 136 | static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) | 115 | static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) |
| 137 | { | 116 | { |
| 138 | writel(val, priv->io + reg); | 117 | writel(val, priv->io + reg); |
| @@ -161,36 +140,6 @@ static void rcar_i2c_init(struct rcar_i2c_priv *priv) | |||
| 161 | rcar_i2c_write(priv, ICMAR, 0); | 140 | rcar_i2c_write(priv, ICMAR, 0); |
| 162 | } | 141 | } |
| 163 | 142 | ||
| 164 | static void rcar_i2c_irq_mask(struct rcar_i2c_priv *priv, int open) | ||
| 165 | { | ||
| 166 | u32 val = MNRE | MALE | MSTE | MATE; /* default */ | ||
| 167 | |||
| 168 | switch (open) { | ||
| 169 | case RCAR_IRQ_OPEN_FOR_SEND: | ||
| 170 | val |= MDEE; /* default + send */ | ||
| 171 | break; | ||
| 172 | case RCAR_IRQ_OPEN_FOR_RECV: | ||
| 173 | val |= MDRE; /* default + read */ | ||
| 174 | break; | ||
| 175 | case RCAR_IRQ_OPEN_FOR_STOP: | ||
| 176 | val = MSTE; /* stop irq only */ | ||
| 177 | break; | ||
| 178 | case RCAR_IRQ_CLOSE: | ||
| 179 | default: | ||
| 180 | val = 0; /* all close */ | ||
| 181 | break; | ||
| 182 | } | ||
| 183 | rcar_i2c_write(priv, ICMIER, val); | ||
| 184 | } | ||
| 185 | |||
| 186 | static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv) | ||
| 187 | { | ||
| 188 | rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv); | ||
| 189 | } | ||
| 190 | |||
| 191 | /* | ||
| 192 | * bus control functions | ||
| 193 | */ | ||
| 194 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) | 143 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) |
| 195 | { | 144 | { |
| 196 | int i; | 145 | int i; |
| @@ -205,24 +154,6 @@ static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) | |||
| 205 | return -EBUSY; | 154 | return -EBUSY; |
| 206 | } | 155 | } |
| 207 | 156 | ||
| 208 | static void rcar_i2c_bus_phase(struct rcar_i2c_priv *priv, int phase) | ||
| 209 | { | ||
| 210 | switch (phase) { | ||
| 211 | case RCAR_BUS_PHASE_ADDR: | ||
| 212 | rcar_i2c_write(priv, ICMCR, MDBS | MIE | ESG); | ||
| 213 | break; | ||
| 214 | case RCAR_BUS_PHASE_DATA: | ||
| 215 | rcar_i2c_write(priv, ICMCR, MDBS | MIE); | ||
| 216 | break; | ||
| 217 | case RCAR_BUS_PHASE_STOP: | ||
| 218 | rcar_i2c_write(priv, ICMCR, MDBS | MIE | FSB); | ||
| 219 | break; | ||
| 220 | } | ||
| 221 | } | ||
| 222 | |||
| 223 | /* | ||
| 224 | * clock function | ||
| 225 | */ | ||
| 226 | static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, | 157 | static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, |
| 227 | u32 bus_speed, | 158 | u32 bus_speed, |
| 228 | struct device *dev) | 159 | struct device *dev) |
| @@ -312,60 +243,18 @@ scgd_find: | |||
| 312 | return 0; | 243 | return 0; |
| 313 | } | 244 | } |
| 314 | 245 | ||
| 315 | static void rcar_i2c_clock_start(struct rcar_i2c_priv *priv) | 246 | static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) |
| 316 | { | 247 | { |
| 317 | rcar_i2c_write(priv, ICCCR, priv->icccr); | 248 | int read = !!rcar_i2c_is_recv(priv); |
| 318 | } | ||
| 319 | 249 | ||
| 320 | /* | 250 | rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read); |
| 321 | * status functions | 251 | rcar_i2c_write(priv, ICMSR, 0); |
| 322 | */ | 252 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); |
| 323 | static u32 rcar_i2c_status_get(struct rcar_i2c_priv *priv) | 253 | rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); |
| 324 | { | ||
| 325 | return rcar_i2c_read(priv, ICMSR); | ||
| 326 | } | ||
| 327 | |||
| 328 | #define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff) | ||
| 329 | static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit) | ||
| 330 | { | ||
| 331 | rcar_i2c_write(priv, ICMSR, ~bit); | ||
| 332 | } | ||
| 333 | |||
| 334 | /* | ||
| 335 | * recv/send functions | ||
| 336 | */ | ||
| 337 | static int rcar_i2c_recv(struct rcar_i2c_priv *priv) | ||
| 338 | { | ||
| 339 | rcar_i2c_set_addr(priv, 1); | ||
| 340 | rcar_i2c_status_clear(priv); | ||
| 341 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); | ||
| 342 | rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_RECV); | ||
| 343 | |||
| 344 | return 0; | ||
| 345 | } | ||
| 346 | |||
| 347 | static int rcar_i2c_send(struct rcar_i2c_priv *priv) | ||
| 348 | { | ||
| 349 | int ret; | ||
| 350 | |||
| 351 | /* | ||
| 352 | * It should check bus status when send case | ||
| 353 | */ | ||
| 354 | ret = rcar_i2c_bus_barrier(priv); | ||
| 355 | if (ret < 0) | ||
| 356 | return ret; | ||
| 357 | |||
| 358 | rcar_i2c_set_addr(priv, 0); | ||
| 359 | rcar_i2c_status_clear(priv); | ||
| 360 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); | ||
| 361 | rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_SEND); | ||
| 362 | 254 | ||
| 363 | return 0; | 255 | return 0; |
| 364 | } | 256 | } |
| 365 | 257 | ||
| 366 | #define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDE)) | ||
| 367 | #define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDR)) | ||
| 368 | |||
| 369 | /* | 258 | /* |
| 370 | * interrupt functions | 259 | * interrupt functions |
| 371 | */ | 260 | */ |
| @@ -386,7 +275,7 @@ static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) | |||
| 386 | * goto data phase. | 275 | * goto data phase. |
| 387 | */ | 276 | */ |
| 388 | if (msr & MAT) | 277 | if (msr & MAT) |
| 389 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); | 278 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); |
| 390 | 279 | ||
| 391 | if (priv->pos < msg->len) { | 280 | if (priv->pos < msg->len) { |
| 392 | /* | 281 | /* |
| @@ -414,7 +303,7 @@ static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) | |||
| 414 | * prepare stop condition here. | 303 | * prepare stop condition here. |
| 415 | * ID_DONE will be set on STOP irq. | 304 | * ID_DONE will be set on STOP irq. |
| 416 | */ | 305 | */ |
| 417 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); | 306 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
| 418 | else | 307 | else |
| 419 | /* | 308 | /* |
| 420 | * If current msg is _NOT_ last msg, | 309 | * If current msg is _NOT_ last msg, |
| @@ -425,7 +314,7 @@ static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) | |||
| 425 | return ID_DONE; | 314 | return ID_DONE; |
| 426 | } | 315 | } |
| 427 | 316 | ||
| 428 | rcar_i2c_send_restart(priv); | 317 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); |
| 429 | 318 | ||
| 430 | return 0; | 319 | return 0; |
| 431 | } | 320 | } |
| @@ -462,11 +351,11 @@ static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) | |||
| 462 | * otherwise, go to DATA phase. | 351 | * otherwise, go to DATA phase. |
| 463 | */ | 352 | */ |
| 464 | if (priv->pos + 1 >= msg->len) | 353 | if (priv->pos + 1 >= msg->len) |
| 465 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); | 354 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
| 466 | else | 355 | else |
| 467 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); | 356 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); |
| 468 | 357 | ||
| 469 | rcar_i2c_recv_restart(priv); | 358 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); |
| 470 | 359 | ||
| 471 | return 0; | 360 | return 0; |
| 472 | } | 361 | } |
| @@ -474,53 +363,31 @@ static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) | |||
| 474 | static irqreturn_t rcar_i2c_irq(int irq, void *ptr) | 363 | static irqreturn_t rcar_i2c_irq(int irq, void *ptr) |
| 475 | { | 364 | { |
| 476 | struct rcar_i2c_priv *priv = ptr; | 365 | struct rcar_i2c_priv *priv = ptr; |
| 477 | struct device *dev = rcar_i2c_priv_to_dev(priv); | ||
| 478 | u32 msr; | 366 | u32 msr; |
| 479 | 367 | ||
| 480 | /*-------------- spin lock -----------------*/ | 368 | msr = rcar_i2c_read(priv, ICMSR); |
| 481 | spin_lock(&priv->lock); | ||
| 482 | 369 | ||
| 483 | msr = rcar_i2c_status_get(priv); | 370 | /* Arbitration lost */ |
| 484 | |||
| 485 | /* | ||
| 486 | * Arbitration lost | ||
| 487 | */ | ||
| 488 | if (msr & MAL) { | 371 | if (msr & MAL) { |
| 489 | /* | ||
| 490 | * CAUTION | ||
| 491 | * | ||
| 492 | * When arbitration lost, device become _slave_ mode. | ||
| 493 | */ | ||
| 494 | dev_dbg(dev, "Arbitration Lost\n"); | ||
| 495 | rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); | 372 | rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); |
| 496 | goto out; | 373 | goto out; |
| 497 | } | 374 | } |
| 498 | 375 | ||
| 499 | /* | 376 | /* Stop */ |
| 500 | * Stop | ||
| 501 | */ | ||
| 502 | if (msr & MST) { | 377 | if (msr & MST) { |
| 503 | dev_dbg(dev, "Stop\n"); | ||
| 504 | rcar_i2c_flags_set(priv, ID_DONE); | 378 | rcar_i2c_flags_set(priv, ID_DONE); |
| 505 | goto out; | 379 | goto out; |
| 506 | } | 380 | } |
| 507 | 381 | ||
| 508 | /* | 382 | /* Nack */ |
| 509 | * Nack | ||
| 510 | */ | ||
| 511 | if (msr & MNR) { | 383 | if (msr & MNR) { |
| 512 | dev_dbg(dev, "Nack\n"); | ||
| 513 | |||
| 514 | /* go to stop phase */ | 384 | /* go to stop phase */ |
| 515 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); | 385 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
| 516 | rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_STOP); | 386 | rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); |
| 517 | rcar_i2c_flags_set(priv, ID_NACK); | 387 | rcar_i2c_flags_set(priv, ID_NACK); |
| 518 | goto out; | 388 | goto out; |
| 519 | } | 389 | } |
| 520 | 390 | ||
| 521 | /* | ||
| 522 | * recv/send | ||
| 523 | */ | ||
| 524 | if (rcar_i2c_is_recv(priv)) | 391 | if (rcar_i2c_is_recv(priv)) |
| 525 | rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); | 392 | rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); |
| 526 | else | 393 | else |
| @@ -528,14 +395,11 @@ static irqreturn_t rcar_i2c_irq(int irq, void *ptr) | |||
| 528 | 395 | ||
| 529 | out: | 396 | out: |
| 530 | if (rcar_i2c_flags_has(priv, ID_DONE)) { | 397 | if (rcar_i2c_flags_has(priv, ID_DONE)) { |
| 531 | rcar_i2c_irq_mask(priv, RCAR_IRQ_CLOSE); | 398 | rcar_i2c_write(priv, ICMIER, 0); |
| 532 | rcar_i2c_status_clear(priv); | 399 | rcar_i2c_write(priv, ICMSR, 0); |
| 533 | wake_up(&priv->wait); | 400 | wake_up(&priv->wait); |
| 534 | } | 401 | } |
| 535 | 402 | ||
| 536 | spin_unlock(&priv->lock); | ||
| 537 | /*-------------- spin unlock -----------------*/ | ||
| 538 | |||
| 539 | return IRQ_HANDLED; | 403 | return IRQ_HANDLED; |
| 540 | } | 404 | } |
| 541 | 405 | ||
| @@ -545,24 +409,24 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |||
| 545 | { | 409 | { |
| 546 | struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); | 410 | struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); |
| 547 | struct device *dev = rcar_i2c_priv_to_dev(priv); | 411 | struct device *dev = rcar_i2c_priv_to_dev(priv); |
| 548 | unsigned long flags; | ||
| 549 | int i, ret, timeout; | 412 | int i, ret, timeout; |
| 550 | 413 | ||
| 551 | pm_runtime_get_sync(dev); | 414 | pm_runtime_get_sync(dev); |
| 552 | 415 | ||
| 553 | /*-------------- spin lock -----------------*/ | ||
| 554 | spin_lock_irqsave(&priv->lock, flags); | ||
| 555 | |||
| 556 | rcar_i2c_init(priv); | 416 | rcar_i2c_init(priv); |
| 557 | rcar_i2c_clock_start(priv); | 417 | /* start clock */ |
| 418 | rcar_i2c_write(priv, ICCCR, priv->icccr); | ||
| 558 | 419 | ||
| 559 | spin_unlock_irqrestore(&priv->lock, flags); | 420 | ret = rcar_i2c_bus_barrier(priv); |
| 560 | /*-------------- spin unlock -----------------*/ | 421 | if (ret < 0) |
| 422 | goto out; | ||
| 561 | 423 | ||
| 562 | ret = -EINVAL; | ||
| 563 | for (i = 0; i < num; i++) { | 424 | for (i = 0; i < num; i++) { |
| 564 | /*-------------- spin lock -----------------*/ | 425 | /* This HW can't send STOP after address phase */ |
| 565 | spin_lock_irqsave(&priv->lock, flags); | 426 | if (msgs[i].len == 0) { |
| 427 | ret = -EOPNOTSUPP; | ||
| 428 | break; | ||
| 429 | } | ||
| 566 | 430 | ||
| 567 | /* init each data */ | 431 | /* init each data */ |
| 568 | priv->msg = &msgs[i]; | 432 | priv->msg = &msgs[i]; |
| @@ -571,21 +435,11 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |||
| 571 | if (priv->msg == &msgs[num - 1]) | 435 | if (priv->msg == &msgs[num - 1]) |
| 572 | rcar_i2c_flags_set(priv, ID_LAST_MSG); | 436 | rcar_i2c_flags_set(priv, ID_LAST_MSG); |
| 573 | 437 | ||
| 574 | /* start send/recv */ | 438 | ret = rcar_i2c_prepare_msg(priv); |
| 575 | if (rcar_i2c_is_recv(priv)) | ||
| 576 | ret = rcar_i2c_recv(priv); | ||
| 577 | else | ||
| 578 | ret = rcar_i2c_send(priv); | ||
| 579 | |||
| 580 | spin_unlock_irqrestore(&priv->lock, flags); | ||
| 581 | /*-------------- spin unlock -----------------*/ | ||
| 582 | 439 | ||
| 583 | if (ret < 0) | 440 | if (ret < 0) |
| 584 | break; | 441 | break; |
| 585 | 442 | ||
| 586 | /* | ||
| 587 | * wait result | ||
| 588 | */ | ||
| 589 | timeout = wait_event_timeout(priv->wait, | 443 | timeout = wait_event_timeout(priv->wait, |
| 590 | rcar_i2c_flags_has(priv, ID_DONE), | 444 | rcar_i2c_flags_has(priv, ID_DONE), |
| 591 | 5 * HZ); | 445 | 5 * HZ); |
| @@ -594,9 +448,6 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |||
| 594 | break; | 448 | break; |
| 595 | } | 449 | } |
| 596 | 450 | ||
| 597 | /* | ||
| 598 | * error handling | ||
| 599 | */ | ||
| 600 | if (rcar_i2c_flags_has(priv, ID_NACK)) { | 451 | if (rcar_i2c_flags_has(priv, ID_NACK)) { |
| 601 | ret = -ENXIO; | 452 | ret = -ENXIO; |
| 602 | break; | 453 | break; |
| @@ -614,7 +465,7 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |||
| 614 | 465 | ||
| 615 | ret = i + 1; /* The number of transfer */ | 466 | ret = i + 1; /* The number of transfer */ |
| 616 | } | 467 | } |
| 617 | 468 | out: | |
| 618 | pm_runtime_put(dev); | 469 | pm_runtime_put(dev); |
| 619 | 470 | ||
| 620 | if (ret < 0 && ret != -ENXIO) | 471 | if (ret < 0 && ret != -ENXIO) |
| @@ -625,7 +476,8 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |||
| 625 | 476 | ||
| 626 | static u32 rcar_i2c_func(struct i2c_adapter *adap) | 477 | static u32 rcar_i2c_func(struct i2c_adapter *adap) |
| 627 | { | 478 | { |
| 628 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | 479 | /* This HW can't do SMBUS_QUICK and NOSTART */ |
| 480 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | ||
| 629 | } | 481 | } |
| 630 | 482 | ||
| 631 | static const struct i2c_algorithm rcar_i2c_algo = { | 483 | static const struct i2c_algorithm rcar_i2c_algo = { |
| @@ -639,6 +491,9 @@ static const struct of_device_id rcar_i2c_dt_ids[] = { | |||
| 639 | { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, | 491 | { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, |
| 640 | { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, | 492 | { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, |
| 641 | { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, | 493 | { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, |
| 494 | { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, | ||
| 495 | { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, | ||
| 496 | { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, | ||
| 642 | {}, | 497 | {}, |
| 643 | }; | 498 | }; |
| 644 | MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); | 499 | MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); |
| @@ -651,13 +506,11 @@ static int rcar_i2c_probe(struct platform_device *pdev) | |||
| 651 | struct resource *res; | 506 | struct resource *res; |
| 652 | struct device *dev = &pdev->dev; | 507 | struct device *dev = &pdev->dev; |
| 653 | u32 bus_speed; | 508 | u32 bus_speed; |
| 654 | int ret; | 509 | int irq, ret; |
| 655 | 510 | ||
| 656 | priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); | 511 | priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); |
| 657 | if (!priv) { | 512 | if (!priv) |
| 658 | dev_err(dev, "no mem for private data\n"); | ||
| 659 | return -ENOMEM; | 513 | return -ENOMEM; |
| 660 | } | ||
| 661 | 514 | ||
| 662 | priv->clk = devm_clk_get(dev, NULL); | 515 | priv->clk = devm_clk_get(dev, NULL); |
| 663 | if (IS_ERR(priv->clk)) { | 516 | if (IS_ERR(priv->clk)) { |
| @@ -685,9 +538,8 @@ static int rcar_i2c_probe(struct platform_device *pdev) | |||
| 685 | if (IS_ERR(priv->io)) | 538 | if (IS_ERR(priv->io)) |
| 686 | return PTR_ERR(priv->io); | 539 | return PTR_ERR(priv->io); |
| 687 | 540 | ||
| 688 | priv->irq = platform_get_irq(pdev, 0); | 541 | irq = platform_get_irq(pdev, 0); |
| 689 | init_waitqueue_head(&priv->wait); | 542 | init_waitqueue_head(&priv->wait); |
| 690 | spin_lock_init(&priv->lock); | ||
| 691 | 543 | ||
| 692 | adap = &priv->adap; | 544 | adap = &priv->adap; |
| 693 | adap->nr = pdev->id; | 545 | adap->nr = pdev->id; |
| @@ -699,10 +551,10 @@ static int rcar_i2c_probe(struct platform_device *pdev) | |||
| 699 | i2c_set_adapdata(adap, priv); | 551 | i2c_set_adapdata(adap, priv); |
| 700 | strlcpy(adap->name, pdev->name, sizeof(adap->name)); | 552 | strlcpy(adap->name, pdev->name, sizeof(adap->name)); |
| 701 | 553 | ||
| 702 | ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, | 554 | ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, |
| 703 | dev_name(dev), priv); | 555 | dev_name(dev), priv); |
| 704 | if (ret < 0) { | 556 | if (ret < 0) { |
| 705 | dev_err(dev, "cannot get irq %d\n", priv->irq); | 557 | dev_err(dev, "cannot get irq %d\n", irq); |
| 706 | return ret; | 558 | return ret; |
| 707 | } | 559 | } |
| 708 | 560 | ||
| @@ -752,6 +604,6 @@ static struct platform_driver rcar_i2c_driver = { | |||
| 752 | 604 | ||
| 753 | module_platform_driver(rcar_i2c_driver); | 605 | module_platform_driver(rcar_i2c_driver); |
| 754 | 606 | ||
| 755 | MODULE_LICENSE("GPL"); | 607 | MODULE_LICENSE("GPL v2"); |
| 756 | MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); | 608 | MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); |
| 757 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); | 609 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); |
