diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/i915_dma.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_fb.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_fbcon.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_notifier.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600_blit_kms.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_atombios.c | 18 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_combios.c | 26 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_fb.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_object.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_object.h | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rs600.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rs690.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/ttm/ttm_bo.c | 83 |
18 files changed, 115 insertions, 46 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index c74e4e8006d4..2dd2c93ebfa3 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c | |||
@@ -2231,6 +2231,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) | |||
2231 | dev_priv->mchdev_lock = &mchdev_lock; | 2231 | dev_priv->mchdev_lock = &mchdev_lock; |
2232 | spin_unlock(&mchdev_lock); | 2232 | spin_unlock(&mchdev_lock); |
2233 | 2233 | ||
2234 | /* XXX Prevent module unload due to memory corruption bugs. */ | ||
2235 | __module_get(THIS_MODULE); | ||
2236 | |||
2234 | return 0; | 2237 | return 0; |
2235 | 2238 | ||
2236 | out_workqueue_free: | 2239 | out_workqueue_free: |
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c index 56ad9df2ccb5..b61966c126d3 100644 --- a/drivers/gpu/drm/i915/intel_fb.c +++ b/drivers/gpu/drm/i915/intel_fb.c | |||
@@ -238,8 +238,8 @@ int intel_fbdev_destroy(struct drm_device *dev, | |||
238 | 238 | ||
239 | drm_framebuffer_cleanup(&ifb->base); | 239 | drm_framebuffer_cleanup(&ifb->base); |
240 | if (ifb->obj) { | 240 | if (ifb->obj) { |
241 | drm_gem_object_handle_unreference(ifb->obj); | ||
242 | drm_gem_object_unreference(ifb->obj); | 241 | drm_gem_object_unreference(ifb->obj); |
242 | ifb->obj = NULL; | ||
243 | } | 243 | } |
244 | 244 | ||
245 | return 0; | 245 | return 0; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index d2047713dc59..dbd30b2e43fd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c | |||
@@ -352,7 +352,6 @@ nouveau_fbcon_destroy(struct drm_device *dev, struct nouveau_fbdev *nfbdev) | |||
352 | 352 | ||
353 | if (nouveau_fb->nvbo) { | 353 | if (nouveau_fb->nvbo) { |
354 | nouveau_bo_unmap(nouveau_fb->nvbo); | 354 | nouveau_bo_unmap(nouveau_fb->nvbo); |
355 | drm_gem_object_handle_unreference_unlocked(nouveau_fb->nvbo->gem); | ||
356 | drm_gem_object_unreference_unlocked(nouveau_fb->nvbo->gem); | 355 | drm_gem_object_unreference_unlocked(nouveau_fb->nvbo->gem); |
357 | nouveau_fb->nvbo = NULL; | 356 | nouveau_fb->nvbo = NULL; |
358 | } | 357 | } |
diff --git a/drivers/gpu/drm/nouveau/nouveau_notifier.c b/drivers/gpu/drm/nouveau/nouveau_notifier.c index 3c9964a8fbad..3ec181ff50ce 100644 --- a/drivers/gpu/drm/nouveau/nouveau_notifier.c +++ b/drivers/gpu/drm/nouveau/nouveau_notifier.c | |||
@@ -79,7 +79,6 @@ nouveau_notifier_takedown_channel(struct nouveau_channel *chan) | |||
79 | mutex_lock(&dev->struct_mutex); | 79 | mutex_lock(&dev->struct_mutex); |
80 | nouveau_bo_unpin(chan->notifier_bo); | 80 | nouveau_bo_unpin(chan->notifier_bo); |
81 | mutex_unlock(&dev->struct_mutex); | 81 | mutex_unlock(&dev->struct_mutex); |
82 | drm_gem_object_handle_unreference_unlocked(chan->notifier_bo->gem); | ||
83 | drm_gem_object_unreference_unlocked(chan->notifier_bo->gem); | 82 | drm_gem_object_unreference_unlocked(chan->notifier_bo->gem); |
84 | drm_mm_takedown(&chan->notifier_heap); | 83 | drm_mm_takedown(&chan->notifier_heap); |
85 | } | 84 | } |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 79082d4398ae..2f93d46ae69a 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -1137,7 +1137,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) | |||
1137 | 1137 | ||
1138 | WREG32(RCU_IND_INDEX, 0x203); | 1138 | WREG32(RCU_IND_INDEX, 0x203); |
1139 | efuse_straps_3 = RREG32(RCU_IND_DATA); | 1139 | efuse_straps_3 = RREG32(RCU_IND_DATA); |
1140 | efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28; | 1140 | efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28); |
1141 | 1141 | ||
1142 | switch(efuse_box_bit_127_124) { | 1142 | switch(efuse_box_bit_127_124) { |
1143 | case 0x0: | 1143 | case 0x0: |
@@ -1407,6 +1407,7 @@ int evergreen_mc_init(struct radeon_device *rdev) | |||
1407 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | 1407 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; |
1408 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | 1408 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; |
1409 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | 1409 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
1410 | rdev->mc.active_vram_size = rdev->mc.visible_vram_size; | ||
1410 | r600_vram_gtt_location(rdev, &rdev->mc); | 1411 | r600_vram_gtt_location(rdev, &rdev->mc); |
1411 | radeon_update_bandwidth_info(rdev); | 1412 | radeon_update_bandwidth_info(rdev); |
1412 | 1413 | ||
@@ -1520,7 +1521,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) | |||
1520 | { | 1521 | { |
1521 | u32 tmp; | 1522 | u32 tmp; |
1522 | 1523 | ||
1523 | WREG32(CP_INT_CNTL, 0); | 1524 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
1524 | WREG32(GRBM_INT_CNTL, 0); | 1525 | WREG32(GRBM_INT_CNTL, 0); |
1525 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | 1526 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
1526 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | 1527 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index e151f16a8f86..e59422320bb6 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -1030,6 +1030,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) | |||
1030 | return r; | 1030 | return r; |
1031 | } | 1031 | } |
1032 | rdev->cp.ready = true; | 1032 | rdev->cp.ready = true; |
1033 | rdev->mc.active_vram_size = rdev->mc.real_vram_size; | ||
1033 | return 0; | 1034 | return 0; |
1034 | } | 1035 | } |
1035 | 1036 | ||
@@ -1047,6 +1048,7 @@ void r100_cp_fini(struct radeon_device *rdev) | |||
1047 | void r100_cp_disable(struct radeon_device *rdev) | 1048 | void r100_cp_disable(struct radeon_device *rdev) |
1048 | { | 1049 | { |
1049 | /* Disable ring */ | 1050 | /* Disable ring */ |
1051 | rdev->mc.active_vram_size = rdev->mc.visible_vram_size; | ||
1050 | rdev->cp.ready = false; | 1052 | rdev->cp.ready = false; |
1051 | WREG32(RADEON_CP_CSQ_MODE, 0); | 1053 | WREG32(RADEON_CP_CSQ_MODE, 0); |
1052 | WREG32(RADEON_CP_CSQ_CNTL, 0); | 1054 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
@@ -2295,6 +2297,7 @@ void r100_vram_init_sizes(struct radeon_device *rdev) | |||
2295 | /* FIXME we don't use the second aperture yet when we could use it */ | 2297 | /* FIXME we don't use the second aperture yet when we could use it */ |
2296 | if (rdev->mc.visible_vram_size > rdev->mc.aper_size) | 2298 | if (rdev->mc.visible_vram_size > rdev->mc.aper_size) |
2297 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | 2299 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
2300 | rdev->mc.active_vram_size = rdev->mc.visible_vram_size; | ||
2298 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); | 2301 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
2299 | if (rdev->flags & RADEON_IS_IGP) { | 2302 | if (rdev->flags & RADEON_IS_IGP) { |
2300 | uint32_t tom; | 2303 | uint32_t tom; |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 7a04959ba0ee..7b65e4efe8af 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -1248,6 +1248,7 @@ int r600_mc_init(struct radeon_device *rdev) | |||
1248 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | 1248 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
1249 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | 1249 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
1250 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | 1250 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
1251 | rdev->mc.active_vram_size = rdev->mc.visible_vram_size; | ||
1251 | r600_vram_gtt_location(rdev, &rdev->mc); | 1252 | r600_vram_gtt_location(rdev, &rdev->mc); |
1252 | 1253 | ||
1253 | if (rdev->flags & RADEON_IS_IGP) { | 1254 | if (rdev->flags & RADEON_IS_IGP) { |
@@ -1917,6 +1918,7 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |||
1917 | */ | 1918 | */ |
1918 | void r600_cp_stop(struct radeon_device *rdev) | 1919 | void r600_cp_stop(struct radeon_device *rdev) |
1919 | { | 1920 | { |
1921 | rdev->mc.active_vram_size = rdev->mc.visible_vram_size; | ||
1920 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); | 1922 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
1921 | } | 1923 | } |
1922 | 1924 | ||
@@ -2910,7 +2912,7 @@ static void r600_disable_interrupt_state(struct radeon_device *rdev) | |||
2910 | { | 2912 | { |
2911 | u32 tmp; | 2913 | u32 tmp; |
2912 | 2914 | ||
2913 | WREG32(CP_INT_CNTL, 0); | 2915 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
2914 | WREG32(GRBM_INT_CNTL, 0); | 2916 | WREG32(GRBM_INT_CNTL, 0); |
2915 | WREG32(DxMODE_INT_MASK, 0); | 2917 | WREG32(DxMODE_INT_MASK, 0); |
2916 | if (ASIC_IS_DCE3(rdev)) { | 2918 | if (ASIC_IS_DCE3(rdev)) { |
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index 9ceb2a1ce799..3473c00781ff 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c | |||
@@ -532,6 +532,7 @@ int r600_blit_init(struct radeon_device *rdev) | |||
532 | memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); | 532 | memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); |
533 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); | 533 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
534 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | 534 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
535 | rdev->mc.active_vram_size = rdev->mc.real_vram_size; | ||
535 | return 0; | 536 | return 0; |
536 | } | 537 | } |
537 | 538 | ||
@@ -539,6 +540,7 @@ void r600_blit_fini(struct radeon_device *rdev) | |||
539 | { | 540 | { |
540 | int r; | 541 | int r; |
541 | 542 | ||
543 | rdev->mc.active_vram_size = rdev->mc.visible_vram_size; | ||
542 | if (rdev->r600_blit.shader_obj == NULL) | 544 | if (rdev->r600_blit.shader_obj == NULL) |
543 | return; | 545 | return; |
544 | /* If we can't reserve the bo, unref should be enough to destroy | 546 | /* If we can't reserve the bo, unref should be enough to destroy |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index a168d644bf9e..9ff38c99a6ea 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -344,6 +344,7 @@ struct radeon_mc { | |||
344 | * about vram size near mc fb location */ | 344 | * about vram size near mc fb location */ |
345 | u64 mc_vram_size; | 345 | u64 mc_vram_size; |
346 | u64 visible_vram_size; | 346 | u64 visible_vram_size; |
347 | u64 active_vram_size; | ||
347 | u64 gtt_size; | 348 | u64 gtt_size; |
348 | u64 gtt_start; | 349 | u64 gtt_start; |
349 | u64 gtt_end; | 350 | u64 gtt_end; |
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 68932ba7b8a4..8e43ddae70cc 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c | |||
@@ -1558,39 +1558,39 @@ radeon_atombios_get_tv_info(struct radeon_device *rdev) | |||
1558 | switch (tv_info->ucTV_BootUpDefaultStandard) { | 1558 | switch (tv_info->ucTV_BootUpDefaultStandard) { |
1559 | case ATOM_TV_NTSC: | 1559 | case ATOM_TV_NTSC: |
1560 | tv_std = TV_STD_NTSC; | 1560 | tv_std = TV_STD_NTSC; |
1561 | DRM_INFO("Default TV standard: NTSC\n"); | 1561 | DRM_DEBUG_KMS("Default TV standard: NTSC\n"); |
1562 | break; | 1562 | break; |
1563 | case ATOM_TV_NTSCJ: | 1563 | case ATOM_TV_NTSCJ: |
1564 | tv_std = TV_STD_NTSC_J; | 1564 | tv_std = TV_STD_NTSC_J; |
1565 | DRM_INFO("Default TV standard: NTSC-J\n"); | 1565 | DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); |
1566 | break; | 1566 | break; |
1567 | case ATOM_TV_PAL: | 1567 | case ATOM_TV_PAL: |
1568 | tv_std = TV_STD_PAL; | 1568 | tv_std = TV_STD_PAL; |
1569 | DRM_INFO("Default TV standard: PAL\n"); | 1569 | DRM_DEBUG_KMS("Default TV standard: PAL\n"); |
1570 | break; | 1570 | break; |
1571 | case ATOM_TV_PALM: | 1571 | case ATOM_TV_PALM: |
1572 | tv_std = TV_STD_PAL_M; | 1572 | tv_std = TV_STD_PAL_M; |
1573 | DRM_INFO("Default TV standard: PAL-M\n"); | 1573 | DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); |
1574 | break; | 1574 | break; |
1575 | case ATOM_TV_PALN: | 1575 | case ATOM_TV_PALN: |
1576 | tv_std = TV_STD_PAL_N; | 1576 | tv_std = TV_STD_PAL_N; |
1577 | DRM_INFO("Default TV standard: PAL-N\n"); | 1577 | DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); |
1578 | break; | 1578 | break; |
1579 | case ATOM_TV_PALCN: | 1579 | case ATOM_TV_PALCN: |
1580 | tv_std = TV_STD_PAL_CN; | 1580 | tv_std = TV_STD_PAL_CN; |
1581 | DRM_INFO("Default TV standard: PAL-CN\n"); | 1581 | DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); |
1582 | break; | 1582 | break; |
1583 | case ATOM_TV_PAL60: | 1583 | case ATOM_TV_PAL60: |
1584 | tv_std = TV_STD_PAL_60; | 1584 | tv_std = TV_STD_PAL_60; |
1585 | DRM_INFO("Default TV standard: PAL-60\n"); | 1585 | DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); |
1586 | break; | 1586 | break; |
1587 | case ATOM_TV_SECAM: | 1587 | case ATOM_TV_SECAM: |
1588 | tv_std = TV_STD_SECAM; | 1588 | tv_std = TV_STD_SECAM; |
1589 | DRM_INFO("Default TV standard: SECAM\n"); | 1589 | DRM_DEBUG_KMS("Default TV standard: SECAM\n"); |
1590 | break; | 1590 | break; |
1591 | default: | 1591 | default: |
1592 | tv_std = TV_STD_NTSC; | 1592 | tv_std = TV_STD_NTSC; |
1593 | DRM_INFO("Unknown TV standard; defaulting to NTSC\n"); | 1593 | DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); |
1594 | break; | 1594 | break; |
1595 | } | 1595 | } |
1596 | } | 1596 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index a04b7a6ad95f..7b7ea269549c 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c | |||
@@ -913,47 +913,47 @@ radeon_combios_get_tv_info(struct radeon_device *rdev) | |||
913 | switch (RBIOS8(tv_info + 7) & 0xf) { | 913 | switch (RBIOS8(tv_info + 7) & 0xf) { |
914 | case 1: | 914 | case 1: |
915 | tv_std = TV_STD_NTSC; | 915 | tv_std = TV_STD_NTSC; |
916 | DRM_INFO("Default TV standard: NTSC\n"); | 916 | DRM_DEBUG_KMS("Default TV standard: NTSC\n"); |
917 | break; | 917 | break; |
918 | case 2: | 918 | case 2: |
919 | tv_std = TV_STD_PAL; | 919 | tv_std = TV_STD_PAL; |
920 | DRM_INFO("Default TV standard: PAL\n"); | 920 | DRM_DEBUG_KMS("Default TV standard: PAL\n"); |
921 | break; | 921 | break; |
922 | case 3: | 922 | case 3: |
923 | tv_std = TV_STD_PAL_M; | 923 | tv_std = TV_STD_PAL_M; |
924 | DRM_INFO("Default TV standard: PAL-M\n"); | 924 | DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); |
925 | break; | 925 | break; |
926 | case 4: | 926 | case 4: |
927 | tv_std = TV_STD_PAL_60; | 927 | tv_std = TV_STD_PAL_60; |
928 | DRM_INFO("Default TV standard: PAL-60\n"); | 928 | DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); |
929 | break; | 929 | break; |
930 | case 5: | 930 | case 5: |
931 | tv_std = TV_STD_NTSC_J; | 931 | tv_std = TV_STD_NTSC_J; |
932 | DRM_INFO("Default TV standard: NTSC-J\n"); | 932 | DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); |
933 | break; | 933 | break; |
934 | case 6: | 934 | case 6: |
935 | tv_std = TV_STD_SCART_PAL; | 935 | tv_std = TV_STD_SCART_PAL; |
936 | DRM_INFO("Default TV standard: SCART-PAL\n"); | 936 | DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); |
937 | break; | 937 | break; |
938 | default: | 938 | default: |
939 | tv_std = TV_STD_NTSC; | 939 | tv_std = TV_STD_NTSC; |
940 | DRM_INFO | 940 | DRM_DEBUG_KMS |
941 | ("Unknown TV standard; defaulting to NTSC\n"); | 941 | ("Unknown TV standard; defaulting to NTSC\n"); |
942 | break; | 942 | break; |
943 | } | 943 | } |
944 | 944 | ||
945 | switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { | 945 | switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { |
946 | case 0: | 946 | case 0: |
947 | DRM_INFO("29.498928713 MHz TV ref clk\n"); | 947 | DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); |
948 | break; | 948 | break; |
949 | case 1: | 949 | case 1: |
950 | DRM_INFO("28.636360000 MHz TV ref clk\n"); | 950 | DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); |
951 | break; | 951 | break; |
952 | case 2: | 952 | case 2: |
953 | DRM_INFO("14.318180000 MHz TV ref clk\n"); | 953 | DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); |
954 | break; | 954 | break; |
955 | case 3: | 955 | case 3: |
956 | DRM_INFO("27.000000000 MHz TV ref clk\n"); | 956 | DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); |
957 | break; | 957 | break; |
958 | default: | 958 | default: |
959 | break; | 959 | break; |
@@ -1324,7 +1324,7 @@ bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, | |||
1324 | 1324 | ||
1325 | if (tmds_info) { | 1325 | if (tmds_info) { |
1326 | ver = RBIOS8(tmds_info); | 1326 | ver = RBIOS8(tmds_info); |
1327 | DRM_INFO("DFP table revision: %d\n", ver); | 1327 | DRM_DEBUG_KMS("DFP table revision: %d\n", ver); |
1328 | if (ver == 3) { | 1328 | if (ver == 3) { |
1329 | n = RBIOS8(tmds_info + 5) + 1; | 1329 | n = RBIOS8(tmds_info + 5) + 1; |
1330 | if (n > 4) | 1330 | if (n > 4) |
@@ -1408,7 +1408,7 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder | |||
1408 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); | 1408 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
1409 | if (offset) { | 1409 | if (offset) { |
1410 | ver = RBIOS8(offset); | 1410 | ver = RBIOS8(offset); |
1411 | DRM_INFO("External TMDS Table revision: %d\n", ver); | 1411 | DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); |
1412 | tmds->slave_addr = RBIOS8(offset + 4 + 2); | 1412 | tmds->slave_addr = RBIOS8(offset + 4 + 2); |
1413 | tmds->slave_addr >>= 1; /* 7 bit addressing */ | 1413 | tmds->slave_addr >>= 1; /* 7 bit addressing */ |
1414 | gpio = RBIOS8(offset + 4 + 3); | 1414 | gpio = RBIOS8(offset + 4 + 3); |
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 9cdf6a35bc2c..40b0c087b592 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c | |||
@@ -97,7 +97,6 @@ static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj) | |||
97 | radeon_bo_unpin(rbo); | 97 | radeon_bo_unpin(rbo); |
98 | radeon_bo_unreserve(rbo); | 98 | radeon_bo_unreserve(rbo); |
99 | } | 99 | } |
100 | drm_gem_object_handle_unreference(gobj); | ||
101 | drm_gem_object_unreference_unlocked(gobj); | 100 | drm_gem_object_unreference_unlocked(gobj); |
102 | } | 101 | } |
103 | 102 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index 0afd1e62347d..b3b5306bb578 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c | |||
@@ -69,7 +69,7 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) | |||
69 | u32 c = 0; | 69 | u32 c = 0; |
70 | 70 | ||
71 | rbo->placement.fpfn = 0; | 71 | rbo->placement.fpfn = 0; |
72 | rbo->placement.lpfn = 0; | 72 | rbo->placement.lpfn = rbo->rdev->mc.active_vram_size >> PAGE_SHIFT; |
73 | rbo->placement.placement = rbo->placements; | 73 | rbo->placement.placement = rbo->placements; |
74 | rbo->placement.busy_placement = rbo->placements; | 74 | rbo->placement.busy_placement = rbo->placements; |
75 | if (domain & RADEON_GEM_DOMAIN_VRAM) | 75 | if (domain & RADEON_GEM_DOMAIN_VRAM) |
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h index 353998dc2c03..3481bc7f6f58 100644 --- a/drivers/gpu/drm/radeon/radeon_object.h +++ b/drivers/gpu/drm/radeon/radeon_object.h | |||
@@ -124,11 +124,8 @@ static inline int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, | |||
124 | int r; | 124 | int r; |
125 | 125 | ||
126 | r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); | 126 | r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); |
127 | if (unlikely(r != 0)) { | 127 | if (unlikely(r != 0)) |
128 | if (r != -ERESTARTSYS) | ||
129 | dev_err(bo->rdev->dev, "%p reserve failed for wait\n", bo); | ||
130 | return r; | 128 | return r; |
131 | } | ||
132 | spin_lock(&bo->tbo.lock); | 129 | spin_lock(&bo->tbo.lock); |
133 | if (mem_type) | 130 | if (mem_type) |
134 | *mem_type = bo->tbo.mem.mem_type; | 131 | *mem_type = bo->tbo.mem.mem_type; |
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index cc05b230d7ef..51d5f7b5ab21 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c | |||
@@ -693,6 +693,7 @@ void rs600_mc_init(struct radeon_device *rdev) | |||
693 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); | 693 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
694 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | 694 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
695 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | 695 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
696 | rdev->mc.active_vram_size = rdev->mc.visible_vram_size; | ||
696 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); | 697 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
697 | base = RREG32_MC(R_000004_MC_FB_LOCATION); | 698 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
698 | base = G_000004_MC_FB_START(base) << 16; | 699 | base = G_000004_MC_FB_START(base) << 16; |
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index 3e3f75718be3..4dc2a87ea680 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c | |||
@@ -157,6 +157,7 @@ void rs690_mc_init(struct radeon_device *rdev) | |||
157 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); | 157 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
158 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | 158 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
159 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | 159 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
160 | rdev->mc.active_vram_size = rdev->mc.visible_vram_size; | ||
160 | base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); | 161 | base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); |
161 | base = G_000100_MC_FB_START(base) << 16; | 162 | base = G_000100_MC_FB_START(base) << 16; |
162 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); | 163 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index bfa59db374d2..9490da700749 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -267,6 +267,7 @@ static void rv770_mc_program(struct radeon_device *rdev) | |||
267 | */ | 267 | */ |
268 | void r700_cp_stop(struct radeon_device *rdev) | 268 | void r700_cp_stop(struct radeon_device *rdev) |
269 | { | 269 | { |
270 | rdev->mc.active_vram_size = rdev->mc.visible_vram_size; | ||
270 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); | 271 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
271 | } | 272 | } |
272 | 273 | ||
@@ -992,6 +993,7 @@ int rv770_mc_init(struct radeon_device *rdev) | |||
992 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | 993 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
993 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | 994 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
994 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | 995 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
996 | rdev->mc.active_vram_size = rdev->mc.visible_vram_size; | ||
995 | r600_vram_gtt_location(rdev, &rdev->mc); | 997 | r600_vram_gtt_location(rdev, &rdev->mc); |
996 | radeon_update_bandwidth_info(rdev); | 998 | radeon_update_bandwidth_info(rdev); |
997 | 999 | ||
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index cb4cf7ef4d1e..db809e034cc4 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c | |||
@@ -442,6 +442,43 @@ out_err: | |||
442 | } | 442 | } |
443 | 443 | ||
444 | /** | 444 | /** |
445 | * Call bo::reserved and with the lru lock held. | ||
446 | * Will release GPU memory type usage on destruction. | ||
447 | * This is the place to put in driver specific hooks. | ||
448 | * Will release the bo::reserved lock and the | ||
449 | * lru lock on exit. | ||
450 | */ | ||
451 | |||
452 | static void ttm_bo_cleanup_memtype_use(struct ttm_buffer_object *bo) | ||
453 | { | ||
454 | struct ttm_bo_global *glob = bo->glob; | ||
455 | |||
456 | if (bo->ttm) { | ||
457 | |||
458 | /** | ||
459 | * Release the lru_lock, since we don't want to have | ||
460 | * an atomic requirement on ttm_tt[unbind|destroy]. | ||
461 | */ | ||
462 | |||
463 | spin_unlock(&glob->lru_lock); | ||
464 | ttm_tt_unbind(bo->ttm); | ||
465 | ttm_tt_destroy(bo->ttm); | ||
466 | bo->ttm = NULL; | ||
467 | spin_lock(&glob->lru_lock); | ||
468 | } | ||
469 | |||
470 | if (bo->mem.mm_node) { | ||
471 | drm_mm_put_block(bo->mem.mm_node); | ||
472 | bo->mem.mm_node = NULL; | ||
473 | } | ||
474 | |||
475 | atomic_set(&bo->reserved, 0); | ||
476 | wake_up_all(&bo->event_queue); | ||
477 | spin_unlock(&glob->lru_lock); | ||
478 | } | ||
479 | |||
480 | |||
481 | /** | ||
445 | * If bo idle, remove from delayed- and lru lists, and unref. | 482 | * If bo idle, remove from delayed- and lru lists, and unref. |
446 | * If not idle, and already on delayed list, do nothing. | 483 | * If not idle, and already on delayed list, do nothing. |
447 | * If not idle, and not on delayed list, put on delayed list, | 484 | * If not idle, and not on delayed list, put on delayed list, |
@@ -456,6 +493,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) | |||
456 | int ret; | 493 | int ret; |
457 | 494 | ||
458 | spin_lock(&bo->lock); | 495 | spin_lock(&bo->lock); |
496 | retry: | ||
459 | (void) ttm_bo_wait(bo, false, false, !remove_all); | 497 | (void) ttm_bo_wait(bo, false, false, !remove_all); |
460 | 498 | ||
461 | if (!bo->sync_obj) { | 499 | if (!bo->sync_obj) { |
@@ -464,31 +502,52 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) | |||
464 | spin_unlock(&bo->lock); | 502 | spin_unlock(&bo->lock); |
465 | 503 | ||
466 | spin_lock(&glob->lru_lock); | 504 | spin_lock(&glob->lru_lock); |
467 | put_count = ttm_bo_del_from_lru(bo); | 505 | ret = ttm_bo_reserve_locked(bo, false, !remove_all, false, 0); |
506 | |||
507 | /** | ||
508 | * Someone else has the object reserved. Bail and retry. | ||
509 | */ | ||
468 | 510 | ||
469 | ret = ttm_bo_reserve_locked(bo, false, false, false, 0); | 511 | if (unlikely(ret == -EBUSY)) { |
470 | BUG_ON(ret); | 512 | spin_unlock(&glob->lru_lock); |
471 | if (bo->ttm) | 513 | spin_lock(&bo->lock); |
472 | ttm_tt_unbind(bo->ttm); | 514 | goto requeue; |
515 | } | ||
516 | |||
517 | /** | ||
518 | * We can re-check for sync object without taking | ||
519 | * the bo::lock since setting the sync object requires | ||
520 | * also bo::reserved. A busy object at this point may | ||
521 | * be caused by another thread starting an accelerated | ||
522 | * eviction. | ||
523 | */ | ||
524 | |||
525 | if (unlikely(bo->sync_obj)) { | ||
526 | atomic_set(&bo->reserved, 0); | ||
527 | wake_up_all(&bo->event_queue); | ||
528 | spin_unlock(&glob->lru_lock); | ||
529 | spin_lock(&bo->lock); | ||
530 | if (remove_all) | ||
531 | goto retry; | ||
532 | else | ||
533 | goto requeue; | ||
534 | } | ||
535 | |||
536 | put_count = ttm_bo_del_from_lru(bo); | ||
473 | 537 | ||
474 | if (!list_empty(&bo->ddestroy)) { | 538 | if (!list_empty(&bo->ddestroy)) { |
475 | list_del_init(&bo->ddestroy); | 539 | list_del_init(&bo->ddestroy); |
476 | ++put_count; | 540 | ++put_count; |
477 | } | 541 | } |
478 | if (bo->mem.mm_node) { | ||
479 | drm_mm_put_block(bo->mem.mm_node); | ||
480 | bo->mem.mm_node = NULL; | ||
481 | } | ||
482 | spin_unlock(&glob->lru_lock); | ||
483 | 542 | ||
484 | atomic_set(&bo->reserved, 0); | 543 | ttm_bo_cleanup_memtype_use(bo); |
485 | 544 | ||
486 | while (put_count--) | 545 | while (put_count--) |
487 | kref_put(&bo->list_kref, ttm_bo_ref_bug); | 546 | kref_put(&bo->list_kref, ttm_bo_ref_bug); |
488 | 547 | ||
489 | return 0; | 548 | return 0; |
490 | } | 549 | } |
491 | 550 | requeue: | |
492 | spin_lock(&glob->lru_lock); | 551 | spin_lock(&glob->lru_lock); |
493 | if (list_empty(&bo->ddestroy)) { | 552 | if (list_empty(&bo->ddestroy)) { |
494 | void *sync_obj = bo->sync_obj; | 553 | void *sync_obj = bo->sync_obj; |