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-rw-r--r--drivers/gpu/drm/radeon/r100.c14
-rw-r--r--drivers/gpu/drm/radeon/r100d.h38
-rw-r--r--drivers/gpu/drm/radeon/r300.c16
-rw-r--r--drivers/gpu/drm/radeon/r300d.h92
-rw-r--r--drivers/gpu/drm/radeon/r420.c5
-rw-r--r--drivers/gpu/drm/radeon/r420d.h24
-rw-r--r--drivers/gpu/drm/radeon/radeon.h4
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h45
-rw-r--r--drivers/gpu/drm/radeon/rs400.c276
-rw-r--r--drivers/gpu/drm/radeon/rs400d.h160
-rw-r--r--drivers/gpu/drm/radeon/rv350d.h52
11 files changed, 582 insertions, 144 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index d2099146fc40..dc45ec1d4189 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3100,7 +3100,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3100 WREG32(R_000740_CP_CSQ_CNTL, 0); 3100 WREG32(R_000740_CP_CSQ_CNTL, 0);
3101 3101
3102 /* Save few CRTC registers */ 3102 /* Save few CRTC registers */
3103 save->GENMO_WT = RREG32(R_0003C0_GENMO_WT); 3103 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3104 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3104 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3105 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3105 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3106 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3106 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
@@ -3110,7 +3110,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3110 } 3110 }
3111 3111
3112 /* Disable VGA aperture access */ 3112 /* Disable VGA aperture access */
3113 WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT); 3113 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3114 /* Disable cursor, overlay, crtc */ 3114 /* Disable cursor, overlay, crtc */
3115 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3115 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3116 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3116 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
@@ -3142,10 +3142,18 @@ void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3142 rdev->mc.vram_location); 3142 rdev->mc.vram_location);
3143 } 3143 }
3144 /* Restore CRTC registers */ 3144 /* Restore CRTC registers */
3145 WREG32(R_0003C0_GENMO_WT, save->GENMO_WT); 3145 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3146 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3146 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3147 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3147 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3148 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3148 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3149 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3149 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3150 } 3150 }
3151} 3151}
3152
3153void r100_vga_render_disable(struct radeon_device *rdev)
3154{
3155 u32 tmp;
3156
3157 tmp = RREG8(R_0003C2_GENMO_WT);
3158 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3159}
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h
index c4b257ec920e..1595a5d132df 100644
--- a/drivers/gpu/drm/radeon/r100d.h
+++ b/drivers/gpu/drm/radeon/r100d.h
@@ -403,25 +403,25 @@
403#define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) 403#define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31)
404#define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) 404#define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1)
405#define C_000360_CUR2_LOCK 0x7FFFFFFF 405#define C_000360_CUR2_LOCK 0x7FFFFFFF
406#define R_0003C0_GENMO_WT 0x0003C0 406#define R_0003C2_GENMO_WT 0x0003C0
407#define S_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) 407#define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0)
408#define G_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) 408#define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1)
409#define C_0003C0_GENMO_MONO_ADDRESS_B 0xFFFFFFFE 409#define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE
410#define S_0003C0_VGA_RAM_EN(x) (((x) & 0x1) << 1) 410#define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1)
411#define G_0003C0_VGA_RAM_EN(x) (((x) >> 1) & 0x1) 411#define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1)
412#define C_0003C0_VGA_RAM_EN 0xFFFFFFFD 412#define C_0003C2_VGA_RAM_EN 0xFD
413#define S_0003C0_VGA_CKSEL(x) (((x) & 0x3) << 2) 413#define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2)
414#define G_0003C0_VGA_CKSEL(x) (((x) >> 2) & 0x3) 414#define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3)
415#define C_0003C0_VGA_CKSEL 0xFFFFFFF3 415#define C_0003C2_VGA_CKSEL 0xF3
416#define S_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) 416#define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5)
417#define G_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) 417#define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1)
418#define C_0003C0_ODD_EVEN_MD_PGSEL 0xFFFFFFDF 418#define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF
419#define S_0003C0_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) 419#define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6)
420#define G_0003C0_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) 420#define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1)
421#define C_0003C0_VGA_HSYNC_POL 0xFFFFFFBF 421#define C_0003C2_VGA_HSYNC_POL 0xBF
422#define S_0003C0_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) 422#define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7)
423#define G_0003C0_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) 423#define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1)
424#define C_0003C0_VGA_VSYNC_POL 0xFFFFFF7F 424#define C_0003C2_VGA_VSYNC_POL 0x7F
425#define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 425#define R_0003F8_CRTC2_GEN_CNTL 0x0003F8
426#define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 426#define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0)
427#define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 427#define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1)
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 1ebea8cc8c93..e491d40d4d54 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -33,6 +33,7 @@
33#include "radeon_drm.h" 33#include "radeon_drm.h"
34#include "r100_track.h" 34#include "r100_track.h"
35#include "r300d.h" 35#include "r300d.h"
36#include "rv350d.h"
36 37
37#include "r300_reg_safe.h" 38#include "r300_reg_safe.h"
38 39
@@ -63,7 +64,6 @@ int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
63 * Some of these functions might be used by newer ASICs. 64 * Some of these functions might be used by newer ASICs.
64 */ 65 */
65void r300_gpu_init(struct radeon_device *rdev); 66void r300_gpu_init(struct radeon_device *rdev);
66int r300_mc_wait_for_idle(struct radeon_device *rdev);
67int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 67int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
68 68
69 69
@@ -1265,3 +1265,17 @@ void r300_mc_program(struct radeon_device *rdev)
1265 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1265 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1266 r100_mc_resume(rdev, &save); 1266 r100_mc_resume(rdev, &save);
1267} 1267}
1268
1269void r300_clock_startup(struct radeon_device *rdev)
1270{
1271 u32 tmp;
1272
1273 if (radeon_dynclks != -1 && radeon_dynclks)
1274 radeon_legacy_set_clock_gating(rdev, 1);
1275 /* We need to force on some of the block */
1276 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1277 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1278 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1279 tmp |= S_00000D_FORCE_VAP(1);
1280 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1281}
diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h
index d4fa3eb1074f..a6d54dabc50f 100644
--- a/drivers/gpu/drm/radeon/r300d.h
+++ b/drivers/gpu/drm/radeon/r300d.h
@@ -98,4 +98,96 @@
98#define C_000170_AGP_BASE_ADDR 0x00000000 98#define C_000170_AGP_BASE_ADDR 0x00000000
99 99
100 100
101#define R_00000D_SCLK_CNTL 0x00000D
102#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0)
103#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7)
104#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8
105#define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3)
106#define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1)
107#define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7
108#define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4)
109#define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1)
110#define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF
111#define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5)
112#define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1)
113#define C_00000D_TV_MAX_DYN_STOP_LAT 0xFFFFFFDF
114#define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6)
115#define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1)
116#define C_00000D_E2_MAX_DYN_STOP_LAT 0xFFFFFFBF
117#define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7)
118#define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1)
119#define C_00000D_SE_MAX_DYN_STOP_LAT 0xFFFFFF7F
120#define S_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 8)
121#define G_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 8) & 0x1)
122#define C_00000D_IDCT_MAX_DYN_STOP_LAT 0xFFFFFEFF
123#define S_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 9)
124#define G_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) >> 9) & 0x1)
125#define C_00000D_VIP_MAX_DYN_STOP_LAT 0xFFFFFDFF
126#define S_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 10)
127#define G_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) >> 10) & 0x1)
128#define C_00000D_RE_MAX_DYN_STOP_LAT 0xFFFFFBFF
129#define S_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 11)
130#define G_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) >> 11) & 0x1)
131#define C_00000D_PB_MAX_DYN_STOP_LAT 0xFFFFF7FF
132#define S_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 12)
133#define G_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) >> 12) & 0x1)
134#define C_00000D_TAM_MAX_DYN_STOP_LAT 0xFFFFEFFF
135#define S_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 13)
136#define G_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) >> 13) & 0x1)
137#define C_00000D_TDM_MAX_DYN_STOP_LAT 0xFFFFDFFF
138#define S_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 14)
139#define G_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) >> 14) & 0x1)
140#define C_00000D_RB_MAX_DYN_STOP_LAT 0xFFFFBFFF
141#define S_00000D_FORCE_DISP2(x) (((x) & 0x1) << 15)
142#define G_00000D_FORCE_DISP2(x) (((x) >> 15) & 0x1)
143#define C_00000D_FORCE_DISP2 0xFFFF7FFF
144#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16)
145#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1)
146#define C_00000D_FORCE_CP 0xFFFEFFFF
147#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17)
148#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1)
149#define C_00000D_FORCE_HDP 0xFFFDFFFF
150#define S_00000D_FORCE_DISP1(x) (((x) & 0x1) << 18)
151#define G_00000D_FORCE_DISP1(x) (((x) >> 18) & 0x1)
152#define C_00000D_FORCE_DISP1 0xFFFBFFFF
153#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19)
154#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1)
155#define C_00000D_FORCE_TOP 0xFFF7FFFF
156#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20)
157#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1)
158#define C_00000D_FORCE_E2 0xFFEFFFFF
159#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21)
160#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1)
161#define C_00000D_FORCE_SE 0xFFDFFFFF
162#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22)
163#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1)
164#define C_00000D_FORCE_IDCT 0xFFBFFFFF
165#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23)
166#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1)
167#define C_00000D_FORCE_VIP 0xFF7FFFFF
168#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24)
169#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1)
170#define C_00000D_FORCE_RE 0xFEFFFFFF
171#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25)
172#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1)
173#define C_00000D_FORCE_PB 0xFDFFFFFF
174#define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26)
175#define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1)
176#define C_00000D_FORCE_TAM 0xFBFFFFFF
177#define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27)
178#define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1)
179#define C_00000D_FORCE_TDM 0xF7FFFFFF
180#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28)
181#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1)
182#define C_00000D_FORCE_RB 0xEFFFFFFF
183#define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29)
184#define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1)
185#define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF
186#define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30)
187#define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1)
188#define C_00000D_FORCE_SUBPIC 0xBFFFFFFF
189#define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31)
190#define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1)
191#define C_00000D_FORCE_OV0 0x7FFFFFFF
192
101#endif 193#endif
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 49a2fdc57d27..c5d3ba47f5df 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -155,6 +155,9 @@ static void r420_debugfs(struct radeon_device *rdev)
155static void r420_clock_resume(struct radeon_device *rdev) 155static void r420_clock_resume(struct radeon_device *rdev)
156{ 156{
157 u32 sclk_cntl; 157 u32 sclk_cntl;
158
159 if (radeon_dynclks != -1 && radeon_dynclks)
160 radeon_atom_set_clock_gating(rdev, 1);
158 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 161 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
159 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 162 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
160 if (rdev->family == CHIP_R420) 163 if (rdev->family == CHIP_R420)
@@ -167,6 +170,8 @@ static int r420_startup(struct radeon_device *rdev)
167 int r; 170 int r;
168 171
169 r300_mc_program(rdev); 172 r300_mc_program(rdev);
173 /* Resume clock */
174 r420_clock_resume(rdev);
170 /* Initialize GART (initialize after TTM so we can allocate 175 /* Initialize GART (initialize after TTM so we can allocate
171 * memory through TTM but finalize after TTM) */ 176 * memory through TTM but finalize after TTM) */
172 if (rdev->flags & RADEON_IS_PCIE) { 177 if (rdev->flags & RADEON_IS_PCIE) {
diff --git a/drivers/gpu/drm/radeon/r420d.h b/drivers/gpu/drm/radeon/r420d.h
index a48a7db1e2aa..fc78d31a0b4a 100644
--- a/drivers/gpu/drm/radeon/r420d.h
+++ b/drivers/gpu/drm/radeon/r420d.h
@@ -212,9 +212,9 @@
212#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) 212#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20)
213#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) 213#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1)
214#define C_00000D_FORCE_E2 0xFFEFFFFF 214#define C_00000D_FORCE_E2 0xFFEFFFFF
215#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) 215#define S_00000D_FORCE_VAP(x) (((x) & 0x1) << 21)
216#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) 216#define G_00000D_FORCE_VAP(x) (((x) >> 21) & 0x1)
217#define C_00000D_FORCE_SE 0xFFDFFFFF 217#define C_00000D_FORCE_VAP 0xFFDFFFFF
218#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) 218#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22)
219#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) 219#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1)
220#define C_00000D_FORCE_IDCT 0xFFBFFFFF 220#define C_00000D_FORCE_IDCT 0xFFBFFFFF
@@ -224,24 +224,24 @@
224#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) 224#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24)
225#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) 225#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1)
226#define C_00000D_FORCE_RE 0xFEFFFFFF 226#define C_00000D_FORCE_RE 0xFEFFFFFF
227#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) 227#define S_00000D_FORCE_SR(x) (((x) & 0x1) << 25)
228#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) 228#define G_00000D_FORCE_SR(x) (((x) >> 25) & 0x1)
229#define C_00000D_FORCE_PB 0xFDFFFFFF 229#define C_00000D_FORCE_SR 0xFDFFFFFF
230#define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26) 230#define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26)
231#define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1) 231#define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1)
232#define C_00000D_FORCE_PX 0xFBFFFFFF 232#define C_00000D_FORCE_PX 0xFBFFFFFF
233#define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27) 233#define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27)
234#define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1) 234#define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1)
235#define C_00000D_FORCE_TX 0xF7FFFFFF 235#define C_00000D_FORCE_TX 0xF7FFFFFF
236#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) 236#define S_00000D_FORCE_US(x) (((x) & 0x1) << 28)
237#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) 237#define G_00000D_FORCE_US(x) (((x) >> 28) & 0x1)
238#define C_00000D_FORCE_RB 0xEFFFFFFF 238#define C_00000D_FORCE_US 0xEFFFFFFF
239#define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29) 239#define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29)
240#define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1) 240#define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1)
241#define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF 241#define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF
242#define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30) 242#define S_00000D_FORCE_SU(x) (((x) & 0x1) << 30)
243#define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1) 243#define G_00000D_FORCE_SU(x) (((x) >> 30) & 0x1)
244#define C_00000D_FORCE_SUBPIC 0xBFFFFFFF 244#define C_00000D_FORCE_SU 0xBFFFFFFF
245#define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31) 245#define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31)
246#define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1) 246#define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1)
247#define C_00000D_FORCE_OV0 0x7FFFFFFF 247#define C_00000D_FORCE_OV0 0x7FFFFFFF
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 7b0965f54958..012cdff193c2 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -994,6 +994,7 @@ extern void radeon_clocks_fini(struct radeon_device *rdev);
994extern void radeon_scratch_init(struct radeon_device *rdev); 994extern void radeon_scratch_init(struct radeon_device *rdev);
995extern void radeon_surface_init(struct radeon_device *rdev); 995extern void radeon_surface_init(struct radeon_device *rdev);
996extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 996extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
997extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
997extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 998extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
998 999
999/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 1000/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
@@ -1029,11 +1030,14 @@ extern int r100_wb_init(struct radeon_device *rdev);
1029extern void r100_hdp_reset(struct radeon_device *rdev); 1030extern void r100_hdp_reset(struct radeon_device *rdev);
1030extern int r100_rb2d_reset(struct radeon_device *rdev); 1031extern int r100_rb2d_reset(struct radeon_device *rdev);
1031extern int r100_cp_reset(struct radeon_device *rdev); 1032extern int r100_cp_reset(struct radeon_device *rdev);
1033extern void r100_vga_render_disable(struct radeon_device *rdev);
1032 1034
1033/* r300,r350,rv350,rv370,rv380 */ 1035/* r300,r350,rv350,rv370,rv380 */
1034extern void r300_set_reg_safe(struct radeon_device *rdev); 1036extern void r300_set_reg_safe(struct radeon_device *rdev);
1035extern void r300_mc_program(struct radeon_device *rdev); 1037extern void r300_mc_program(struct radeon_device *rdev);
1036extern void r300_vram_info(struct radeon_device *rdev); 1038extern void r300_vram_info(struct radeon_device *rdev);
1039extern void r300_clock_startup(struct radeon_device *rdev);
1040extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1037extern int rv370_pcie_gart_init(struct radeon_device *rdev); 1041extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1038extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 1042extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1039extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 1043extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index bce0cb063867..0fa117afc742 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -246,41 +246,40 @@ static struct radeon_asic r420_asic = {
246/* 246/*
247 * rs400,rs480 247 * rs400,rs480
248 */ 248 */
249void rs400_errata(struct radeon_device *rdev); 249extern int rs400_init(struct radeon_device *rdev);
250void rs400_vram_info(struct radeon_device *rdev); 250extern void rs400_fini(struct radeon_device *rdev);
251int rs400_mc_init(struct radeon_device *rdev); 251extern int rs400_suspend(struct radeon_device *rdev);
252void rs400_mc_fini(struct radeon_device *rdev); 252extern int rs400_resume(struct radeon_device *rdev);
253int rs400_gart_init(struct radeon_device *rdev);
254void rs400_gart_fini(struct radeon_device *rdev);
255int rs400_gart_enable(struct radeon_device *rdev);
256void rs400_gart_disable(struct radeon_device *rdev);
257void rs400_gart_tlb_flush(struct radeon_device *rdev); 253void rs400_gart_tlb_flush(struct radeon_device *rdev);
258int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 254int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
259uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 255uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
260void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 256void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
261static struct radeon_asic rs400_asic = { 257static struct radeon_asic rs400_asic = {
262 .init = &r300_init, 258 .init = &rs400_init,
263 .errata = &rs400_errata, 259 .fini = &rs400_fini,
264 .vram_info = &rs400_vram_info, 260 .suspend = &rs400_suspend,
261 .resume = &rs400_resume,
262 .errata = NULL,
263 .vram_info = NULL,
265 .gpu_reset = &r300_gpu_reset, 264 .gpu_reset = &r300_gpu_reset,
266 .mc_init = &rs400_mc_init, 265 .mc_init = NULL,
267 .mc_fini = &rs400_mc_fini, 266 .mc_fini = NULL,
268 .wb_init = &r100_wb_init, 267 .wb_init = NULL,
269 .wb_fini = &r100_wb_fini, 268 .wb_fini = NULL,
270 .gart_init = &rs400_gart_init, 269 .gart_init = NULL,
271 .gart_fini = &rs400_gart_fini, 270 .gart_fini = NULL,
272 .gart_enable = &rs400_gart_enable, 271 .gart_enable = NULL,
273 .gart_disable = &rs400_gart_disable, 272 .gart_disable = NULL,
274 .gart_tlb_flush = &rs400_gart_tlb_flush, 273 .gart_tlb_flush = &rs400_gart_tlb_flush,
275 .gart_set_page = &rs400_gart_set_page, 274 .gart_set_page = &rs400_gart_set_page,
276 .cp_init = &r100_cp_init, 275 .cp_init = NULL,
277 .cp_fini = &r100_cp_fini, 276 .cp_fini = NULL,
278 .cp_disable = &r100_cp_disable, 277 .cp_disable = NULL,
279 .cp_commit = &r100_cp_commit, 278 .cp_commit = &r100_cp_commit,
280 .ring_start = &r300_ring_start, 279 .ring_start = &r300_ring_start,
281 .ring_test = &r100_ring_test, 280 .ring_test = &r100_ring_test,
282 .ring_ib_execute = &r100_ring_ib_execute, 281 .ring_ib_execute = &r100_ring_ib_execute,
283 .ib_test = &r100_ib_test, 282 .ib_test = NULL,
284 .irq_set = &r100_irq_set, 283 .irq_set = &r100_irq_set,
285 .irq_process = &r100_irq_process, 284 .irq_process = &r100_irq_process,
286 .get_vblank_counter = &r100_get_vblank_counter, 285 .get_vblank_counter = &r100_get_vblank_counter,
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index a3fbdad938c7..8b67605dbf3d 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -27,27 +27,12 @@
27 */ 27 */
28#include <linux/seq_file.h> 28#include <linux/seq_file.h>
29#include <drm/drmP.h> 29#include <drm/drmP.h>
30#include "radeon_reg.h"
31#include "radeon.h" 30#include "radeon.h"
31#include "rs400d.h"
32 32
33/* rs400,rs480 depends on : */ 33/* This files gather functions specifics to : rs400,rs480 */
34void r100_hdp_reset(struct radeon_device *rdev); 34static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
35void r100_mc_disable_clients(struct radeon_device *rdev);
36int r300_mc_wait_for_idle(struct radeon_device *rdev);
37void r420_pipes_init(struct radeon_device *rdev);
38 35
39/* This files gather functions specifics to :
40 * rs400,rs480
41 *
42 * Some of these functions might be used by newer ASICs.
43 */
44void rs400_gpu_init(struct radeon_device *rdev);
45int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
46
47
48/*
49 * GART functions.
50 */
51void rs400_gart_adjust_size(struct radeon_device *rdev) 36void rs400_gart_adjust_size(struct radeon_device *rdev)
52{ 37{
53 /* Check gart size */ 38 /* Check gart size */
@@ -238,61 +223,6 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
238 return 0; 223 return 0;
239} 224}
240 225
241
242/*
243 * MC functions.
244 */
245int rs400_mc_init(struct radeon_device *rdev)
246{
247 uint32_t tmp;
248 int r;
249
250 if (r100_debugfs_rbbm_init(rdev)) {
251 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
252 }
253
254 rs400_gpu_init(rdev);
255 rs400_gart_disable(rdev);
256 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
257 rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
258 rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
259 r = radeon_mc_setup(rdev);
260 if (r) {
261 return r;
262 }
263
264 r100_mc_disable_clients(rdev);
265 if (r300_mc_wait_for_idle(rdev)) {
266 printk(KERN_WARNING "Failed to wait MC idle while "
267 "programming pipes. Bad things might happen.\n");
268 }
269
270 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
271 tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
272 tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
273 WREG32(RADEON_MC_FB_LOCATION, tmp);
274 tmp = RREG32(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS;
275 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
276 (void)RREG32(RADEON_HOST_PATH_CNTL);
277 WREG32(RADEON_HOST_PATH_CNTL, tmp);
278 (void)RREG32(RADEON_HOST_PATH_CNTL);
279
280 return 0;
281}
282
283void rs400_mc_fini(struct radeon_device *rdev)
284{
285}
286
287
288/*
289 * Global GPU functions
290 */
291void rs400_errata(struct radeon_device *rdev)
292{
293 rdev->pll_errata = 0;
294}
295
296void rs400_gpu_init(struct radeon_device *rdev) 226void rs400_gpu_init(struct radeon_device *rdev)
297{ 227{
298 /* FIXME: HDP same place on rs400 ? */ 228 /* FIXME: HDP same place on rs400 ? */
@@ -305,10 +235,6 @@ void rs400_gpu_init(struct radeon_device *rdev)
305 } 235 }
306} 236}
307 237
308
309/*
310 * VRAM info.
311 */
312void rs400_vram_info(struct radeon_device *rdev) 238void rs400_vram_info(struct radeon_device *rdev)
313{ 239{
314 rs400_gart_adjust_size(rdev); 240 rs400_gart_adjust_size(rdev);
@@ -319,10 +245,6 @@ void rs400_vram_info(struct radeon_device *rdev)
319 r100_vram_init_sizes(rdev); 245 r100_vram_init_sizes(rdev);
320} 246}
321 247
322
323/*
324 * Indirect registers accessor
325 */
326uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 248uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
327{ 249{
328 uint32_t r; 250 uint32_t r;
@@ -340,10 +262,6 @@ void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
340 WREG32(RS480_NB_MC_INDEX, 0xff); 262 WREG32(RS480_NB_MC_INDEX, 0xff);
341} 263}
342 264
343
344/*
345 * Debugfs info
346 */
347#if defined(CONFIG_DEBUG_FS) 265#if defined(CONFIG_DEBUG_FS)
348static int rs400_debugfs_gart_info(struct seq_file *m, void *data) 266static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
349{ 267{
@@ -419,7 +337,7 @@ static struct drm_info_list rs400_gart_info_list[] = {
419}; 337};
420#endif 338#endif
421 339
422int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 340static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
423{ 341{
424#if defined(CONFIG_DEBUG_FS) 342#if defined(CONFIG_DEBUG_FS)
425 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); 343 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
@@ -427,3 +345,189 @@ int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
427 return 0; 345 return 0;
428#endif 346#endif
429} 347}
348
349static int rs400_mc_init(struct radeon_device *rdev)
350{
351 int r;
352 u32 tmp;
353
354 /* Setup GPU memory space */
355 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
356 rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
357 rdev->mc.gtt_location = 0xFFFFFFFFUL;
358 r = radeon_mc_setup(rdev);
359 if (r)
360 return r;
361 return 0;
362}
363
364void rs400_mc_program(struct radeon_device *rdev)
365{
366 struct r100_mc_save save;
367
368 /* Stops all mc clients */
369 r100_mc_stop(rdev, &save);
370
371 /* Wait for mc idle */
372 if (r300_mc_wait_for_idle(rdev))
373 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
374 WREG32(R_000148_MC_FB_LOCATION,
375 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
376 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
377
378 r100_mc_resume(rdev, &save);
379}
380
381static int rs400_startup(struct radeon_device *rdev)
382{
383 int r;
384
385 rs400_mc_program(rdev);
386 /* Resume clock */
387 r300_clock_startup(rdev);
388 /* Initialize GPU configuration (# pipes, ...) */
389 rs400_gpu_init(rdev);
390 /* Initialize GART (initialize after TTM so we can allocate
391 * memory through TTM but finalize after TTM) */
392 r = rs400_gart_enable(rdev);
393 if (r)
394 return r;
395 /* Enable IRQ */
396 rdev->irq.sw_int = true;
397 r100_irq_set(rdev);
398 /* 1M ring buffer */
399 r = r100_cp_init(rdev, 1024 * 1024);
400 if (r) {
401 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
402 return r;
403 }
404 r = r100_wb_init(rdev);
405 if (r)
406 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
407 r = r100_ib_init(rdev);
408 if (r) {
409 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
410 return r;
411 }
412 return 0;
413}
414
415int rs400_resume(struct radeon_device *rdev)
416{
417 /* Make sur GART are not working */
418 rs400_gart_disable(rdev);
419 /* Resume clock before doing reset */
420 r300_clock_startup(rdev);
421 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
422 if (radeon_gpu_reset(rdev)) {
423 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
424 RREG32(R_000E40_RBBM_STATUS),
425 RREG32(R_0007C0_CP_STAT));
426 }
427 /* post */
428 radeon_combios_asic_init(rdev->ddev);
429 /* Resume clock after posting */
430 r300_clock_startup(rdev);
431 return rs400_startup(rdev);
432}
433
434int rs400_suspend(struct radeon_device *rdev)
435{
436 r100_cp_disable(rdev);
437 r100_wb_disable(rdev);
438 r100_irq_disable(rdev);
439 rs400_gart_disable(rdev);
440 return 0;
441}
442
443void rs400_fini(struct radeon_device *rdev)
444{
445 rs400_suspend(rdev);
446 r100_cp_fini(rdev);
447 r100_wb_fini(rdev);
448 r100_ib_fini(rdev);
449 radeon_gem_fini(rdev);
450 rs400_gart_fini(rdev);
451 radeon_irq_kms_fini(rdev);
452 radeon_fence_driver_fini(rdev);
453 radeon_object_fini(rdev);
454 radeon_atombios_fini(rdev);
455 kfree(rdev->bios);
456 rdev->bios = NULL;
457}
458
459int rs400_init(struct radeon_device *rdev)
460{
461 int r;
462
463 rdev->new_init_path = true;
464 /* Disable VGA */
465 r100_vga_render_disable(rdev);
466 /* Initialize scratch registers */
467 radeon_scratch_init(rdev);
468 /* Initialize surface registers */
469 radeon_surface_init(rdev);
470 /* TODO: disable VGA need to use VGA request */
471 /* BIOS*/
472 if (!radeon_get_bios(rdev)) {
473 if (ASIC_IS_AVIVO(rdev))
474 return -EINVAL;
475 }
476 if (rdev->is_atom_bios) {
477 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
478 return -EINVAL;
479 } else {
480 r = radeon_combios_init(rdev);
481 if (r)
482 return r;
483 }
484 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
485 if (radeon_gpu_reset(rdev)) {
486 dev_warn(rdev->dev,
487 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
488 RREG32(R_000E40_RBBM_STATUS),
489 RREG32(R_0007C0_CP_STAT));
490 }
491 /* check if cards are posted or not */
492 if (!radeon_card_posted(rdev) && rdev->bios) {
493 DRM_INFO("GPU not posted. posting now...\n");
494 radeon_combios_asic_init(rdev->ddev);
495 }
496 /* Initialize clocks */
497 radeon_get_clock_info(rdev->ddev);
498 /* Get vram informations */
499 rs400_vram_info(rdev);
500 /* Initialize memory controller (also test AGP) */
501 r = rs400_mc_init(rdev);
502 if (r)
503 return r;
504 /* Fence driver */
505 r = radeon_fence_driver_init(rdev);
506 if (r)
507 return r;
508 r = radeon_irq_kms_init(rdev);
509 if (r)
510 return r;
511 /* Memory manager */
512 r = radeon_object_init(rdev);
513 if (r)
514 return r;
515 r = rs400_gart_init(rdev);
516 if (r)
517 return r;
518 r300_set_reg_safe(rdev);
519 rdev->accel_working = true;
520 r = rs400_startup(rdev);
521 if (r) {
522 /* Somethings want wront with the accel init stop accel */
523 dev_err(rdev->dev, "Disabling GPU acceleration\n");
524 rs400_suspend(rdev);
525 r100_cp_fini(rdev);
526 r100_wb_fini(rdev);
527 r100_ib_fini(rdev);
528 rs400_gart_fini(rdev);
529 radeon_irq_kms_fini(rdev);
530 rdev->accel_working = false;
531 }
532 return 0;
533}
diff --git a/drivers/gpu/drm/radeon/rs400d.h b/drivers/gpu/drm/radeon/rs400d.h
new file mode 100644
index 000000000000..6d8bac58ced9
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rs400d.h
@@ -0,0 +1,160 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RS400D_H__
29#define __RS400D_H__
30
31/* Registers */
32#define R_000148_MC_FB_LOCATION 0x000148
33#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)
34#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
35#define C_000148_MC_FB_START 0xFFFF0000
36#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
37#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
38#define C_000148_MC_FB_TOP 0x0000FFFF
39#define R_00015C_NB_TOM 0x00015C
40#define S_00015C_MC_FB_START(x) (((x) & 0xFFFF) << 0)
41#define G_00015C_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
42#define C_00015C_MC_FB_START 0xFFFF0000
43#define S_00015C_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
44#define G_00015C_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
45#define C_00015C_MC_FB_TOP 0x0000FFFF
46#define R_0007C0_CP_STAT 0x0007C0
47#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
48#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
49#define C_0007C0_MRU_BUSY 0xFFFFFFFE
50#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
51#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
52#define C_0007C0_MWU_BUSY 0xFFFFFFFD
53#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
54#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
55#define C_0007C0_RSIU_BUSY 0xFFFFFFFB
56#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
57#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
58#define C_0007C0_RCIU_BUSY 0xFFFFFFF7
59#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
60#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
61#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
62#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
63#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
64#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
65#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
66#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
67#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
68#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
69#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
70#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
71#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
72#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
73#define C_0007C0_CSI_BUSY 0xFFFFDFFF
74#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
75#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
76#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
77#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
78#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
79#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
80#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
81#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
82#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
83#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
84#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
85#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
86#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
87#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
88#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
89#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
90#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
91#define C_0007C0_CP_BUSY 0x7FFFFFFF
92#define R_000E40_RBBM_STATUS 0x000E40
93#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
94#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
95#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
96#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
97#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
98#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
99#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
100#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
101#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
102#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
103#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
104#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
105#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
106#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
107#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
108#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
109#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
110#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
111#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
112#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
113#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
114#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
115#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
116#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
117#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
118#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
119#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
120#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
121#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
122#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
123#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
124#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
125#define C_000E40_E2_BUSY 0xFFFDFFFF
126#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
127#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
128#define C_000E40_RB2D_BUSY 0xFFFBFFFF
129#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
130#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
131#define C_000E40_RB3D_BUSY 0xFFF7FFFF
132#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
133#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
134#define C_000E40_VAP_BUSY 0xFFEFFFFF
135#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
136#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
137#define C_000E40_RE_BUSY 0xFFDFFFFF
138#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
139#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
140#define C_000E40_TAM_BUSY 0xFFBFFFFF
141#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
142#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
143#define C_000E40_TDM_BUSY 0xFF7FFFFF
144#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
145#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
146#define C_000E40_PB_BUSY 0xFEFFFFFF
147#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
148#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
149#define C_000E40_TIM_BUSY 0xFDFFFFFF
150#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
151#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
152#define C_000E40_GA_BUSY 0xFBFFFFFF
153#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
154#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
155#define C_000E40_CBA2D_BUSY 0xF7FFFFFF
156#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
157#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
158#define C_000E40_GUI_ACTIVE 0x7FFFFFFF
159
160#endif
diff --git a/drivers/gpu/drm/radeon/rv350d.h b/drivers/gpu/drm/radeon/rv350d.h
new file mode 100644
index 000000000000..c75c5ed9e654
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv350d.h
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RV350D_H__
29#define __RV350D_H__
30
31/* RV350, RV380 registers */
32/* #define R_00000D_SCLK_CNTL 0x00000D */
33#define S_00000D_FORCE_VAP(x) (((x) & 0x1) << 21)
34#define G_00000D_FORCE_VAP(x) (((x) >> 21) & 0x1)
35#define C_00000D_FORCE_VAP 0xFFDFFFFF
36#define S_00000D_FORCE_SR(x) (((x) & 0x1) << 25)
37#define G_00000D_FORCE_SR(x) (((x) >> 25) & 0x1)
38#define C_00000D_FORCE_SR 0xFDFFFFFF
39#define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26)
40#define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1)
41#define C_00000D_FORCE_PX 0xFBFFFFFF
42#define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27)
43#define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1)
44#define C_00000D_FORCE_TX 0xF7FFFFFF
45#define S_00000D_FORCE_US(x) (((x) & 0x1) << 28)
46#define G_00000D_FORCE_US(x) (((x) >> 28) & 0x1)
47#define C_00000D_FORCE_US 0xEFFFFFFF
48#define S_00000D_FORCE_SU(x) (((x) & 0x1) << 30)
49#define G_00000D_FORCE_SU(x) (((x) >> 30) & 0x1)
50#define C_00000D_FORCE_SU 0xBFFFFFFF
51
52#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 07:13:36 -0500