diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/i915_dma.c | 112 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 113 |
2 files changed, 113 insertions, 112 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index b5a1a72d3325..006ea473b57d 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c | |||
@@ -1375,113 +1375,6 @@ void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |||
1375 | master->driver_priv = NULL; | 1375 | master->driver_priv = NULL; |
1376 | } | 1376 | } |
1377 | 1377 | ||
1378 | static void i915_pineview_get_mem_freq(struct drm_device *dev) | ||
1379 | { | ||
1380 | drm_i915_private_t *dev_priv = dev->dev_private; | ||
1381 | u32 tmp; | ||
1382 | |||
1383 | tmp = I915_READ(CLKCFG); | ||
1384 | |||
1385 | switch (tmp & CLKCFG_FSB_MASK) { | ||
1386 | case CLKCFG_FSB_533: | ||
1387 | dev_priv->fsb_freq = 533; /* 133*4 */ | ||
1388 | break; | ||
1389 | case CLKCFG_FSB_800: | ||
1390 | dev_priv->fsb_freq = 800; /* 200*4 */ | ||
1391 | break; | ||
1392 | case CLKCFG_FSB_667: | ||
1393 | dev_priv->fsb_freq = 667; /* 167*4 */ | ||
1394 | break; | ||
1395 | case CLKCFG_FSB_400: | ||
1396 | dev_priv->fsb_freq = 400; /* 100*4 */ | ||
1397 | break; | ||
1398 | } | ||
1399 | |||
1400 | switch (tmp & CLKCFG_MEM_MASK) { | ||
1401 | case CLKCFG_MEM_533: | ||
1402 | dev_priv->mem_freq = 533; | ||
1403 | break; | ||
1404 | case CLKCFG_MEM_667: | ||
1405 | dev_priv->mem_freq = 667; | ||
1406 | break; | ||
1407 | case CLKCFG_MEM_800: | ||
1408 | dev_priv->mem_freq = 800; | ||
1409 | break; | ||
1410 | } | ||
1411 | |||
1412 | /* detect pineview DDR3 setting */ | ||
1413 | tmp = I915_READ(CSHRDDR3CTL); | ||
1414 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | ||
1415 | } | ||
1416 | |||
1417 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | ||
1418 | { | ||
1419 | drm_i915_private_t *dev_priv = dev->dev_private; | ||
1420 | u16 ddrpll, csipll; | ||
1421 | |||
1422 | ddrpll = I915_READ16(DDRMPLL1); | ||
1423 | csipll = I915_READ16(CSIPLL0); | ||
1424 | |||
1425 | switch (ddrpll & 0xff) { | ||
1426 | case 0xc: | ||
1427 | dev_priv->mem_freq = 800; | ||
1428 | break; | ||
1429 | case 0x10: | ||
1430 | dev_priv->mem_freq = 1066; | ||
1431 | break; | ||
1432 | case 0x14: | ||
1433 | dev_priv->mem_freq = 1333; | ||
1434 | break; | ||
1435 | case 0x18: | ||
1436 | dev_priv->mem_freq = 1600; | ||
1437 | break; | ||
1438 | default: | ||
1439 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | ||
1440 | ddrpll & 0xff); | ||
1441 | dev_priv->mem_freq = 0; | ||
1442 | break; | ||
1443 | } | ||
1444 | |||
1445 | dev_priv->r_t = dev_priv->mem_freq; | ||
1446 | |||
1447 | switch (csipll & 0x3ff) { | ||
1448 | case 0x00c: | ||
1449 | dev_priv->fsb_freq = 3200; | ||
1450 | break; | ||
1451 | case 0x00e: | ||
1452 | dev_priv->fsb_freq = 3733; | ||
1453 | break; | ||
1454 | case 0x010: | ||
1455 | dev_priv->fsb_freq = 4266; | ||
1456 | break; | ||
1457 | case 0x012: | ||
1458 | dev_priv->fsb_freq = 4800; | ||
1459 | break; | ||
1460 | case 0x014: | ||
1461 | dev_priv->fsb_freq = 5333; | ||
1462 | break; | ||
1463 | case 0x016: | ||
1464 | dev_priv->fsb_freq = 5866; | ||
1465 | break; | ||
1466 | case 0x018: | ||
1467 | dev_priv->fsb_freq = 6400; | ||
1468 | break; | ||
1469 | default: | ||
1470 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | ||
1471 | csipll & 0x3ff); | ||
1472 | dev_priv->fsb_freq = 0; | ||
1473 | break; | ||
1474 | } | ||
1475 | |||
1476 | if (dev_priv->fsb_freq == 3200) { | ||
1477 | dev_priv->c_m = 0; | ||
1478 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { | ||
1479 | dev_priv->c_m = 1; | ||
1480 | } else { | ||
1481 | dev_priv->c_m = 2; | ||
1482 | } | ||
1483 | } | ||
1484 | |||
1485 | static void | 1378 | static void |
1486 | i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base, | 1379 | i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base, |
1487 | unsigned long size) | 1380 | unsigned long size) |
@@ -1634,11 +1527,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) | |||
1634 | goto out_gem_unload; | 1527 | goto out_gem_unload; |
1635 | } | 1528 | } |
1636 | 1529 | ||
1637 | if (IS_PINEVIEW(dev)) | ||
1638 | i915_pineview_get_mem_freq(dev); | ||
1639 | else if (IS_GEN5(dev)) | ||
1640 | i915_ironlake_get_mem_freq(dev); | ||
1641 | |||
1642 | /* On the 945G/GM, the chipset reports the MSI capability on the | 1530 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1643 | * integrated graphics even though the support isn't actually there | 1531 | * integrated graphics even though the support isn't actually there |
1644 | * according to the published specs. It doesn't appear to function | 1532 | * according to the published specs. It doesn't appear to function |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e0f016c24dce..6ddf80774335 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -526,6 +526,113 @@ out_disable: | |||
526 | } | 526 | } |
527 | } | 527 | } |
528 | 528 | ||
529 | static void i915_pineview_get_mem_freq(struct drm_device *dev) | ||
530 | { | ||
531 | drm_i915_private_t *dev_priv = dev->dev_private; | ||
532 | u32 tmp; | ||
533 | |||
534 | tmp = I915_READ(CLKCFG); | ||
535 | |||
536 | switch (tmp & CLKCFG_FSB_MASK) { | ||
537 | case CLKCFG_FSB_533: | ||
538 | dev_priv->fsb_freq = 533; /* 133*4 */ | ||
539 | break; | ||
540 | case CLKCFG_FSB_800: | ||
541 | dev_priv->fsb_freq = 800; /* 200*4 */ | ||
542 | break; | ||
543 | case CLKCFG_FSB_667: | ||
544 | dev_priv->fsb_freq = 667; /* 167*4 */ | ||
545 | break; | ||
546 | case CLKCFG_FSB_400: | ||
547 | dev_priv->fsb_freq = 400; /* 100*4 */ | ||
548 | break; | ||
549 | } | ||
550 | |||
551 | switch (tmp & CLKCFG_MEM_MASK) { | ||
552 | case CLKCFG_MEM_533: | ||
553 | dev_priv->mem_freq = 533; | ||
554 | break; | ||
555 | case CLKCFG_MEM_667: | ||
556 | dev_priv->mem_freq = 667; | ||
557 | break; | ||
558 | case CLKCFG_MEM_800: | ||
559 | dev_priv->mem_freq = 800; | ||
560 | break; | ||
561 | } | ||
562 | |||
563 | /* detect pineview DDR3 setting */ | ||
564 | tmp = I915_READ(CSHRDDR3CTL); | ||
565 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | ||
566 | } | ||
567 | |||
568 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | ||
569 | { | ||
570 | drm_i915_private_t *dev_priv = dev->dev_private; | ||
571 | u16 ddrpll, csipll; | ||
572 | |||
573 | ddrpll = I915_READ16(DDRMPLL1); | ||
574 | csipll = I915_READ16(CSIPLL0); | ||
575 | |||
576 | switch (ddrpll & 0xff) { | ||
577 | case 0xc: | ||
578 | dev_priv->mem_freq = 800; | ||
579 | break; | ||
580 | case 0x10: | ||
581 | dev_priv->mem_freq = 1066; | ||
582 | break; | ||
583 | case 0x14: | ||
584 | dev_priv->mem_freq = 1333; | ||
585 | break; | ||
586 | case 0x18: | ||
587 | dev_priv->mem_freq = 1600; | ||
588 | break; | ||
589 | default: | ||
590 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | ||
591 | ddrpll & 0xff); | ||
592 | dev_priv->mem_freq = 0; | ||
593 | break; | ||
594 | } | ||
595 | |||
596 | dev_priv->r_t = dev_priv->mem_freq; | ||
597 | |||
598 | switch (csipll & 0x3ff) { | ||
599 | case 0x00c: | ||
600 | dev_priv->fsb_freq = 3200; | ||
601 | break; | ||
602 | case 0x00e: | ||
603 | dev_priv->fsb_freq = 3733; | ||
604 | break; | ||
605 | case 0x010: | ||
606 | dev_priv->fsb_freq = 4266; | ||
607 | break; | ||
608 | case 0x012: | ||
609 | dev_priv->fsb_freq = 4800; | ||
610 | break; | ||
611 | case 0x014: | ||
612 | dev_priv->fsb_freq = 5333; | ||
613 | break; | ||
614 | case 0x016: | ||
615 | dev_priv->fsb_freq = 5866; | ||
616 | break; | ||
617 | case 0x018: | ||
618 | dev_priv->fsb_freq = 6400; | ||
619 | break; | ||
620 | default: | ||
621 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | ||
622 | csipll & 0x3ff); | ||
623 | dev_priv->fsb_freq = 0; | ||
624 | break; | ||
625 | } | ||
626 | |||
627 | if (dev_priv->fsb_freq == 3200) { | ||
628 | dev_priv->c_m = 0; | ||
629 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { | ||
630 | dev_priv->c_m = 1; | ||
631 | } else { | ||
632 | dev_priv->c_m = 2; | ||
633 | } | ||
634 | } | ||
635 | |||
529 | static const struct cxsr_latency cxsr_latency_table[] = { | 636 | static const struct cxsr_latency cxsr_latency_table[] = { |
530 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | 637 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
531 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | 638 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
@@ -3440,6 +3547,12 @@ void intel_init_pm(struct drm_device *dev) | |||
3440 | /* 855GM needs testing */ | 3547 | /* 855GM needs testing */ |
3441 | } | 3548 | } |
3442 | 3549 | ||
3550 | /* For cxsr */ | ||
3551 | if (IS_PINEVIEW(dev)) | ||
3552 | i915_pineview_get_mem_freq(dev); | ||
3553 | else if (IS_GEN5(dev)) | ||
3554 | i915_ironlake_get_mem_freq(dev); | ||
3555 | |||
3443 | /* For FIFO watermark updates */ | 3556 | /* For FIFO watermark updates */ |
3444 | if (HAS_PCH_SPLIT(dev)) { | 3557 | if (HAS_PCH_SPLIT(dev)) { |
3445 | dev_priv->display.force_wake_get = __gen6_gt_force_wake_get; | 3558 | dev_priv->display.force_wake_get = __gen6_gt_force_wake_get; |