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-rw-r--r--drivers/gpu/drm/exynos/Kconfig4
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fimd.c109
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c8
-rw-r--r--drivers/gpu/drm/gma500/framebuffer.c8
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c31
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c1
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c56
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h10
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c3
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c11
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h6
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c23
-rw-r--r--drivers/gpu/drm/i915/intel_display.c22
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c8
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c41
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c8
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c8
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c138
18 files changed, 236 insertions, 259 deletions
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index f9aaa56eae07..b9e5266c341b 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -13,7 +13,7 @@ config DRM_EXYNOS
13 13
14config DRM_EXYNOS_FIMD 14config DRM_EXYNOS_FIMD
15 tristate "Exynos DRM FIMD" 15 tristate "Exynos DRM FIMD"
16 depends on DRM_EXYNOS 16 depends on DRM_EXYNOS && !FB_S3C
17 default n 17 default n
18 help 18 help
19 Choose this option if you want to use Exynos FIMD for DRM. 19 Choose this option if you want to use Exynos FIMD for DRM.
@@ -21,7 +21,7 @@ config DRM_EXYNOS_FIMD
21 21
22config DRM_EXYNOS_HDMI 22config DRM_EXYNOS_HDMI
23 tristate "Exynos DRM HDMI" 23 tristate "Exynos DRM HDMI"
24 depends on DRM_EXYNOS 24 depends on DRM_EXYNOS && !VIDEO_SAMSUNG_S5P_TV
25 help 25 help
26 Choose this option if you want to use Exynos HDMI for DRM. 26 Choose this option if you want to use Exynos HDMI for DRM.
27 If M is selected, the module will be called exynos_drm_hdmi 27 If M is selected, the module will be called exynos_drm_hdmi
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index ca83139cd309..b6a737d196ae 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -158,7 +158,8 @@ static void fimd_dpms(struct device *subdrv_dev, int mode)
158 case DRM_MODE_DPMS_STANDBY: 158 case DRM_MODE_DPMS_STANDBY:
159 case DRM_MODE_DPMS_SUSPEND: 159 case DRM_MODE_DPMS_SUSPEND:
160 case DRM_MODE_DPMS_OFF: 160 case DRM_MODE_DPMS_OFF:
161 pm_runtime_put_sync(subdrv_dev); 161 if (!ctx->suspended)
162 pm_runtime_put_sync(subdrv_dev);
162 break; 163 break;
163 default: 164 default:
164 DRM_DEBUG_KMS("unspecified mode %d\n", mode); 165 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
@@ -734,6 +735,46 @@ static void fimd_clear_win(struct fimd_context *ctx, int win)
734 writel(val, ctx->regs + SHADOWCON); 735 writel(val, ctx->regs + SHADOWCON);
735} 736}
736 737
738static int fimd_power_on(struct fimd_context *ctx, bool enable)
739{
740 struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
741 struct device *dev = subdrv->manager.dev;
742
743 DRM_DEBUG_KMS("%s\n", __FILE__);
744
745 if (enable != false && enable != true)
746 return -EINVAL;
747
748 if (enable) {
749 int ret;
750
751 ret = clk_enable(ctx->bus_clk);
752 if (ret < 0)
753 return ret;
754
755 ret = clk_enable(ctx->lcd_clk);
756 if (ret < 0) {
757 clk_disable(ctx->bus_clk);
758 return ret;
759 }
760
761 ctx->suspended = false;
762
763 /* if vblank was enabled status, enable it again. */
764 if (test_and_clear_bit(0, &ctx->irq_flags))
765 fimd_enable_vblank(dev);
766
767 fimd_apply(dev);
768 } else {
769 clk_disable(ctx->lcd_clk);
770 clk_disable(ctx->bus_clk);
771
772 ctx->suspended = true;
773 }
774
775 return 0;
776}
777
737static int __devinit fimd_probe(struct platform_device *pdev) 778static int __devinit fimd_probe(struct platform_device *pdev)
738{ 779{
739 struct device *dev = &pdev->dev; 780 struct device *dev = &pdev->dev;
@@ -911,39 +952,30 @@ out:
911#ifdef CONFIG_PM_SLEEP 952#ifdef CONFIG_PM_SLEEP
912static int fimd_suspend(struct device *dev) 953static int fimd_suspend(struct device *dev)
913{ 954{
914 int ret; 955 struct fimd_context *ctx = get_fimd_context(dev);
915 956
916 if (pm_runtime_suspended(dev)) 957 if (pm_runtime_suspended(dev))
917 return 0; 958 return 0;
918 959
919 ret = pm_runtime_suspend(dev); 960 /*
920 if (ret < 0) 961 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
921 return ret; 962 * called here, an error would be returned by that interface
922 963 * because the usage_count of pm runtime is more than 1.
923 return 0; 964 */
965 return fimd_power_on(ctx, false);
924} 966}
925 967
926static int fimd_resume(struct device *dev) 968static int fimd_resume(struct device *dev)
927{ 969{
928 int ret; 970 struct fimd_context *ctx = get_fimd_context(dev);
929
930 ret = pm_runtime_resume(dev);
931 if (ret < 0) {
932 DRM_ERROR("failed to resume runtime pm.\n");
933 return ret;
934 }
935
936 pm_runtime_disable(dev);
937
938 ret = pm_runtime_set_active(dev);
939 if (ret < 0) {
940 DRM_ERROR("failed to active runtime pm.\n");
941 pm_runtime_enable(dev);
942 pm_runtime_suspend(dev);
943 return ret;
944 }
945 971
946 pm_runtime_enable(dev); 972 /*
973 * if entered to sleep when lcd panel was on, the usage_count
974 * of pm runtime would still be 1 so in this case, fimd driver
975 * should be on directly not drawing on pm runtime interface.
976 */
977 if (!pm_runtime_suspended(dev))
978 return fimd_power_on(ctx, true);
947 979
948 return 0; 980 return 0;
949} 981}
@@ -956,39 +988,16 @@ static int fimd_runtime_suspend(struct device *dev)
956 988
957 DRM_DEBUG_KMS("%s\n", __FILE__); 989 DRM_DEBUG_KMS("%s\n", __FILE__);
958 990
959 clk_disable(ctx->lcd_clk); 991 return fimd_power_on(ctx, false);
960 clk_disable(ctx->bus_clk);
961
962 ctx->suspended = true;
963 return 0;
964} 992}
965 993
966static int fimd_runtime_resume(struct device *dev) 994static int fimd_runtime_resume(struct device *dev)
967{ 995{
968 struct fimd_context *ctx = get_fimd_context(dev); 996 struct fimd_context *ctx = get_fimd_context(dev);
969 int ret;
970 997
971 DRM_DEBUG_KMS("%s\n", __FILE__); 998 DRM_DEBUG_KMS("%s\n", __FILE__);
972 999
973 ret = clk_enable(ctx->bus_clk); 1000 return fimd_power_on(ctx, true);
974 if (ret < 0)
975 return ret;
976
977 ret = clk_enable(ctx->lcd_clk);
978 if (ret < 0) {
979 clk_disable(ctx->bus_clk);
980 return ret;
981 }
982
983 ctx->suspended = false;
984
985 /* if vblank was enabled status, enable it again. */
986 if (test_and_clear_bit(0, &ctx->irq_flags))
987 fimd_enable_vblank(dev);
988
989 fimd_apply(dev);
990
991 return 0;
992} 1001}
993#endif 1002#endif
994 1003
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index f48f7ce92f5f..3429d3fd93f3 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1116,8 +1116,8 @@ err_ddc:
1116err_iomap: 1116err_iomap:
1117 iounmap(hdata->regs); 1117 iounmap(hdata->regs);
1118err_req_region: 1118err_req_region:
1119 release_resource(hdata->regs_res); 1119 release_mem_region(hdata->regs_res->start,
1120 kfree(hdata->regs_res); 1120 resource_size(hdata->regs_res));
1121err_resource: 1121err_resource:
1122 hdmi_resources_cleanup(hdata); 1122 hdmi_resources_cleanup(hdata);
1123err_data: 1123err_data:
@@ -1145,8 +1145,8 @@ static int __devexit hdmi_remove(struct platform_device *pdev)
1145 1145
1146 iounmap(hdata->regs); 1146 iounmap(hdata->regs);
1147 1147
1148 release_resource(hdata->regs_res); 1148 release_mem_region(hdata->regs_res->start,
1149 kfree(hdata->regs_res); 1149 resource_size(hdata->regs_res));
1150 1150
1151 /* hdmiphy i2c driver */ 1151 /* hdmiphy i2c driver */
1152 i2c_del_driver(&hdmiphy_driver); 1152 i2c_del_driver(&hdmiphy_driver);
diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c
index 791c0ef1a65b..830dfdd6bf15 100644
--- a/drivers/gpu/drm/gma500/framebuffer.c
+++ b/drivers/gpu/drm/gma500/framebuffer.c
@@ -113,12 +113,12 @@ static int psbfb_pan(struct fb_var_screeninfo *var, struct fb_info *info)
113 113
114void psbfb_suspend(struct drm_device *dev) 114void psbfb_suspend(struct drm_device *dev)
115{ 115{
116 struct drm_framebuffer *fb = 0; 116 struct drm_framebuffer *fb;
117 struct psb_framebuffer *psbfb = to_psb_fb(fb);
118 117
119 console_lock(); 118 console_lock();
120 mutex_lock(&dev->mode_config.mutex); 119 mutex_lock(&dev->mode_config.mutex);
121 list_for_each_entry(fb, &dev->mode_config.fb_list, head) { 120 list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
121 struct psb_framebuffer *psbfb = to_psb_fb(fb);
122 struct fb_info *info = psbfb->fbdev; 122 struct fb_info *info = psbfb->fbdev;
123 fb_set_suspend(info, 1); 123 fb_set_suspend(info, 1);
124 drm_fb_helper_blank(FB_BLANK_POWERDOWN, info); 124 drm_fb_helper_blank(FB_BLANK_POWERDOWN, info);
@@ -129,12 +129,12 @@ void psbfb_suspend(struct drm_device *dev)
129 129
130void psbfb_resume(struct drm_device *dev) 130void psbfb_resume(struct drm_device *dev)
131{ 131{
132 struct drm_framebuffer *fb = 0; 132 struct drm_framebuffer *fb;
133 struct psb_framebuffer *psbfb = to_psb_fb(fb);
134 133
135 console_lock(); 134 console_lock();
136 mutex_lock(&dev->mode_config.mutex); 135 mutex_lock(&dev->mode_config.mutex);
137 list_for_each_entry(fb, &dev->mode_config.fb_list, head) { 136 list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
137 struct psb_framebuffer *psbfb = to_psb_fb(fb);
138 struct fb_info *info = psbfb->fbdev; 138 struct fb_info *info = psbfb->fbdev;
139 fb_set_suspend(info, 0); 139 fb_set_suspend(info, 0);
140 drm_fb_helper_blank(FB_BLANK_UNBLANK, info); 140 drm_fb_helper_blank(FB_BLANK_UNBLANK, info);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 11807989f918..deaa657292b4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -121,11 +121,11 @@ static const char *cache_level_str(int type)
121static void 121static void
122describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 122describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
123{ 123{
124 seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s", 124 seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s",
125 &obj->base, 125 &obj->base,
126 get_pin_flag(obj), 126 get_pin_flag(obj),
127 get_tiling_flag(obj), 127 get_tiling_flag(obj),
128 obj->base.size, 128 obj->base.size / 1024,
129 obj->base.read_domains, 129 obj->base.read_domains,
130 obj->base.write_domain, 130 obj->base.write_domain,
131 obj->last_rendering_seqno, 131 obj->last_rendering_seqno,
@@ -653,7 +653,7 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
653 seq_printf(m, " Size : %08x\n", ring->size); 653 seq_printf(m, " Size : %08x\n", ring->size);
654 seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring)); 654 seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
655 seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring)); 655 seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
656 if (IS_GEN6(dev)) { 656 if (IS_GEN6(dev) || IS_GEN7(dev)) {
657 seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring)); 657 seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
658 seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring)); 658 seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
659 } 659 }
@@ -1075,6 +1075,7 @@ static int gen6_drpc_info(struct seq_file *m)
1075 struct drm_device *dev = node->minor->dev; 1075 struct drm_device *dev = node->minor->dev;
1076 struct drm_i915_private *dev_priv = dev->dev_private; 1076 struct drm_i915_private *dev_priv = dev->dev_private;
1077 u32 rpmodectl1, gt_core_status, rcctl1; 1077 u32 rpmodectl1, gt_core_status, rcctl1;
1078 unsigned forcewake_count;
1078 int count=0, ret; 1079 int count=0, ret;
1079 1080
1080 1081
@@ -1082,9 +1083,13 @@ static int gen6_drpc_info(struct seq_file *m)
1082 if (ret) 1083 if (ret)
1083 return ret; 1084 return ret;
1084 1085
1085 if (atomic_read(&dev_priv->forcewake_count)) { 1086 spin_lock_irq(&dev_priv->gt_lock);
1086 seq_printf(m, "RC information inaccurate because userspace " 1087 forcewake_count = dev_priv->forcewake_count;
1087 "holds a reference \n"); 1088 spin_unlock_irq(&dev_priv->gt_lock);
1089
1090 if (forcewake_count) {
1091 seq_printf(m, "RC information inaccurate because somebody "
1092 "holds a forcewake reference \n");
1088 } else { 1093 } else {
1089 /* NB: we cannot use forcewake, else we read the wrong values */ 1094 /* NB: we cannot use forcewake, else we read the wrong values */
1090 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) 1095 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
@@ -1106,7 +1111,7 @@ static int gen6_drpc_info(struct seq_file *m)
1106 seq_printf(m, "SW control enabled: %s\n", 1111 seq_printf(m, "SW control enabled: %s\n",
1107 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1112 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1108 GEN6_RP_MEDIA_SW_MODE)); 1113 GEN6_RP_MEDIA_SW_MODE));
1109 seq_printf(m, "RC6 Enabled: %s\n", 1114 seq_printf(m, "RC1e Enabled: %s\n",
1110 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 1115 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1111 seq_printf(m, "RC6 Enabled: %s\n", 1116 seq_printf(m, "RC6 Enabled: %s\n",
1112 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 1117 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
@@ -1398,9 +1403,13 @@ static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1398 struct drm_info_node *node = (struct drm_info_node *) m->private; 1403 struct drm_info_node *node = (struct drm_info_node *) m->private;
1399 struct drm_device *dev = node->minor->dev; 1404 struct drm_device *dev = node->minor->dev;
1400 struct drm_i915_private *dev_priv = dev->dev_private; 1405 struct drm_i915_private *dev_priv = dev->dev_private;
1406 unsigned forcewake_count;
1407
1408 spin_lock_irq(&dev_priv->gt_lock);
1409 forcewake_count = dev_priv->forcewake_count;
1410 spin_unlock_irq(&dev_priv->gt_lock);
1401 1411
1402 seq_printf(m, "forcewake count = %d\n", 1412 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1403 atomic_read(&dev_priv->forcewake_count));
1404 1413
1405 return 0; 1414 return 0;
1406} 1415}
@@ -1665,7 +1674,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
1665 struct drm_i915_private *dev_priv = dev->dev_private; 1674 struct drm_i915_private *dev_priv = dev->dev_private;
1666 int ret; 1675 int ret;
1667 1676
1668 if (!IS_GEN6(dev)) 1677 if (INTEL_INFO(dev)->gen < 6)
1669 return 0; 1678 return 0;
1670 1679
1671 ret = mutex_lock_interruptible(&dev->struct_mutex); 1680 ret = mutex_lock_interruptible(&dev->struct_mutex);
@@ -1682,7 +1691,7 @@ int i915_forcewake_release(struct inode *inode, struct file *file)
1682 struct drm_device *dev = inode->i_private; 1691 struct drm_device *dev = inode->i_private;
1683 struct drm_i915_private *dev_priv = dev->dev_private; 1692 struct drm_i915_private *dev_priv = dev->dev_private;
1684 1693
1685 if (!IS_GEN6(dev)) 1694 if (INTEL_INFO(dev)->gen < 6)
1686 return 0; 1695 return 0;
1687 1696
1688 /* 1697 /*
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 5f4d5893e983..ddfe3d902b2a 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2045,6 +2045,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2045 if (!IS_I945G(dev) && !IS_I945GM(dev)) 2045 if (!IS_I945G(dev) && !IS_I945GM(dev))
2046 pci_enable_msi(dev->pdev); 2046 pci_enable_msi(dev->pdev);
2047 2047
2048 spin_lock_init(&dev_priv->gt_lock);
2048 spin_lock_init(&dev_priv->irq_lock); 2049 spin_lock_init(&dev_priv->irq_lock);
2049 spin_lock_init(&dev_priv->error_lock); 2050 spin_lock_init(&dev_priv->error_lock);
2050 spin_lock_init(&dev_priv->rps_lock); 2051 spin_lock_init(&dev_priv->rps_lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8f7187915b0d..308f81913562 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -368,11 +368,12 @@ void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
368 */ 368 */
369void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 369void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
370{ 370{
371 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); 371 unsigned long irqflags;
372 372
373 /* Forcewake is atomic in case we get in here without the lock */ 373 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
374 if (atomic_add_return(1, &dev_priv->forcewake_count) == 1) 374 if (dev_priv->forcewake_count++ == 0)
375 dev_priv->display.force_wake_get(dev_priv); 375 dev_priv->display.force_wake_get(dev_priv);
376 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
376} 377}
377 378
378void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 379void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
@@ -392,10 +393,12 @@ void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
392 */ 393 */
393void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 394void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
394{ 395{
395 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); 396 unsigned long irqflags;
396 397
397 if (atomic_dec_and_test(&dev_priv->forcewake_count)) 398 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
399 if (--dev_priv->forcewake_count == 0)
398 dev_priv->display.force_wake_put(dev_priv); 400 dev_priv->display.force_wake_put(dev_priv);
401 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
399} 402}
400 403
401void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 404void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
@@ -597,9 +600,36 @@ static int ironlake_do_reset(struct drm_device *dev, u8 flags)
597static int gen6_do_reset(struct drm_device *dev, u8 flags) 600static int gen6_do_reset(struct drm_device *dev, u8 flags)
598{ 601{
599 struct drm_i915_private *dev_priv = dev->dev_private; 602 struct drm_i915_private *dev_priv = dev->dev_private;
603 int ret;
604 unsigned long irqflags;
600 605
601 I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL); 606 /* Hold gt_lock across reset to prevent any register access
602 return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); 607 * with forcewake not set correctly
608 */
609 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
610
611 /* Reset the chip */
612
613 /* GEN6_GDRST is not in the gt power well, no need to check
614 * for fifo space for the write or forcewake the chip for
615 * the read
616 */
617 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
618
619 /* Spin waiting for the device to ack the reset request */
620 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
621
622 /* If reset with a user forcewake, try to restore, otherwise turn it off */
623 if (dev_priv->forcewake_count)
624 dev_priv->display.force_wake_get(dev_priv);
625 else
626 dev_priv->display.force_wake_put(dev_priv);
627
628 /* Restore fifo count */
629 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
630
631 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
632 return ret;
603} 633}
604 634
605/** 635/**
@@ -643,9 +673,6 @@ int i915_reset(struct drm_device *dev, u8 flags)
643 case 7: 673 case 7:
644 case 6: 674 case 6:
645 ret = gen6_do_reset(dev, flags); 675 ret = gen6_do_reset(dev, flags);
646 /* If reset with a user forcewake, try to restore */
647 if (atomic_read(&dev_priv->forcewake_count))
648 __gen6_gt_force_wake_get(dev_priv);
649 break; 676 break;
650 case 5: 677 case 5:
651 ret = ironlake_do_reset(dev, flags); 678 ret = ironlake_do_reset(dev, flags);
@@ -927,9 +954,14 @@ MODULE_LICENSE("GPL and additional rights");
927u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 954u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
928 u##x val = 0; \ 955 u##x val = 0; \
929 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 956 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
930 gen6_gt_force_wake_get(dev_priv); \ 957 unsigned long irqflags; \
958 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
959 if (dev_priv->forcewake_count == 0) \
960 dev_priv->display.force_wake_get(dev_priv); \
931 val = read##y(dev_priv->regs + reg); \ 961 val = read##y(dev_priv->regs + reg); \
932 gen6_gt_force_wake_put(dev_priv); \ 962 if (dev_priv->forcewake_count == 0) \
963 dev_priv->display.force_wake_put(dev_priv); \
964 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
933 } else { \ 965 } else { \
934 val = read##y(dev_priv->regs + reg); \ 966 val = read##y(dev_priv->regs + reg); \
935 } \ 967 } \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 602bc80baabb..9689ca38b2b3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -288,7 +288,13 @@ typedef struct drm_i915_private {
288 int relative_constants_mode; 288 int relative_constants_mode;
289 289
290 void __iomem *regs; 290 void __iomem *regs;
291 u32 gt_fifo_count; 291 /** gt_fifo_count and the subsequent register write are synchronized
292 * with dev->struct_mutex. */
293 unsigned gt_fifo_count;
294 /** forcewake_count is protected by gt_lock */
295 unsigned forcewake_count;
296 /** gt_lock is also taken in irq contexts. */
297 struct spinlock gt_lock;
292 298
293 struct intel_gmbus { 299 struct intel_gmbus {
294 struct i2c_adapter adapter; 300 struct i2c_adapter adapter;
@@ -741,8 +747,6 @@ typedef struct drm_i915_private {
741 747
742 struct drm_property *broadcast_rgb_property; 748 struct drm_property *broadcast_rgb_property;
743 struct drm_property *force_audio_property; 749 struct drm_property *force_audio_property;
744
745 atomic_t forcewake_count;
746} drm_i915_private_t; 750} drm_i915_private_t;
747 751
748enum i915_cache_level { 752enum i915_cache_level {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d433fc11ace..5bd4361ea84d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1751,7 +1751,8 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
1751 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); 1751 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1752 1752
1753 I915_WRITE(HWSTAM, 0xeffe); 1753 I915_WRITE(HWSTAM, 0xeffe);
1754 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1754
1755 if (IS_GEN6(dev)) {
1755 /* Workaround stalls observed on Sandy Bridge GPUs by 1756 /* Workaround stalls observed on Sandy Bridge GPUs by
1756 * making the blitter command streamer generate a 1757 * making the blitter command streamer generate a
1757 * write to the Hardware Status Page for 1758 * write to the Hardware Status Page for
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 7886e4fb60e3..2b5eb229ff2c 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -28,14 +28,19 @@
28#include "drm.h" 28#include "drm.h"
29#include "i915_drm.h" 29#include "i915_drm.h"
30#include "intel_drv.h" 30#include "intel_drv.h"
31#include "i915_reg.h"
31 32
32static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) 33static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
33{ 34{
34 struct drm_i915_private *dev_priv = dev->dev_private; 35 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg; 36 u32 dpll_reg;
36 37
38 /* On IVB, 3rd pipe shares PLL with another one */
39 if (pipe > 1)
40 return false;
41
37 if (HAS_PCH_SPLIT(dev)) 42 if (HAS_PCH_SPLIT(dev))
38 dpll_reg = (pipe == PIPE_A) ? _PCH_DPLL_A : _PCH_DPLL_B; 43 dpll_reg = PCH_DPLL(pipe);
39 else 44 else
40 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B; 45 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
41 46
@@ -822,7 +827,7 @@ int i915_save_state(struct drm_device *dev)
822 827
823 if (IS_IRONLAKE_M(dev)) 828 if (IS_IRONLAKE_M(dev))
824 ironlake_disable_drps(dev); 829 ironlake_disable_drps(dev);
825 if (IS_GEN6(dev)) 830 if (INTEL_INFO(dev)->gen >= 6)
826 gen6_disable_rps(dev); 831 gen6_disable_rps(dev);
827 832
828 /* Cache mode state */ 833 /* Cache mode state */
@@ -881,7 +886,7 @@ int i915_restore_state(struct drm_device *dev)
881 intel_init_emon(dev); 886 intel_init_emon(dev);
882 } 887 }
883 888
884 if (IS_GEN6(dev)) { 889 if (INTEL_INFO(dev)->gen >= 6) {
885 gen6_enable_rps(dev_priv); 890 gen6_enable_rps(dev_priv);
886 gen6_update_ring_freq(dev_priv); 891 gen6_update_ring_freq(dev_priv);
887 } 892 }
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 8af3735e27c6..dbda6e3bdf07 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -467,8 +467,12 @@ struct edp_link_params {
467struct bdb_edp { 467struct bdb_edp {
468 struct edp_power_seq power_seqs[16]; 468 struct edp_power_seq power_seqs[16];
469 u32 color_depth; 469 u32 color_depth;
470 u32 sdrrs_msa_timing_delay;
471 struct edp_link_params link_params[16]; 470 struct edp_link_params link_params[16];
471 u32 sdrrs_msa_timing_delay;
472
473 /* ith bit indicates enabled/disabled for (i+1)th panel */
474 u16 edp_s3d_feature;
475 u16 edp_t3_optimization;
472} __attribute__ ((packed)); 476} __attribute__ ((packed));
473 477
474void intel_setup_bios(struct drm_device *dev); 478void intel_setup_bios(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index fee0ad02c6d0..dd729d46a61f 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -24,6 +24,7 @@
24 * Eric Anholt <eric@anholt.net> 24 * Eric Anholt <eric@anholt.net>
25 */ 25 */
26 26
27#include <linux/dmi.h>
27#include <linux/i2c.h> 28#include <linux/i2c.h>
28#include <linux/slab.h> 29#include <linux/slab.h>
29#include "drmP.h" 30#include "drmP.h"
@@ -540,6 +541,24 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = {
540 .destroy = intel_encoder_destroy, 541 .destroy = intel_encoder_destroy,
541}; 542};
542 543
544static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
545{
546 DRM_DEBUG_KMS("Skipping CRT initialization for %s\n", id->ident);
547 return 1;
548}
549
550static const struct dmi_system_id intel_no_crt[] = {
551 {
552 .callback = intel_no_crt_dmi_callback,
553 .ident = "ACER ZGB",
554 .matches = {
555 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
556 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
557 },
558 },
559 { }
560};
561
543void intel_crt_init(struct drm_device *dev) 562void intel_crt_init(struct drm_device *dev)
544{ 563{
545 struct drm_connector *connector; 564 struct drm_connector *connector;
@@ -547,6 +566,10 @@ void intel_crt_init(struct drm_device *dev)
547 struct intel_connector *intel_connector; 566 struct intel_connector *intel_connector;
548 struct drm_i915_private *dev_priv = dev->dev_private; 567 struct drm_i915_private *dev_priv = dev->dev_private;
549 568
569 /* Skip machines without VGA that falsely report hotplug events */
570 if (dmi_check_system(intel_no_crt))
571 return;
572
550 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 573 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
551 if (!crt) 574 if (!crt)
552 return; 575 return;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2a3f707caab8..b3b51c43dad0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5808,12 +5808,15 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5808 if (is_lvds) { 5808 if (is_lvds) {
5809 temp = I915_READ(PCH_LVDS); 5809 temp = I915_READ(PCH_LVDS);
5810 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 5810 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5811 if (HAS_PCH_CPT(dev)) 5811 if (HAS_PCH_CPT(dev)) {
5812 temp &= ~PORT_TRANS_SEL_MASK;
5812 temp |= PORT_TRANS_SEL_CPT(pipe); 5813 temp |= PORT_TRANS_SEL_CPT(pipe);
5813 else if (pipe == 1) 5814 } else {
5814 temp |= LVDS_PIPEB_SELECT; 5815 if (pipe == 1)
5815 else 5816 temp |= LVDS_PIPEB_SELECT;
5816 temp &= ~LVDS_PIPEB_SELECT; 5817 else
5818 temp &= ~LVDS_PIPEB_SELECT;
5819 }
5817 5820
5818 /* set the corresponsding LVDS_BORDER bit */ 5821 /* set the corresponsding LVDS_BORDER bit */
5819 temp |= dev_priv->lvds_border_bits; 5822 temp |= dev_priv->lvds_border_bits;
@@ -9025,12 +9028,9 @@ void intel_modeset_init(struct drm_device *dev)
9025 9028
9026 for (i = 0; i < dev_priv->num_pipe; i++) { 9029 for (i = 0; i < dev_priv->num_pipe; i++) {
9027 intel_crtc_init(dev, i); 9030 intel_crtc_init(dev, i);
9028 if (HAS_PCH_SPLIT(dev)) { 9031 ret = intel_plane_init(dev, i);
9029 ret = intel_plane_init(dev, i); 9032 if (ret)
9030 if (ret) 9033 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9031 DRM_ERROR("plane %d init failed: %d\n",
9032 i, ret);
9033 }
9034 } 9034 }
9035 9035
9036 /* Just disable it once at startup */ 9036 /* Just disable it once at startup */
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index e44191132ac4..798f6e1aa544 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -708,6 +708,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
708 }, 708 },
709 }, 709 },
710 { 710 {
711 .callback = intel_no_lvds_dmi_callback,
712 .ident = "Clientron E830",
713 .matches = {
714 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
715 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
716 },
717 },
718 {
711 .callback = intel_no_lvds_dmi_callback, 719 .callback = intel_no_lvds_dmi_callback,
712 .ident = "Asus EeeBox PC EB1007", 720 .ident = "Asus EeeBox PC EB1007",
713 .matches = { 721 .matches = {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 77e729d4e4f0..1ab842c6032e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -636,6 +636,19 @@ render_ring_add_request(struct intel_ring_buffer *ring,
636} 636}
637 637
638static u32 638static u32
639gen6_ring_get_seqno(struct intel_ring_buffer *ring)
640{
641 struct drm_device *dev = ring->dev;
642
643 /* Workaround to force correct ordering between irq and seqno writes on
644 * ivb (and maybe also on snb) by reading from a CS register (like
645 * ACTHD) before reading the status page. */
646 if (IS_GEN7(dev))
647 intel_ring_get_active_head(ring);
648 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
649}
650
651static u32
639ring_get_seqno(struct intel_ring_buffer *ring) 652ring_get_seqno(struct intel_ring_buffer *ring)
640{ 653{
641 return intel_read_status_page(ring, I915_GEM_HWS_INDEX); 654 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
@@ -792,17 +805,6 @@ ring_add_request(struct intel_ring_buffer *ring,
792} 805}
793 806
794static bool 807static bool
795gen7_blt_ring_get_irq(struct intel_ring_buffer *ring)
796{
797 /* The BLT ring on IVB appears to have broken synchronization
798 * between the seqno write and the interrupt, so that the
799 * interrupt appears first. Returning false here makes
800 * i915_wait_request() do a polling loop, instead.
801 */
802 return false;
803}
804
805static bool
806gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) 808gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
807{ 809{
808 struct drm_device *dev = ring->dev; 810 struct drm_device *dev = ring->dev;
@@ -811,6 +813,12 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
811 if (!dev->irq_enabled) 813 if (!dev->irq_enabled)
812 return false; 814 return false;
813 815
816 /* It looks like we need to prevent the gt from suspending while waiting
817 * for an notifiy irq, otherwise irqs seem to get lost on at least the
818 * blt/bsd rings on ivb. */
819 if (IS_GEN7(dev))
820 gen6_gt_force_wake_get(dev_priv);
821
814 spin_lock(&ring->irq_lock); 822 spin_lock(&ring->irq_lock);
815 if (ring->irq_refcount++ == 0) { 823 if (ring->irq_refcount++ == 0) {
816 ring->irq_mask &= ~rflag; 824 ring->irq_mask &= ~rflag;
@@ -835,6 +843,9 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
835 ironlake_disable_irq(dev_priv, gflag); 843 ironlake_disable_irq(dev_priv, gflag);
836 } 844 }
837 spin_unlock(&ring->irq_lock); 845 spin_unlock(&ring->irq_lock);
846
847 if (IS_GEN7(dev))
848 gen6_gt_force_wake_put(dev_priv);
838} 849}
839 850
840static bool 851static bool
@@ -1341,7 +1352,7 @@ static const struct intel_ring_buffer gen6_bsd_ring = {
1341 .write_tail = gen6_bsd_ring_write_tail, 1352 .write_tail = gen6_bsd_ring_write_tail,
1342 .flush = gen6_ring_flush, 1353 .flush = gen6_ring_flush,
1343 .add_request = gen6_add_request, 1354 .add_request = gen6_add_request,
1344 .get_seqno = ring_get_seqno, 1355 .get_seqno = gen6_ring_get_seqno,
1345 .irq_get = gen6_bsd_ring_get_irq, 1356 .irq_get = gen6_bsd_ring_get_irq,
1346 .irq_put = gen6_bsd_ring_put_irq, 1357 .irq_put = gen6_bsd_ring_put_irq,
1347 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, 1358 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
@@ -1476,7 +1487,7 @@ static const struct intel_ring_buffer gen6_blt_ring = {
1476 .write_tail = ring_write_tail, 1487 .write_tail = ring_write_tail,
1477 .flush = blt_ring_flush, 1488 .flush = blt_ring_flush,
1478 .add_request = gen6_add_request, 1489 .add_request = gen6_add_request,
1479 .get_seqno = ring_get_seqno, 1490 .get_seqno = gen6_ring_get_seqno,
1480 .irq_get = blt_ring_get_irq, 1491 .irq_get = blt_ring_get_irq,
1481 .irq_put = blt_ring_put_irq, 1492 .irq_put = blt_ring_put_irq,
1482 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, 1493 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
@@ -1499,6 +1510,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
1499 ring->flush = gen6_render_ring_flush; 1510 ring->flush = gen6_render_ring_flush;
1500 ring->irq_get = gen6_render_ring_get_irq; 1511 ring->irq_get = gen6_render_ring_get_irq;
1501 ring->irq_put = gen6_render_ring_put_irq; 1512 ring->irq_put = gen6_render_ring_put_irq;
1513 ring->get_seqno = gen6_ring_get_seqno;
1502 } else if (IS_GEN5(dev)) { 1514 } else if (IS_GEN5(dev)) {
1503 ring->add_request = pc_render_add_request; 1515 ring->add_request = pc_render_add_request;
1504 ring->get_seqno = pc_render_get_seqno; 1516 ring->get_seqno = pc_render_get_seqno;
@@ -1577,8 +1589,5 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
1577 1589
1578 *ring = gen6_blt_ring; 1590 *ring = gen6_blt_ring;
1579 1591
1580 if (IS_GEN7(dev))
1581 ring->irq_get = gen7_blt_ring_get_irq;
1582
1583 return intel_init_ring_buffer(dev, ring); 1592 return intel_init_ring_buffer(dev, ring);
1584} 1593}
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index f7b9268df266..e334ec33a47d 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1066,15 +1066,13 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1066 1066
1067 /* Set the SDVO control regs. */ 1067 /* Set the SDVO control regs. */
1068 if (INTEL_INFO(dev)->gen >= 4) { 1068 if (INTEL_INFO(dev)->gen >= 4) {
1069 sdvox = 0; 1069 /* The real mode polarity is set by the SDVO commands, using
1070 * struct intel_sdvo_dtd. */
1071 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1070 if (intel_sdvo->is_hdmi) 1072 if (intel_sdvo->is_hdmi)
1071 sdvox |= intel_sdvo->color_range; 1073 sdvox |= intel_sdvo->color_range;
1072 if (INTEL_INFO(dev)->gen < 5) 1074 if (INTEL_INFO(dev)->gen < 5)
1073 sdvox |= SDVO_BORDER_ENABLE; 1075 sdvox |= SDVO_BORDER_ENABLE;
1074 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1075 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1076 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1077 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
1078 } else { 1076 } else {
1079 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1077 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1080 switch (intel_sdvo->sdvo_reg) { 1078 switch (intel_sdvo->sdvo_reg) {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index d13989fda501..2288abf88cce 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -466,10 +466,8 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
466 mutex_lock(&dev->struct_mutex); 466 mutex_lock(&dev->struct_mutex);
467 467
468 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); 468 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
469 if (ret) { 469 if (ret)
470 DRM_ERROR("failed to pin object\n");
471 goto out_unlock; 470 goto out_unlock;
472 }
473 471
474 intel_plane->obj = obj; 472 intel_plane->obj = obj;
475 473
@@ -632,10 +630,8 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
632 unsigned long possible_crtcs; 630 unsigned long possible_crtcs;
633 int ret; 631 int ret;
634 632
635 if (!(IS_GEN6(dev) || IS_GEN7(dev))) { 633 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
636 DRM_ERROR("new plane code only for SNB+\n");
637 return -ENODEV; 634 return -ENODEV;
638 }
639 635
640 intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); 636 intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL);
641 if (!intel_plane) 637 if (!intel_plane)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index f3c6a9a8b081..1571be37ce3e 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -417,7 +417,7 @@ static const struct tv_mode tv_modes[] = {
417 { 417 {
418 .name = "NTSC-M", 418 .name = "NTSC-M",
419 .clock = 108000, 419 .clock = 108000,
420 .refresh = 29970, 420 .refresh = 59940,
421 .oversample = TV_OVERSAMPLE_8X, 421 .oversample = TV_OVERSAMPLE_8X,
422 .component_only = 0, 422 .component_only = 0,
423 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 423 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
@@ -460,7 +460,7 @@ static const struct tv_mode tv_modes[] = {
460 { 460 {
461 .name = "NTSC-443", 461 .name = "NTSC-443",
462 .clock = 108000, 462 .clock = 108000,
463 .refresh = 29970, 463 .refresh = 59940,
464 .oversample = TV_OVERSAMPLE_8X, 464 .oversample = TV_OVERSAMPLE_8X,
465 .component_only = 0, 465 .component_only = 0,
466 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */ 466 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
@@ -502,7 +502,7 @@ static const struct tv_mode tv_modes[] = {
502 { 502 {
503 .name = "NTSC-J", 503 .name = "NTSC-J",
504 .clock = 108000, 504 .clock = 108000,
505 .refresh = 29970, 505 .refresh = 59940,
506 .oversample = TV_OVERSAMPLE_8X, 506 .oversample = TV_OVERSAMPLE_8X,
507 .component_only = 0, 507 .component_only = 0,
508 508
@@ -545,7 +545,7 @@ static const struct tv_mode tv_modes[] = {
545 { 545 {
546 .name = "PAL-M", 546 .name = "PAL-M",
547 .clock = 108000, 547 .clock = 108000,
548 .refresh = 29970, 548 .refresh = 59940,
549 .oversample = TV_OVERSAMPLE_8X, 549 .oversample = TV_OVERSAMPLE_8X,
550 .component_only = 0, 550 .component_only = 0,
551 551
@@ -589,7 +589,7 @@ static const struct tv_mode tv_modes[] = {
589 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 589 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
590 .name = "PAL-N", 590 .name = "PAL-N",
591 .clock = 108000, 591 .clock = 108000,
592 .refresh = 25000, 592 .refresh = 50000,
593 .oversample = TV_OVERSAMPLE_8X, 593 .oversample = TV_OVERSAMPLE_8X,
594 .component_only = 0, 594 .component_only = 0,
595 595
@@ -634,7 +634,7 @@ static const struct tv_mode tv_modes[] = {
634 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 634 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
635 .name = "PAL", 635 .name = "PAL",
636 .clock = 108000, 636 .clock = 108000,
637 .refresh = 25000, 637 .refresh = 50000,
638 .oversample = TV_OVERSAMPLE_8X, 638 .oversample = TV_OVERSAMPLE_8X,
639 .component_only = 0, 639 .component_only = 0,
640 640
@@ -674,78 +674,6 @@ static const struct tv_mode tv_modes[] = {
674 .filter_table = filter_table, 674 .filter_table = filter_table,
675 }, 675 },
676 { 676 {
677 .name = "480p@59.94Hz",
678 .clock = 107520,
679 .refresh = 59940,
680 .oversample = TV_OVERSAMPLE_4X,
681 .component_only = 1,
682
683 .hsync_end = 64, .hblank_end = 122,
684 .hblank_start = 842, .htotal = 857,
685
686 .progressive = true, .trilevel_sync = false,
687
688 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
689 .vsync_len = 12,
690
691 .veq_ena = false,
692
693 .vi_end_f1 = 44, .vi_end_f2 = 44,
694 .nbr_end = 479,
695
696 .burst_ena = false,
697
698 .filter_table = filter_table,
699 },
700 {
701 .name = "480p@60Hz",
702 .clock = 107520,
703 .refresh = 60000,
704 .oversample = TV_OVERSAMPLE_4X,
705 .component_only = 1,
706
707 .hsync_end = 64, .hblank_end = 122,
708 .hblank_start = 842, .htotal = 856,
709
710 .progressive = true, .trilevel_sync = false,
711
712 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
713 .vsync_len = 12,
714
715 .veq_ena = false,
716
717 .vi_end_f1 = 44, .vi_end_f2 = 44,
718 .nbr_end = 479,
719
720 .burst_ena = false,
721
722 .filter_table = filter_table,
723 },
724 {
725 .name = "576p",
726 .clock = 107520,
727 .refresh = 50000,
728 .oversample = TV_OVERSAMPLE_4X,
729 .component_only = 1,
730
731 .hsync_end = 64, .hblank_end = 139,
732 .hblank_start = 859, .htotal = 863,
733
734 .progressive = true, .trilevel_sync = false,
735
736 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
737 .vsync_len = 10,
738
739 .veq_ena = false,
740
741 .vi_end_f1 = 48, .vi_end_f2 = 48,
742 .nbr_end = 575,
743
744 .burst_ena = false,
745
746 .filter_table = filter_table,
747 },
748 {
749 .name = "720p@60Hz", 677 .name = "720p@60Hz",
750 .clock = 148800, 678 .clock = 148800,
751 .refresh = 60000, 679 .refresh = 60000,
@@ -770,30 +698,6 @@ static const struct tv_mode tv_modes[] = {
770 .filter_table = filter_table, 698 .filter_table = filter_table,
771 }, 699 },
772 { 700 {
773 .name = "720p@59.94Hz",
774 .clock = 148800,
775 .refresh = 59940,
776 .oversample = TV_OVERSAMPLE_2X,
777 .component_only = 1,
778
779 .hsync_end = 80, .hblank_end = 300,
780 .hblank_start = 1580, .htotal = 1651,
781
782 .progressive = true, .trilevel_sync = true,
783
784 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
785 .vsync_len = 10,
786
787 .veq_ena = false,
788
789 .vi_end_f1 = 29, .vi_end_f2 = 29,
790 .nbr_end = 719,
791
792 .burst_ena = false,
793
794 .filter_table = filter_table,
795 },
796 {
797 .name = "720p@50Hz", 701 .name = "720p@50Hz",
798 .clock = 148800, 702 .clock = 148800,
799 .refresh = 50000, 703 .refresh = 50000,
@@ -821,7 +725,7 @@ static const struct tv_mode tv_modes[] = {
821 { 725 {
822 .name = "1080i@50Hz", 726 .name = "1080i@50Hz",
823 .clock = 148800, 727 .clock = 148800,
824 .refresh = 25000, 728 .refresh = 50000,
825 .oversample = TV_OVERSAMPLE_2X, 729 .oversample = TV_OVERSAMPLE_2X,
826 .component_only = 1, 730 .component_only = 1,
827 731
@@ -847,7 +751,7 @@ static const struct tv_mode tv_modes[] = {
847 { 751 {
848 .name = "1080i@60Hz", 752 .name = "1080i@60Hz",
849 .clock = 148800, 753 .clock = 148800,
850 .refresh = 30000, 754 .refresh = 60000,
851 .oversample = TV_OVERSAMPLE_2X, 755 .oversample = TV_OVERSAMPLE_2X,
852 .component_only = 1, 756 .component_only = 1,
853 757
@@ -870,32 +774,6 @@ static const struct tv_mode tv_modes[] = {
870 774
871 .filter_table = filter_table, 775 .filter_table = filter_table,
872 }, 776 },
873 {
874 .name = "1080i@59.94Hz",
875 .clock = 148800,
876 .refresh = 29970,
877 .oversample = TV_OVERSAMPLE_2X,
878 .component_only = 1,
879
880 .hsync_end = 88, .hblank_end = 235,
881 .hblank_start = 2155, .htotal = 2201,
882
883 .progressive = false, .trilevel_sync = true,
884
885 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
886 .vsync_len = 10,
887
888 .veq_ena = true, .veq_start_f1 = 4,
889 .veq_start_f2 = 4, .veq_len = 10,
890
891
892 .vi_end_f1 = 21, .vi_end_f2 = 22,
893 .nbr_end = 539,
894
895 .burst_ena = false,
896
897 .filter_table = filter_table,
898 },
899}; 777};
900 778
901static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder) 779static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder)