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-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c26
1 files changed, 15 insertions, 11 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index aadbd36e64b9..8abee5fa93bd 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -144,7 +144,12 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
144 144
145 for (i = 0; i < c; ++i) { 145 for (i = 0; i < c; ++i) {
146 rbo->placements[i].fpfn = 0; 146 rbo->placements[i].fpfn = 0;
147 rbo->placements[i].lpfn = 0; 147 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
148 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM))
149 rbo->placements[i].lpfn =
150 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
151 else
152 rbo->placements[i].lpfn = 0;
148 } 153 }
149 154
150 /* 155 /*
@@ -152,7 +157,9 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
152 * improve fragmentation quality. 157 * improve fragmentation quality.
153 * 512kb was measured as the most optimal number. 158 * 512kb was measured as the most optimal number.
154 */ 159 */
155 if (rbo->tbo.mem.size > 512 * 1024) { 160 if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
161 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) &&
162 rbo->tbo.mem.size > 512 * 1024) {
156 for (i = 0; i < c; i++) { 163 for (i = 0; i < c; i++) {
157 rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN; 164 rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
158 } 165 }
@@ -304,18 +311,15 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
304 } 311 }
305 radeon_ttm_placement_from_domain(bo, domain); 312 radeon_ttm_placement_from_domain(bo, domain);
306 for (i = 0; i < bo->placement.num_placement; i++) { 313 for (i = 0; i < bo->placement.num_placement; i++) {
307 unsigned lpfn = 0;
308
309 /* force to pin into visible video ram */ 314 /* force to pin into visible video ram */
310 if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) 315 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
311 lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 316 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
317 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
318 bo->placements[i].lpfn =
319 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
312 else 320 else
313 lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */ 321 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
314
315 if (max_offset)
316 lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT));
317 322
318 bo->placements[i].lpfn = lpfn;
319 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 323 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
320 } 324 }
321 325