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-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c1
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c3
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c3
4 files changed, 0 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4960bf629615..2365bb299276 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2016,7 +2016,6 @@ static int i915_pc8_status(struct seq_file *m, void *unused)
2016 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); 2016 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2017 seq_printf(m, "IRQs disabled: %s\n", 2017 seq_printf(m, "IRQs disabled: %s\n",
2018 yesno(dev_priv->pc8.irqs_disabled)); 2018 yesno(dev_priv->pc8.irqs_disabled));
2019 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
2020 mutex_unlock(&dev_priv->pc8.lock); 2019 mutex_unlock(&dev_priv->pc8.lock);
2021 2020
2022 return 0; 2021 return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 41efb09282ae..02102712465e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1391,8 +1391,6 @@ struct ilk_wm_values {
1391 */ 1391 */
1392struct i915_package_c8 { 1392struct i915_package_c8 {
1393 bool irqs_disabled; 1393 bool irqs_disabled;
1394 /* Only true after the delayed work task actually enables it. */
1395 bool enabled;
1396 struct mutex lock; 1394 struct mutex lock;
1397 1395
1398 struct { 1396 struct {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 90d16a1fa650..1553fe7542c7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7033,8 +7033,6 @@ void __hsw_do_enable_pc8(struct drm_i915_private *dev_priv)
7033 7033
7034 DRM_DEBUG_KMS("Enabling package C8+\n"); 7034 DRM_DEBUG_KMS("Enabling package C8+\n");
7035 7035
7036 dev_priv->pc8.enabled = true;
7037
7038 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { 7036 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7039 val = I915_READ(SOUTH_DSPCLK_GATE_D); 7037 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7040 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; 7038 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
@@ -7070,7 +7068,6 @@ void __hsw_do_disable_pc8(struct drm_i915_private *dev_priv)
7070 mutex_lock(&dev_priv->rps.hw_lock); 7068 mutex_lock(&dev_priv->rps.hw_lock);
7071 gen6_update_ring_freq(dev); 7069 gen6_update_ring_freq(dev);
7072 mutex_unlock(&dev_priv->rps.hw_lock); 7070 mutex_unlock(&dev_priv->rps.hw_lock);
7073 dev_priv->pc8.enabled = false;
7074} 7071}
7075 7072
7076static void haswell_modeset_global_resources(struct drm_device *dev) 7073static void haswell_modeset_global_resources(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 012867e85cda..ddd0368460ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5345,8 +5345,6 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5345 bool is_enabled, enable_requested; 5345 bool is_enabled, enable_requested;
5346 uint32_t tmp; 5346 uint32_t tmp;
5347 5347
5348 WARN_ON(dev_priv->pc8.enabled);
5349
5350 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 5348 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5351 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 5349 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5352 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 5350 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
@@ -6161,7 +6159,6 @@ void intel_pm_setup(struct drm_device *dev)
6161 6159
6162 mutex_init(&dev_priv->pc8.lock); 6160 mutex_init(&dev_priv->pc8.lock);
6163 dev_priv->pc8.irqs_disabled = false; 6161 dev_priv->pc8.irqs_disabled = false;
6164 dev_priv->pc8.enabled = false;
6165 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 6162 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6166 intel_gen6_powersave_work); 6163 intel_gen6_powersave_work);
6167} 6164}