diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/i915_dma.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 39 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 30 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_suspend.c | 305 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_bios.c | 14 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 178 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_lvds.c | 10 |
8 files changed, 486 insertions, 95 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 92aeb918e0c0..e5b138be45fa 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c | |||
@@ -1227,8 +1227,7 @@ static int i915_load_modeset_init(struct drm_device *dev, | |||
1227 | goto out; | 1227 | goto out; |
1228 | 1228 | ||
1229 | /* Try to set up FBC with a reasonable compressed buffer size */ | 1229 | /* Try to set up FBC with a reasonable compressed buffer size */ |
1230 | if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev) || IS_GM45(dev)) && | 1230 | if (I915_HAS_FBC(dev) && i915_powersave) { |
1231 | i915_powersave) { | ||
1232 | int cfb_size; | 1231 | int cfb_size; |
1233 | 1232 | ||
1234 | /* Try to get an 8M buffer... */ | 1233 | /* Try to get an 8M buffer... */ |
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c5df2234418d..57204e298975 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -296,6 +296,12 @@ typedef struct drm_i915_private { | |||
296 | u32 saveVBLANK_A; | 296 | u32 saveVBLANK_A; |
297 | u32 saveVSYNC_A; | 297 | u32 saveVSYNC_A; |
298 | u32 saveBCLRPAT_A; | 298 | u32 saveBCLRPAT_A; |
299 | u32 saveTRANS_HTOTAL_A; | ||
300 | u32 saveTRANS_HBLANK_A; | ||
301 | u32 saveTRANS_HSYNC_A; | ||
302 | u32 saveTRANS_VTOTAL_A; | ||
303 | u32 saveTRANS_VBLANK_A; | ||
304 | u32 saveTRANS_VSYNC_A; | ||
299 | u32 savePIPEASTAT; | 305 | u32 savePIPEASTAT; |
300 | u32 saveDSPASTRIDE; | 306 | u32 saveDSPASTRIDE; |
301 | u32 saveDSPASIZE; | 307 | u32 saveDSPASIZE; |
@@ -304,8 +310,11 @@ typedef struct drm_i915_private { | |||
304 | u32 saveDSPASURF; | 310 | u32 saveDSPASURF; |
305 | u32 saveDSPATILEOFF; | 311 | u32 saveDSPATILEOFF; |
306 | u32 savePFIT_PGM_RATIOS; | 312 | u32 savePFIT_PGM_RATIOS; |
313 | u32 saveBLC_HIST_CTL; | ||
307 | u32 saveBLC_PWM_CTL; | 314 | u32 saveBLC_PWM_CTL; |
308 | u32 saveBLC_PWM_CTL2; | 315 | u32 saveBLC_PWM_CTL2; |
316 | u32 saveBLC_CPU_PWM_CTL; | ||
317 | u32 saveBLC_CPU_PWM_CTL2; | ||
309 | u32 saveFPB0; | 318 | u32 saveFPB0; |
310 | u32 saveFPB1; | 319 | u32 saveFPB1; |
311 | u32 saveDPLL_B; | 320 | u32 saveDPLL_B; |
@@ -317,6 +326,12 @@ typedef struct drm_i915_private { | |||
317 | u32 saveVBLANK_B; | 326 | u32 saveVBLANK_B; |
318 | u32 saveVSYNC_B; | 327 | u32 saveVSYNC_B; |
319 | u32 saveBCLRPAT_B; | 328 | u32 saveBCLRPAT_B; |
329 | u32 saveTRANS_HTOTAL_B; | ||
330 | u32 saveTRANS_HBLANK_B; | ||
331 | u32 saveTRANS_HSYNC_B; | ||
332 | u32 saveTRANS_VTOTAL_B; | ||
333 | u32 saveTRANS_VBLANK_B; | ||
334 | u32 saveTRANS_VSYNC_B; | ||
320 | u32 savePIPEBSTAT; | 335 | u32 savePIPEBSTAT; |
321 | u32 saveDSPBSTRIDE; | 336 | u32 saveDSPBSTRIDE; |
322 | u32 saveDSPBSIZE; | 337 | u32 saveDSPBSIZE; |
@@ -342,6 +357,7 @@ typedef struct drm_i915_private { | |||
342 | u32 savePFIT_CONTROL; | 357 | u32 savePFIT_CONTROL; |
343 | u32 save_palette_a[256]; | 358 | u32 save_palette_a[256]; |
344 | u32 save_palette_b[256]; | 359 | u32 save_palette_b[256]; |
360 | u32 saveDPFC_CB_BASE; | ||
345 | u32 saveFBC_CFB_BASE; | 361 | u32 saveFBC_CFB_BASE; |
346 | u32 saveFBC_LL_BASE; | 362 | u32 saveFBC_LL_BASE; |
347 | u32 saveFBC_CONTROL; | 363 | u32 saveFBC_CONTROL; |
@@ -349,6 +365,12 @@ typedef struct drm_i915_private { | |||
349 | u32 saveIER; | 365 | u32 saveIER; |
350 | u32 saveIIR; | 366 | u32 saveIIR; |
351 | u32 saveIMR; | 367 | u32 saveIMR; |
368 | u32 saveDEIER; | ||
369 | u32 saveDEIMR; | ||
370 | u32 saveGTIER; | ||
371 | u32 saveGTIMR; | ||
372 | u32 saveFDI_RXA_IMR; | ||
373 | u32 saveFDI_RXB_IMR; | ||
352 | u32 saveCACHE_MODE_0; | 374 | u32 saveCACHE_MODE_0; |
353 | u32 saveD_STATE; | 375 | u32 saveD_STATE; |
354 | u32 saveDSPCLK_GATE_D; | 376 | u32 saveDSPCLK_GATE_D; |
@@ -382,6 +404,16 @@ typedef struct drm_i915_private { | |||
382 | u32 savePIPEB_DP_LINK_M; | 404 | u32 savePIPEB_DP_LINK_M; |
383 | u32 savePIPEA_DP_LINK_N; | 405 | u32 savePIPEA_DP_LINK_N; |
384 | u32 savePIPEB_DP_LINK_N; | 406 | u32 savePIPEB_DP_LINK_N; |
407 | u32 saveFDI_RXA_CTL; | ||
408 | u32 saveFDI_TXA_CTL; | ||
409 | u32 saveFDI_RXB_CTL; | ||
410 | u32 saveFDI_TXB_CTL; | ||
411 | u32 savePFA_CTL_1; | ||
412 | u32 savePFB_CTL_1; | ||
413 | u32 savePFA_WIN_SZ; | ||
414 | u32 savePFB_WIN_SZ; | ||
415 | u32 savePFA_WIN_POS; | ||
416 | u32 savePFB_WIN_POS; | ||
385 | 417 | ||
386 | struct { | 418 | struct { |
387 | struct drm_mm gtt_space; | 419 | struct drm_mm gtt_space; |
@@ -492,6 +524,8 @@ typedef struct drm_i915_private { | |||
492 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | 524 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
493 | } mm; | 525 | } mm; |
494 | struct sdvo_device_mapping sdvo_mappings[2]; | 526 | struct sdvo_device_mapping sdvo_mappings[2]; |
527 | /* indicate whether the LVDS_BORDER should be enabled or not */ | ||
528 | unsigned int lvds_border_bits; | ||
495 | 529 | ||
496 | /* Reclocking support */ | 530 | /* Reclocking support */ |
497 | bool render_reclock_avail; | 531 | bool render_reclock_avail; |
@@ -981,7 +1015,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); | |||
981 | 1015 | ||
982 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) | 1016 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) |
983 | #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) | 1017 | #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) |
984 | #define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev))) | 1018 | #define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \ |
1019 | (IS_I9XX(dev) || IS_GM45(dev)) && \ | ||
1020 | !IS_IGD(dev) && \ | ||
1021 | !IS_IGDNG(dev)) | ||
985 | 1022 | ||
986 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) | 1023 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
987 | 1024 | ||
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0466ddbeba32..1687edf68795 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -968,6 +968,8 @@ | |||
968 | #define LVDS_PORT_EN (1 << 31) | 968 | #define LVDS_PORT_EN (1 << 31) |
969 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ | 969 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ |
970 | #define LVDS_PIPEB_SELECT (1 << 30) | 970 | #define LVDS_PIPEB_SELECT (1 << 30) |
971 | /* Enable border for unscaled (or aspect-scaled) display */ | ||
972 | #define LVDS_BORDER_ENABLE (1 << 15) | ||
971 | /* | 973 | /* |
972 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per | 974 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per |
973 | * pixel. | 975 | * pixel. |
@@ -1078,6 +1080,8 @@ | |||
1078 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) | 1080 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) |
1079 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) | 1081 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
1080 | 1082 | ||
1083 | #define BLC_HIST_CTL 0x61260 | ||
1084 | |||
1081 | /* TV port control */ | 1085 | /* TV port control */ |
1082 | #define TV_CTL 0x68000 | 1086 | #define TV_CTL 0x68000 |
1083 | /** Enables the TV encoder */ | 1087 | /** Enables the TV encoder */ |
@@ -1780,6 +1784,11 @@ | |||
1780 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ | 1784 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ |
1781 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) | 1785 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) |
1782 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) | 1786 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) |
1787 | #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ | ||
1788 | #define PIPE_8BPC (0 << 5) | ||
1789 | #define PIPE_10BPC (1 << 5) | ||
1790 | #define PIPE_6BPC (2 << 5) | ||
1791 | #define PIPE_12BPC (3 << 5) | ||
1783 | 1792 | ||
1784 | #define DSPARB 0x70030 | 1793 | #define DSPARB 0x70030 |
1785 | #define DSPARB_CSTART_MASK (0x7f << 7) | 1794 | #define DSPARB_CSTART_MASK (0x7f << 7) |
@@ -1790,17 +1799,29 @@ | |||
1790 | #define DSPARB_AEND_SHIFT 0 | 1799 | #define DSPARB_AEND_SHIFT 0 |
1791 | 1800 | ||
1792 | #define DSPFW1 0x70034 | 1801 | #define DSPFW1 0x70034 |
1802 | #define DSPFW_SR_SHIFT 23 | ||
1803 | #define DSPFW_CURSORB_SHIFT 16 | ||
1804 | #define DSPFW_PLANEB_SHIFT 8 | ||
1793 | #define DSPFW2 0x70038 | 1805 | #define DSPFW2 0x70038 |
1806 | #define DSPFW_CURSORA_MASK 0x00003f00 | ||
1807 | #define DSPFW_CURSORA_SHIFT 16 | ||
1794 | #define DSPFW3 0x7003c | 1808 | #define DSPFW3 0x7003c |
1809 | #define DSPFW_HPLL_SR_EN (1<<31) | ||
1810 | #define DSPFW_CURSOR_SR_SHIFT 24 | ||
1795 | #define IGD_SELF_REFRESH_EN (1<<30) | 1811 | #define IGD_SELF_REFRESH_EN (1<<30) |
1796 | 1812 | ||
1797 | /* FIFO watermark sizes etc */ | 1813 | /* FIFO watermark sizes etc */ |
1814 | #define G4X_FIFO_LINE_SIZE 64 | ||
1798 | #define I915_FIFO_LINE_SIZE 64 | 1815 | #define I915_FIFO_LINE_SIZE 64 |
1799 | #define I830_FIFO_LINE_SIZE 32 | 1816 | #define I830_FIFO_LINE_SIZE 32 |
1817 | |||
1818 | #define G4X_FIFO_SIZE 127 | ||
1800 | #define I945_FIFO_SIZE 127 /* 945 & 965 */ | 1819 | #define I945_FIFO_SIZE 127 /* 945 & 965 */ |
1801 | #define I915_FIFO_SIZE 95 | 1820 | #define I915_FIFO_SIZE 95 |
1802 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ | 1821 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
1803 | #define I830_FIFO_SIZE 95 | 1822 | #define I830_FIFO_SIZE 95 |
1823 | |||
1824 | #define G4X_MAX_WM 0x3f | ||
1804 | #define I915_MAX_WM 0x3f | 1825 | #define I915_MAX_WM 0x3f |
1805 | 1826 | ||
1806 | #define IGD_DISPLAY_FIFO 512 /* in 64byte unit */ | 1827 | #define IGD_DISPLAY_FIFO 512 /* in 64byte unit */ |
@@ -2030,6 +2051,11 @@ | |||
2030 | #define PFA_CTL_1 0x68080 | 2051 | #define PFA_CTL_1 0x68080 |
2031 | #define PFB_CTL_1 0x68880 | 2052 | #define PFB_CTL_1 0x68880 |
2032 | #define PF_ENABLE (1<<31) | 2053 | #define PF_ENABLE (1<<31) |
2054 | #define PF_FILTER_MASK (3<<23) | ||
2055 | #define PF_FILTER_PROGRAMMED (0<<23) | ||
2056 | #define PF_FILTER_MED_3x3 (1<<23) | ||
2057 | #define PF_FILTER_EDGE_ENHANCE (2<<23) | ||
2058 | #define PF_FILTER_EDGE_SOFTEN (3<<23) | ||
2033 | #define PFA_WIN_SZ 0x68074 | 2059 | #define PFA_WIN_SZ 0x68074 |
2034 | #define PFB_WIN_SZ 0x68874 | 2060 | #define PFB_WIN_SZ 0x68874 |
2035 | #define PFA_WIN_POS 0x68070 | 2061 | #define PFA_WIN_POS 0x68070 |
@@ -2149,11 +2175,11 @@ | |||
2149 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) | 2175 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) |
2150 | #define DREF_SSC_SOURCE_DISABLE (0<<11) | 2176 | #define DREF_SSC_SOURCE_DISABLE (0<<11) |
2151 | #define DREF_SSC_SOURCE_ENABLE (2<<11) | 2177 | #define DREF_SSC_SOURCE_ENABLE (2<<11) |
2152 | #define DREF_SSC_SOURCE_MASK (2<<11) | 2178 | #define DREF_SSC_SOURCE_MASK (3<<11) |
2153 | #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) | 2179 | #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) |
2154 | #define DREF_NONSPREAD_CK505_ENABLE (1<<9) | 2180 | #define DREF_NONSPREAD_CK505_ENABLE (1<<9) |
2155 | #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) | 2181 | #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) |
2156 | #define DREF_NONSPREAD_SOURCE_MASK (2<<9) | 2182 | #define DREF_NONSPREAD_SOURCE_MASK (3<<9) |
2157 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) | 2183 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) |
2158 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) | 2184 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) |
2159 | #define DREF_SSC4_DOWNSPREAD (0<<6) | 2185 | #define DREF_SSC4_DOWNSPREAD (0<<6) |
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index bd6d8d91ca9f..992d5617e798 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c | |||
@@ -32,11 +32,15 @@ | |||
32 | static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) | 32 | static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) |
33 | { | 33 | { |
34 | struct drm_i915_private *dev_priv = dev->dev_private; | 34 | struct drm_i915_private *dev_priv = dev->dev_private; |
35 | u32 dpll_reg; | ||
35 | 36 | ||
36 | if (pipe == PIPE_A) | 37 | if (IS_IGDNG(dev)) { |
37 | return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE); | 38 | dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B; |
38 | else | 39 | } else { |
39 | return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE); | 40 | dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B; |
41 | } | ||
42 | |||
43 | return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE); | ||
40 | } | 44 | } |
41 | 45 | ||
42 | static void i915_save_palette(struct drm_device *dev, enum pipe pipe) | 46 | static void i915_save_palette(struct drm_device *dev, enum pipe pipe) |
@@ -49,6 +53,9 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe) | |||
49 | if (!i915_pipe_enabled(dev, pipe)) | 53 | if (!i915_pipe_enabled(dev, pipe)) |
50 | return; | 54 | return; |
51 | 55 | ||
56 | if (IS_IGDNG(dev)) | ||
57 | reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; | ||
58 | |||
52 | if (pipe == PIPE_A) | 59 | if (pipe == PIPE_A) |
53 | array = dev_priv->save_palette_a; | 60 | array = dev_priv->save_palette_a; |
54 | else | 61 | else |
@@ -68,6 +75,9 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe) | |||
68 | if (!i915_pipe_enabled(dev, pipe)) | 75 | if (!i915_pipe_enabled(dev, pipe)) |
69 | return; | 76 | return; |
70 | 77 | ||
78 | if (IS_IGDNG(dev)) | ||
79 | reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; | ||
80 | |||
71 | if (pipe == PIPE_A) | 81 | if (pipe == PIPE_A) |
72 | array = dev_priv->save_palette_a; | 82 | array = dev_priv->save_palette_a; |
73 | else | 83 | else |
@@ -232,10 +242,16 @@ static void i915_save_modeset_reg(struct drm_device *dev) | |||
232 | /* Pipe & plane A info */ | 242 | /* Pipe & plane A info */ |
233 | dev_priv->savePIPEACONF = I915_READ(PIPEACONF); | 243 | dev_priv->savePIPEACONF = I915_READ(PIPEACONF); |
234 | dev_priv->savePIPEASRC = I915_READ(PIPEASRC); | 244 | dev_priv->savePIPEASRC = I915_READ(PIPEASRC); |
235 | dev_priv->saveFPA0 = I915_READ(FPA0); | 245 | if (IS_IGDNG(dev)) { |
236 | dev_priv->saveFPA1 = I915_READ(FPA1); | 246 | dev_priv->saveFPA0 = I915_READ(PCH_FPA0); |
237 | dev_priv->saveDPLL_A = I915_READ(DPLL_A); | 247 | dev_priv->saveFPA1 = I915_READ(PCH_FPA1); |
238 | if (IS_I965G(dev)) | 248 | dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A); |
249 | } else { | ||
250 | dev_priv->saveFPA0 = I915_READ(FPA0); | ||
251 | dev_priv->saveFPA1 = I915_READ(FPA1); | ||
252 | dev_priv->saveDPLL_A = I915_READ(DPLL_A); | ||
253 | } | ||
254 | if (IS_I965G(dev) && !IS_IGDNG(dev)) | ||
239 | dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); | 255 | dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); |
240 | dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); | 256 | dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); |
241 | dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); | 257 | dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); |
@@ -243,7 +259,24 @@ static void i915_save_modeset_reg(struct drm_device *dev) | |||
243 | dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); | 259 | dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); |
244 | dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); | 260 | dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); |
245 | dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); | 261 | dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); |
246 | dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); | 262 | if (!IS_IGDNG(dev)) |
263 | dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); | ||
264 | |||
265 | if (IS_IGDNG(dev)) { | ||
266 | dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL); | ||
267 | dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL); | ||
268 | |||
269 | dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1); | ||
270 | dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ); | ||
271 | dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS); | ||
272 | |||
273 | dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A); | ||
274 | dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A); | ||
275 | dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A); | ||
276 | dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A); | ||
277 | dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A); | ||
278 | dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A); | ||
279 | } | ||
247 | 280 | ||
248 | dev_priv->saveDSPACNTR = I915_READ(DSPACNTR); | 281 | dev_priv->saveDSPACNTR = I915_READ(DSPACNTR); |
249 | dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); | 282 | dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); |
@@ -260,10 +293,16 @@ static void i915_save_modeset_reg(struct drm_device *dev) | |||
260 | /* Pipe & plane B info */ | 293 | /* Pipe & plane B info */ |
261 | dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); | 294 | dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); |
262 | dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); | 295 | dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); |
263 | dev_priv->saveFPB0 = I915_READ(FPB0); | 296 | if (IS_IGDNG(dev)) { |
264 | dev_priv->saveFPB1 = I915_READ(FPB1); | 297 | dev_priv->saveFPB0 = I915_READ(PCH_FPB0); |
265 | dev_priv->saveDPLL_B = I915_READ(DPLL_B); | 298 | dev_priv->saveFPB1 = I915_READ(PCH_FPB1); |
266 | if (IS_I965G(dev)) | 299 | dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B); |
300 | } else { | ||
301 | dev_priv->saveFPB0 = I915_READ(FPB0); | ||
302 | dev_priv->saveFPB1 = I915_READ(FPB1); | ||
303 | dev_priv->saveDPLL_B = I915_READ(DPLL_B); | ||
304 | } | ||
305 | if (IS_I965G(dev) && !IS_IGDNG(dev)) | ||
267 | dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); | 306 | dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); |
268 | dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); | 307 | dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); |
269 | dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); | 308 | dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); |
@@ -271,7 +310,24 @@ static void i915_save_modeset_reg(struct drm_device *dev) | |||
271 | dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); | 310 | dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); |
272 | dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); | 311 | dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); |
273 | dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); | 312 | dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); |
274 | dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); | 313 | if (!IS_IGDNG(dev)) |
314 | dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B); | ||
315 | |||
316 | if (IS_IGDNG(dev)) { | ||
317 | dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL); | ||
318 | dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL); | ||
319 | |||
320 | dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1); | ||
321 | dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ); | ||
322 | dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS); | ||
323 | |||
324 | dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B); | ||
325 | dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B); | ||
326 | dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B); | ||
327 | dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B); | ||
328 | dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B); | ||
329 | dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B); | ||
330 | } | ||
275 | 331 | ||
276 | dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR); | 332 | dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR); |
277 | dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); | 333 | dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); |
@@ -290,23 +346,41 @@ static void i915_save_modeset_reg(struct drm_device *dev) | |||
290 | static void i915_restore_modeset_reg(struct drm_device *dev) | 346 | static void i915_restore_modeset_reg(struct drm_device *dev) |
291 | { | 347 | { |
292 | struct drm_i915_private *dev_priv = dev->dev_private; | 348 | struct drm_i915_private *dev_priv = dev->dev_private; |
349 | int dpll_a_reg, fpa0_reg, fpa1_reg; | ||
350 | int dpll_b_reg, fpb0_reg, fpb1_reg; | ||
293 | 351 | ||
294 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | 352 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
295 | return; | 353 | return; |
296 | 354 | ||
355 | if (IS_IGDNG(dev)) { | ||
356 | dpll_a_reg = PCH_DPLL_A; | ||
357 | dpll_b_reg = PCH_DPLL_B; | ||
358 | fpa0_reg = PCH_FPA0; | ||
359 | fpb0_reg = PCH_FPB0; | ||
360 | fpa1_reg = PCH_FPA1; | ||
361 | fpb1_reg = PCH_FPB1; | ||
362 | } else { | ||
363 | dpll_a_reg = DPLL_A; | ||
364 | dpll_b_reg = DPLL_B; | ||
365 | fpa0_reg = FPA0; | ||
366 | fpb0_reg = FPB0; | ||
367 | fpa1_reg = FPA1; | ||
368 | fpb1_reg = FPB1; | ||
369 | } | ||
370 | |||
297 | /* Pipe & plane A info */ | 371 | /* Pipe & plane A info */ |
298 | /* Prime the clock */ | 372 | /* Prime the clock */ |
299 | if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { | 373 | if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { |
300 | I915_WRITE(DPLL_A, dev_priv->saveDPLL_A & | 374 | I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A & |
301 | ~DPLL_VCO_ENABLE); | 375 | ~DPLL_VCO_ENABLE); |
302 | DRM_UDELAY(150); | 376 | DRM_UDELAY(150); |
303 | } | 377 | } |
304 | I915_WRITE(FPA0, dev_priv->saveFPA0); | 378 | I915_WRITE(fpa0_reg, dev_priv->saveFPA0); |
305 | I915_WRITE(FPA1, dev_priv->saveFPA1); | 379 | I915_WRITE(fpa1_reg, dev_priv->saveFPA1); |
306 | /* Actually enable it */ | 380 | /* Actually enable it */ |
307 | I915_WRITE(DPLL_A, dev_priv->saveDPLL_A); | 381 | I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); |
308 | DRM_UDELAY(150); | 382 | DRM_UDELAY(150); |
309 | if (IS_I965G(dev)) | 383 | if (IS_I965G(dev) && !IS_IGDNG(dev)) |
310 | I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); | 384 | I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); |
311 | DRM_UDELAY(150); | 385 | DRM_UDELAY(150); |
312 | 386 | ||
@@ -317,7 +391,24 @@ static void i915_restore_modeset_reg(struct drm_device *dev) | |||
317 | I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); | 391 | I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); |
318 | I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); | 392 | I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); |
319 | I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); | 393 | I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); |
320 | I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); | 394 | if (!IS_IGDNG(dev)) |
395 | I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); | ||
396 | |||
397 | if (IS_IGDNG(dev)) { | ||
398 | I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL); | ||
399 | I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL); | ||
400 | |||
401 | I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1); | ||
402 | I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ); | ||
403 | I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS); | ||
404 | |||
405 | I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A); | ||
406 | I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A); | ||
407 | I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A); | ||
408 | I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A); | ||
409 | I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A); | ||
410 | I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A); | ||
411 | } | ||
321 | 412 | ||
322 | /* Restore plane info */ | 413 | /* Restore plane info */ |
323 | I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); | 414 | I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); |
@@ -339,14 +430,14 @@ static void i915_restore_modeset_reg(struct drm_device *dev) | |||
339 | 430 | ||
340 | /* Pipe & plane B info */ | 431 | /* Pipe & plane B info */ |
341 | if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { | 432 | if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { |
342 | I915_WRITE(DPLL_B, dev_priv->saveDPLL_B & | 433 | I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B & |
343 | ~DPLL_VCO_ENABLE); | 434 | ~DPLL_VCO_ENABLE); |
344 | DRM_UDELAY(150); | 435 | DRM_UDELAY(150); |
345 | } | 436 | } |
346 | I915_WRITE(FPB0, dev_priv->saveFPB0); | 437 | I915_WRITE(fpb0_reg, dev_priv->saveFPB0); |
347 | I915_WRITE(FPB1, dev_priv->saveFPB1); | 438 | I915_WRITE(fpb1_reg, dev_priv->saveFPB1); |
348 | /* Actually enable it */ | 439 | /* Actually enable it */ |
349 | I915_WRITE(DPLL_B, dev_priv->saveDPLL_B); | 440 | I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B); |
350 | DRM_UDELAY(150); | 441 | DRM_UDELAY(150); |
351 | if (IS_I965G(dev)) | 442 | if (IS_I965G(dev)) |
352 | I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); | 443 | I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); |
@@ -359,7 +450,24 @@ static void i915_restore_modeset_reg(struct drm_device *dev) | |||
359 | I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); | 450 | I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); |
360 | I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); | 451 | I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); |
361 | I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); | 452 | I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); |
362 | I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); | 453 | if (!IS_IGDNG(dev)) |
454 | I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); | ||
455 | |||
456 | if (IS_IGDNG(dev)) { | ||
457 | I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL); | ||
458 | I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL); | ||
459 | |||
460 | I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1); | ||
461 | I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ); | ||
462 | I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS); | ||
463 | |||
464 | I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B); | ||
465 | I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B); | ||
466 | I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B); | ||
467 | I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B); | ||
468 | I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B); | ||
469 | I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B); | ||
470 | } | ||
363 | 471 | ||
364 | /* Restore plane info */ | 472 | /* Restore plane info */ |
365 | I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); | 473 | I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); |
@@ -404,21 +512,43 @@ void i915_save_display(struct drm_device *dev) | |||
404 | dev_priv->saveCURSIZE = I915_READ(CURSIZE); | 512 | dev_priv->saveCURSIZE = I915_READ(CURSIZE); |
405 | 513 | ||
406 | /* CRT state */ | 514 | /* CRT state */ |
407 | dev_priv->saveADPA = I915_READ(ADPA); | 515 | if (IS_IGDNG(dev)) { |
516 | dev_priv->saveADPA = I915_READ(PCH_ADPA); | ||
517 | } else { | ||
518 | dev_priv->saveADPA = I915_READ(ADPA); | ||
519 | } | ||
408 | 520 | ||
409 | /* LVDS state */ | 521 | /* LVDS state */ |
410 | dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); | 522 | if (IS_IGDNG(dev)) { |
411 | dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); | 523 | dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL); |
412 | dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); | 524 | dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); |
413 | if (IS_I965G(dev)) | 525 | dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); |
414 | dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); | 526 | dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL); |
415 | if (IS_MOBILE(dev) && !IS_I830(dev)) | 527 | dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2); |
416 | dev_priv->saveLVDS = I915_READ(LVDS); | 528 | dev_priv->saveLVDS = I915_READ(PCH_LVDS); |
417 | if (!IS_I830(dev) && !IS_845G(dev)) | 529 | } else { |
530 | dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); | ||
531 | dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); | ||
532 | dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); | ||
533 | dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL); | ||
534 | if (IS_I965G(dev)) | ||
535 | dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); | ||
536 | if (IS_MOBILE(dev) && !IS_I830(dev)) | ||
537 | dev_priv->saveLVDS = I915_READ(LVDS); | ||
538 | } | ||
539 | |||
540 | if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev)) | ||
418 | dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); | 541 | dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); |
419 | dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); | 542 | |
420 | dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); | 543 | if (IS_IGDNG(dev)) { |
421 | dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); | 544 | dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); |
545 | dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); | ||
546 | dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); | ||
547 | } else { | ||
548 | dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); | ||
549 | dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); | ||
550 | dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); | ||
551 | } | ||
422 | 552 | ||
423 | /* Display Port state */ | 553 | /* Display Port state */ |
424 | if (SUPPORTS_INTEGRATED_DP(dev)) { | 554 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
@@ -437,16 +567,23 @@ void i915_save_display(struct drm_device *dev) | |||
437 | /* FIXME: save TV & SDVO state */ | 567 | /* FIXME: save TV & SDVO state */ |
438 | 568 | ||
439 | /* FBC state */ | 569 | /* FBC state */ |
440 | dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); | 570 | if (IS_GM45(dev)) { |
441 | dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); | 571 | dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE); |
442 | dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); | 572 | } else { |
443 | dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); | 573 | dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); |
574 | dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); | ||
575 | dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); | ||
576 | dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); | ||
577 | } | ||
444 | 578 | ||
445 | /* VGA state */ | 579 | /* VGA state */ |
446 | dev_priv->saveVGA0 = I915_READ(VGA0); | 580 | dev_priv->saveVGA0 = I915_READ(VGA0); |
447 | dev_priv->saveVGA1 = I915_READ(VGA1); | 581 | dev_priv->saveVGA1 = I915_READ(VGA1); |
448 | dev_priv->saveVGA_PD = I915_READ(VGA_PD); | 582 | dev_priv->saveVGA_PD = I915_READ(VGA_PD); |
449 | dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); | 583 | if (IS_IGDNG(dev)) |
584 | dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL); | ||
585 | else | ||
586 | dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); | ||
450 | 587 | ||
451 | i915_save_vga(dev); | 588 | i915_save_vga(dev); |
452 | } | 589 | } |
@@ -485,22 +622,41 @@ void i915_restore_display(struct drm_device *dev) | |||
485 | I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); | 622 | I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); |
486 | 623 | ||
487 | /* CRT state */ | 624 | /* CRT state */ |
488 | I915_WRITE(ADPA, dev_priv->saveADPA); | 625 | if (IS_IGDNG(dev)) |
626 | I915_WRITE(PCH_ADPA, dev_priv->saveADPA); | ||
627 | else | ||
628 | I915_WRITE(ADPA, dev_priv->saveADPA); | ||
489 | 629 | ||
490 | /* LVDS state */ | 630 | /* LVDS state */ |
491 | if (IS_I965G(dev)) | 631 | if (IS_I965G(dev) && !IS_IGDNG(dev)) |
492 | I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); | 632 | I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); |
493 | if (IS_MOBILE(dev) && !IS_I830(dev)) | 633 | |
634 | if (IS_IGDNG(dev)) { | ||
635 | I915_WRITE(PCH_LVDS, dev_priv->saveLVDS); | ||
636 | } else if (IS_MOBILE(dev) && !IS_I830(dev)) | ||
494 | I915_WRITE(LVDS, dev_priv->saveLVDS); | 637 | I915_WRITE(LVDS, dev_priv->saveLVDS); |
495 | if (!IS_I830(dev) && !IS_845G(dev)) | 638 | |
639 | if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev)) | ||
496 | I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); | 640 | I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); |
497 | 641 | ||
498 | I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); | 642 | if (IS_IGDNG(dev)) { |
499 | I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); | 643 | I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL); |
500 | I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); | 644 | I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2); |
501 | I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); | 645 | I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL); |
502 | I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); | 646 | I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2); |
503 | I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); | 647 | I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); |
648 | I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); | ||
649 | I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); | ||
650 | I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL); | ||
651 | } else { | ||
652 | I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); | ||
653 | I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); | ||
654 | I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL); | ||
655 | I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); | ||
656 | I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); | ||
657 | I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); | ||
658 | I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); | ||
659 | } | ||
504 | 660 | ||
505 | /* Display Port state */ | 661 | /* Display Port state */ |
506 | if (SUPPORTS_INTEGRATED_DP(dev)) { | 662 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
@@ -511,13 +667,22 @@ void i915_restore_display(struct drm_device *dev) | |||
511 | /* FIXME: restore TV & SDVO state */ | 667 | /* FIXME: restore TV & SDVO state */ |
512 | 668 | ||
513 | /* FBC info */ | 669 | /* FBC info */ |
514 | I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE); | 670 | if (IS_GM45(dev)) { |
515 | I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE); | 671 | g4x_disable_fbc(dev); |
516 | I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2); | 672 | I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE); |
517 | I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL); | 673 | } else { |
674 | i8xx_disable_fbc(dev); | ||
675 | I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE); | ||
676 | I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE); | ||
677 | I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2); | ||
678 | I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL); | ||
679 | } | ||
518 | 680 | ||
519 | /* VGA state */ | 681 | /* VGA state */ |
520 | I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); | 682 | if (IS_IGDNG(dev)) |
683 | I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); | ||
684 | else | ||
685 | I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); | ||
521 | I915_WRITE(VGA0, dev_priv->saveVGA0); | 686 | I915_WRITE(VGA0, dev_priv->saveVGA0); |
522 | I915_WRITE(VGA1, dev_priv->saveVGA1); | 687 | I915_WRITE(VGA1, dev_priv->saveVGA1); |
523 | I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); | 688 | I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); |
@@ -543,8 +708,17 @@ int i915_save_state(struct drm_device *dev) | |||
543 | i915_save_display(dev); | 708 | i915_save_display(dev); |
544 | 709 | ||
545 | /* Interrupt state */ | 710 | /* Interrupt state */ |
546 | dev_priv->saveIER = I915_READ(IER); | 711 | if (IS_IGDNG(dev)) { |
547 | dev_priv->saveIMR = I915_READ(IMR); | 712 | dev_priv->saveDEIER = I915_READ(DEIER); |
713 | dev_priv->saveDEIMR = I915_READ(DEIMR); | ||
714 | dev_priv->saveGTIER = I915_READ(GTIER); | ||
715 | dev_priv->saveGTIMR = I915_READ(GTIMR); | ||
716 | dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR); | ||
717 | dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR); | ||
718 | } else { | ||
719 | dev_priv->saveIER = I915_READ(IER); | ||
720 | dev_priv->saveIMR = I915_READ(IMR); | ||
721 | } | ||
548 | 722 | ||
549 | /* Clock gating state */ | 723 | /* Clock gating state */ |
550 | dev_priv->saveD_STATE = I915_READ(D_STATE); | 724 | dev_priv->saveD_STATE = I915_READ(D_STATE); |
@@ -609,8 +783,17 @@ int i915_restore_state(struct drm_device *dev) | |||
609 | i915_restore_display(dev); | 783 | i915_restore_display(dev); |
610 | 784 | ||
611 | /* Interrupt state */ | 785 | /* Interrupt state */ |
612 | I915_WRITE (IER, dev_priv->saveIER); | 786 | if (IS_IGDNG(dev)) { |
613 | I915_WRITE (IMR, dev_priv->saveIMR); | 787 | I915_WRITE(DEIER, dev_priv->saveDEIER); |
788 | I915_WRITE(DEIMR, dev_priv->saveDEIMR); | ||
789 | I915_WRITE(GTIER, dev_priv->saveGTIER); | ||
790 | I915_WRITE(GTIMR, dev_priv->saveGTIMR); | ||
791 | I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR); | ||
792 | I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR); | ||
793 | } else { | ||
794 | I915_WRITE (IER, dev_priv->saveIER); | ||
795 | I915_WRITE (IMR, dev_priv->saveIMR); | ||
796 | } | ||
614 | 797 | ||
615 | /* Clock gating state */ | 798 | /* Clock gating state */ |
616 | I915_WRITE (D_STATE, dev_priv->saveD_STATE); | 799 | I915_WRITE (D_STATE, dev_priv->saveD_STATE); |
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 4337414846b6..96cd256e60e6 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c | |||
@@ -351,20 +351,18 @@ parse_driver_features(struct drm_i915_private *dev_priv, | |||
351 | struct drm_device *dev = dev_priv->dev; | 351 | struct drm_device *dev = dev_priv->dev; |
352 | struct bdb_driver_features *driver; | 352 | struct bdb_driver_features *driver; |
353 | 353 | ||
354 | /* set default for chips without eDP */ | ||
355 | if (!SUPPORTS_EDP(dev)) { | ||
356 | dev_priv->edp_support = 0; | ||
357 | return; | ||
358 | } | ||
359 | |||
360 | driver = find_section(bdb, BDB_DRIVER_FEATURES); | 354 | driver = find_section(bdb, BDB_DRIVER_FEATURES); |
361 | if (!driver) | 355 | if (!driver) |
362 | return; | 356 | return; |
363 | 357 | ||
364 | if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP) | 358 | if (driver && SUPPORTS_EDP(dev) && |
359 | driver->lvds_config == BDB_DRIVER_FEATURE_EDP) { | ||
365 | dev_priv->edp_support = 1; | 360 | dev_priv->edp_support = 1; |
361 | } else { | ||
362 | dev_priv->edp_support = 0; | ||
363 | } | ||
366 | 364 | ||
367 | if (driver->dual_frequency) | 365 | if (driver && driver->dual_frequency) |
368 | dev_priv->render_reclock_avail = true; | 366 | dev_priv->render_reclock_avail = true; |
369 | } | 367 | } |
370 | 368 | ||
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3c14240cc002..3ba6546b7c7f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -943,6 +943,7 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |||
943 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | 943 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); |
944 | clock.p = (clock.p1 * clock.p2); | 944 | clock.p = (clock.p1 * clock.p2); |
945 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | 945 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; |
946 | clock.vco = 0; | ||
946 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | 947 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
947 | return true; | 948 | return true; |
948 | } | 949 | } |
@@ -1260,9 +1261,11 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, | |||
1260 | return ret; | 1261 | return ret; |
1261 | } | 1262 | } |
1262 | 1263 | ||
1263 | /* Pre-i965 needs to install a fence for tiled scan-out */ | 1264 | /* Install a fence for tiled scan-out. Pre-i965 always needs a fence, |
1264 | if (!IS_I965G(dev) && | 1265 | * whereas 965+ only requires a fence if using framebuffer compression. |
1265 | obj_priv->fence_reg == I915_FENCE_REG_NONE && | 1266 | * For simplicity, we always install a fence as the cost is not that onerous. |
1267 | */ | ||
1268 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE && | ||
1266 | obj_priv->tiling_mode != I915_TILING_NONE) { | 1269 | obj_priv->tiling_mode != I915_TILING_NONE) { |
1267 | ret = i915_gem_object_get_fence_reg(obj); | 1270 | ret = i915_gem_object_get_fence_reg(obj); |
1268 | if (ret != 0) { | 1271 | if (ret != 0) { |
@@ -1513,7 +1516,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
1513 | /* Enable panel fitting for LVDS */ | 1516 | /* Enable panel fitting for LVDS */ |
1514 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | 1517 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
1515 | temp = I915_READ(pf_ctl_reg); | 1518 | temp = I915_READ(pf_ctl_reg); |
1516 | I915_WRITE(pf_ctl_reg, temp | PF_ENABLE); | 1519 | I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3); |
1517 | 1520 | ||
1518 | /* currently full aspect */ | 1521 | /* currently full aspect */ |
1519 | I915_WRITE(pf_win_pos, 0); | 1522 | I915_WRITE(pf_win_pos, 0); |
@@ -1801,6 +1804,8 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
1801 | case DRM_MODE_DPMS_ON: | 1804 | case DRM_MODE_DPMS_ON: |
1802 | case DRM_MODE_DPMS_STANDBY: | 1805 | case DRM_MODE_DPMS_STANDBY: |
1803 | case DRM_MODE_DPMS_SUSPEND: | 1806 | case DRM_MODE_DPMS_SUSPEND: |
1807 | intel_update_watermarks(dev); | ||
1808 | |||
1804 | /* Enable the DPLL */ | 1809 | /* Enable the DPLL */ |
1805 | temp = I915_READ(dpll_reg); | 1810 | temp = I915_READ(dpll_reg); |
1806 | if ((temp & DPLL_VCO_ENABLE) == 0) { | 1811 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
@@ -1838,7 +1843,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
1838 | 1843 | ||
1839 | /* Give the overlay scaler a chance to enable if it's on this pipe */ | 1844 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
1840 | //intel_crtc_dpms_video(crtc, true); TODO | 1845 | //intel_crtc_dpms_video(crtc, true); TODO |
1841 | intel_update_watermarks(dev); | ||
1842 | break; | 1846 | break; |
1843 | case DRM_MODE_DPMS_OFF: | 1847 | case DRM_MODE_DPMS_OFF: |
1844 | intel_update_watermarks(dev); | 1848 | intel_update_watermarks(dev); |
@@ -2082,7 +2086,7 @@ fdi_reduce_ratio(u32 *num, u32 *den) | |||
2082 | #define LINK_N 0x80000 | 2086 | #define LINK_N 0x80000 |
2083 | 2087 | ||
2084 | static void | 2088 | static void |
2085 | igdng_compute_m_n(int bytes_per_pixel, int nlanes, | 2089 | igdng_compute_m_n(int bits_per_pixel, int nlanes, |
2086 | int pixel_clock, int link_clock, | 2090 | int pixel_clock, int link_clock, |
2087 | struct fdi_m_n *m_n) | 2091 | struct fdi_m_n *m_n) |
2088 | { | 2092 | { |
@@ -2092,7 +2096,8 @@ igdng_compute_m_n(int bytes_per_pixel, int nlanes, | |||
2092 | 2096 | ||
2093 | temp = (u64) DATA_N * pixel_clock; | 2097 | temp = (u64) DATA_N * pixel_clock; |
2094 | temp = div_u64(temp, link_clock); | 2098 | temp = div_u64(temp, link_clock); |
2095 | m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes); | 2099 | m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes); |
2100 | m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */ | ||
2096 | m_n->gmch_n = DATA_N; | 2101 | m_n->gmch_n = DATA_N; |
2097 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | 2102 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
2098 | 2103 | ||
@@ -2140,6 +2145,13 @@ static struct intel_watermark_params igd_cursor_hplloff_wm = { | |||
2140 | IGD_CURSOR_GUARD_WM, | 2145 | IGD_CURSOR_GUARD_WM, |
2141 | IGD_FIFO_LINE_SIZE | 2146 | IGD_FIFO_LINE_SIZE |
2142 | }; | 2147 | }; |
2148 | static struct intel_watermark_params g4x_wm_info = { | ||
2149 | G4X_FIFO_SIZE, | ||
2150 | G4X_MAX_WM, | ||
2151 | G4X_MAX_WM, | ||
2152 | 2, | ||
2153 | G4X_FIFO_LINE_SIZE, | ||
2154 | }; | ||
2143 | static struct intel_watermark_params i945_wm_info = { | 2155 | static struct intel_watermark_params i945_wm_info = { |
2144 | I945_FIFO_SIZE, | 2156 | I945_FIFO_SIZE, |
2145 | I915_MAX_WM, | 2157 | I915_MAX_WM, |
@@ -2430,17 +2442,74 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane) | |||
2430 | return size; | 2442 | return size; |
2431 | } | 2443 | } |
2432 | 2444 | ||
2433 | static void g4x_update_wm(struct drm_device *dev, int unused, int unused2, | 2445 | static void g4x_update_wm(struct drm_device *dev, int planea_clock, |
2434 | int unused3, int unused4) | 2446 | int planeb_clock, int sr_hdisplay, int pixel_size) |
2435 | { | 2447 | { |
2436 | struct drm_i915_private *dev_priv = dev->dev_private; | 2448 | struct drm_i915_private *dev_priv = dev->dev_private; |
2437 | u32 fw_blc_self = I915_READ(FW_BLC_SELF); | 2449 | int total_size, cacheline_size; |
2450 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr; | ||
2451 | struct intel_watermark_params planea_params, planeb_params; | ||
2452 | unsigned long line_time_us; | ||
2453 | int sr_clock, sr_entries = 0, entries_required; | ||
2438 | 2454 | ||
2439 | if (i915_powersave) | 2455 | /* Create copies of the base settings for each pipe */ |
2440 | fw_blc_self |= FW_BLC_SELF_EN; | 2456 | planea_params = planeb_params = g4x_wm_info; |
2441 | else | 2457 | |
2442 | fw_blc_self &= ~FW_BLC_SELF_EN; | 2458 | /* Grab a couple of global values before we overwrite them */ |
2443 | I915_WRITE(FW_BLC_SELF, fw_blc_self); | 2459 | total_size = planea_params.fifo_size; |
2460 | cacheline_size = planea_params.cacheline_size; | ||
2461 | |||
2462 | /* | ||
2463 | * Note: we need to make sure we don't overflow for various clock & | ||
2464 | * latency values. | ||
2465 | * clocks go from a few thousand to several hundred thousand. | ||
2466 | * latency is usually a few thousand | ||
2467 | */ | ||
2468 | entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) / | ||
2469 | 1000; | ||
2470 | entries_required /= G4X_FIFO_LINE_SIZE; | ||
2471 | planea_wm = entries_required + planea_params.guard_size; | ||
2472 | |||
2473 | entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) / | ||
2474 | 1000; | ||
2475 | entries_required /= G4X_FIFO_LINE_SIZE; | ||
2476 | planeb_wm = entries_required + planeb_params.guard_size; | ||
2477 | |||
2478 | cursora_wm = cursorb_wm = 16; | ||
2479 | cursor_sr = 32; | ||
2480 | |||
2481 | DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | ||
2482 | |||
2483 | /* Calc sr entries for one plane configs */ | ||
2484 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | ||
2485 | /* self-refresh has much higher latency */ | ||
2486 | const static int sr_latency_ns = 12000; | ||
2487 | |||
2488 | sr_clock = planea_clock ? planea_clock : planeb_clock; | ||
2489 | line_time_us = ((sr_hdisplay * 1000) / sr_clock); | ||
2490 | |||
2491 | /* Use ns/us then divide to preserve precision */ | ||
2492 | sr_entries = (((sr_latency_ns / line_time_us) + 1) * | ||
2493 | pixel_size * sr_hdisplay) / 1000; | ||
2494 | sr_entries = roundup(sr_entries / cacheline_size, 1); | ||
2495 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); | ||
2496 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | ||
2497 | } | ||
2498 | |||
2499 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", | ||
2500 | planea_wm, planeb_wm, sr_entries); | ||
2501 | |||
2502 | planea_wm &= 0x3f; | ||
2503 | planeb_wm &= 0x3f; | ||
2504 | |||
2505 | I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) | | ||
2506 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | ||
2507 | (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm); | ||
2508 | I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | ||
2509 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | ||
2510 | /* HPLL off in SR has some issues on G4x... disable it */ | ||
2511 | I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | ||
2512 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | ||
2444 | } | 2513 | } |
2445 | 2514 | ||
2446 | static void i965_update_wm(struct drm_device *dev, int unused, int unused2, | 2515 | static void i965_update_wm(struct drm_device *dev, int unused, int unused2, |
@@ -2586,6 +2655,9 @@ static void intel_update_watermarks(struct drm_device *dev) | |||
2586 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; | 2655 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; |
2587 | int enabled = 0, pixel_size = 0; | 2656 | int enabled = 0, pixel_size = 0; |
2588 | 2657 | ||
2658 | if (!dev_priv->display.update_wm) | ||
2659 | return; | ||
2660 | |||
2589 | /* Get the clock config from both planes */ | 2661 | /* Get the clock config from both planes */ |
2590 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | 2662 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2591 | intel_crtc = to_intel_crtc(crtc); | 2663 | intel_crtc = to_intel_crtc(crtc); |
@@ -2763,7 +2835,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, | |||
2763 | 2835 | ||
2764 | /* FDI link */ | 2836 | /* FDI link */ |
2765 | if (IS_IGDNG(dev)) { | 2837 | if (IS_IGDNG(dev)) { |
2766 | int lane, link_bw; | 2838 | int lane, link_bw, bpp; |
2767 | /* eDP doesn't require FDI link, so just set DP M/N | 2839 | /* eDP doesn't require FDI link, so just set DP M/N |
2768 | according to current link config */ | 2840 | according to current link config */ |
2769 | if (is_edp) { | 2841 | if (is_edp) { |
@@ -2782,10 +2854,72 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, | |||
2782 | lane = 4; | 2854 | lane = 4; |
2783 | link_bw = 270000; | 2855 | link_bw = 270000; |
2784 | } | 2856 | } |
2785 | igdng_compute_m_n(3, lane, target_clock, | 2857 | |
2858 | /* determine panel color depth */ | ||
2859 | temp = I915_READ(pipeconf_reg); | ||
2860 | |||
2861 | switch (temp & PIPE_BPC_MASK) { | ||
2862 | case PIPE_8BPC: | ||
2863 | bpp = 24; | ||
2864 | break; | ||
2865 | case PIPE_10BPC: | ||
2866 | bpp = 30; | ||
2867 | break; | ||
2868 | case PIPE_6BPC: | ||
2869 | bpp = 18; | ||
2870 | break; | ||
2871 | case PIPE_12BPC: | ||
2872 | bpp = 36; | ||
2873 | break; | ||
2874 | default: | ||
2875 | DRM_ERROR("unknown pipe bpc value\n"); | ||
2876 | bpp = 24; | ||
2877 | } | ||
2878 | |||
2879 | igdng_compute_m_n(bpp, lane, target_clock, | ||
2786 | link_bw, &m_n); | 2880 | link_bw, &m_n); |
2787 | } | 2881 | } |
2788 | 2882 | ||
2883 | /* Ironlake: try to setup display ref clock before DPLL | ||
2884 | * enabling. This is only under driver's control after | ||
2885 | * PCH B stepping, previous chipset stepping should be | ||
2886 | * ignoring this setting. | ||
2887 | */ | ||
2888 | if (IS_IGDNG(dev)) { | ||
2889 | temp = I915_READ(PCH_DREF_CONTROL); | ||
2890 | /* Always enable nonspread source */ | ||
2891 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | ||
2892 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | ||
2893 | I915_WRITE(PCH_DREF_CONTROL, temp); | ||
2894 | POSTING_READ(PCH_DREF_CONTROL); | ||
2895 | |||
2896 | temp &= ~DREF_SSC_SOURCE_MASK; | ||
2897 | temp |= DREF_SSC_SOURCE_ENABLE; | ||
2898 | I915_WRITE(PCH_DREF_CONTROL, temp); | ||
2899 | POSTING_READ(PCH_DREF_CONTROL); | ||
2900 | |||
2901 | udelay(200); | ||
2902 | |||
2903 | if (is_edp) { | ||
2904 | if (dev_priv->lvds_use_ssc) { | ||
2905 | temp |= DREF_SSC1_ENABLE; | ||
2906 | I915_WRITE(PCH_DREF_CONTROL, temp); | ||
2907 | POSTING_READ(PCH_DREF_CONTROL); | ||
2908 | |||
2909 | udelay(200); | ||
2910 | |||
2911 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | ||
2912 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | ||
2913 | I915_WRITE(PCH_DREF_CONTROL, temp); | ||
2914 | POSTING_READ(PCH_DREF_CONTROL); | ||
2915 | } else { | ||
2916 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | ||
2917 | I915_WRITE(PCH_DREF_CONTROL, temp); | ||
2918 | POSTING_READ(PCH_DREF_CONTROL); | ||
2919 | } | ||
2920 | } | ||
2921 | } | ||
2922 | |||
2789 | if (IS_IGD(dev)) { | 2923 | if (IS_IGD(dev)) { |
2790 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; | 2924 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
2791 | if (has_reduced_clock) | 2925 | if (has_reduced_clock) |
@@ -2936,6 +3070,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, | |||
2936 | 3070 | ||
2937 | lvds = I915_READ(lvds_reg); | 3071 | lvds = I915_READ(lvds_reg); |
2938 | lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; | 3072 | lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; |
3073 | /* set the corresponsding LVDS_BORDER bit */ | ||
3074 | lvds |= dev_priv->lvds_border_bits; | ||
2939 | /* Set the B0-B3 data pairs corresponding to whether we're going to | 3075 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
2940 | * set the DPLLs for dual-channel mode or not. | 3076 | * set the DPLLs for dual-channel mode or not. |
2941 | */ | 3077 | */ |
@@ -4124,7 +4260,9 @@ void intel_init_clock_gating(struct drm_device *dev) | |||
4124 | * Disable clock gating reported to work incorrectly according to the | 4260 | * Disable clock gating reported to work incorrectly according to the |
4125 | * specs, but enable as much else as we can. | 4261 | * specs, but enable as much else as we can. |
4126 | */ | 4262 | */ |
4127 | if (IS_G4X(dev)) { | 4263 | if (IS_IGDNG(dev)) { |
4264 | return; | ||
4265 | } else if (IS_G4X(dev)) { | ||
4128 | uint32_t dspclk_gate; | 4266 | uint32_t dspclk_gate; |
4129 | I915_WRITE(RENCLK_GATE_D1, 0); | 4267 | I915_WRITE(RENCLK_GATE_D1, 0); |
4130 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | 4268 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
@@ -4212,7 +4350,9 @@ static void intel_init_display(struct drm_device *dev) | |||
4212 | i830_get_display_clock_speed; | 4350 | i830_get_display_clock_speed; |
4213 | 4351 | ||
4214 | /* For FIFO watermark updates */ | 4352 | /* For FIFO watermark updates */ |
4215 | if (IS_G4X(dev)) | 4353 | if (IS_IGDNG(dev)) |
4354 | dev_priv->display.update_wm = NULL; | ||
4355 | else if (IS_G4X(dev)) | ||
4216 | dev_priv->display.update_wm = g4x_update_wm; | 4356 | dev_priv->display.update_wm = g4x_update_wm; |
4217 | else if (IS_I965G(dev)) | 4357 | else if (IS_I965G(dev)) |
4218 | dev_priv->display.update_wm = i965_update_wm; | 4358 | dev_priv->display.update_wm = i965_update_wm; |
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index f4856a510476..d83447557f9b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -400,7 +400,7 @@ intel_dp_i2c_init(struct intel_output *intel_output, const char *name) | |||
400 | { | 400 | { |
401 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; | 401 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
402 | 402 | ||
403 | DRM_ERROR("i2c_init %s\n", name); | 403 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
404 | dp_priv->algo.running = false; | 404 | dp_priv->algo.running = false; |
405 | dp_priv->algo.address = 0; | 405 | dp_priv->algo.address = 0; |
406 | dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch; | 406 | dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch; |
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 808bbe412ba8..05598ae10c4b 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c | |||
@@ -380,7 +380,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, | |||
380 | adjusted_mode->crtc_vblank_start + vsync_pos; | 380 | adjusted_mode->crtc_vblank_start + vsync_pos; |
381 | /* keep the vsync width constant */ | 381 | /* keep the vsync width constant */ |
382 | adjusted_mode->crtc_vsync_end = | 382 | adjusted_mode->crtc_vsync_end = |
383 | adjusted_mode->crtc_vblank_start + vsync_width; | 383 | adjusted_mode->crtc_vsync_start + vsync_width; |
384 | border = 1; | 384 | border = 1; |
385 | break; | 385 | break; |
386 | case DRM_MODE_SCALE_ASPECT: | 386 | case DRM_MODE_SCALE_ASPECT: |
@@ -526,6 +526,14 @@ out: | |||
526 | lvds_priv->pfit_control = pfit_control; | 526 | lvds_priv->pfit_control = pfit_control; |
527 | lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios; | 527 | lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios; |
528 | /* | 528 | /* |
529 | * When there exists the border, it means that the LVDS_BORDR | ||
530 | * should be enabled. | ||
531 | */ | ||
532 | if (border) | ||
533 | dev_priv->lvds_border_bits |= LVDS_BORDER_ENABLE; | ||
534 | else | ||
535 | dev_priv->lvds_border_bits &= ~(LVDS_BORDER_ENABLE); | ||
536 | /* | ||
529 | * XXX: It would be nice to support lower refresh rates on the | 537 | * XXX: It would be nice to support lower refresh rates on the |
530 | * panels to reduce power consumption, and perhaps match the | 538 | * panels to reduce power consumption, and perhaps match the |
531 | * user's requested refresh rate. | 539 | * user's requested refresh rate. |