diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/nouveau/core/core/engctx.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/include/core/engctx.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/include/engine/fifo.h | 1 |
11 files changed, 23 insertions, 2 deletions
diff --git a/drivers/gpu/drm/nouveau/core/core/engctx.c b/drivers/gpu/drm/nouveau/core/core/engctx.c index 38c0612a5122..ad4bbe106b0e 100644 --- a/drivers/gpu/drm/nouveau/core/core/engctx.c +++ b/drivers/gpu/drm/nouveau/core/core/engctx.c | |||
@@ -105,6 +105,7 @@ nouveau_engctx_create_(struct nouveau_object *parent, | |||
105 | if (client->vm) | 105 | if (client->vm) |
106 | atomic_inc(&client->vm->engref[nv_engidx(engobj)]); | 106 | atomic_inc(&client->vm->engref[nv_engidx(engobj)]); |
107 | list_add(&nv_engctx(engctx)->head, &engine->contexts); | 107 | list_add(&nv_engctx(engctx)->head, &engine->contexts); |
108 | nv_engctx(engctx)->addr = ~0ULL; | ||
108 | spin_unlock_irqrestore(&engine->lock, save); | 109 | spin_unlock_irqrestore(&engine->lock, save); |
109 | return 0; | 110 | return 0; |
110 | } | 111 | } |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c index 8b7513f4dc8f..7cd5d76dad29 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c | |||
@@ -102,6 +102,14 @@ nv04_fifo_object_detach(struct nouveau_object *parent, int cookie) | |||
102 | mutex_unlock(&nv_subdev(priv)->mutex); | 102 | mutex_unlock(&nv_subdev(priv)->mutex); |
103 | } | 103 | } |
104 | 104 | ||
105 | int | ||
106 | nv04_fifo_context_attach(struct nouveau_object *parent, | ||
107 | struct nouveau_object *object) | ||
108 | { | ||
109 | nv_engctx(object)->addr = nouveau_fifo_chan(parent)->chid; | ||
110 | return 0; | ||
111 | } | ||
112 | |||
105 | static int | 113 | static int |
106 | nv04_fifo_chan_ctor(struct nouveau_object *parent, | 114 | nv04_fifo_chan_ctor(struct nouveau_object *parent, |
107 | struct nouveau_object *engine, | 115 | struct nouveau_object *engine, |
@@ -127,6 +135,7 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent, | |||
127 | 135 | ||
128 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; | 136 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; |
129 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; | 137 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; |
138 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; | ||
130 | chan->ramfc = chan->base.chid * 32; | 139 | chan->ramfc = chan->base.chid * 32; |
131 | 140 | ||
132 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); | 141 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c index 391fefa7c472..5d3638bddb8b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c | |||
@@ -78,6 +78,7 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent, | |||
78 | 78 | ||
79 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; | 79 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; |
80 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; | 80 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; |
81 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; | ||
81 | chan->ramfc = chan->base.chid * 32; | 82 | chan->ramfc = chan->base.chid * 32; |
82 | 83 | ||
83 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); | 84 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c index 3b9d6c97f9ba..f223eb9c773c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c | |||
@@ -85,6 +85,7 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent, | |||
85 | 85 | ||
86 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; | 86 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; |
87 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; | 87 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; |
88 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; | ||
88 | chan->ramfc = chan->base.chid * 64; | 89 | chan->ramfc = chan->base.chid * 64; |
89 | 90 | ||
90 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); | 91 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c index 43d5c9eea865..ce97c5ee4658 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | |||
@@ -128,11 +128,12 @@ nv40_fifo_context_attach(struct nouveau_object *parent, | |||
128 | } | 128 | } |
129 | 129 | ||
130 | spin_lock_irqsave(&priv->base.lock, flags); | 130 | spin_lock_irqsave(&priv->base.lock, flags); |
131 | nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4; | ||
131 | nv_mask(priv, 0x002500, 0x00000001, 0x00000000); | 132 | nv_mask(priv, 0x002500, 0x00000001, 0x00000000); |
132 | 133 | ||
133 | if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) | 134 | if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) |
134 | nv_wr32(priv, reg, nv_gpuobj(engctx)->addr >> 4); | 135 | nv_wr32(priv, reg, nv_engctx(engctx)->addr); |
135 | nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_gpuobj(engctx)->addr >> 4); | 136 | nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr); |
136 | 137 | ||
137 | nv_mask(priv, 0x002500, 0x00000001, 0x00000001); | 138 | nv_mask(priv, 0x002500, 0x00000001, 0x00000001); |
138 | spin_unlock_irqrestore(&priv->base.lock, flags); | 139 | spin_unlock_irqrestore(&priv->base.lock, flags); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c index 5b80f3e10a6f..452f2241783a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | |||
@@ -81,6 +81,7 @@ nv50_fifo_context_attach(struct nouveau_object *parent, | |||
81 | return -EINVAL; | 81 | return -EINVAL; |
82 | } | 82 | } |
83 | 83 | ||
84 | nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; | ||
84 | nv_wo32(base->eng, addr + 0x00, 0x00190000); | 85 | nv_wo32(base->eng, addr + 0x00, 0x00190000); |
85 | nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); | 86 | nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); |
86 | nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); | 87 | nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c index 694a9bbaa02f..80c39270b589 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c | |||
@@ -62,6 +62,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent, | |||
62 | return -EINVAL; | 62 | return -EINVAL; |
63 | } | 63 | } |
64 | 64 | ||
65 | nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; | ||
65 | nv_wo32(base->eng, addr + 0x00, 0x00190000); | 66 | nv_wo32(base->eng, addr + 0x00, 0x00190000); |
66 | nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); | 67 | nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); |
67 | nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); | 68 | nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c index a4ae2bfd6035..d10dca237ca3 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | |||
@@ -112,6 +112,8 @@ nvc0_fifo_context_attach(struct nouveau_object *parent, | |||
112 | NV_MEM_ACCESS_RW, &ectx->vma); | 112 | NV_MEM_ACCESS_RW, &ectx->vma); |
113 | if (ret) | 113 | if (ret) |
114 | return ret; | 114 | return ret; |
115 | |||
116 | nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; | ||
115 | } | 117 | } |
116 | 118 | ||
117 | nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); | 119 | nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index c3f4955fef56..042afadbdf2e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | |||
@@ -147,6 +147,8 @@ nve0_fifo_context_attach(struct nouveau_object *parent, | |||
147 | NV_MEM_ACCESS_RW, &ectx->vma); | 147 | NV_MEM_ACCESS_RW, &ectx->vma); |
148 | if (ret) | 148 | if (ret) |
149 | return ret; | 149 | return ret; |
150 | |||
151 | nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; | ||
150 | } | 152 | } |
151 | 153 | ||
152 | nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); | 154 | nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); |
diff --git a/drivers/gpu/drm/nouveau/core/include/core/engctx.h b/drivers/gpu/drm/nouveau/core/include/core/engctx.h index 3bc6ccd6cbd8..227b2c190f1c 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/engctx.h +++ b/drivers/gpu/drm/nouveau/core/include/core/engctx.h | |||
@@ -13,6 +13,7 @@ struct nouveau_engctx { | |||
13 | struct nouveau_gpuobj base; | 13 | struct nouveau_gpuobj base; |
14 | struct nouveau_vma vma; | 14 | struct nouveau_vma vma; |
15 | struct list_head head; | 15 | struct list_head head; |
16 | u64 addr; | ||
16 | }; | 17 | }; |
17 | 18 | ||
18 | static inline struct nouveau_engctx * | 19 | static inline struct nouveau_engctx * |
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h index f2133872bd7c..d67fed1e3970 100644 --- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h | |||
@@ -106,5 +106,6 @@ extern struct nouveau_oclass nvc0_fifo_oclass; | |||
106 | extern struct nouveau_oclass nve0_fifo_oclass; | 106 | extern struct nouveau_oclass nve0_fifo_oclass; |
107 | 107 | ||
108 | void nv04_fifo_intr(struct nouveau_subdev *); | 108 | void nv04_fifo_intr(struct nouveau_subdev *); |
109 | int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *); | ||
109 | 110 | ||
110 | #endif | 111 | #endif |