4 files changed, 98 insertions, 51 deletions

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7ef3e8b6864d..02f96fd0d52d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -313,10 +313,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
                 if (encoder->hot_plug)
                         encoder->hot_plug(encoder);
 
+        mutex_unlock(&mode_config->mutex);
+
         /* Just fire off a uevent and let userspace tell us what to do */
         drm_helper_hpd_irq_event(dev);
-
-        mutex_unlock(&mode_config->mutex);
 }
 
 static void i915_handle_rps_change(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02db299f621a..a900809baf2a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2084,9 +2084,6 @@
 #define   DP_PIPEB_SELECT               (1 << 30)
 #define   DP_PIPE_MASK                  (1 << 30)
 
-#define DP_PIPE_ENABLED(V, P) \
-        (((V) & (DP_PIPE_MASK | DP_PORT_EN)) == ((P) << 30 | DP_PORT_EN))
-
 /* Link training mode - select a suitable mode for each stage */
 #define   DP_LINK_TRAIN_PAT_1           (0 << 28)
 #define   DP_LINK_TRAIN_PAT_2           (1 << 28)
@@ -3076,6 +3073,11 @@
 #define  TRANS_6BPC             (2<<5)
 #define  TRANS_12BPC            (3<<5)
 
+#define _TRANSA_CHICKEN2         0xf0064
+#define _TRANSB_CHICKEN2         0xf1064
+#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define   TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
+
 #define SOUTH_CHICKEN2          0xc2004
 #define  DPLS_EDP_PPS_FIX_DIS   (1<<0)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 97d28013db79..ce908ec02900 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -980,11 +980,29 @@ static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
              pipe_name(pipe));
 }
 
+static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
+                            int reg, u32 port_sel, u32 val)
+{
+        if ((val & DP_PORT_EN) == 0)
+                return false;
+
+        if (HAS_PCH_CPT(dev_priv->dev)) {
+                u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
+                u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
+                if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
+                        return false;
+        } else {
+                if ((val & DP_PIPE_MASK) != (pipe << 30))
+                        return false;
+        }
+        return true;
+}
+
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
-                                   enum pipe pipe, int reg)
+                                   enum pipe pipe, int reg, u32 port_sel)
 {
         u32 val = I915_READ(reg);
-        WARN(DP_PIPE_ENABLED(val, pipe),
+        WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
              reg, pipe_name(pipe));
 }
@@ -1004,9 +1022,9 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
         int reg;
         u32 val;
 
-        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
-        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
-        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
+        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
+        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
+        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
 
         reg = PCH_ADPA;
         val = I915_READ(reg);
@@ -1276,6 +1294,17 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
         intel_wait_for_pipe_off(dev_priv->dev, pipe);
 }
 
+/*
+ * Plane regs are double buffered, going from enabled->disabled needs a
+ * trigger in order to latch.  The display address reg provides this.
+ */
+static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
+                                      enum plane plane)
+{
+        I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
+        I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
+}
+
 /**
  * intel_enable_plane - enable a display plane on a given pipe
  * @dev_priv: i915 private structure
@@ -1299,20 +1328,10 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv,
                 return;
 
         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
+        intel_flush_display_plane(dev_priv, plane);
         intel_wait_for_vblank(dev_priv->dev, pipe);
 }
 
-/*
- * Plane regs are double buffered, going from enabled->disabled needs a
- * trigger in order to latch.  The display address reg provides this.
- */
-static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
-                                      enum plane plane)
-{
-        u32 reg = DSPADDR(plane);
-        I915_WRITE(reg, I915_READ(reg));
-}
-
 /**
  * intel_disable_plane - disable a display plane
  * @dev_priv: i915 private structure
@@ -1338,19 +1357,24 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv,
 }
 
 static void disable_pch_dp(struct drm_i915_private *dev_priv,
-                           enum pipe pipe, int reg)
+                           enum pipe pipe, int reg, u32 port_sel)
 {
         u32 val = I915_READ(reg);
-        if (DP_PIPE_ENABLED(val, pipe))
+        if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
+                DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
                 I915_WRITE(reg, val & ~DP_PORT_EN);
+        }
 }
 
 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
                              enum pipe pipe, int reg)
 {
         u32 val = I915_READ(reg);
-        if (HDMI_PIPE_ENABLED(val, pipe))
+        if (HDMI_PIPE_ENABLED(val, pipe)) {
+                DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
+                              reg, pipe);
                 I915_WRITE(reg, val & ~PORT_ENABLE);
+        }
 }
 
 /* Disable any ports connected to this transcoder */
@@ -1362,9 +1386,9 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
         val = I915_READ(PCH_PP_CONTROL);