diff options
Diffstat (limited to 'drivers/gpu')
42 files changed, 3533 insertions, 1526 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 5fae1e074b4b..013d38059943 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile | |||
@@ -13,7 +13,8 @@ radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \ | |||
13 | radeon_encoders.o radeon_display.o radeon_cursor.o radeon_i2c.o \ | 13 | radeon_encoders.o radeon_display.o radeon_cursor.o radeon_i2c.o \ |
14 | radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \ | 14 | radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \ |
15 | radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ | 15 | radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ |
16 | rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o | 16 | rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \ |
17 | radeon_test.o | ||
17 | 18 | ||
18 | radeon-$(CONFIG_COMPAT) += radeon_ioc32.o | 19 | radeon-$(CONFIG_COMPAT) += radeon_ioc32.o |
19 | 20 | ||
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index c0080cc9bf8d..74d034f77c6b 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -31,6 +31,132 @@ | |||
31 | #include "atom.h" | 31 | #include "atom.h" |
32 | #include "atom-bits.h" | 32 | #include "atom-bits.h" |
33 | 33 | ||
34 | static void atombios_overscan_setup(struct drm_crtc *crtc, | ||
35 | struct drm_display_mode *mode, | ||
36 | struct drm_display_mode *adjusted_mode) | ||
37 | { | ||
38 | struct drm_device *dev = crtc->dev; | ||
39 | struct radeon_device *rdev = dev->dev_private; | ||
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
41 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; | ||
42 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); | ||
43 | int a1, a2; | ||
44 | |||
45 | memset(&args, 0, sizeof(args)); | ||
46 | |||
47 | args.usOverscanRight = 0; | ||
48 | args.usOverscanLeft = 0; | ||
49 | args.usOverscanBottom = 0; | ||
50 | args.usOverscanTop = 0; | ||
51 | args.ucCRTC = radeon_crtc->crtc_id; | ||
52 | |||
53 | switch (radeon_crtc->rmx_type) { | ||
54 | case RMX_CENTER: | ||
55 | args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; | ||
56 | args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; | ||
57 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; | ||
58 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; | ||
59 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | ||
60 | break; | ||
61 | case RMX_ASPECT: | ||
62 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; | ||
63 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; | ||
64 | |||
65 | if (a1 > a2) { | ||
66 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; | ||
67 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; | ||
68 | } else if (a2 > a1) { | ||
69 | args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; | ||
70 | args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; | ||
71 | } | ||
72 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | ||
73 | break; | ||
74 | case RMX_FULL: | ||
75 | default: | ||
76 | args.usOverscanRight = 0; | ||
77 | args.usOverscanLeft = 0; | ||
78 | args.usOverscanBottom = 0; | ||
79 | args.usOverscanTop = 0; | ||
80 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | ||
81 | break; | ||
82 | } | ||
83 | } | ||
84 | |||
85 | static void atombios_scaler_setup(struct drm_crtc *crtc) | ||
86 | { | ||
87 | struct drm_device *dev = crtc->dev; | ||
88 | struct radeon_device *rdev = dev->dev_private; | ||
89 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
90 | ENABLE_SCALER_PS_ALLOCATION args; | ||
91 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); | ||
92 | /* fixme - fill in enc_priv for atom dac */ | ||
93 | enum radeon_tv_std tv_std = TV_STD_NTSC; | ||
94 | |||
95 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) | ||
96 | return; | ||
97 | |||
98 | memset(&args, 0, sizeof(args)); | ||
99 | |||
100 | args.ucScaler = radeon_crtc->crtc_id; | ||
101 | |||
102 | if (radeon_crtc->devices & (ATOM_DEVICE_TV_SUPPORT)) { | ||
103 | switch (tv_std) { | ||
104 | case TV_STD_NTSC: | ||
105 | default: | ||
106 | args.ucTVStandard = ATOM_TV_NTSC; | ||
107 | break; | ||
108 | case TV_STD_PAL: | ||
109 | args.ucTVStandard = ATOM_TV_PAL; | ||
110 | break; | ||
111 | case TV_STD_PAL_M: | ||
112 | args.ucTVStandard = ATOM_TV_PALM; | ||
113 | break; | ||
114 | case TV_STD_PAL_60: | ||
115 | args.ucTVStandard = ATOM_TV_PAL60; | ||
116 | break; | ||
117 | case TV_STD_NTSC_J: | ||
118 | args.ucTVStandard = ATOM_TV_NTSCJ; | ||
119 | break; | ||
120 | case TV_STD_SCART_PAL: | ||
121 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ | ||
122 | break; | ||
123 | case TV_STD_SECAM: | ||
124 | args.ucTVStandard = ATOM_TV_SECAM; | ||
125 | break; | ||
126 | case TV_STD_PAL_CN: | ||
127 | args.ucTVStandard = ATOM_TV_PALCN; | ||
128 | break; | ||
129 | } | ||
130 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; | ||
131 | } else if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT)) { | ||
132 | args.ucTVStandard = ATOM_TV_CV; | ||
133 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; | ||
134 | } else { | ||
135 | switch (radeon_crtc->rmx_type) { | ||
136 | case RMX_FULL: | ||
137 | args.ucEnable = ATOM_SCALER_EXPANSION; | ||
138 | break; | ||
139 | case RMX_CENTER: | ||
140 | args.ucEnable = ATOM_SCALER_CENTER; | ||
141 | break; | ||
142 | case RMX_ASPECT: | ||
143 | args.ucEnable = ATOM_SCALER_EXPANSION; | ||
144 | break; | ||
145 | default: | ||
146 | if (ASIC_IS_AVIVO(rdev)) | ||
147 | args.ucEnable = ATOM_SCALER_DISABLE; | ||
148 | else | ||
149 | args.ucEnable = ATOM_SCALER_CENTER; | ||
150 | break; | ||
151 | } | ||
152 | } | ||
153 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | ||
154 | if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT) | ||
155 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) { | ||
156 | atom_rv515_force_tv_scaler(rdev); | ||
157 | } | ||
158 | } | ||
159 | |||
34 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) | 160 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
35 | { | 161 | { |
36 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 162 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
@@ -203,6 +329,12 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) | |||
203 | if (ASIC_IS_AVIVO(rdev)) { | 329 | if (ASIC_IS_AVIVO(rdev)) { |
204 | uint32_t ss_cntl; | 330 | uint32_t ss_cntl; |
205 | 331 | ||
332 | if ((rdev->family == CHIP_RS600) || | ||
333 | (rdev->family == CHIP_RS690) || | ||
334 | (rdev->family == CHIP_RS740)) | ||
335 | pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV | | ||
336 | RADEON_PLL_PREFER_CLOSEST_LOWER); | ||
337 | |||
206 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ | 338 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
207 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; | 339 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
208 | else | 340 | else |
@@ -321,7 +453,7 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
321 | struct drm_gem_object *obj; | 453 | struct drm_gem_object *obj; |
322 | struct drm_radeon_gem_object *obj_priv; | 454 | struct drm_radeon_gem_object *obj_priv; |
323 | uint64_t fb_location; | 455 | uint64_t fb_location; |
324 | uint32_t fb_format, fb_pitch_pixels; | 456 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
325 | 457 | ||
326 | if (!crtc->fb) | 458 | if (!crtc->fb) |
327 | return -EINVAL; | 459 | return -EINVAL; |
@@ -358,7 +490,14 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
358 | return -EINVAL; | 490 | return -EINVAL; |
359 | } | 491 | } |
360 | 492 | ||
361 | /* TODO tiling */ | 493 | radeon_object_get_tiling_flags(obj->driver_private, |
494 | &tiling_flags, NULL); | ||
495 | if (tiling_flags & RADEON_TILING_MACRO) | ||
496 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; | ||
497 | |||
498 | if (tiling_flags & RADEON_TILING_MICRO) | ||
499 | fb_format |= AVIVO_D1GRPH_TILED; | ||
500 | |||
362 | if (radeon_crtc->crtc_id == 0) | 501 | if (radeon_crtc->crtc_id == 0) |
363 | WREG32(AVIVO_D1VGA_CONTROL, 0); | 502 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
364 | else | 503 | else |
@@ -509,6 +648,9 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, | |||
509 | radeon_crtc_set_base(crtc, x, y, old_fb); | 648 | radeon_crtc_set_base(crtc, x, y, old_fb); |
510 | radeon_legacy_atom_set_surface(crtc); | 649 | radeon_legacy_atom_set_surface(crtc); |
511 | } | 650 | } |
651 | atombios_overscan_setup(crtc, mode, adjusted_mode); | ||
652 | atombios_scaler_setup(crtc); | ||
653 | radeon_bandwidth_update(rdev); | ||
512 | return 0; | 654 | return 0; |
513 | } | 655 | } |
514 | 656 | ||
@@ -516,6 +658,8 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, | |||
516 | struct drm_display_mode *mode, | 658 | struct drm_display_mode *mode, |
517 | struct drm_display_mode *adjusted_mode) | 659 | struct drm_display_mode *adjusted_mode) |
518 | { | 660 | { |
661 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) | ||
662 | return false; | ||
519 | return true; | 663 | return true; |
520 | } | 664 | } |
521 | 665 | ||
@@ -548,148 +692,3 @@ void radeon_atombios_init_crtc(struct drm_device *dev, | |||
548 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; | 692 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
549 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); | 693 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
550 | } | 694 | } |
551 | |||
552 | void radeon_init_disp_bw_avivo(struct drm_device *dev, | ||
553 | struct drm_display_mode *mode1, | ||
554 | uint32_t pixel_bytes1, | ||
555 | struct drm_display_mode *mode2, | ||
556 | uint32_t pixel_bytes2) | ||
557 | { | ||
558 | struct radeon_device *rdev = dev->dev_private; | ||
559 | fixed20_12 min_mem_eff; | ||
560 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; | ||
561 | fixed20_12 sclk_ff, mclk_ff; | ||
562 | uint32_t dc_lb_memory_split, temp; | ||
563 | |||
564 | min_mem_eff.full = rfixed_const_8(0); | ||
565 | if (rdev->disp_priority == 2) { | ||
566 | uint32_t mc_init_misc_lat_timer = 0; | ||
567 | if (rdev->family == CHIP_RV515) | ||
568 | mc_init_misc_lat_timer = | ||
569 | RREG32_MC(RV515_MC_INIT_MISC_LAT_TIMER); | ||
570 | else if (rdev->family == CHIP_RS690) | ||
571 | mc_init_misc_lat_timer = | ||
572 | RREG32_MC(RS690_MC_INIT_MISC_LAT_TIMER); | ||
573 | |||
574 | mc_init_misc_lat_timer &= | ||
575 | ~(R300_MC_DISP1R_INIT_LAT_MASK << | ||
576 | R300_MC_DISP1R_INIT_LAT_SHIFT); | ||
577 | mc_init_misc_lat_timer &= | ||
578 | ~(R300_MC_DISP0R_INIT_LAT_MASK << | ||
579 | R300_MC_DISP0R_INIT_LAT_SHIFT); | ||
580 | |||
581 | if (mode2) | ||
582 | mc_init_misc_lat_timer |= | ||
583 | (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); | ||
584 | if (mode1) | ||
585 | mc_init_misc_lat_timer |= | ||
586 | (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); | ||
587 | |||
588 | if (rdev->family == CHIP_RV515) | ||
589 | WREG32_MC(RV515_MC_INIT_MISC_LAT_TIMER, | ||
590 | mc_init_misc_lat_timer); | ||
591 | else if (rdev->family == CHIP_RS690) | ||
592 | WREG32_MC(RS690_MC_INIT_MISC_LAT_TIMER, | ||
593 | mc_init_misc_lat_timer); | ||
594 | } | ||
595 | |||
596 | /* | ||
597 | * determine is there is enough bw for current mode | ||
598 | */ | ||
599 | temp_ff.full = rfixed_const(100); | ||
600 | mclk_ff.full = rfixed_const(rdev->clock.default_mclk); | ||
601 | mclk_ff.full = rfixed_div(mclk_ff, temp_ff); | ||
602 | sclk_ff.full = rfixed_const(rdev->clock.default_sclk); | ||
603 | sclk_ff.full = rfixed_div(sclk_ff, temp_ff); | ||
604 | |||
605 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); | ||
606 | temp_ff.full = rfixed_const(temp); | ||
607 | mem_bw.full = rfixed_mul(mclk_ff, temp_ff); | ||
608 | mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); | ||
609 | |||
610 | pix_clk.full = 0; | ||
611 | pix_clk2.full = 0; | ||
612 | peak_disp_bw.full = 0; | ||
613 | if (mode1) { | ||
614 | temp_ff.full = rfixed_const(1000); | ||
615 | pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ | ||
616 | pix_clk.full = rfixed_div(pix_clk, temp_ff); | ||
617 | temp_ff.full = rfixed_const(pixel_bytes1); | ||
618 | peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); | ||
619 | } | ||
620 | if (mode2) { | ||
621 | temp_ff.full = rfixed_const(1000); | ||
622 | pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ | ||
623 | pix_clk2.full = rfixed_div(pix_clk2, temp_ff); | ||
624 | temp_ff.full = rfixed_const(pixel_bytes2); | ||
625 | peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); | ||
626 | } | ||
627 | |||
628 | if (peak_disp_bw.full >= mem_bw.full) { | ||
629 | DRM_ERROR | ||
630 | ("You may not have enough display bandwidth for current mode\n" | ||
631 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); | ||
632 | printk("peak disp bw %d, mem_bw %d\n", | ||
633 | rfixed_trunc(peak_disp_bw), rfixed_trunc(mem_bw)); | ||
634 | } | ||
635 | |||
636 | /* | ||
637 | * Line Buffer Setup | ||
638 | * There is a single line buffer shared by both display controllers. | ||
639 | * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between the display | ||
640 | * controllers. The paritioning can either be done manually or via one of four | ||
641 | * preset allocations specified in bits 1:0: | ||
642 | * 0 - line buffer is divided in half and shared between each display controller | ||
643 | * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 | ||
644 | * 2 - D1 gets the whole buffer | ||
645 | * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 | ||
646 | * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual allocation mode. | ||
647 | * In manual allocation mode, D1 always starts at 0, D1 end/2 is specified in bits | ||
648 | * 14:4; D2 allocation follows D1. | ||
649 | */ | ||
650 | |||
651 | /* is auto or manual better ? */ | ||
652 | dc_lb_memory_split = | ||
653 | RREG32(AVIVO_DC_LB_MEMORY_SPLIT) & ~AVIVO_DC_LB_MEMORY_SPLIT_MASK; | ||
654 | dc_lb_memory_split &= ~AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE; | ||
655 | #if 1 | ||
656 | /* auto */ | ||
657 | if (mode1 && mode2) { | ||
658 | if (mode1->hdisplay > mode2->hdisplay) { | ||
659 | if (mode1->hdisplay > 2560) | ||
660 | dc_lb_memory_split |= | ||
661 | AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; | ||
662 | else | ||
663 | dc_lb_memory_split |= | ||
664 | AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; | ||
665 | } else if (mode2->hdisplay > mode1->hdisplay) { | ||
666 | if (mode2->hdisplay > 2560) | ||
667 | dc_lb_memory_split |= | ||
668 | AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; | ||
669 | else | ||
670 | dc_lb_memory_split |= | ||
671 | AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; | ||
672 | } else | ||
673 | dc_lb_memory_split |= | ||
674 | AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; | ||
675 | } else if (mode1) { | ||
676 | dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY; | ||
677 | } else if (mode2) { | ||
678 | dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; | ||
679 | } | ||
680 | #else | ||
681 | /* manual */ | ||
682 | dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE; | ||
683 | dc_lb_memory_split &= | ||
684 | ~(AVIVO_DC_LB_DISP1_END_ADR_MASK << | ||
685 | AVIVO_DC_LB_DISP1_END_ADR_SHIFT); | ||
686 | if (mode1) { | ||
687 | dc_lb_memory_split |= | ||
688 | ((((mode1->hdisplay / 2) + 64) & AVIVO_DC_LB_DISP1_END_ADR_MASK) | ||
689 | << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); | ||
690 | } else if (mode2) { | ||
691 | dc_lb_memory_split |= (0 << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); | ||
692 | } | ||
693 | #endif | ||
694 | WREG32(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split); | ||
695 | } | ||
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index c550932a108f..05a44896dffb 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -110,7 +110,7 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |||
110 | if (i < 0 || i > rdev->gart.num_gpu_pages) { | 110 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
111 | return -EINVAL; | 111 | return -EINVAL; |
112 | } | 112 | } |
113 | rdev->gart.table.ram.ptr[i] = cpu_to_le32((uint32_t)addr); | 113 | rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr)); |
114 | return 0; | 114 | return 0; |
115 | } | 115 | } |
116 | 116 | ||
@@ -173,8 +173,12 @@ void r100_mc_setup(struct radeon_device *rdev) | |||
173 | DRM_ERROR("Failed to register debugfs file for R100 MC !\n"); | 173 | DRM_ERROR("Failed to register debugfs file for R100 MC !\n"); |
174 | } | 174 | } |
175 | /* Write VRAM size in case we are limiting it */ | 175 | /* Write VRAM size in case we are limiting it */ |
176 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); | 176 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
177 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; | 177 | /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM, |
178 | * if the aperture is 64MB but we have 32MB VRAM | ||
179 | * we report only 32MB VRAM but we have to set MC_FB_LOCATION | ||
180 | * to 64MB, otherwise the gpu accidentially dies */ | ||
181 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; | ||
178 | tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16); | 182 | tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16); |
179 | tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16); | 183 | tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16); |
180 | WREG32(RADEON_MC_FB_LOCATION, tmp); | 184 | WREG32(RADEON_MC_FB_LOCATION, tmp); |
@@ -215,7 +219,6 @@ int r100_mc_init(struct radeon_device *rdev) | |||
215 | r100_pci_gart_disable(rdev); | 219 | r100_pci_gart_disable(rdev); |
216 | 220 | ||
217 | /* Setup GPU memory space */ | 221 | /* Setup GPU memory space */ |
218 | rdev->mc.vram_location = 0xFFFFFFFFUL; | ||
219 | rdev->mc.gtt_location = 0xFFFFFFFFUL; | 222 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
220 | if (rdev->flags & RADEON_IS_AGP) { | 223 | if (rdev->flags & RADEON_IS_AGP) { |
221 | r = radeon_agp_init(rdev); | 224 | r = radeon_agp_init(rdev); |
@@ -753,6 +756,102 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p, | |||
753 | } | 756 | } |
754 | 757 | ||
755 | /** | 758 | /** |
759 | * r100_cs_packet_next_vline() - parse userspace VLINE packet | ||
760 | * @parser: parser structure holding parsing context. | ||
761 | * | ||
762 | * Userspace sends a special sequence for VLINE waits. | ||
763 | * PACKET0 - VLINE_START_END + value | ||
764 | * PACKET0 - WAIT_UNTIL +_value | ||
765 | * RELOC (P3) - crtc_id in reloc. | ||
766 | * | ||
767 | * This function parses this and relocates the VLINE START END | ||
768 | * and WAIT UNTIL packets to the correct crtc. | ||
769 | * It also detects a switched off crtc and nulls out the | ||
770 | * wait in that case. | ||
771 | */ | ||
772 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) | ||
773 | { | ||
774 | struct radeon_cs_chunk *ib_chunk; | ||
775 | struct drm_mode_object *obj; | ||
776 | struct drm_crtc *crtc; | ||
777 | struct radeon_crtc *radeon_crtc; | ||
778 | struct radeon_cs_packet p3reloc, waitreloc; | ||
779 | int crtc_id; | ||
780 | int r; | ||
781 | uint32_t header, h_idx, reg; | ||
782 | |||
783 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
784 | |||
785 | /* parse the wait until */ | ||
786 | r = r100_cs_packet_parse(p, &waitreloc, p->idx); | ||
787 | if (r) | ||
788 | return r; | ||
789 | |||
790 | /* check its a wait until and only 1 count */ | ||
791 | if (waitreloc.reg != RADEON_WAIT_UNTIL || | ||
792 | waitreloc.count != 0) { | ||
793 | DRM_ERROR("vline wait had illegal wait until segment\n"); | ||
794 | r = -EINVAL; | ||
795 | return r; | ||
796 | } | ||
797 | |||
798 | if (ib_chunk->kdata[waitreloc.idx + 1] != RADEON_WAIT_CRTC_VLINE) { | ||
799 | DRM_ERROR("vline wait had illegal wait until\n"); | ||
800 | r = -EINVAL; | ||
801 | return r; | ||
802 | } | ||
803 | |||
804 | /* jump over the NOP */ | ||
805 | r = r100_cs_packet_parse(p, &p3reloc, p->idx); | ||
806 | if (r) | ||
807 | return r; | ||
808 | |||
809 | h_idx = p->idx - 2; | ||
810 | p->idx += waitreloc.count; | ||
811 | p->idx += p3reloc.count; | ||
812 | |||
813 | header = ib_chunk->kdata[h_idx]; | ||
814 | crtc_id = ib_chunk->kdata[h_idx + 5]; | ||
815 | reg = ib_chunk->kdata[h_idx] >> 2; | ||
816 | mutex_lock(&p->rdev->ddev->mode_config.mutex); | ||
817 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); | ||
818 | if (!obj) { | ||
819 | DRM_ERROR("cannot find crtc %d\n", crtc_id); | ||
820 | r = -EINVAL; | ||
821 | goto out; | ||
822 | } | ||
823 | crtc = obj_to_crtc(obj); | ||
824 | radeon_crtc = to_radeon_crtc(crtc); | ||
825 | crtc_id = radeon_crtc->crtc_id; | ||
826 | |||
827 | if (!crtc->enabled) { | ||
828 | /* if the CRTC isn't enabled - we need to nop out the wait until */ | ||
829 | ib_chunk->kdata[h_idx + 2] = PACKET2(0); | ||
830 | ib_chunk->kdata[h_idx + 3] = PACKET2(0); | ||
831 | } else if (crtc_id == 1) { | ||
832 | switch (reg) { | ||
833 | case AVIVO_D1MODE_VLINE_START_END: | ||
834 | header &= R300_CP_PACKET0_REG_MASK; | ||
835 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; | ||
836 | break; | ||
837 | case RADEON_CRTC_GUI_TRIG_VLINE: | ||
838 | header &= R300_CP_PACKET0_REG_MASK; | ||
839 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; | ||
840 | break; | ||
841 | default: | ||
842 | DRM_ERROR("unknown crtc reloc\n"); | ||
843 | r = -EINVAL; | ||
844 | goto out; | ||
845 | } | ||
846 | ib_chunk->kdata[h_idx] = header; | ||
847 | ib_chunk->kdata[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; | ||
848 | } | ||
849 | out: | ||
850 | mutex_unlock(&p->rdev->ddev->mode_config.mutex); | ||
851 | return r; | ||
852 | } | ||
853 | |||
854 | /** | ||
756 | * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 | 855 | * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 |
757 | * @parser: parser structure holding parsing context. | 856 | * @parser: parser structure holding parsing context. |
758 | * @data: pointer to relocation data | 857 | * @data: pointer to relocation data |
@@ -814,6 +913,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
814 | unsigned idx; | 913 | unsigned idx; |
815 | bool onereg; | 914 | bool onereg; |
816 | int r; | 915 | int r; |
916 | u32 tile_flags = 0; | ||
817 | 917 | ||
818 | ib = p->ib->ptr; | 918 | ib = p->ib->ptr; |
819 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | 919 | ib_chunk = &p->chunks[p->chunk_ib_idx]; |
@@ -825,6 +925,15 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
825 | } | 925 | } |
826 | for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { | 926 | for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { |
827 | switch (reg) { | 927 | switch (reg) { |
928 | case RADEON_CRTC_GUI_TRIG_VLINE: | ||
929 | r = r100_cs_packet_parse_vline(p); | ||
930 | if (r) { | ||
931 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | ||
932 | idx, reg); | ||
933 | r100_cs_dump_packet(p, pkt); | ||
934 | return r; | ||
935 | } | ||
936 | break; | ||
828 | /* FIXME: only allow PACKET3 blit? easier to check for out of | 937 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
829 | * range access */ | 938 | * range access */ |
830 | case RADEON_DST_PITCH_OFFSET: | 939 | case RADEON_DST_PITCH_OFFSET: |
@@ -838,7 +947,20 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
838 | } | 947 | } |
839 | tmp = ib_chunk->kdata[idx] & 0x003fffff; | 948 | tmp = ib_chunk->kdata[idx] & 0x003fffff; |
840 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); | 949 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); |
841 | ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) | tmp; | 950 | |
951 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | ||
952 | tile_flags |= RADEON_DST_TILE_MACRO; | ||
953 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { | ||
954 | if (reg == RADEON_SRC_PITCH_OFFSET) { | ||
955 | DRM_ERROR("Cannot src blit from microtiled surface\n"); | ||
956 | r100_cs_dump_packet(p, pkt); | ||
957 | return -EINVAL; | ||
958 | } | ||
959 | tile_flags |= RADEON_DST_TILE_MICRO; | ||
960 | } | ||
961 | |||
962 | tmp |= tile_flags; | ||
963 | ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; | ||
842 | break; | 964 | break; |
843 | case RADEON_RB3D_DEPTHOFFSET: | 965 | case RADEON_RB3D_DEPTHOFFSET: |
844 | case RADEON_RB3D_COLOROFFSET: | 966 | case RADEON_RB3D_COLOROFFSET: |
@@ -869,6 +991,11 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
869 | case R300_TX_OFFSET_0+52: | 991 | case R300_TX_OFFSET_0+52: |
870 | case R300_TX_OFFSET_0+56: | 992 | case R300_TX_OFFSET_0+56: |
871 | case R300_TX_OFFSET_0+60: | 993 | case R300_TX_OFFSET_0+60: |
994 | /* rn50 has no 3D engine so fail on any 3d setup */ | ||
995 | if (ASIC_IS_RN50(p->rdev)) { | ||
996 | DRM_ERROR("attempt to use RN50 3D engine failed\n"); | ||
997 | return -EINVAL; | ||
998 | } | ||
872 | r = r100_cs_packet_next_reloc(p, &reloc); | 999 | r = r100_cs_packet_next_reloc(p, &reloc); |
873 | if (r) { | 1000 | if (r) { |
874 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | 1001 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
@@ -878,6 +1005,25 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
878 | } | 1005 | } |
879 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 1006 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
880 | break; | 1007 | break; |
1008 | case R300_RB3D_COLORPITCH0: | ||
1009 | case RADEON_RB3D_COLORPITCH: | ||
1010 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
1011 | if (r) { | ||
1012 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | ||
1013 | idx, reg); | ||
1014 | r100_cs_dump_packet(p, pkt); | ||
1015 | return r; | ||
1016 | } | ||
1017 | |||
1018 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | ||
1019 | tile_flags |= RADEON_COLOR_TILE_ENABLE; | ||
1020 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | ||
1021 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; | ||
1022 | |||
1023 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); | ||
1024 | tmp |= tile_flags; | ||
1025 | ib[idx] = tmp; | ||
1026 | break; | ||
881 | default: | 1027 | default: |
882 | /* FIXME: we don't want to allow anyothers packet */ | 1028 | /* FIXME: we don't want to allow anyothers packet */ |
883 | break; | 1029 | break; |
@@ -1256,29 +1402,100 @@ static void r100_vram_get_type(struct radeon_device *rdev) | |||
1256 | } | 1402 | } |
1257 | } | 1403 | } |
1258 | 1404 | ||
1259 | void r100_vram_info(struct radeon_device *rdev) | 1405 | static u32 r100_get_accessible_vram(struct radeon_device *rdev) |
1260 | { | 1406 | { |
1261 | r100_vram_get_type(rdev); | 1407 | u32 aper_size; |
1408 | u8 byte; | ||
1409 | |||
1410 | aper_size = RREG32(RADEON_CONFIG_APER_SIZE); | ||
1411 | |||
1412 | /* Set HDP_APER_CNTL only on cards that are known not to be broken, | ||
1413 | * that is has the 2nd generation multifunction PCI interface | ||
1414 | */ | ||
1415 | if (rdev->family == CHIP_RV280 || | ||
1416 | rdev->family >= CHIP_RV350) { | ||
1417 | WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, | ||
1418 | ~RADEON_HDP_APER_CNTL); | ||
1419 | DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); | ||
1420 | return aper_size * 2; | ||
1421 | } | ||
1422 | |||
1423 | /* Older cards have all sorts of funny issues to deal with. First | ||
1424 | * check if it's a multifunction card by reading the PCI config | ||
1425 | * header type... Limit those to one aperture size | ||
1426 | */ | ||
1427 | pci_read_config_byte(rdev->pdev, 0xe, &byte); | ||
1428 | if (byte & 0x80) { | ||
1429 | DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); | ||
1430 | DRM_INFO("Limiting VRAM to one aperture\n"); | ||
1431 | return aper_size; | ||
1432 | } | ||
1433 | |||
1434 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS | ||
1435 | * have set it up. We don't write this as it's broken on some ASICs but | ||
1436 | * we expect the BIOS to have done the right thing (might be too optimistic...) | ||
1437 | */ | ||
1438 | if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) | ||
1439 | return aper_size * 2; | ||
1440 | return aper_size; | ||
1441 | } | ||
1442 | |||
1443 | void r100_vram_init_sizes(struct radeon_device *rdev) | ||
1444 | { | ||
1445 | u64 config_aper_size; | ||
1446 | u32 accessible; | ||
1447 | |||
1448 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); | ||
1262 | 1449 | ||
1263 | if (rdev->flags & RADEON_IS_IGP) { | 1450 | if (rdev->flags & RADEON_IS_IGP) { |
1264 | uint32_t tom; | 1451 | uint32_t tom; |
1265 | /* read NB_TOM to get the amount of ram stolen for the GPU */ | 1452 | /* read NB_TOM to get the amount of ram stolen for the GPU */ |
1266 | tom = RREG32(RADEON_NB_TOM); | 1453 | tom = RREG32(RADEON_NB_TOM); |
1267 | rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); | 1454 | rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); |
1268 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); | 1455 | /* for IGPs we need to keep VRAM where it was put by the BIOS */ |
1456 | rdev->mc.vram_location = (tom & 0xffff) << 16; | ||
1457 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | ||
1458 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | ||
1269 | } else { | 1459 | } else { |
1270 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); | 1460 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
1271 | /* Some production boards of m6 will report 0 | 1461 | /* Some production boards of m6 will report 0 |
1272 | * if it's 8 MB | 1462 | * if it's 8 MB |
1273 | */ | 1463 | */ |
1274 | if (rdev->mc.vram_size == 0) { | 1464 | if (rdev->mc.real_vram_size == 0) { |
1275 | rdev->mc.vram_size = 8192 * 1024; | 1465 | rdev->mc.real_vram_size = 8192 * 1024; |
1276 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); | 1466 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
1277 | } | 1467 | } |
1468 | /* let driver place VRAM */ | ||
1469 | rdev->mc.vram_location = 0xFFFFFFFFUL; | ||
1470 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - | ||
1471 | * Novell bug 204882 + along with lots of ubuntu ones */ | ||
1472 | if (config_aper_size > rdev->mc.real_vram_size) | ||
1473 | rdev->mc.mc_vram_size = config_aper_size; | ||
1474 | else | ||
1475 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | ||
1278 | } | 1476 | } |
1279 | 1477 | ||
1478 | /* work out accessible VRAM */ | ||
1479 | accessible = r100_get_accessible_vram(rdev); | ||
1480 | |||
1280 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | 1481 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
1281 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | 1482 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
1483 | |||
1484 | if (accessible > rdev->mc.aper_size) | ||
1485 | accessible = rdev->mc.aper_size; | ||
1486 | |||
1487 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) | ||
1488 | rdev->mc.mc_vram_size = rdev->mc.aper_size; | ||
1489 | |||
1490 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) | ||
1491 | rdev->mc.real_vram_size = rdev->mc.aper_size; | ||
1492 | } | ||
1493 | |||
1494 | void r100_vram_info(struct radeon_device *rdev) | ||
1495 | { | ||
1496 | r100_vram_get_type(rdev); | ||
1497 | |||
1498 | r100_vram_init_sizes(rdev); | ||
1282 | } | 1499 | } |
1283 | 1500 | ||
1284 | 1501 | ||
@@ -1533,3 +1750,530 @@ int r100_debugfs_mc_info_init(struct radeon_device *rdev) | |||
1533 | return 0; | 1750 | return 0; |
1534 | #endif | 1751 | #endif |
1535 | } | 1752 | } |
1753 | |||
1754 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, | ||
1755 | uint32_t tiling_flags, uint32_t pitch, | ||
1756 | uint32_t offset, uint32_t obj_size) | ||
1757 | { | ||
1758 | int surf_index = reg * 16; | ||
1759 | int flags = 0; | ||
1760 | |||
1761 | /* r100/r200 divide by 16 */ | ||
1762 | if (rdev->family < CHIP_R300) | ||
1763 | flags = pitch / 16; | ||
1764 | else | ||
1765 | flags = pitch / 8; | ||
1766 | |||
1767 | if (rdev->family <= CHIP_RS200) { | ||
1768 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | ||
1769 | == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | ||
1770 | flags |= RADEON_SURF_TILE_COLOR_BOTH; | ||
1771 | if (tiling_flags & RADEON_TILING_MACRO) | ||
1772 | flags |= RADEON_SURF_TILE_COLOR_MACRO; | ||
1773 | } else if (rdev->family <= CHIP_RV280) { | ||
1774 | if (tiling_flags & (RADEON_TILING_MACRO)) | ||
1775 | flags |= R200_SURF_TILE_COLOR_MACRO; | ||
1776 | if (tiling_flags & RADEON_TILING_MICRO) | ||
1777 | flags |= R200_SURF_TILE_COLOR_MICRO; | ||
1778 | } else { | ||
1779 | if (tiling_flags & RADEON_TILING_MACRO) | ||
1780 | flags |= R300_SURF_TILE_MACRO; | ||
1781 | if (tiling_flags & RADEON_TILING_MICRO) | ||
1782 | flags |= R300_SURF_TILE_MICRO; | ||
1783 | } | ||
1784 | |||
1785 | DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); | ||
1786 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); | ||
1787 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); | ||
1788 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); | ||
1789 | return 0; | ||
1790 | } | ||
1791 | |||
1792 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg) | ||
1793 | { | ||
1794 | int surf_index = reg * 16; | ||
1795 | WREG32(RADEON_SURFACE0_INFO + surf_index, 0); | ||
1796 | } | ||
1797 | |||
1798 | void r100_bandwidth_update(struct radeon_device *rdev) | ||
1799 | { | ||
1800 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; | ||
1801 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; | ||
1802 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; | ||
1803 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; | ||
1804 | fixed20_12 memtcas_ff[8] = { | ||
1805 | fixed_init(1), | ||
1806 | fixed_init(2), | ||
1807 | fixed_init(3), | ||
1808 | fixed_init(0), | ||
1809 | fixed_init_half(1), | ||
1810 | fixed_init_half(2), | ||
1811 | fixed_init(0), | ||
1812 | }; | ||
1813 | fixed20_12 memtcas_rs480_ff[8] = { | ||
1814 | fixed_init(0), | ||
1815 | fixed_init(1), | ||
1816 | fixed_init(2), | ||
1817 | fixed_init(3), | ||
1818 | fixed_init(0), | ||
1819 | fixed_init_half(1), | ||
1820 | fixed_init_half(2), | ||
1821 | fixed_init_half(3), | ||
1822 | }; | ||
1823 | fixed20_12 memtcas2_ff[8] = { | ||
1824 | fixed_init(0), | ||
1825 | fixed_init(1), | ||
1826 | fixed_init(2), | ||
1827 | fixed_init(3), | ||
1828 | fixed_init(4), | ||
1829 | fixed_init(5), | ||
1830 | fixed_init(6), | ||
1831 | fixed_init(7), | ||
1832 | }; | ||
1833 | fixed20_12 memtrbs[8] = { | ||
1834 | fixed_init(1), | ||
1835 | fixed_init_half(1), | ||
1836 | fixed_init(2), | ||
1837 | fixed_init_half(2), | ||
1838 | fixed_init(3), | ||
1839 | fixed_init_half(3), | ||
1840 | fixed_init(4), | ||
1841 | fixed_init_half(4) | ||
1842 | }; | ||
1843 | fixed20_12 memtrbs_r4xx[8] = { | ||
1844 | fixed_init(4), | ||
1845 | fixed_init(5), | ||
1846 | fixed_init(6), | ||
1847 | fixed_init(7), | ||
1848 | fixed_init(8), | ||
1849 | fixed_init(9), | ||
1850 | fixed_init(10), | ||
1851 | fixed_init(11) | ||
1852 | }; | ||
1853 | fixed20_12 min_mem_eff; | ||
1854 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; | ||
1855 | fixed20_12 cur_latency_mclk, cur_latency_sclk; | ||
1856 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, | ||
1857 | disp_drain_rate2, read_return_rate; | ||
1858 | fixed20_12 time_disp1_drop_priority; | ||
1859 | int c; | ||
1860 | int cur_size = 16; /* in octawords */ | ||
1861 | int critical_point = 0, critical_point2; | ||
1862 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ | ||
1863 | int stop_req, max_stop_req; | ||
1864 | struct drm_display_mode *mode1 = NULL; | ||
1865 | struct drm_display_mode *mode2 = NULL; | ||
1866 | uint32_t pixel_bytes1 = 0; | ||
1867 | uint32_t pixel_bytes2 = 0; | ||
1868 | |||
1869 | if (rdev->mode_info.crtcs[0]->base.enabled) { | ||
1870 | mode1 = &rdev->mode_info.crtcs[0]->base.mode; | ||
1871 | pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; | ||
1872 | } | ||
1873 | if (rdev->mode_info.crtcs[1]->base.enabled) { | ||
1874 | mode2 = &rdev->mode_info.crtcs[1]->base.mode; | ||
1875 | pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; | ||
1876 | } | ||
1877 | |||
1878 | min_mem_eff.full = rfixed_const_8(0); | ||
1879 | /* get modes */ | ||
1880 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { | ||
1881 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); | ||
1882 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); | ||
1883 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); | ||
1884 | /* check crtc enables */ | ||
1885 | if (mode2) | ||
1886 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); | ||
1887 | if (mode1) | ||
1888 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); | ||
1889 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); | ||
1890 | } | ||
1891 | |||
1892 | /* | ||
1893 | * determine is there is enough bw for current mode | ||
1894 | */ | ||
1895 | mclk_ff.full = rfixed_const(rdev->clock.default_mclk); | ||
1896 | temp_ff.full = rfixed_const(100); | ||
1897 | mclk_ff.full = rfixed_div(mclk_ff, temp_ff); | ||
1898 | sclk_ff.full = rfixed_const(rdev->clock.default_sclk); | ||
1899 | sclk_ff.full = rfixed_div(sclk_ff, temp_ff); | ||
1900 | |||
1901 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); | ||
1902 | temp_ff.full = rfixed_const(temp); | ||
1903 | mem_bw.full = rfixed_mul(mclk_ff, temp_ff); | ||
1904 | |||
1905 | pix_clk.full = 0; | ||
1906 | pix_clk2.full = 0; | ||
1907 | peak_disp_bw.full = 0; | ||
1908 | if (mode1) { | ||
1909 | temp_ff.full = rfixed_const(1000); | ||
1910 | pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ | ||
1911 | pix_clk.full = rfixed_div(pix_clk, temp_ff); | ||
1912 | temp_ff.full = rfixed_const(pixel_bytes1); | ||
1913 | peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); | ||
1914 | } | ||
1915 | if (mode2) { | ||
1916 | temp_ff.full = rfixed_const(1000); | ||
1917 | pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ | ||
1918 | pix_clk2.full = rfixed_div(pix_clk2, temp_ff); | ||
1919 | temp_ff.full = rfixed_const(pixel_bytes2); | ||
1920 | peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); | ||
1921 | } | ||
1922 | |||
1923 | mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); | ||
1924 | if (peak_disp_bw.full >= mem_bw.full) { | ||
1925 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" | ||
1926 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); | ||
1927 | } | ||
1928 | |||
1929 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ | ||
1930 | temp = RREG32(RADEON_MEM_TIMING_CNTL); | ||
1931 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ | ||
1932 | mem_trcd = ((temp >> 2) & 0x3) + 1; | ||
1933 | mem_trp = ((temp & 0x3)) + 1; | ||
1934 | mem_tras = ((temp & 0x70) >> 4) + 1; | ||
1935 | } else if (rdev->family == CHIP_R300 || | ||
1936 | rdev->family == CHIP_R350) { /* r300, r350 */ | ||
1937 | mem_trcd = (temp & 0x7) + 1; | ||
1938 | mem_trp = ((temp >> 8) & 0x7) + 1; | ||
1939 | mem_tras = ((temp >> 11) & 0xf) + 4; | ||
1940 | } else if (rdev->family == CHIP_RV350 || | ||
1941 | rdev->family <= CHIP_RV380) { | ||
1942 | /* rv3x0 */ | ||
1943 | mem_trcd = (temp & 0x7) + 3; | ||
1944 | mem_trp = ((temp >> 8) & 0x7) + 3; | ||
1945 | mem_tras = ((temp >> 11) & 0xf) + 6; | ||
1946 | } else if (rdev->family == CHIP_R420 || | ||
1947 | rdev->family == CHIP_R423 || | ||
1948 | rdev->family == CHIP_RV410) { | ||
1949 | /* r4xx */ | ||
1950 | mem_trcd = (temp & 0xf) + 3; | ||
1951 | if (mem_trcd > 15) | ||
1952 | mem_trcd = 15; | ||
1953 | mem_trp = ((temp >> 8) & 0xf) + 3; | ||
1954 | if (mem_trp > 15) | ||
1955 | mem_trp = 15; | ||
1956 | mem_tras = ((temp >> 12) & 0x1f) + 6; | ||
1957 | if (mem_tras > 31) | ||
1958 | mem_tras = 31; | ||
1959 | } else { /* RV200, R200 */ | ||
1960 | mem_trcd = (temp & 0x7) + 1; | ||
1961 | mem_trp = ((temp >> 8) & 0x7) + 1; | ||
1962 | mem_tras = ((temp >> 12) & 0xf) + 4; | ||
1963 | } | ||
1964 | /* convert to FF */ | ||
1965 | trcd_ff.full = rfixed_const(mem_trcd); | ||
1966 | trp_ff.full = rfixed_const(mem_trp); | ||
1967 | tras_ff.full = rfixed_const(mem_tras); | ||
1968 | |||
1969 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ | ||
1970 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); | ||
1971 | data = (temp & (7 << 20)) >> 20; | ||
1972 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { | ||
1973 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ | ||
1974 | tcas_ff = memtcas_rs480_ff[data]; | ||
1975 | else | ||
1976 | tcas_ff = memtcas_ff[data]; | ||
1977 | } else | ||
1978 | tcas_ff = memtcas2_ff[data]; | ||
1979 | |||
1980 | if (rdev->family == CHIP_RS400 || | ||
1981 | rdev->family == CHIP_RS480) { | ||
1982 | /* extra cas latency stored in bits 23-25 0-4 clocks */ | ||
1983 | data = (temp >> 23) & 0x7; | ||
1984 | if (data < 5) | ||
1985 | tcas_ff.full += rfixed_const(data); | ||
1986 | } | ||
1987 | |||
1988 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { | ||
1989 | /* on the R300, Tcas is included in Trbs. | ||
1990 | */ | ||
1991 | temp = RREG32(RADEON_MEM_CNTL); | ||
1992 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); | ||
1993 | if (data == 1) { | ||
1994 | if (R300_MEM_USE_CD_CH_ONLY & temp) { | ||
1995 | temp = RREG32(R300_MC_IND_INDEX); | ||
1996 | temp &= ~R300_MC_IND_ADDR_MASK; | ||
1997 | temp |= R300_MC_READ_CNTL_CD_mcind; | ||
1998 | WREG32(R300_MC_IND_INDEX, temp); | ||
1999 | temp = RREG32(R300_MC_IND_DATA); | ||
2000 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); | ||
2001 | } else { | ||
2002 | temp = RREG32(R300_MC_READ_CNTL_AB); | ||
2003 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | ||
2004 | } | ||
2005 | } else { | ||
2006 | temp = RREG32(R300_MC_READ_CNTL_AB); | ||
2007 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | ||
2008 | } | ||
2009 | if (rdev->family == CHIP_RV410 || | ||
2010 | rdev->family == CHIP_R420 || | ||
2011 | rdev->family == CHIP_R423) | ||
2012 | trbs_ff = memtrbs_r4xx[data]; | ||
2013 | else | ||
2014 | trbs_ff = memtrbs[data]; | ||
2015 | tcas_ff.full += trbs_ff.full; | ||
2016 | } | ||
2017 | |||
2018 | sclk_eff_ff.full = sclk_ff.full; | ||
2019 | |||
2020 | if (rdev->flags & RADEON_IS_AGP) { | ||
2021 | fixed20_12 agpmode_ff; | ||
2022 | agpmode_ff.full = rfixed_const(radeon_agpmode); | ||
2023 | temp_ff.full = rfixed_const_666(16); | ||
2024 | sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff); | ||
2025 | } | ||
2026 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ | ||
2027 | |||
2028 | if (ASIC_IS_R300(rdev)) { | ||
2029 | sclk_delay_ff.full = rfixed_const(250); | ||
2030 | } else { | ||
2031 | if ((rdev->family == CHIP_RV100) || | ||
2032 | rdev->flags & RADEON_IS_IGP) { | ||
2033 | if (rdev->mc.vram_is_ddr) | ||
2034 | sclk_delay_ff.full = rfixed_const(41); | ||
2035 | else | ||
2036 | sclk_delay_ff.full = rfixed_const(33); | ||
2037 | } else { | ||
2038 | if (rdev->mc.vram_width == 128) | ||
2039 | sclk_delay_ff.full = rfixed_const(57); | ||
2040 | else | ||
2041 | sclk_delay_ff.full = rfixed_const(41); | ||
2042 | } | ||
2043 | } | ||
2044 | |||
2045 | mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff); | ||
2046 | |||
2047 | if (rdev->mc.vram_is_ddr) { | ||
2048 | if (rdev->mc.vram_width == 32) { | ||
2049 | k1.full = rfixed_const(40); | ||
2050 | c = 3; | ||
2051 | } else { | ||
2052 | k1.full = rfixed_const(20); | ||
2053 | c = 1; | ||
2054 | } | ||
2055 | } else { | ||
2056 | k1.full = rfixed_const(40); | ||
2057 | c = 3; | ||
2058 | } | ||
2059 | |||
2060 | temp_ff.full = rfixed_const(2); | ||
2061 | mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff); | ||
2062 | temp_ff.full = rfixed_const(c); | ||
2063 | mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff); | ||
2064 | temp_ff.full = rfixed_const(4); | ||
2065 | mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff); | ||
2066 | mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff); | ||
2067 | mc_latency_mclk.full += k1.full; | ||
2068 | |||
2069 | mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff); | ||
2070 | mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff); | ||
2071 | |||
2072 | /* | ||
2073 | HW cursor time assuming worst case of full size colour cursor. | ||
2074 | */ | ||
2075 | temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); | ||
2076 | temp_ff.full += trcd_ff.full; | ||
2077 | if (temp_ff.full < tras_ff.full) | ||
2078 | temp_ff.full = tras_ff.full; | ||
2079 | cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff); | ||
2080 | |||
2081 | temp_ff.full = rfixed_const(cur_size); | ||
2082 | cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff); | ||
2083 | /* | ||
2084 | Find the total latency for the display data. | ||
2085 | */ | ||
2086 | disp_latency_overhead.full = rfixed_const(80); | ||
2087 | disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff); | ||
2088 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; | ||
2089 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; | ||
2090 | |||
2091 | if (mc_latency_mclk.full > mc_latency_sclk.full) | ||
2092 | disp_latency.full = mc_latency_mclk.full; | ||
2093 | else | ||
2094 | disp_latency.full = mc_latency_sclk.full; | ||
2095 | |||
2096 | /* setup Max GRPH_STOP_REQ default value */ | ||
2097 | if (ASIC_IS_RV100(rdev)) | ||
2098 | max_stop_req = 0x5c; | ||
2099 | else | ||
2100 | max_stop_req = 0x7c; | ||
2101 | |||
2102 | if (mode1) { | ||
2103 | /* CRTC1 | ||
2104 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. | ||
2105 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] | ||
2106 | */ | ||
2107 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; | ||
2108 | |||
2109 | if (stop_req > max_stop_req) | ||
2110 | stop_req = max_stop_req; | ||
2111 | |||
2112 | /* | ||
2113 | Find the drain rate of the display buffer. | ||
2114 | */ | ||
2115 | temp_ff.full = rfixed_const((16/pixel_bytes1)); | ||
2116 | disp_drain_rate.full = rfixed_div(pix_clk, temp_ff); | ||
2117 | |||
2118 | /* | ||
2119 | Find the critical point of the display buffer. | ||
2120 | */ | ||
2121 | crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency); | ||
2122 | crit_point_ff.full += rfixed_const_half(0); | ||
2123 | |||
2124 | critical_point = rfixed_trunc(crit_point_ff); | ||
2125 | |||
2126 | if (rdev->disp_priority == 2) { | ||
2127 | critical_point = 0; | ||
2128 | } | ||
2129 | |||
2130 | /* | ||
2131 | The critical point should never be above max_stop_req-4. Setting | ||
2132 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. | ||
2133 | */ | ||
2134 | if (max_stop_req - critical_point < 4) | ||
2135 | critical_point = 0; | ||
2136 | |||
2137 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { | ||
2138 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ | ||
2139 | critical_point = 0x10; | ||
2140 | } | ||
2141 | |||
2142 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); | ||
2143 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); | ||
2144 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | ||
2145 | temp &= ~(RADEON_GRPH_START_REQ_MASK); | ||
2146 | if ((rdev->family == CHIP_R350) && | ||
2147 | (stop_req > 0x15)) { | ||
2148 | stop_req -= 0x10; | ||
2149 | } | ||
2150 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); | ||
2151 | temp |= RADEON_GRPH_BUFFER_SIZE; | ||
2152 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | | ||
2153 | RADEON_GRPH_CRITICAL_AT_SOF | | ||
2154 | RADEON_GRPH_STOP_CNTL); | ||
2155 | /* | ||
2156 | Write the result into the register. | ||
2157 | */ | ||
2158 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | | ||
2159 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | ||
2160 | |||
2161 | #if 0 | ||
2162 | if ((rdev->family == CHIP_RS400) || | ||
2163 | (rdev->family == CHIP_RS480)) { | ||
2164 | /* attempt to program RS400 disp regs correctly ??? */ | ||
2165 | temp = RREG32(RS400_DISP1_REG_CNTL); | ||
2166 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | | ||
2167 | RS400_DISP1_STOP_REQ_LEVEL_MASK); | ||
2168 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | | ||
2169 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | ||
2170 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | ||
2171 | temp = RREG32(RS400_DMIF_MEM_CNTL1); | ||
2172 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | | ||
2173 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); | ||
2174 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | | ||
2175 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | | ||
2176 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); | ||
2177 | } | ||
2178 | #endif | ||
2179 | |||
2180 | DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n", | ||
2181 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ | ||
2182 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); | ||
2183 | } | ||
2184 | |||
2185 | if (mode2) { | ||
2186 | u32 grph2_cntl; | ||
2187 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; | ||
2188 | |||
2189 | if (stop_req > max_stop_req) | ||
2190 | stop_req = max_stop_req; | ||
2191 | |||
2192 | /* | ||
2193 | Find the drain rate of the display buffer. | ||
2194 | */ | ||
2195 | temp_ff.full = rfixed_const((16/pixel_bytes2)); | ||
2196 | disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff); | ||
2197 | |||
2198 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); | ||
2199 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); | ||
2200 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | ||
2201 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); | ||
2202 | if ((rdev->family == CHIP_R350) && | ||
2203 | (stop_req > 0x15)) { | ||
2204 | stop_req -= 0x10; | ||
2205 | } | ||
2206 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); | ||
2207 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; | ||
2208 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | | ||
2209 | RADEON_GRPH_CRITICAL_AT_SOF | | ||
2210 | RADEON_GRPH_STOP_CNTL); | ||
2211 | |||
2212 | if ((rdev->family == CHIP_RS100) || | ||
2213 | (rdev->family == CHIP_RS200)) | ||
2214 | critical_point2 = 0; | ||
2215 | else { | ||
2216 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; | ||
2217 | temp_ff.full = rfixed_const(temp); | ||
2218 | temp_ff.full = rfixed_mul(mclk_ff, temp_ff); | ||
2219 | if (sclk_ff.full < temp_ff.full) | ||
2220 | temp_ff.full = sclk_ff.full; | ||
2221 | |||
2222 | read_return_rate.full = temp_ff.full; | ||
2223 | |||
2224 | if (mode1) { | ||
2225 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; | ||
2226 | time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff); | ||
2227 | } else { | ||
2228 | time_disp1_drop_priority.full = 0; | ||
2229 | } | ||
2230 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; | ||
2231 | crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2); | ||
2232 | crit_point_ff.full += rfixed_const_half(0); | ||
2233 | |||
2234 | critical_point2 = rfixed_trunc(crit_point_ff); | ||
2235 | |||
2236 | if (rdev->disp_priority == 2) { | ||
2237 | critical_point2 = 0; | ||
2238 | } | ||
2239 | |||
2240 | if (max_stop_req - critical_point2 < 4) | ||
2241 | critical_point2 = 0; | ||
2242 | |||
2243 | } | ||
2244 | |||
2245 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { | ||
2246 | /* some R300 cards have problem with this set to 0 */ | ||
2247 | critical_point2 = 0x10; | ||
2248 | } | ||
2249 | |||
2250 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | | ||
2251 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | ||
2252 | |||
2253 | if ((rdev->family == CHIP_RS400) || | ||
2254 | (rdev->family == CHIP_RS480)) { | ||
2255 | #if 0 | ||
2256 | /* attempt to program RS400 disp2 regs correctly ??? */ | ||
2257 | temp = RREG32(RS400_DISP2_REQ_CNTL1); | ||
2258 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | | ||
2259 | RS400_DISP2_STOP_REQ_LEVEL_MASK); | ||
2260 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | | ||
2261 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | ||
2262 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | ||
2263 | temp = RREG32(RS400_DISP2_REQ_CNTL2); | ||
2264 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | | ||
2265 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); | ||
2266 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | | ||
2267 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | | ||
2268 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); | ||
2269 | #endif | ||
2270 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); | ||
2271 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); | ||
2272 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); | ||
2273 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); | ||
2274 | } | ||
2275 | |||
2276 | DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", | ||
2277 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); | ||
2278 | } | ||
2279 | } | ||
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index e2ed5bc08170..9c8d41534a5d 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -30,6 +30,8 @@ | |||
30 | #include "drm.h" | 30 | #include "drm.h" |
31 | #include "radeon_reg.h" | 31 | #include "radeon_reg.h" |
32 | #include "radeon.h" | 32 | #include "radeon.h" |
33 | #include "radeon_drm.h" | ||
34 | #include "radeon_share.h" | ||
33 | 35 | ||
34 | /* r300,r350,rv350,rv370,rv380 depends on : */ | 36 | /* r300,r350,rv350,rv370,rv380 depends on : */ |
35 | void r100_hdp_reset(struct radeon_device *rdev); | 37 | void r100_hdp_reset(struct radeon_device *rdev); |
@@ -44,6 +46,7 @@ int r100_gui_wait_for_idle(struct radeon_device *rdev); | |||
44 | int r100_cs_packet_parse(struct radeon_cs_parser *p, | 46 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
45 | struct radeon_cs_packet *pkt, | 47 | struct radeon_cs_packet *pkt, |
46 | unsigned idx); | 48 | unsigned idx); |
49 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); | ||
47 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, | 50 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, |
48 | struct radeon_cs_reloc **cs_reloc); | 51 | struct radeon_cs_reloc **cs_reloc); |
49 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, | 52 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
@@ -150,8 +153,13 @@ int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |||
150 | if (i < 0 || i > rdev->gart.num_gpu_pages) { | 153 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
151 | return -EINVAL; | 154 | return -EINVAL; |
152 | } | 155 | } |
153 | addr = (((u32)addr) >> 8) | ((upper_32_bits(addr) & 0xff) << 4) | 0xC; | 156 | addr = (lower_32_bits(addr) >> 8) | |
154 | writel(cpu_to_le32(addr), ((void __iomem *)ptr) + (i * 4)); | 157 | ((upper_32_bits(addr) & 0xff) << 24) | |
158 | 0xc; | ||
159 | /* on x86 we want this to be CPU endian, on powerpc | ||
160 | * on powerpc without HW swappers, it'll get swapped on way | ||
161 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ | ||
162 | writel(addr, ((void __iomem *)ptr) + (i * 4)); | ||
155 | return 0; | 163 | return 0; |
156 | } | 164 | } |
157 | 165 | ||
@@ -579,10 +587,8 @@ void r300_vram_info(struct radeon_device *rdev) | |||
579 | } else { | 587 | } else { |
580 | rdev->mc.vram_width = 64; | 588 | rdev->mc.vram_width = 64; |
581 | } | 589 | } |
582 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); | ||
583 | 590 | ||
584 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | 591 | r100_vram_init_sizes(rdev); |
585 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | ||
586 | } | 592 | } |
587 | 593 | ||
588 | 594 | ||
@@ -970,7 +976,7 @@ static inline void r300_cs_track_clear(struct r300_cs_track *track) | |||
970 | 976 | ||
971 | static const unsigned r300_reg_safe_bm[159] = { | 977 | static const unsigned r300_reg_safe_bm[159] = { |
972 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | 978 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
973 | 0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF, | 979 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
974 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | 980 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
975 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | 981 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
976 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | 982 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
@@ -1019,7 +1025,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1019 | struct radeon_cs_reloc *reloc; | 1025 | struct radeon_cs_reloc *reloc; |
1020 | struct r300_cs_track *track; | 1026 | struct r300_cs_track *track; |
1021 | volatile uint32_t *ib; | 1027 | volatile uint32_t *ib; |
1022 | uint32_t tmp; | 1028 | uint32_t tmp, tile_flags = 0; |
1023 | unsigned i; | 1029 | unsigned i; |
1024 | int r; | 1030 | int r; |
1025 | 1031 | ||
@@ -1027,6 +1033,16 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1027 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | 1033 | ib_chunk = &p->chunks[p->chunk_ib_idx]; |
1028 | track = (struct r300_cs_track*)p->track; | 1034 | track = (struct r300_cs_track*)p->track; |
1029 | switch(reg) { | 1035 | switch(reg) { |
1036 | case AVIVO_D1MODE_VLINE_START_END: | ||
1037 | case RADEON_CRTC_GUI_TRIG_VLINE: | ||
1038 | r = r100_cs_packet_parse_vline(p); | ||
1039 | if (r) { | ||
1040 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | ||
1041 | idx, reg); | ||
1042 | r100_cs_dump_packet(p, pkt); | ||
1043 | return r; | ||
1044 | } | ||
1045 | break; | ||
1030 | case RADEON_DST_PITCH_OFFSET: | 1046 | case RADEON_DST_PITCH_OFFSET: |
1031 | case RADEON_SRC_PITCH_OFFSET: | 1047 | case RADEON_SRC_PITCH_OFFSET: |
1032 | r = r100_cs_packet_next_reloc(p, &reloc); | 1048 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -1038,7 +1054,19 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1038 | } | 1054 | } |
1039 | tmp = ib_chunk->kdata[idx] & 0x003fffff; | 1055 | tmp = ib_chunk->kdata[idx] & 0x003fffff; |
1040 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); | 1056 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); |
1041 | ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) | tmp; | 1057 | |
1058 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | ||
1059 | tile_flags |= RADEON_DST_TILE_MACRO; | ||
1060 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { | ||
1061 | if (reg == RADEON_SRC_PITCH_OFFSET) { | ||
1062 | DRM_ERROR("Cannot src blit from microtiled surface\n"); | ||
1063 | r100_cs_dump_packet(p, pkt); | ||
1064 | return -EINVAL; | ||
1065 | } | ||
1066 | tile_flags |= RADEON_DST_TILE_MICRO; | ||
1067 | } | ||
1068 | tmp |= tile_flags; | ||
1069 | ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; | ||
1042 | break; | 1070 | break; |
1043 | case R300_RB3D_COLOROFFSET0: | 1071 | case R300_RB3D_COLOROFFSET0: |
1044 | case R300_RB3D_COLOROFFSET1: | 1072 | case R300_RB3D_COLOROFFSET1: |
@@ -1127,6 +1155,23 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1127 | /* RB3D_COLORPITCH1 */ | 1155 | /* RB3D_COLORPITCH1 */ |
1128 | /* RB3D_COLORPITCH2 */ | 1156 | /* RB3D_COLORPITCH2 */ |
1129 | /* RB3D_COLORPITCH3 */ | 1157 | /* RB3D_COLORPITCH3 */ |
1158 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
1159 | if (r) { | ||
1160 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | ||
1161 | idx, reg); | ||
1162 | r100_cs_dump_packet(p, pkt); | ||
1163 | return r; | ||
1164 | } | ||
1165 | |||
1166 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | ||
1167 | tile_flags |= R300_COLOR_TILE_ENABLE; | ||
1168 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | ||
1169 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; | ||
1170 | |||
1171 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); | ||
1172 | tmp |= tile_flags; | ||
1173 | ib[idx] = tmp; | ||
1174 | |||
1130 | i = (reg - 0x4E38) >> 2; | 1175 | i = (reg - 0x4E38) >> 2; |
1131 | track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE; | 1176 | track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE; |
1132 | switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) { | 1177 | switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) { |
@@ -1182,6 +1227,23 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1182 | break; | 1227 | break; |
1183 | case 0x4F24: | 1228 | case 0x4F24: |
1184 | /* ZB_DEPTHPITCH */ | 1229 | /* ZB_DEPTHPITCH */ |
1230 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
1231 | if (r) { | ||
1232 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | ||
1233 | idx, reg); | ||
1234 | r100_cs_dump_packet(p, pkt); | ||
1235 | return r; | ||
1236 | } | ||
1237 | |||
1238 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | ||
1239 | tile_flags |= R300_DEPTHMACROTILE_ENABLE; | ||
1240 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | ||
1241 | tile_flags |= R300_DEPTHMICROTILE_TILED;; | ||
1242 | |||
1243 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); | ||
1244 | tmp |= tile_flags; | ||
1245 | ib[idx] = tmp; | ||
1246 | |||
1185 | track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC; | 1247 | track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC; |
1186 | break; | 1248 | break; |
1187 | case 0x4104: | 1249 | case 0x4104: |
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h index 70f48609515e..4b7afef35a65 100644 --- a/drivers/gpu/drm/radeon/r300_reg.h +++ b/drivers/gpu/drm/radeon/r300_reg.h | |||
@@ -27,7 +27,9 @@ | |||
27 | #ifndef _R300_REG_H_ | 27 | #ifndef _R300_REG_H_ |
28 | #define _R300_REG_H_ | 28 | #define _R300_REG_H_ |
29 | 29 | ||
30 | 30 | #define R300_SURF_TILE_MACRO (1<<16) | |
31 | #define R300_SURF_TILE_MICRO (2<<16) | ||
32 | #define R300_SURF_TILE_BOTH (3<<16) | ||
31 | 33 | ||
32 | 34 | ||
33 | #define R300_MC_INIT_MISC_LAT_TIMER 0x180 | 35 | #define R300_MC_INIT_MISC_LAT_TIMER 0x180 |
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h index 9070a1c2ce23..036691b38cb7 100644 --- a/drivers/gpu/drm/radeon/r500_reg.h +++ b/drivers/gpu/drm/radeon/r500_reg.h | |||
@@ -445,6 +445,7 @@ | |||
445 | #define AVIVO_D1MODE_DATA_FORMAT 0x6528 | 445 | #define AVIVO_D1MODE_DATA_FORMAT 0x6528 |
446 | # define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) | 446 | # define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) |
447 | #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C | 447 | #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C |
448 | #define AVIVO_D1MODE_VLINE_START_END 0x6538 | ||
448 | #define AVIVO_D1MODE_VIEWPORT_START 0x6580 | 449 | #define AVIVO_D1MODE_VIEWPORT_START 0x6580 |
449 | #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 | 450 | #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 |
450 | #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 | 451 | #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 |
@@ -496,6 +497,7 @@ | |||
496 | #define AVIVO_D2CUR_SIZE 0x6c10 | 497 | #define AVIVO_D2CUR_SIZE 0x6c10 |
497 | #define AVIVO_D2CUR_POSITION 0x6c14 | 498 | #define AVIVO_D2CUR_POSITION 0x6c14 |
498 | 499 | ||
500 | #define AVIVO_D2MODE_VLINE_START_END 0x6d38 | ||
499 | #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 | 501 | #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 |
500 | #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 | 502 | #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 |
501 | #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 | 503 | #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 |
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c index 570a244bd88b..09fb0b6ec7dd 100644 --- a/drivers/gpu/drm/radeon/r520.c +++ b/drivers/gpu/drm/radeon/r520.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include "drmP.h" | 28 | #include "drmP.h" |
29 | #include "radeon_reg.h" | 29 | #include "radeon_reg.h" |
30 | #include "radeon.h" | 30 | #include "radeon.h" |
31 | #include "radeon_share.h" | ||
31 | 32 | ||
32 | /* r520,rv530,rv560,rv570,r580 depends on : */ | 33 | /* r520,rv530,rv560,rv570,r580 depends on : */ |
33 | void r100_hdp_reset(struct radeon_device *rdev); | 34 | void r100_hdp_reset(struct radeon_device *rdev); |
@@ -94,8 +95,8 @@ int r520_mc_init(struct radeon_device *rdev) | |||
94 | "programming pipes. Bad things might happen.\n"); | 95 | "programming pipes. Bad things might happen.\n"); |
95 | } | 96 | } |
96 | /* Write VRAM size in case we are limiting it */ | 97 | /* Write VRAM size in case we are limiting it */ |
97 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); | 98 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
98 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; | 99 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
99 | tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); | 100 | tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); |
100 | tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); | 101 | tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); |
101 | WREG32_MC(R520_MC_FB_LOCATION, tmp); | 102 | WREG32_MC(R520_MC_FB_LOCATION, tmp); |
@@ -226,9 +227,20 @@ static void r520_vram_get_type(struct radeon_device *rdev) | |||
226 | 227 | ||
227 | void r520_vram_info(struct radeon_device *rdev) | 228 | void r520_vram_info(struct radeon_device *rdev) |
228 | { | 229 | { |
230 | fixed20_12 a; | ||
231 | |||
229 | r520_vram_get_type(rdev); | 232 | r520_vram_get_type(rdev); |
230 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); | ||
231 | 233 | ||
232 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | 234 | r100_vram_init_sizes(rdev); |
233 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | 235 | /* FIXME: we should enforce default clock in case GPU is not in |
236 | * default setup | ||
237 | */ | ||
238 | a.full = rfixed_const(100); | ||
239 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); | ||
240 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | ||
241 | } | ||
242 | |||
243 | void r520_bandwidth_update(struct radeon_device *rdev) | ||
244 | { | ||
245 | rv515_bandwidth_avivo_update(rdev); | ||
234 | } | 246 | } |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index c45559fc97fd..538cd907df69 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -67,7 +67,7 @@ int r600_mc_init(struct radeon_device *rdev) | |||
67 | "programming pipes. Bad things might happen.\n"); | 67 | "programming pipes. Bad things might happen.\n"); |
68 | } | 68 | } |
69 | 69 | ||
70 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; | 70 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
71 | tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24); | 71 | tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24); |
72 | tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24); | 72 | tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24); |
73 | WREG32(R600_MC_VM_FB_LOCATION, tmp); | 73 | WREG32(R600_MC_VM_FB_LOCATION, tmp); |
@@ -140,7 +140,8 @@ void r600_vram_get_type(struct radeon_device *rdev) | |||
140 | void r600_vram_info(struct radeon_device *rdev) | 140 | void r600_vram_info(struct radeon_device *rdev) |
141 | { | 141 | { |
142 | r600_vram_get_type(rdev); | 142 | r600_vram_get_type(rdev); |
143 | rdev->mc.vram_size = RREG32(R600_CONFIG_MEMSIZE); | 143 | rdev->mc.real_vram_size = RREG32(R600_CONFIG_MEMSIZE); |
144 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | ||
144 | 145 | ||
145 | /* Could aper size report 0 ? */ | 146 | /* Could aper size report 0 ? */ |
146 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | 147 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index d61f2fc61df5..b1d945b8ed6c 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -64,6 +64,7 @@ extern int radeon_agpmode; | |||
64 | extern int radeon_vram_limit; | 64 | extern int radeon_vram_limit; |
65 | extern int radeon_gart_size; | 65 | extern int radeon_gart_size; |
66 | extern int radeon_benchmarking; | 66 | extern int radeon_benchmarking; |
67 | extern int radeon_testing; | ||
67 | extern int radeon_connector_table; | 68 | extern int radeon_connector_table; |
68 | 69 | ||
69 | /* | 70 | /* |
@@ -113,6 +114,7 @@ enum radeon_family { | |||
113 | CHIP_RV770, | 114 | CHIP_RV770, |
114 | CHIP_RV730, | 115 | CHIP_RV730, |
115 | CHIP_RV710, | 116 | CHIP_RV710, |
117 | CHIP_RS880, | ||
116 | CHIP_LAST, | 118 | CHIP_LAST, |
117 | }; | 119 | }; |
118 | 120 | ||
@@ -201,6 +203,14 @@ int radeon_fence_wait_last(struct radeon_device *rdev); | |||
201 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); | 203 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
202 | void radeon_fence_unref(struct radeon_fence **fence); | 204 | void radeon_fence_unref(struct radeon_fence **fence); |
203 | 205 | ||
206 | /* | ||
207 | * Tiling registers | ||
208 | */ | ||
209 | struct radeon_surface_reg { | ||
210 | struct radeon_object *robj; | ||
211 | }; | ||
212 | |||
213 | #define RADEON_GEM_MAX_SURFACES 8 | ||
204 | 214 | ||
205 | /* | 215 | /* |
206 | * Radeon buffer. | 216 | * Radeon buffer. |
@@ -213,6 +223,7 @@ struct radeon_object_list { | |||
213 | uint64_t gpu_offset; | 223 | uint64_t gpu_offset; |
214 | unsigned rdomain; | 224 | unsigned rdomain; |
215 | unsigned wdomain; | 225 | unsigned wdomain; |
226 | uint32_t tiling_flags; | ||
216 | }; | 227 | }; |
217 | 228 | ||
218 | int radeon_object_init(struct radeon_device *rdev); | 229 | int radeon_object_init(struct radeon_device *rdev); |
@@ -242,8 +253,15 @@ void radeon_object_list_clean(struct list_head *head); | |||
242 | int radeon_object_fbdev_mmap(struct radeon_object *robj, | 253 | int radeon_object_fbdev_mmap(struct radeon_object *robj, |
243 | struct vm_area_struct *vma); | 254 | struct vm_area_struct *vma); |
244 | unsigned long radeon_object_size(struct radeon_object *robj); | 255 | unsigned long radeon_object_size(struct radeon_object *robj); |
245 | 256 | void radeon_object_clear_surface_reg(struct radeon_object *robj); | |
246 | 257 | int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved, | |
258 | bool force_drop); | ||
259 | void radeon_object_set_tiling_flags(struct radeon_object *robj, | ||
260 | uint32_t tiling_flags, uint32_t pitch); | ||
261 | void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch); | ||
262 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | ||
263 | struct ttm_mem_reg *mem); | ||
264 | void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo); | ||
247 | /* | 265 | /* |
248 | * GEM objects. | 266 | * GEM objects. |
249 | */ | 267 | */ |
@@ -315,8 +333,11 @@ struct radeon_mc { | |||
315 | unsigned gtt_location; | 333 | unsigned gtt_location; |
316 | unsigned gtt_size; | 334 | unsigned gtt_size; |
317 | unsigned vram_location; | 335 | unsigned vram_location; |
318 | unsigned vram_size; | 336 | /* for some chips with <= 32MB we need to lie |
337 | * about vram size near mc fb location */ | ||
338 | unsigned mc_vram_size; | ||
319 | unsigned vram_width; | 339 | unsigned vram_width; |
340 | unsigned real_vram_size; | ||
320 | int vram_mtrr; | 341 | int vram_mtrr; |
321 | bool vram_is_ddr; | 342 | bool vram_is_ddr; |
322 | }; | 343 | }; |
@@ -474,6 +495,39 @@ struct radeon_wb { | |||
474 | uint64_t gpu_addr; | 495 | uint64_t gpu_addr; |
475 | }; | 496 | }; |
476 | 497 | ||
498 | /** | ||
499 | * struct radeon_pm - power management datas | ||
500 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | ||
501 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | ||
502 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | ||
503 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | ||
504 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | ||
505 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | ||
506 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | ||
507 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | ||
508 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | ||
509 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) | ||
510 | * @needed_bandwidth: current bandwidth needs | ||
511 | * | ||
512 | * It keeps track of various data needed to take powermanagement decision. | ||
513 | * Bandwith need is used to determine minimun clock of the GPU and memory. | ||
514 | * Equation between gpu/memory clock and available bandwidth is hw dependent | ||
515 | * (type of memory, bus size, efficiency, ...) | ||
516 | */ | ||
517 | struct radeon_pm { | ||
518 | fixed20_12 max_bandwidth; | ||
519 | fixed20_12 igp_sideport_mclk; | ||
520 | fixed20_12 igp_system_mclk; | ||
521 | fixed20_12 igp_ht_link_clk; | ||
522 | fixed20_12 igp_ht_link_width; | ||
523 | fixed20_12 k8_bandwidth; | ||
524 | fixed20_12 sideport_bandwidth; | ||
525 | fixed20_12 ht_bandwidth; | ||
526 | fixed20_12 core_bandwidth; | ||
527 | fixed20_12 sclk; | ||
528 | fixed20_12 needed_bandwidth; | ||
529 | }; | ||
530 | |||
477 | 531 | ||
478 | /* | 532 | /* |
479 | * Benchmarking | 533 | * Benchmarking |
@@ -482,6 +536,12 @@ void radeon_benchmark(struct radeon_device *rdev); | |||
482 | 536 | ||
483 | 537 | ||
484 | /* | 538 | /* |
539 | * Testing | ||
540 | */ | ||
541 | void radeon_test_moves(struct radeon_device *rdev); | ||
542 | |||
543 | |||
544 | /* | ||
485 | * Debugfs | 545 | * Debugfs |
486 | */ | 546 | */ |
487 | int radeon_debugfs_add_files(struct radeon_device *rdev, | 547 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
@@ -535,6 +595,11 @@ struct radeon_asic { | |||
535 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); | 595 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
536 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); | 596 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
537 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | 597 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
598 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, | ||
599 | uint32_t tiling_flags, uint32_t pitch, | ||
600 | uint32_t offset, uint32_t obj_size); | ||
601 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); | ||
602 | void (*bandwidth_update)(struct radeon_device *rdev); | ||
538 | }; | 603 | }; |
539 | 604 | ||
540 | union radeon_asic_config { | 605 | union radeon_asic_config { |
@@ -566,6 +631,10 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |||
566 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | 631 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
567 | struct drm_file *filp); | 632 | struct drm_file *filp); |
568 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | 633 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
634 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, | ||
635 | struct drm_file *filp); | ||
636 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | ||
637 | struct drm_file *filp); | ||
569 | 638 | ||
570 | 639 | ||
571 | /* | 640 | /* |
@@ -594,8 +663,8 @@ struct radeon_device { | |||
594 | struct radeon_object *fbdev_robj; | 663 | struct radeon_object *fbdev_robj; |
595 | struct radeon_framebuffer *fbdev_rfb; | 664 | struct radeon_framebuffer *fbdev_rfb; |
596 | /* Register mmio */ | 665 | /* Register mmio */ |
597 | unsigned long rmmio_base; | 666 | resource_size_t rmmio_base; |
598 | unsigned long rmmio_size; | 667 | resource_size_t rmmio_size; |
599 | void *rmmio; | 668 | void *rmmio; |
600 | radeon_rreg_t mm_rreg; | 669 | radeon_rreg_t mm_rreg; |
601 | radeon_wreg_t mm_wreg; | 670 | radeon_wreg_t mm_wreg; |
@@ -619,11 +688,14 @@ struct radeon_device { | |||
619 | struct radeon_irq irq; | 688 | struct radeon_irq irq; |
620 | struct radeon_asic *asic; | 689 | struct radeon_asic *asic; |
621 | struct radeon_gem gem; | 690 | struct radeon_gem gem; |
691 | struct radeon_pm pm; | ||
622 | struct mutex cs_mutex; | 692 | struct mutex cs_mutex; |
623 | struct radeon_wb wb; | 693 | struct radeon_wb wb; |
624 | bool gpu_lockup; | 694 | bool gpu_lockup; |
625 | bool shutdown; | 695 | bool shutdown; |
626 | bool suspend; | 696 | bool suspend; |
697 | bool need_dma32; | ||
698 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; | ||
627 | }; | 699 | }; |
628 | 700 | ||
629 | int radeon_device_init(struct radeon_device *rdev, | 701 | int radeon_device_init(struct radeon_device *rdev, |
@@ -670,6 +742,8 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); | |||
670 | /* | 742 | /* |
671 | * ASICs helpers. | 743 | * ASICs helpers. |
672 | */ | 744 | */ |
745 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ | ||
746 | (rdev->pdev->device == 0x5969)) | ||
673 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ | 747 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
674 | (rdev->family == CHIP_RV200) || \ | 748 | (rdev->family == CHIP_RV200) || \ |
675 | (rdev->family == CHIP_RS100) || \ | 749 | (rdev->family == CHIP_RS100) || \ |
@@ -796,5 +870,8 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) | |||
796 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) | 870 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
797 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) | 871 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
798 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) | 872 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
873 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) | ||
874 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) | ||
875 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) | ||
799 | 876 | ||
800 | #endif | 877 | #endif |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index e2e567395df8..9a75876e0c3b 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h | |||
@@ -71,6 +71,11 @@ int r100_copy_blit(struct radeon_device *rdev, | |||
71 | uint64_t dst_offset, | 71 | uint64_t dst_offset, |
72 | unsigned num_pages, | 72 | unsigned num_pages, |
73 | struct radeon_fence *fence); | 73 | struct radeon_fence *fence); |
74 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, | ||
75 | uint32_t tiling_flags, uint32_t pitch, | ||
76 | uint32_t offset, uint32_t obj_size); | ||
77 | int r100_clear_surface_reg(struct radeon_device *rdev, int reg); | ||
78 | void r100_bandwidth_update(struct radeon_device *rdev); | ||
74 | 79 | ||
75 | static struct radeon_asic r100_asic = { | 80 | static struct radeon_asic r100_asic = { |
76 | .init = &r100_init, | 81 | .init = &r100_init, |
@@ -100,6 +105,9 @@ static struct radeon_asic r100_asic = { | |||
100 | .set_memory_clock = NULL, | 105 | .set_memory_clock = NULL, |
101 | .set_pcie_lanes = NULL, | 106 | .set_pcie_lanes = NULL, |
102 | .set_clock_gating = &radeon_legacy_set_clock_gating, | 107 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
108 | .set_surface_reg = r100_set_surface_reg, | ||
109 | .clear_surface_reg = r100_clear_surface_reg, | ||
110 | .bandwidth_update = &r100_bandwidth_update, | ||
103 | }; | 111 | }; |
104 | 112 | ||
105 | 113 | ||
@@ -128,6 +136,7 @@ int r300_copy_dma(struct radeon_device *rdev, | |||
128 | uint64_t dst_offset, | 136 | uint64_t dst_offset, |
129 | unsigned num_pages, | 137 | unsigned num_pages, |
130 | struct radeon_fence *fence); | 138 | struct radeon_fence *fence); |
139 | |||
131 | static struct radeon_asic r300_asic = { | 140 | static struct radeon_asic r300_asic = { |
132 | .init = &r300_init, | 141 | .init = &r300_init, |
133 | .errata = &r300_errata, | 142 | .errata = &r300_errata, |
@@ -156,6 +165,9 @@ static struct radeon_asic r300_asic = { | |||
156 | .set_memory_clock = NULL, | 165 | .set_memory_clock = NULL, |
157 | .set_pcie_lanes = &rv370_set_pcie_lanes, | 166 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
158 | .set_clock_gating = &radeon_legacy_set_clock_gating, | 167 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
168 | .set_surface_reg = r100_set_surface_reg, | ||
169 | .clear_surface_reg = r100_clear_surface_reg, | ||
170 | .bandwidth_update = &r100_bandwidth_update, | ||
159 | }; | 171 | }; |
160 | 172 | ||
161 | /* | 173 | /* |
@@ -193,6 +205,9 @@ static struct radeon_asic r420_asic = { | |||
193 | .set_memory_clock = &radeon_atom_set_memory_clock, | 205 | .set_memory_clock = &radeon_atom_set_memory_clock, |
194 | .set_pcie_lanes = &rv370_set_pcie_lanes, | 206 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
195 | .set_clock_gating = &radeon_atom_set_clock_gating, | 207 | .set_clock_gating = &radeon_atom_set_clock_gating, |
208 | .set_surface_reg = r100_set_surface_reg, | ||
209 | .clear_surface_reg = r100_clear_surface_reg, | ||
210 | .bandwidth_update = &r100_bandwidth_update, | ||
196 | }; | 211 | }; |
197 | 212 | ||
198 | 213 | ||
@@ -237,6 +252,9 @@ static struct radeon_asic rs400_asic = { | |||
237 | .set_memory_clock = NULL, | 252 | .set_memory_clock = NULL, |
238 | .set_pcie_lanes = NULL, | 253 | .set_pcie_lanes = NULL, |
239 | .set_clock_gating = &radeon_legacy_set_clock_gating, | 254 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
255 | .set_surface_reg = r100_set_surface_reg, | ||
256 | .clear_surface_reg = r100_clear_surface_reg, | ||
257 | .bandwidth_update = &r100_bandwidth_update, | ||
240 | }; | 258 | }; |
241 | 259 | ||
242 | 260 | ||
@@ -254,6 +272,7 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev); | |||
254 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | 272 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
255 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); | 273 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
256 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | 274 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
275 | void rs600_bandwidth_update(struct radeon_device *rdev); | ||
257 | static struct radeon_asic rs600_asic = { | 276 | static struct radeon_asic rs600_asic = { |
258 | .init = &r300_init, | 277 | .init = &r300_init, |
259 | .errata = &rs600_errata, | 278 | .errata = &rs600_errata, |
@@ -282,6 +301,7 @@ static struct radeon_asic rs600_asic = { | |||
282 | .set_memory_clock = &radeon_atom_set_memory_clock, | 301 | .set_memory_clock = &radeon_atom_set_memory_clock, |
283 | .set_pcie_lanes = NULL, | 302 | .set_pcie_lanes = NULL, |
284 | .set_clock_gating = &radeon_atom_set_clock_gating, | 303 | .set_clock_gating = &radeon_atom_set_clock_gating, |
304 | .bandwidth_update = &rs600_bandwidth_update, | ||
285 | }; | 305 | }; |
286 | 306 | ||
287 | 307 | ||
@@ -294,6 +314,7 @@ int rs690_mc_init(struct radeon_device *rdev); | |||
294 | void rs690_mc_fini(struct radeon_device *rdev); | 314 | void rs690_mc_fini(struct radeon_device *rdev); |
295 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); | 315 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
296 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | 316 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
317 | void rs690_bandwidth_update(struct radeon_device *rdev); | ||
297 | static struct radeon_asic rs690_asic = { | 318 | static struct radeon_asic rs690_asic = { |
298 | .init = &r300_init, | 319 | .init = &r300_init, |
299 | .errata = &rs690_errata, | 320 | .errata = &rs690_errata, |
@@ -322,6 +343,9 @@ static struct radeon_asic rs690_asic = { | |||
322 | .set_memory_clock = &radeon_atom_set_memory_clock, | 343 | .set_memory_clock = &radeon_atom_set_memory_clock, |
323 | .set_pcie_lanes = NULL, | 344 | .set_pcie_lanes = NULL, |
324 | .set_clock_gating = &radeon_atom_set_clock_gating, | 345 | .set_clock_gating = &radeon_atom_set_clock_gating, |
346 | .set_surface_reg = r100_set_surface_reg, | ||
347 | .clear_surface_reg = r100_clear_surface_reg, | ||
348 | .bandwidth_update = &rs690_bandwidth_update, | ||
325 | }; | 349 | }; |
326 | 350 | ||
327 | 351 | ||
@@ -339,6 +363,7 @@ void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |||
339 | void rv515_ring_start(struct radeon_device *rdev); | 363 | void rv515_ring_start(struct radeon_device *rdev); |
340 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); | 364 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
341 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | 365 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
366 | void rv515_bandwidth_update(struct radeon_device *rdev); | ||
342 | static struct radeon_asic rv515_asic = { | 367 | static struct radeon_asic rv515_asic = { |
343 | .init = &rv515_init, | 368 | .init = &rv515_init, |
344 | .errata = &rv515_errata, | 369 | .errata = &rv515_errata, |
@@ -367,6 +392,9 @@ static struct radeon_asic rv515_asic = { | |||
367 | .set_memory_clock = &radeon_atom_set_memory_clock, | 392 | .set_memory_clock = &radeon_atom_set_memory_clock, |
368 | .set_pcie_lanes = &rv370_set_pcie_lanes, | 393 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
369 | .set_clock_gating = &radeon_atom_set_clock_gating, | 394 | .set_clock_gating = &radeon_atom_set_clock_gating, |
395 | .set_surface_reg = r100_set_surface_reg, | ||
396 | .clear_surface_reg = r100_clear_surface_reg, | ||
397 | .bandwidth_update = &rv515_bandwidth_update, | ||
370 | }; | 398 | }; |
371 | 399 | ||
372 | 400 | ||
@@ -377,6 +405,7 @@ void r520_errata(struct radeon_device *rdev); | |||
377 | void r520_vram_info(struct radeon_device *rdev); | 405 | void r520_vram_info(struct radeon_device *rdev); |
378 | int r520_mc_init(struct radeon_device *rdev); | 406 | int r520_mc_init(struct radeon_device *rdev); |
379 | void r520_mc_fini(struct radeon_device *rdev); | 407 | void r520_mc_fini(struct radeon_device *rdev); |
408 | void r520_bandwidth_update(struct radeon_device *rdev); | ||
380 | static struct radeon_asic r520_asic = { | 409 | static struct radeon_asic r520_asic = { |
381 | .init = &rv515_init, | 410 | .init = &rv515_init, |
382 | .errata = &r520_errata, | 411 | .errata = &r520_errata, |
@@ -405,6 +434,9 @@ static struct radeon_asic r520_asic = { | |||
405 | .set_memory_clock = &radeon_atom_set_memory_clock, | 434 | .set_memory_clock = &radeon_atom_set_memory_clock, |
406 | .set_pcie_lanes = &rv370_set_pcie_lanes, | 435 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
407 | .set_clock_gating = &radeon_atom_set_clock_gating, | 436 | .set_clock_gating = &radeon_atom_set_clock_gating, |
437 | .set_surface_reg = r100_set_surface_reg, | ||
438 | .clear_surface_reg = r100_clear_surface_reg, | ||
439 | .bandwidth_update = &r520_bandwidth_update, | ||
408 | }; | 440 | }; |
409 | 441 | ||
410 | /* | 442 | /* |
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 1f5a1a490984..fcfe5c02d744 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c | |||
@@ -103,7 +103,8 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device | |||
103 | static bool radeon_atom_apply_quirks(struct drm_device *dev, | 103 | static bool radeon_atom_apply_quirks(struct drm_device *dev, |
104 | uint32_t supported_device, | 104 | uint32_t supported_device, |
105 | int *connector_type, | 105 | int *connector_type, |
106 | struct radeon_i2c_bus_rec *i2c_bus) | 106 | struct radeon_i2c_bus_rec *i2c_bus, |
107 | uint8_t *line_mux) | ||
107 | { | 108 | { |
108 | 109 | ||
109 | /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ | 110 | /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ |
@@ -127,8 +128,10 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, | |||
127 | if ((dev->pdev->device == 0x5653) && | 128 | if ((dev->pdev->device == 0x5653) && |
128 | (dev->pdev->subsystem_vendor == 0x1462) && | 129 | (dev->pdev->subsystem_vendor == 0x1462) && |
129 | (dev->pdev->subsystem_device == 0x0291)) { | 130 | (dev->pdev->subsystem_device == 0x0291)) { |
130 | if (*connector_type == DRM_MODE_CONNECTOR_LVDS) | 131 | if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { |
131 | i2c_bus->valid = false; | 132 | i2c_bus->valid = false; |
133 | *line_mux = 53; | ||
134 | } | ||
132 | } | 135 | } |
133 | 136 | ||
134 | /* Funky macbooks */ | 137 | /* Funky macbooks */ |
@@ -526,7 +529,7 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct | |||
526 | 529 | ||
527 | if (!radeon_atom_apply_quirks | 530 | if (!radeon_atom_apply_quirks |
528 | (dev, (1 << i), &bios_connectors[i].connector_type, | 531 | (dev, (1 << i), &bios_connectors[i].connector_type, |
529 | &bios_connectors[i].ddc_bus)) | 532 | &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux)) |
530 | continue; | 533 | continue; |
531 | 534 | ||
532 | bios_connectors[i].valid = true; | 535 | bios_connectors[i].valid = true; |
diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c index c44403a2ca76..2e938f7496fb 100644 --- a/drivers/gpu/drm/radeon/radeon_benchmark.c +++ b/drivers/gpu/drm/radeon/radeon_benchmark.c | |||
@@ -63,7 +63,7 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize, | |||
63 | if (r) { | 63 | if (r) { |
64 | goto out_cleanup; | 64 | goto out_cleanup; |
65 | } | 65 | } |
66 | r = radeon_copy_dma(rdev, saddr, daddr, size >> 14, fence); | 66 | r = radeon_copy_dma(rdev, saddr, daddr, size / 4096, fence); |
67 | if (r) { | 67 | if (r) { |
68 | goto out_cleanup; | 68 | goto out_cleanup; |
69 | } | 69 | } |
@@ -88,7 +88,7 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize, | |||
88 | if (r) { | 88 | if (r) { |
89 | goto out_cleanup; | 89 | goto out_cleanup; |
90 | } | 90 | } |
91 | r = radeon_copy_blit(rdev, saddr, daddr, size >> 14, fence); | 91 | r = radeon_copy_blit(rdev, saddr, daddr, size / 4096, fence); |
92 | if (r) { | 92 | if (r) { |
93 | goto out_cleanup; | 93 | goto out_cleanup; |
94 | } | 94 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index b843f9bdfb14..a169067efc4e 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c | |||
@@ -127,17 +127,23 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) | |||
127 | sizeof(struct drm_radeon_cs_chunk))) { | 127 | sizeof(struct drm_radeon_cs_chunk))) { |
128 | return -EFAULT; | 128 | return -EFAULT; |
129 | } | 129 | } |
130 | p->chunks[i].length_dw = user_chunk.length_dw; | ||
131 | p->chunks[i].kdata = NULL; | ||
130 | p->chunks[i].chunk_id = user_chunk.chunk_id; | 132 | p->chunks[i].chunk_id = user_chunk.chunk_id; |
133 | |||
131 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { | 134 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { |
132 | p->chunk_relocs_idx = i; | 135 | p->chunk_relocs_idx = i; |
133 | } | 136 | } |
134 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { | 137 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { |
135 | p->chunk_ib_idx = i; | 138 | p->chunk_ib_idx = i; |
139 | /* zero length IB isn't useful */ | ||
140 | if (p->chunks[i].length_dw == 0) | ||
141 | return -EINVAL; | ||
136 | } | 142 | } |
143 | |||
137 | p->chunks[i].length_dw = user_chunk.length_dw; | 144 | p->chunks[i].length_dw = user_chunk.length_dw; |
138 | cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; | 145 | cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; |
139 | 146 | ||
140 | p->chunks[i].kdata = NULL; | ||
141 | size = p->chunks[i].length_dw * sizeof(uint32_t); | 147 | size = p->chunks[i].length_dw * sizeof(uint32_t); |
142 | p->chunks[i].kdata = kzalloc(size, GFP_KERNEL); | 148 | p->chunks[i].kdata = kzalloc(size, GFP_KERNEL); |
143 | if (p->chunks[i].kdata == NULL) { | 149 | if (p->chunks[i].kdata == NULL) { |
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c index 5232441f119b..b13c79e38bc0 100644 --- a/drivers/gpu/drm/radeon/radeon_cursor.c +++ b/drivers/gpu/drm/radeon/radeon_cursor.c | |||
@@ -111,9 +111,11 @@ static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, | |||
111 | 111 | ||
112 | if (ASIC_IS_AVIVO(rdev)) | 112 | if (ASIC_IS_AVIVO(rdev)) |
113 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); | 113 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); |
114 | else | 114 | else { |
115 | radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; | ||
115 | /* offset is from DISP(2)_BASE_ADDRESS */ | 116 | /* offset is from DISP(2)_BASE_ADDRESS */ |
116 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, gpu_addr); | 117 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); |
118 | } | ||
117 | } | 119 | } |
118 | 120 | ||
119 | int radeon_crtc_cursor_set(struct drm_crtc *crtc, | 121 | int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
@@ -245,6 +247,9 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc, | |||
245 | (RADEON_CUR_LOCK | 247 | (RADEON_CUR_LOCK |
246 | | ((xorigin ? 0 : x) << 16) | 248 | | ((xorigin ? 0 : x) << 16) |
247 | | (yorigin ? 0 : y))); | 249 | | (yorigin ? 0 : y))); |
250 | /* offset is from DISP(2)_BASE_ADDRESS */ | ||
251 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset + | ||
252 | (yorigin * 256))); | ||
248 | } | 253 | } |
249 | radeon_lock_cursor(crtc, false); | 254 | radeon_lock_cursor(crtc, false); |
250 | 255 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index f97563db4e59..a162ade74b7f 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
@@ -48,6 +48,8 @@ static void radeon_surface_init(struct radeon_device *rdev) | |||
48 | i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), | 48 | i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), |
49 | 0); | 49 | 0); |
50 | } | 50 | } |
51 | /* enable surfaces */ | ||
52 | WREG32(RADEON_SURFACE_CNTL, 0); | ||
51 | } | 53 | } |
52 | } | 54 | } |
53 | 55 | ||
@@ -119,7 +121,7 @@ int radeon_mc_setup(struct radeon_device *rdev) | |||
119 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { | 121 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { |
120 | /* vram location was already setup try to put gtt after | 122 | /* vram location was already setup try to put gtt after |
121 | * if it fits */ | 123 | * if it fits */ |
122 | tmp = rdev->mc.vram_location + rdev->mc.vram_size; | 124 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; |
123 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); | 125 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
124 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { | 126 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { |
125 | rdev->mc.gtt_location = tmp; | 127 | rdev->mc.gtt_location = tmp; |
@@ -134,13 +136,13 @@ int radeon_mc_setup(struct radeon_device *rdev) | |||
134 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { | 136 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { |
135 | /* gtt location was already setup try to put vram before | 137 | /* gtt location was already setup try to put vram before |
136 | * if it fits */ | 138 | * if it fits */ |
137 | if (rdev->mc.vram_size < rdev->mc.gtt_location) { | 139 | if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { |
138 | rdev->mc.vram_location = 0; | 140 | rdev->mc.vram_location = 0; |
139 | } else { | 141 | } else { |
140 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; | 142 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; |
141 | tmp += (rdev->mc.vram_size - 1); | 143 | tmp += (rdev->mc.mc_vram_size - 1); |
142 | tmp &= ~(rdev->mc.vram_size - 1); | 144 | tmp &= ~(rdev->mc.mc_vram_size - 1); |
143 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) { | 145 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { |
144 | rdev->mc.vram_location = tmp; | 146 | rdev->mc.vram_location = tmp; |
145 | } else { | 147 | } else { |
146 | printk(KERN_ERR "[drm] vram too big to fit " | 148 | printk(KERN_ERR "[drm] vram too big to fit " |
@@ -150,12 +152,14 @@ int radeon_mc_setup(struct radeon_device *rdev) | |||
150 | } | 152 | } |
151 | } else { | 153 | } else { |
152 | rdev->mc.vram_location = 0; | 154 | rdev->mc.vram_location = 0; |
153 | rdev->mc.gtt_location = rdev->mc.vram_size; | 155 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
154 | } | 156 | } |
155 | DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20); | 157 | DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20); |
156 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", | 158 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", |
157 | rdev->mc.vram_location, | 159 | rdev->mc.vram_location, |
158 | rdev->mc.vram_location + rdev->mc.vram_size - 1); | 160 | rdev->mc.vram_location + rdev->mc.mc_vram_size - 1); |
161 | if (rdev->mc.real_vram_size != rdev->mc.mc_vram_size) | ||
162 | DRM_INFO("radeon: VRAM less than aperture workaround enabled\n"); | ||
159 | DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); | 163 | DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); |
160 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", | 164 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", |
161 | rdev->mc.gtt_location, | 165 | rdev->mc.gtt_location, |
@@ -450,6 +454,7 @@ int radeon_device_init(struct radeon_device *rdev, | |||
450 | uint32_t flags) | 454 | uint32_t flags) |
451 | { | 455 | { |
452 | int r, ret; | 456 | int r, ret; |
457 | int dma_bits; | ||
453 | 458 | ||
454 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); | 459 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); |
455 | rdev->shutdown = false; | 460 | rdev->shutdown = false; |
@@ -492,8 +497,20 @@ int radeon_device_init(struct radeon_device *rdev, | |||
492 | return r; | 497 | return r; |
493 | } | 498 | } |
494 | 499 | ||
495 | /* Report DMA addressing limitation */ | 500 | /* set DMA mask + need_dma32 flags. |
496 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); | 501 | * PCIE - can handle 40-bits. |
502 | * IGP - can handle 40-bits (in theory) | ||
503 | * AGP - generally dma32 is safest | ||
504 | * PCI - only dma32 | ||
505 | */ | ||
506 | rdev->need_dma32 = false; | ||
507 | if (rdev->flags & RADEON_IS_AGP) | ||
508 | rdev->need_dma32 = true; | ||
509 | if (rdev->flags & RADEON_IS_PCI) | ||
510 | rdev->need_dma32 = true; | ||
511 | |||
512 | dma_bits = rdev->need_dma32 ? 32 : 40; | ||
513 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); | ||
497 | if (r) { | 514 | if (r) { |
498 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); | 515 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
499 | } | 516 | } |
@@ -546,27 +563,22 @@ int radeon_device_init(struct radeon_device *rdev, | |||
546 | radeon_combios_asic_init(rdev->ddev); | 563 | radeon_combios_asic_init(rdev->ddev); |
547 | } | 564 | } |
548 | } | 565 | } |
566 | /* Initialize clocks */ | ||
567 | r = radeon_clocks_init(rdev); | ||
568 | if (r) { | ||
569 | return r; | ||
570 | } | ||
549 | /* Get vram informations */ | 571 | /* Get vram informations */ |
550 | radeon_vram_info(rdev); | 572 | radeon_vram_info(rdev); |
551 | /* Device is severly broken if aper size > vram size. | 573 | |
552 | * for RN50/M6/M7 - Novell bug 204882 ? | ||
553 | */ | ||
554 | if (rdev->mc.vram_size < rdev->mc.aper_size) { | ||
555 | rdev->mc.aper_size = rdev->mc.vram_size; | ||
556 | } | ||
557 | /* Add an MTRR for the VRAM */ | 574 | /* Add an MTRR for the VRAM */ |
558 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, | 575 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, |
559 | MTRR_TYPE_WRCOMB, 1); | 576 | MTRR_TYPE_WRCOMB, 1); |
560 | DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", | 577 | DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", |
561 | rdev->mc.vram_size >> 20, | 578 | rdev->mc.real_vram_size >> 20, |
562 | (unsigned)rdev->mc.aper_size >> 20); | 579 | (unsigned)rdev->mc.aper_size >> 20); |
563 | DRM_INFO("RAM width %dbits %cDR\n", | 580 | DRM_INFO("RAM width %dbits %cDR\n", |
564 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); | 581 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
565 | /* Initialize clocks */ | ||
566 | r = radeon_clocks_init(rdev); | ||
567 | if (r) { | ||
568 | return r; | ||
569 | } | ||
570 | /* Initialize memory controller (also test AGP) */ | 582 | /* Initialize memory controller (also test AGP) */ |
571 | r = radeon_mc_init(rdev); | 583 | r = radeon_mc_init(rdev); |
572 | if (r) { | 584 | if (r) { |
@@ -626,6 +638,9 @@ int radeon_device_init(struct radeon_device *rdev, | |||
626 | if (!ret) { | 638 | if (!ret) { |
627 | DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); | 639 | DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); |
628 | } | 640 | } |
641 | if (radeon_testing) { | ||
642 | radeon_test_moves(rdev); | ||
643 | } | ||
629 | if (radeon_benchmarking) { | 644 | if (radeon_benchmarking) { |
630 | radeon_benchmark(rdev); | 645 | radeon_benchmark(rdev); |
631 | } | 646 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 3efcf1a526be..a8fa1bb84cf7 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c | |||
@@ -187,6 +187,7 @@ static void radeon_crtc_init(struct drm_device *dev, int index) | |||
187 | 187 | ||
188 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); | 188 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
189 | radeon_crtc->crtc_id = index; | 189 | radeon_crtc->crtc_id = index; |
190 | rdev->mode_info.crtcs[index] = radeon_crtc; | ||
190 | 191 | ||
191 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; | 192 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
192 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); | 193 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
@@ -491,7 +492,11 @@ void radeon_compute_pll(struct radeon_pll *pll, | |||
491 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; | 492 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
492 | current_freq = radeon_div(tmp, ref_div * post_div); | 493 | current_freq = radeon_div(tmp, ref_div * post_div); |
493 | 494 | ||
494 | error = abs(current_freq - freq); | 495 | if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
496 | error = freq - current_freq; | ||
497 | error = error < 0 ? 0xffffffff : error; | ||
498 | } else | ||
499 | error = abs(current_freq - freq); | ||
495 | vco_diff = abs(vco - best_vco); | 500 | vco_diff = abs(vco - best_vco); |
496 | 501 | ||
497 | if ((best_vco == 0 && error < best_error) || | 502 | if ((best_vco == 0 && error < best_error) || |
@@ -657,36 +662,51 @@ void radeon_modeset_fini(struct radeon_device *rdev) | |||
657 | } | 662 | } |
658 | } | 663 | } |
659 | 664 | ||
660 | void radeon_init_disp_bandwidth(struct drm_device *dev) | 665 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
666 | struct drm_display_mode *mode, | ||
667 | struct drm_display_mode *adjusted_mode) | ||
661 | { | 668 | { |
662 | struct radeon_device *rdev = dev->dev_private; | 669 | struct drm_device *dev = crtc->dev; |
663 | struct drm_display_mode *modes[2]; | 670 | struct drm_encoder *encoder; |
664 | int pixel_bytes[2]; | 671 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
665 | struct drm_crtc *crtc; | 672 | struct radeon_encoder *radeon_encoder; |
666 | 673 | bool first = true; | |
667 | pixel_bytes[0] = pixel_bytes[1] = 0; | ||
668 | modes[0] = modes[1] = NULL; | ||
669 | |||
670 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | ||
671 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
672 | 674 | ||
673 | if (crtc->enabled && crtc->fb) { | 675 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
674 | modes[radeon_crtc->crtc_id] = &crtc->mode; | 676 | radeon_encoder = to_radeon_encoder(encoder); |
675 | pixel_bytes[radeon_crtc->crtc_id] = crtc->fb->bits_per_pixel / 8; | 677 | if (encoder->crtc != crtc) |
678 | continue; | ||
679 | if (first) { | ||
680 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; | ||
681 | radeon_crtc->devices = radeon_encoder->devices; | ||
682 | memcpy(&radeon_crtc->native_mode, | ||
683 | &radeon_encoder->native_mode, | ||
684 | sizeof(struct radeon_native_mode)); | ||
685 | first = false; | ||
686 | } else { | ||
687 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { | ||
688 | /* WARNING: Right now this can't happen but | ||
689 | * in the future we need to check that scaling | ||
690 | * are consistent accross different encoder | ||
691 | * (ie all encoder can work with the same | ||
692 | * scaling). | ||
693 | */ | ||
694 | DRM_ERROR("Scaling not consistent accross encoder.\n"); | ||
695 | return false; | ||
696 | } | ||
676 | } | 697 | } |
677 | } | 698 | } |
678 | 699 | if (radeon_crtc->rmx_type != RMX_OFF) { | |
679 | if (ASIC_IS_AVIVO(rdev)) { | 700 | fixed20_12 a, b; |
680 | radeon_init_disp_bw_avivo(dev, | 701 | a.full = rfixed_const(crtc->mode.vdisplay); |
681 | modes[0], | 702 | b.full = rfixed_const(radeon_crtc->native_mode.panel_xres); |
682 | pixel_bytes[0], | 703 | radeon_crtc->vsc.full = rfixed_div(a, b); |
683 | modes[1], | 704 | a.full = rfixed_const(crtc->mode.hdisplay); |
684 | pixel_bytes[1]); | 705 | b.full = rfixed_const(radeon_crtc->native_mode.panel_yres); |
706 | radeon_crtc->hsc.full = rfixed_div(a, b); | ||
685 | } else { | 707 | } else { |
686 | radeon_init_disp_bw_legacy(dev, | 708 | radeon_crtc->vsc.full = rfixed_const(1); |
687 | modes[0], | 709 | radeon_crtc->hsc.full = rfixed_const(1); |
688 | pixel_bytes[0], | ||
689 | modes[1], | ||
690 | pixel_bytes[1]); | ||
691 | } | 710 | } |
711 | return true; | ||
692 | } | 712 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 84ba69f48784..3cfcee17dc56 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c | |||
@@ -89,6 +89,7 @@ int radeon_agpmode = 0; | |||
89 | int radeon_vram_limit = 0; | 89 | int radeon_vram_limit = 0; |
90 | int radeon_gart_size = 512; /* default gart size */ | 90 | int radeon_gart_size = 512; /* default gart size */ |
91 | int radeon_benchmarking = 0; | 91 | int radeon_benchmarking = 0; |
92 | int radeon_testing = 0; | ||
92 | int radeon_connector_table = 0; | 93 | int radeon_connector_table = 0; |
93 | #endif | 94 | #endif |
94 | 95 | ||
@@ -117,6 +118,9 @@ module_param_named(gartsize, radeon_gart_size, int, 0600); | |||
117 | MODULE_PARM_DESC(benchmark, "Run benchmark"); | 118 | MODULE_PARM_DESC(benchmark, "Run benchmark"); |
118 | module_param_named(benchmark, radeon_benchmarking, int, 0444); | 119 | module_param_named(benchmark, radeon_benchmarking, int, 0444); |
119 | 120 | ||
121 | MODULE_PARM_DESC(test, "Run tests"); | ||
122 | module_param_named(test, radeon_testing, int, 0444); | ||
123 | |||
120 | MODULE_PARM_DESC(connector_table, "Force connector table"); | 124 | MODULE_PARM_DESC(connector_table, "Force connector table"); |
121 | module_param_named(connector_table, radeon_connector_table, int, 0444); | 125 | module_param_named(connector_table, radeon_connector_table, int, 0444); |
122 | #endif | 126 | #endif |
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index c8ef0d14ffab..0a92706eac19 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c | |||
@@ -154,7 +154,6 @@ void radeon_rmx_mode_fixup(struct drm_encoder *encoder, | |||
154 | 154 | ||
155 | if (mode->hdisplay < native_mode->panel_xres || | 155 | if (mode->hdisplay < native_mode->panel_xres || |
156 | mode->vdisplay < native_mode->panel_yres) { | 156 | mode->vdisplay < native_mode->panel_yres) { |
157 | radeon_encoder->flags |= RADEON_USE_RMX; | ||
158 | if (ASIC_IS_AVIVO(rdev)) { | 157 | if (ASIC_IS_AVIVO(rdev)) { |
159 | adjusted_mode->hdisplay = native_mode->panel_xres; | 158 | adjusted_mode->hdisplay = native_mode->panel_xres; |
160 | adjusted_mode->vdisplay = native_mode->panel_yres; | 159 | adjusted_mode->vdisplay = native_mode->panel_yres; |
@@ -197,15 +196,13 @@ void radeon_rmx_mode_fixup(struct drm_encoder *encoder, | |||
197 | } | 196 | } |
198 | } | 197 | } |
199 | 198 | ||
199 | |||
200 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, | 200 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
201 | struct drm_display_mode *mode, | 201 | struct drm_display_mode *mode, |
202 | struct drm_display_mode *adjusted_mode) | 202 | struct drm_display_mode *adjusted_mode) |
203 | { | 203 | { |
204 | |||
205 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 204 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
206 | 205 | ||
207 | radeon_encoder->flags &= ~RADEON_USE_RMX; | ||
208 | |||
209 | drm_mode_set_crtcinfo(adjusted_mode, 0); | 206 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
210 | 207 | ||
211 | if (radeon_encoder->rmx_type != RMX_OFF) | 208 | if (radeon_encoder->rmx_type != RMX_OFF) |
@@ -808,234 +805,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action) | |||
808 | 805 | ||
809 | } | 806 | } |
810 | 807 | ||
811 | static void atom_rv515_force_tv_scaler(struct radeon_device *rdev) | ||
812 | { | ||
813 | |||
814 | WREG32(0x659C, 0x0); | ||
815 | WREG32(0x6594, 0x705); | ||
816 | WREG32(0x65A4, 0x10001); | ||
817 | WREG32(0x65D8, 0x0); | ||
818 | WREG32(0x65B0, 0x0); | ||
819 | WREG32(0x65C0, 0x0); | ||
820 | WREG32(0x65D4, 0x0); | ||
821 | WREG32(0x6578, 0x0); | ||
822 | WREG32(0x657C, 0x841880A8); | ||
823 | WREG32(0x6578, 0x1); | ||
824 | WREG32(0x657C, 0x84208680); | ||
825 | WREG32(0x6578, 0x2); | ||
826 | WREG32(0x657C, 0xBFF880B0); | ||
827 | WREG32(0x6578, 0x100); | ||
828 | WREG32(0x657C, 0x83D88088); | ||
829 | WREG32(0x6578, 0x101); | ||
830 | WREG32(0x657C, 0x84608680); | ||
831 | WREG32(0x6578, 0x102); | ||
832 | WREG32(0x657C, 0xBFF080D0); | ||
833 | WREG32(0x6578, 0x200); | ||
834 | WREG32(0x657C, 0x83988068); | ||
835 | WREG32(0x6578, 0x201); | ||
836 | WREG32(0x657C, 0x84A08680); | ||
837 | WREG32(0x6578, 0x202); | ||
838 | WREG32(0x657C, 0xBFF080F8); | ||
839 | WREG32(0x6578, 0x300); | ||
840 | WREG32(0x657C, 0x83588058); | ||
841 | WREG32(0x6578, 0x301); | ||
842 | WREG32(0x657C, 0x84E08660); | ||
843 | WREG32(0x6578, 0x302); | ||
844 | WREG32(0x657C, 0xBFF88120); | ||
845 | WREG32(0x6578, 0x400); | ||
846 | WREG32(0x657C, 0x83188040); | ||
847 | WREG32(0x6578, 0x401); | ||
848 | WREG32(0x657C, 0x85008660); | ||
849 | WREG32(0x6578, 0x402); | ||
850 | WREG32(0x657C, 0xBFF88150); | ||
851 | WREG32(0x6578, 0x500); | ||
852 | WREG32(0x657C, 0x82D88030); | ||
853 | WREG32(0x6578, 0x501); | ||
854 | WREG32(0x657C, 0x85408640); | ||
855 | WREG32(0x6578, 0x502); | ||
856 | WREG32(0x657C, 0xBFF88180); | ||
857 | WREG32(0x6578, 0x600); | ||
858 | WREG32(0x657C, 0x82A08018); | ||
859 | WREG32(0x6578, 0x601); | ||
860 | WREG32(0x657C, 0x85808620); | ||
861 | WREG32(0x6578, 0x602); | ||
862 | WREG32(0x657C, 0xBFF081B8); | ||
863 | WREG32(0x6578, 0x700); | ||
864 | WREG32(0x657C, 0x82608010); | ||
865 | WREG32(0x6578, 0x701); | ||
866 | WREG32(0x657C, 0x85A08600); | ||
867 | WREG32(0x6578, 0x702); | ||
868 | WREG32(0x657C, 0x800081F0); | ||
869 | WREG32(0x6578, 0x800); | ||
870 | WREG32(0x657C, 0x8228BFF8); | ||
871 | WREG32(0x6578, 0x801); | ||
872 | WREG32(0x657C, 0x85E085E0); | ||
873 | WREG32(0x6578, 0x802); | ||
874 | WREG32(0x657C, 0xBFF88228); | ||
875 | WREG32(0x6578, 0x10000); | ||
876 | WREG32(0x657C, 0x82A8BF00); | ||
877 | WREG32(0x6578, 0x10001); | ||
878 | WREG32(0x657C, 0x82A08CC0); | ||
879 | WREG32(0x6578, 0x10002); | ||
880 | WREG32(0x657C, 0x8008BEF8); | ||
881 | WREG32(0x6578, 0x10100); | ||
882 | WREG32(0x657C, 0x81F0BF28); | ||
883 | WREG32(0x6578, 0x10101); | ||
884 | WREG32(0x657C, 0x83608CA0); | ||
885 | WREG32(0x6578, 0x10102); | ||
886 | WREG32(0x657C, 0x8018BED0); | ||
887 | WREG32(0x6578, 0x10200); | ||
888 | WREG32(0x657C, 0x8148BF38); | ||
889 | WREG32(0x6578, 0x10201); | ||
890 | WREG32(0x657C, 0x84408C80); | ||
891 | WREG32(0x6578, 0x10202); | ||
892 | WREG32(0x657C, 0x8008BEB8); | ||
893 | WREG32(0x6578, 0x10300); | ||
894 | WREG32(0x657C, 0x80B0BF78); | ||
895 | WREG32(0x6578, 0x10301); | ||
896 | WREG32(0x657C, 0x85008C20); | ||
897 | WREG32(0x6578, 0x10302); | ||
898 | WREG32(0x657C, 0x8020BEA0); | ||
899 | WREG32(0x6578, 0x10400); | ||
900 | WREG32(0x657C, 0x8028BF90); | ||
901 | WREG32(0x6578, 0x10401); | ||
902 | WREG32(0x657C, 0x85E08BC0); | ||
903 | WREG32(0x6578, 0x10402); | ||
904 | WREG32(0x657C, 0x8018BE90); | ||
905 | WREG32(0x6578, 0x10500); | ||
906 | WREG32(0x657C, 0xBFB8BFB0); | ||
907 | WREG32(0x6578, 0x10501); | ||
908 | WREG32(0x657C, 0x86C08B40); | ||
909 | WREG32(0x6578, 0x10502); | ||
910 | WREG32(0x657C, 0x8010BE90); | ||
911 | WREG32(0x6578, 0x10600); | ||
912 | WREG32(0x657C, 0xBF58BFC8); | ||
913 | WREG32(0x6578, 0x10601); | ||
914 | WREG32(0x657C, 0x87A08AA0); | ||
915 | WREG32(0x6578, 0x10602); | ||
916 | WREG32(0x657C, 0x8010BE98); | ||
917 | WREG32(0x6578, 0x10700); | ||
918 | WREG32(0x657C, 0xBF10BFF0); | ||
919 | WREG32(0x6578, 0x10701); | ||
920 | WREG32(0x657C, 0x886089E0); | ||
921 | WREG32(0x6578, 0x10702); | ||
922 | WREG32(0x657C, 0x8018BEB0); | ||
923 | WREG32(0x6578, 0x10800); | ||
924 | WREG32(0x657C, 0xBED8BFE8); | ||
925 | WREG32(0x6578, 0x10801); | ||
926 | WREG32(0x657C, 0x89408940); | ||
927 | WREG32(0x6578, 0x10802); | ||
928 | WREG32(0x657C, 0xBFE8BED8); | ||
929 | WREG32(0x6578, 0x20000); | ||
930 | WREG32(0x657C, 0x80008000); | ||
931 | WREG32(0x6578, 0x20001); | ||
932 | WREG32(0x657C, 0x90008000); | ||
933 | WREG32(0x6578, 0x20002); | ||
934 | WREG32(0x657C, 0x80008000); | ||
935 | WREG32(0x6578, 0x20003); | ||
936 | WREG32(0x657C, 0x80008000); | ||
937 | WREG32(0x6578, 0x20100); | ||
938 | WREG32(0x657C, 0x80108000); | ||
939 | WREG32(0x6578, 0x20101); | ||
940 | WREG32(0x657C, 0x8FE0BF70); | ||
941 | WREG32(0x6578, 0x20102); | ||
942 | WREG32(0x657C, 0xBFE880C0); | ||
943 | WREG32(0x6578, 0x20103); | ||
944 | WREG32(0x657C, 0x80008000); | ||
945 | WREG32(0x6578, 0x20200); | ||
946 | WREG32(0x657C, 0x8018BFF8); | ||
947 | WREG32(0x6578, 0x20201); | ||
948 | WREG32(0x657C, 0x8F80BF08); | ||
949 | WREG32(0x6578, 0x20202); | ||
950 | WREG32(0x657C, 0xBFD081A0); | ||
951 | WREG32(0x6578, 0x20203); | ||
952 | WREG32(0x657C, 0xBFF88000); | ||
953 | WREG32(0x6578, 0x20300); | ||
954 | WREG32(0x657C, 0x80188000); | ||
955 | WREG32(0x6578, 0x20301); | ||
956 | WREG32(0x657C, 0x8EE0BEC0); | ||
957 | WREG32(0x6578, 0x20302); | ||
958 | WREG32(0x657C, 0xBFB082A0); | ||
959 | WREG32(0x6578, 0x20303); | ||
960 | WREG32(0x657C, 0x80008000); | ||
961 | WREG32(0x6578, 0x20400); | ||
962 | WREG32(0x657C, 0x80188000); | ||
963 | WREG32(0x6578, 0x20401); | ||
964 | WREG32(0x657C, 0x8E00BEA0); | ||
965 | WREG32(0x6578, 0x20402); | ||
966 | WREG32(0x657C, 0xBF8883C0); | ||
967 | WREG32(0x6578, 0x20403); | ||
968 | WREG32(0x657C, 0x80008000); | ||
969 | WREG32(0x6578, 0x20500); | ||
970 | WREG32(0x657C, 0x80188000); | ||
971 | WREG32(0x6578, 0x20501); | ||
972 | WREG32(0x657C, 0x8D00BE90); | ||
973 | WREG32(0x6578, 0x20502); | ||
974 | WREG32(0x657C, 0xBF588500); | ||
975 | WREG32(0x6578, 0x20503); | ||
976 | WREG32(0x657C, 0x80008008); | ||
977 | WREG32(0x6578, 0x20600); | ||
978 | WREG32(0x657C, 0x80188000); | ||
979 | WREG32(0x6578, 0x20601); | ||
980 | WREG32(0x657C, 0x8BC0BE98); | ||
981 | WREG32(0x6578, 0x20602); | ||
982 | WREG32(0x657C, 0xBF308660); | ||
983 | WREG32(0x6578, 0x20603); | ||
984 | WREG32(0x657C, 0x80008008); | ||
985 | WREG32(0x6578, 0x20700); | ||
986 | WREG32(0x657C, 0x80108000); | ||
987 | WREG32(0x6578, 0x20701); | ||
988 | WREG32(0x657C, 0x8A80BEB0); | ||
989 | WREG32(0x6578, 0x20702); | ||
990 | WREG32(0x657C, 0xBF0087C0); | ||
991 | WREG32(0x6578, 0x20703); | ||
992 | WREG32(0x657C, 0x80008008); | ||
993 | WREG32(0x6578, 0x20800); | ||
994 | WREG32(0x657C, 0x80108000); | ||
995 | WREG32(0x6578, 0x20801); | ||
996 | WREG32(0x657C, 0x8920BED0); | ||
997 | WREG32(0x6578, 0x20802); | ||
998 | WREG32(0x657C, 0xBED08920); | ||
999 | WREG32(0x6578, 0x20803); | ||
1000 | WREG32(0x657C, 0x80008010); | ||
1001 | WREG32(0x6578, 0x30000); | ||
1002 | WREG32(0x657C, 0x90008000); | ||
1003 | WREG32(0x6578, 0x30001); | ||
1004 | WREG32(0x657C, 0x80008000); | ||
1005 | WREG32(0x6578, 0x30100); | ||
1006 | WREG32(0x657C, 0x8FE0BF90); | ||
1007 | WREG32(0x6578, 0x30101); | ||
1008 | WREG32(0x657C, 0xBFF880A0); | ||
1009 | WREG32(0x6578, 0x30200); | ||
1010 | WREG32(0x657C, 0x8F60BF40); | ||
1011 | WREG32(0x6578, 0x30201); | ||
1012 | WREG32(0x657C, 0xBFE88180); | ||
1013 | WREG32(0x6578, 0x30300); | ||
1014 | WREG32(0x657C, 0x8EC0BF00); | ||
1015 | WREG32(0x6578, 0x30301); | ||
1016 | WREG32(0x657C, 0xBFC88280); | ||
1017 | WREG32(0x6578, 0x30400); | ||
1018 | WREG32(0x657C, 0x8DE0BEE0); | ||
1019 | WREG32(0x6578, 0x30401); | ||
1020 | WREG32(0x657C, 0xBFA083A0); | ||
1021 | WREG32(0x6578, 0x30500); | ||
1022 | WREG32(0x657C, 0x8CE0BED0); | ||
1023 | WREG32(0x6578, 0x30501); | ||
1024 | WREG32(0x657C, 0xBF7884E0); | ||
1025 | WREG32(0x6578, 0x30600); | ||
1026 | WREG32(0x657C, 0x8BA0BED8); | ||
1027 | WREG32(0x6578, 0x30601); | ||
1028 | WREG32(0x657C, 0xBF508640); | ||
1029 | WREG32(0x6578, 0x30700); | ||
1030 | WREG32(0x657C, 0x8A60BEE8); | ||
1031 | WREG32(0x6578, 0x30701); | ||
1032 | WREG32(0x657C, 0xBF2087A0); | ||
1033 | WREG32(0x6578, 0x30800); | ||
1034 | WREG32(0x657C, 0x8900BF00); | ||
1035 | WREG32(0x6578, 0x30801); | ||
1036 | WREG32(0x657C, 0xBF008900); | ||
1037 | } | ||
1038 | |||
1039 | static void | 808 | static void |
1040 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) | 809 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
1041 | { | 810 | { |
@@ -1074,129 +843,6 @@ atombios_yuv_setup(struct drm_encoder *encoder, bool enable) | |||
1074 | } | 843 | } |
1075 | 844 | ||
1076 | static void | 845 | static void |
1077 | atombios_overscan_setup(struct drm_encoder *encoder, | ||
1078 | struct drm_display_mode *mode, | ||
1079 | struct drm_display_mode *adjusted_mode) | ||
1080 | { | ||
1081 | struct drm_device *dev = encoder->dev; | ||
1082 | struct radeon_device *rdev = dev->dev_private; | ||
1083 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | ||
1084 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | ||
1085 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; | ||
1086 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); | ||
1087 | |||
1088 | memset(&args, 0, sizeof(args)); | ||
1089 | |||
1090 | args.usOverscanRight = 0; | ||
1091 | args.usOverscanLeft = 0; | ||
1092 | args.usOverscanBottom = 0; | ||
1093 | args.usOverscanTop = 0; | ||
1094 | args.ucCRTC = radeon_crtc->crtc_id; | ||
1095 | |||
1096 | if (radeon_encoder->flags & RADEON_USE_RMX) { | ||
1097 | if (radeon_encoder->rmx_type == RMX_FULL) { | ||
1098 | args.usOverscanRight = 0; | ||
1099 | args.usOverscanLeft = 0; | ||
1100 | args.usOverscanBottom = 0; | ||
1101 | args.usOverscanTop = 0; | ||
1102 | } else if (radeon_encoder->rmx_type == RMX_CENTER) { | ||
1103 | args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; | ||
1104 | args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; | ||
1105 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; | ||
1106 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; | ||
1107 | } else if (radeon_encoder->rmx_type == RMX_ASPECT) { | ||
1108 | int a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; | ||
1109 | int a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; | ||
1110 | |||
1111 | if (a1 > a2) { | ||
1112 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; | ||
1113 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; | ||
1114 | } else if (a2 > a1) { | ||
1115 | args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; | ||
1116 | args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; | ||
1117 | } | ||
1118 | } | ||
1119 | } | ||
1120 | |||
1121 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | ||
1122 | |||
1123 | } | ||
1124 | |||
1125 | static void | ||
1126 | atombios_scaler_setup(struct drm_encoder *encoder) | ||
1127 | { | ||
1128 | struct drm_device *dev = encoder->dev; | ||
1129 | struct radeon_device *rdev = dev->dev_private; | ||
1130 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | ||
1131 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | ||
1132 | ENABLE_SCALER_PS_ALLOCATION args; | ||
1133 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); | ||
1134 | /* fixme - fill in enc_priv for atom dac */ | ||
1135 | enum radeon_tv_std tv_std = TV_STD_NTSC; | ||
1136 | |||
1137 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) | ||
1138 | return; | ||
1139 | |||
1140 | memset(&args, 0, sizeof(args)); | ||
1141 | |||
1142 | args.ucScaler = radeon_crtc->crtc_id; | ||
1143 | |||
1144 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { | ||
1145 | switch (tv_std) { | ||
1146 | case TV_STD_NTSC: | ||
1147 | default: | ||
1148 | args.ucTVStandard = ATOM_TV_NTSC; | ||
1149 | break; | ||
1150 | case TV_STD_PAL: | ||
1151 | args.ucTVStandard = ATOM_TV_PAL; | ||
1152 | break; | ||
1153 | case TV_STD_PAL_M: | ||
1154 | args.ucTVStandard = ATOM_TV_PALM; | ||
1155 | break; | ||
1156 | case TV_STD_PAL_60: | ||
1157 | args.ucTVStandard = ATOM_TV_PAL60; | ||
1158 | break; | ||
1159 | case TV_STD_NTSC_J: | ||
1160 | args.ucTVStandard = ATOM_TV_NTSCJ; | ||
1161 | break; | ||
1162 | case TV_STD_SCART_PAL: | ||
1163 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ | ||
1164 | break; | ||
1165 | case TV_STD_SECAM: | ||
1166 | args.ucTVStandard = ATOM_TV_SECAM; | ||
1167 | break; | ||
1168 | case TV_STD_PAL_CN: | ||
1169 | args.ucTVStandard = ATOM_TV_PALCN; | ||
1170 | break; | ||
1171 | } | ||
1172 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; | ||
1173 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) { | ||
1174 | args.ucTVStandard = ATOM_TV_CV; | ||
1175 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; | ||
1176 | } else if (radeon_encoder->flags & RADEON_USE_RMX) { | ||
1177 | if (radeon_encoder->rmx_type == RMX_FULL) | ||
1178 | args.ucEnable = ATOM_SCALER_EXPANSION; | ||
1179 | else if (radeon_encoder->rmx_type == RMX_CENTER) | ||
1180 | args.ucEnable = ATOM_SCALER_CENTER; | ||
1181 | else if (radeon_encoder->rmx_type == RMX_ASPECT) | ||
1182 | args.ucEnable = ATOM_SCALER_EXPANSION; | ||
1183 | } else { | ||
1184 | if (ASIC_IS_AVIVO(rdev)) | ||
1185 | args.ucEnable = ATOM_SCALER_DISABLE; | ||
1186 | else | ||
1187 | args.ucEnable = ATOM_SCALER_CENTER; | ||
1188 | } | ||
1189 | |||
1190 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | ||
1191 | |||
1192 | if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT) | ||
1193 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) { | ||
1194 | atom_rv515_force_tv_scaler(rdev); | ||
1195 | } | ||
1196 | |||
1197 | } | ||
1198 | |||
1199 | static void | ||
1200 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | 846 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
1201 | { | 847 | { |
1202 | struct drm_device *dev = encoder->dev; | 848 | struct drm_device *dev = encoder->dev; |
@@ -1448,8 +1094,6 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |||
1448 | radeon_encoder->pixel_clock = adjusted_mode->clock; | 1094 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
1449 | 1095 | ||
1450 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); | 1096 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
1451 | atombios_overscan_setup(encoder, mode, adjusted_mode); | ||
1452 | atombios_scaler_setup(encoder); | ||
1453 | atombios_set_encoder_crtc_source(encoder); | 1097 | atombios_set_encoder_crtc_source(encoder); |
1454 | 1098 | ||
1455 | if (ASIC_IS_AVIVO(rdev)) { | 1099 | if (ASIC_IS_AVIVO(rdev)) { |
@@ -1667,6 +1311,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su | |||
1667 | 1311 | ||
1668 | radeon_encoder->encoder_id = encoder_id; | 1312 | radeon_encoder->encoder_id = encoder_id; |
1669 | radeon_encoder->devices = supported_device; | 1313 | radeon_encoder->devices = supported_device; |
1314 | radeon_encoder->rmx_type = RMX_OFF; | ||
1670 | 1315 | ||
1671 | switch (radeon_encoder->encoder_id) { | 1316 | switch (radeon_encoder->encoder_id) { |
1672 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | 1317 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 9e8f191eb64a..3206c0ad7b6c 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c | |||
@@ -101,9 +101,10 @@ static int radeonfb_setcolreg(unsigned regno, | |||
101 | break; | 101 | break; |
102 | case 24: | 102 | case 24: |
103 | case 32: | 103 | case 32: |
104 | fb->pseudo_palette[regno] = ((red & 0xff00) << 8) | | 104 | fb->pseudo_palette[regno] = |
105 | (green & 0xff00) | | 105 | (((red >> 8) & 0xff) << info->var.red.offset) | |
106 | ((blue & 0xff00) >> 8); | 106 | (((green >> 8) & 0xff) << info->var.green.offset) | |
107 | (((blue >> 8) & 0xff) << info->var.blue.offset); | ||
107 | break; | 108 | break; |
108 | } | 109 | } |
109 | } | 110 | } |
@@ -154,6 +155,7 @@ static int radeonfb_check_var(struct fb_var_screeninfo *var, | |||
154 | var->transp.length = 0; | 155 | var->transp.length = 0; |
155 | var->transp.offset = 0; | 156 | var->transp.offset = 0; |
156 | break; | 157 | break; |
158 | #ifdef __LITTLE_ENDIAN | ||
157 | case 15: | 159 | case 15: |
158 | var->red.offset = 10; | 160 | var->red.offset = 10; |
159 | var->green.offset = 5; | 161 | var->green.offset = 5; |
@@ -194,6 +196,28 @@ static int radeonfb_check_var(struct fb_var_screeninfo *var, | |||
194 | var->transp.length = 8; | 196 | var->transp.length = 8; |
195 | var->transp.offset = 24; | 197 | var->transp.offset = 24; |
196 | break; | 198 | break; |
199 | #else | ||
200 | case 24: | ||
201 | var->red.offset = 8; | ||
202 | var->green.offset = 16; | ||
203 | var->blue.offset = 24; | ||
204 | var->red.length = 8; | ||
205 | var->green.length = 8; | ||
206 | var->blue.length = 8; | ||
207 | var->transp.length = 0; | ||
208 | var->transp.offset = 0; | ||
209 | break; | ||
210 | case 32: | ||
211 | var->red.offset = 8; | ||
212 | var->green.offset = 16; | ||
213 | var->blue.offset = 24; | ||
214 | var->red.length = 8; | ||
215 | var->green.length = 8; | ||
216 | var->blue.length = 8; | ||
217 | var->transp.length = 8; | ||
218 | var->transp.offset = 0; | ||
219 | break; | ||
220 | #endif | ||
197 | default: | 221 | default: |
198 | return -EINVAL; | 222 | return -EINVAL; |
199 | } | 223 | } |
@@ -447,10 +471,10 @@ static struct notifier_block paniced = { | |||
447 | .notifier_call = radeonfb_panic, | 471 | .notifier_call = radeonfb_panic, |
448 | }; | 472 | }; |
449 | 473 | ||
450 | static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp) | 474 | static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) |
451 | { | 475 | { |
452 | int aligned = width; | 476 | int aligned = width; |
453 | int align_large = (ASIC_IS_AVIVO(rdev)); | 477 | int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; |
454 | int pitch_mask = 0; | 478 | int pitch_mask = 0; |
455 | 479 | ||
456 | switch (bpp / 8) { | 480 | switch (bpp / 8) { |
@@ -488,12 +512,13 @@ int radeonfb_create(struct radeon_device *rdev, | |||
488 | u64 fb_gpuaddr; | 512 | u64 fb_gpuaddr; |
489 | void *fbptr = NULL; | 513 | void *fbptr = NULL; |
490 | unsigned long tmp; | 514 | unsigned long tmp; |
515 | bool fb_tiled = false; /* useful for testing */ | ||
491 | 516 | ||
492 | mode_cmd.width = surface_width; | 517 | mode_cmd.width = surface_width; |
493 | mode_cmd.height = surface_height; | 518 | mode_cmd.height = surface_height; |
494 | mode_cmd.bpp = 32; | 519 | mode_cmd.bpp = 32; |
495 | /* need to align pitch with crtc limits */ | 520 | /* need to align pitch with crtc limits */ |
496 | mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp) * ((mode_cmd.bpp + 1) / 8); | 521 | mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8); |
497 | mode_cmd.depth = 24; | 522 | mode_cmd.depth = 24; |
498 | 523 | ||
499 | size = mode_cmd.pitch * mode_cmd.height; | 524 | size = mode_cmd.pitch * mode_cmd.height; |
@@ -511,6 +536,8 @@ int radeonfb_create(struct radeon_device *rdev, | |||
511 | } | 536 | } |
512 | robj = gobj->driver_private; | 537 | robj = gobj->driver_private; |
513 | 538 | ||
539 | if (fb_tiled) | ||
540 | radeon_object_set_tiling_flags(robj, RADEON_TILING_MACRO|RADEON_TILING_SURFACE, mode_cmd.pitch); | ||
514 | mutex_lock(&rdev->ddev->struct_mutex); | 541 | mutex_lock(&rdev->ddev->struct_mutex); |
515 | fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj); | 542 | fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj); |
516 | if (fb == NULL) { | 543 | if (fb == NULL) { |
@@ -539,6 +566,9 @@ int radeonfb_create(struct radeon_device *rdev, | |||
539 | } | 566 | } |
540 | rfbdev = info->par; | 567 | rfbdev = info->par; |
541 | 568 | ||
569 | if (fb_tiled) | ||
570 | radeon_object_check_tiling(robj, 0, 0); | ||
571 | |||
542 | ret = radeon_object_kmap(robj, &fbptr); | 572 | ret = radeon_object_kmap(robj, &fbptr); |
543 | if (ret) { | 573 | if (ret) { |
544 | goto out_unref; | 574 | goto out_unref; |
@@ -572,6 +602,11 @@ int radeonfb_create(struct radeon_device *rdev, | |||
572 | info->var.width = -1; | 602 | info->var.width = -1; |
573 | info->var.xres = fb_width; | 603 | info->var.xres = fb_width; |
574 | info->var.yres = fb_height; | 604 | info->var.yres = fb_height; |
605 | |||
606 | /* setup aperture base/size for vesafb takeover */ | ||
607 | info->aperture_base = rdev->ddev->mode_config.fb_base; | ||
608 | info->aperture_size = rdev->mc.real_vram_size; | ||
609 | |||
575 | info->fix.mmio_start = 0; | 610 | info->fix.mmio_start = 0; |
576 | info->fix.mmio_len = 0; | 611 | info->fix.mmio_len = 0; |
577 | info->pixmap.size = 64*1024; | 612 | info->pixmap.size = 64*1024; |
@@ -600,6 +635,7 @@ int radeonfb_create(struct radeon_device *rdev, | |||
600 | info->var.transp.offset = 0; | 635 | info->var.transp.offset = 0; |
601 | info->var.transp.length = 0; | 636 | info->var.transp.length = 0; |
602 | break; | 637 | break; |
638 | #ifdef __LITTLE_ENDIAN | ||
603 | case 15: | 639 | case 15: |
604 | info->var.red.offset = 10; | 640 | info->var.red.offset = 10; |
605 | info->var.green.offset = 5; | 641 | info->var.green.offset = 5; |
@@ -639,7 +675,29 @@ int radeonfb_create(struct radeon_device *rdev, | |||
639 | info->var.transp.offset = 24; | 675 | info->var.transp.offset = 24; |
640 | info->var.transp.length = 8; | 676 | info->var.transp.length = 8; |
641 | break; | 677 | break; |
678 | #else | ||
679 | case 24: | ||
680 | info->var.red.offset = 8; | ||
681 | info->var.green.offset = 16; | ||
682 | info->var.blue.offset = 24; | ||
683 | info->var.red.length = 8; | ||
684 | info->var.green.length = 8; | ||
685 | info->var.blue.length = 8; | ||
686 | info->var.transp.offset = 0; | ||
687 | info->var.transp.length = 0; | ||
688 | break; | ||
689 | case 32: | ||
690 | info->var.red.offset = 8; | ||
691 | info->var.green.offset = 16; | ||
692 | info->var.blue.offset = 24; | ||
693 | info->var.red.length = 8; | ||
694 | info->var.green.length = 8; | ||
695 | info->var.blue.length = 8; | ||
696 | info->var.transp.offset = 0; | ||
697 | info->var.transp.length = 8; | ||
698 | break; | ||
642 | default: | 699 | default: |
700 | #endif | ||
643 | break; | 701 | break; |
644 | } | 702 | } |
645 | 703 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c index 96afbf5ae2ad..b4e48dd2e859 100644 --- a/drivers/gpu/drm/radeon/radeon_fence.c +++ b/drivers/gpu/drm/radeon/radeon_fence.c | |||
@@ -195,7 +195,7 @@ retry: | |||
195 | r = wait_event_interruptible_timeout(rdev->fence_drv.queue, | 195 | r = wait_event_interruptible_timeout(rdev->fence_drv.queue, |
196 | radeon_fence_signaled(fence), timeout); | 196 | radeon_fence_signaled(fence), timeout); |
197 | if (unlikely(r == -ERESTARTSYS)) { | 197 | if (unlikely(r == -ERESTARTSYS)) { |
198 | return -ERESTART; | 198 | return -EBUSY; |
199 | } | 199 | } |
200 | } else { | 200 | } else { |
201 | r = wait_event_timeout(rdev->fence_drv.queue, | 201 | r = wait_event_timeout(rdev->fence_drv.queue, |
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c index d343a15316ec..2977539880fb 100644 --- a/drivers/gpu/drm/radeon/radeon_gart.c +++ b/drivers/gpu/drm/radeon/radeon_gart.c | |||
@@ -177,7 +177,7 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |||
177 | return -ENOMEM; | 177 | return -ENOMEM; |
178 | } | 178 | } |
179 | rdev->gart.pages[p] = pagelist[i]; | 179 | rdev->gart.pages[p] = pagelist[i]; |
180 | page_base = (uint32_t)rdev->gart.pages_addr[p]; | 180 | page_base = rdev->gart.pages_addr[p]; |
181 | for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) { | 181 | for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) { |
182 | radeon_gart_set_page(rdev, t, page_base); | 182 | radeon_gart_set_page(rdev, t, page_base); |
183 | page_base += 4096; | 183 | page_base += 4096; |
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index eb516034235d..cded5180c752 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c | |||
@@ -157,9 +157,9 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |||
157 | struct radeon_device *rdev = dev->dev_private; | 157 | struct radeon_device *rdev = dev->dev_private; |
158 | struct drm_radeon_gem_info *args = data; | 158 | struct drm_radeon_gem_info *args = data; |
159 | 159 | ||
160 | args->vram_size = rdev->mc.vram_size; | 160 | args->vram_size = rdev->mc.real_vram_size; |
161 | /* FIXME: report somethings that makes sense */ | 161 | /* FIXME: report somethings that makes sense */ |
162 | args->vram_visible = rdev->mc.vram_size - (4 * 1024 * 1024); | 162 | args->vram_visible = rdev->mc.real_vram_size - (4 * 1024 * 1024); |
163 | args->gart_size = rdev->mc.gtt_size; | 163 | args->gart_size = rdev->mc.gtt_size; |
164 | return 0; | 164 | return 0; |
165 | } | 165 | } |
@@ -285,3 +285,44 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |||
285 | mutex_unlock(&dev->struct_mutex); | 285 | mutex_unlock(&dev->struct_mutex); |
286 | return r; | 286 | return r; |
287 | } | 287 | } |
288 | |||
289 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, | ||
290 | struct drm_file *filp) | ||
291 | { | ||
292 | struct drm_radeon_gem_set_tiling *args = data; | ||
293 | struct drm_gem_object *gobj; | ||
294 | struct radeon_object *robj; | ||
295 | int r = 0; | ||
296 | |||
297 | DRM_DEBUG("%d \n", args->handle); | ||
298 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | ||
299 | if (gobj == NULL) | ||
300 | return -EINVAL; | ||
301 | robj = gobj->driver_private; | ||
302 | radeon_object_set_tiling_flags(robj, args->tiling_flags, args->pitch); | ||
303 | mutex_lock(&dev->struct_mutex); | ||
304 | drm_gem_object_unreference(gobj); | ||
305 | mutex_unlock(&dev->struct_mutex); | ||
306 | return r; | ||
307 | } | ||
308 | |||
309 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | ||
310 | struct drm_file *filp) | ||
311 | { | ||
312 | struct drm_radeon_gem_get_tiling *args = data; | ||
313 | struct drm_gem_object *gobj; | ||
314 | struct radeon_object *robj; | ||
315 | int r = 0; | ||
316 | |||
317 | DRM_DEBUG("\n"); | ||
318 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | ||
319 | if (gobj == NULL) | ||
320 | return -EINVAL; | ||
321 | robj = gobj->driver_private; | ||
322 | radeon_object_get_tiling_flags(robj, &args->tiling_flags, | ||
323 | &args->pitch); | ||
324 | mutex_lock(&dev->struct_mutex); | ||
325 | drm_gem_object_unreference(gobj); | ||
326 | mutex_unlock(&dev->struct_mutex); | ||
327 | return r; | ||
328 | } | ||
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index 4612a7c146d1..937a2f1cdb46 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c | |||
@@ -291,5 +291,7 @@ struct drm_ioctl_desc radeon_ioctls_kms[] = { | |||
291 | DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH), | 291 | DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH), |
292 | DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH), | 292 | DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH), |
293 | DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH), | 293 | DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH), |
294 | DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH), | ||
295 | DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH), | ||
294 | }; | 296 | }; |
295 | int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); | 297 | int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); |
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index 8086ecf7f03d..7d06dc98a42a 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c | |||
@@ -29,6 +29,171 @@ | |||
29 | #include "radeon_fixed.h" | 29 | #include "radeon_fixed.h" |
30 | #include "radeon.h" | 30 | #include "radeon.h" |
31 | 31 | ||
32 | static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, | ||
33 | struct drm_display_mode *mode, | ||
34 | struct drm_display_mode *adjusted_mode) | ||
35 | { | ||
36 | struct drm_device *dev = crtc->dev; | ||
37 | struct radeon_device *rdev = dev->dev_private; | ||
38 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
39 | int xres = mode->hdisplay; | ||
40 | int yres = mode->vdisplay; | ||
41 | bool hscale = true, vscale = true; | ||
42 | int hsync_wid; | ||
43 | int vsync_wid; | ||
44 | int hsync_start; | ||
45 | int blank_width; | ||
46 | u32 scale, inc, crtc_more_cntl; | ||
47 | u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; | ||
48 | u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; | ||
49 | u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; | ||
50 | struct radeon_native_mode *native_mode = &radeon_crtc->native_mode; | ||
51 | |||
52 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & | ||
53 | (RADEON_VERT_STRETCH_RESERVED | | ||
54 | RADEON_VERT_AUTO_RATIO_INC); | ||
55 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & | ||
56 | (RADEON_HORZ_FP_LOOP_STRETCH | | ||
57 | RADEON_HORZ_AUTO_RATIO_INC); | ||
58 | |||
59 | crtc_more_cntl = 0; | ||
60 | if ((rdev->family == CHIP_RS100) || | ||
61 | (rdev->family == CHIP_RS200)) { | ||
62 | /* This is to workaround the asic bug for RMX, some versions | ||
63 | of BIOS dosen't have this register initialized correctly. */ | ||
64 | crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; | ||
65 | } | ||
66 | |||
67 | |||
68 | fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) | ||
69 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); | ||
70 | |||
71 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; | ||
72 | if (!hsync_wid) | ||
73 | hsync_wid = 1; | ||
74 | hsync_start = mode->crtc_hsync_start - 8; | ||
75 | |||
76 | fp_h_sync_strt_wid = ((hsync_start & 0x1fff) | ||
77 | | ((hsync_wid & 0x3f) << 16) | ||
78 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) | ||
79 | ? RADEON_CRTC_H_SYNC_POL | ||
80 | : 0)); | ||
81 | |||
82 | fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) | ||
83 | | ((mode->crtc_vdisplay - 1) << 16)); | ||
84 | |||
85 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; | ||
86 | if (!vsync_wid) | ||
87 | vsync_wid = 1; | ||
88 | |||
89 | fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) | ||
90 | | ((vsync_wid & 0x1f) << 16) | ||
91 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) | ||
92 | ? RADEON_CRTC_V_SYNC_POL | ||
93 | : 0)); | ||
94 | |||
95 | fp_horz_vert_active = 0; | ||
96 | |||
97 | if (native_mode->panel_xres == 0 || | ||
98 | native_mode->panel_yres == 0) { | ||
99 | hscale = false; | ||
100 | vscale = false; | ||
101 | } else { | ||
102 | if (xres > native_mode->panel_xres) | ||
103 | xres = native_mode->panel_xres; | ||
104 | if (yres > native_mode->panel_yres) | ||
105 | yres = native_mode->panel_yres; | ||
106 | |||
107 | if (xres == native_mode->panel_xres) | ||
108 | hscale = false; | ||
109 | if (yres == native_mode->panel_yres) | ||
110 | vscale = false; | ||
111 | } | ||
112 | |||
113 | switch (radeon_crtc->rmx_type) { | ||
114 | case RMX_FULL: | ||
115 | case RMX_ASPECT: | ||
116 | if (!hscale) | ||
117 | fp_horz_stretch |= ((xres/8-1) << 16); | ||
118 | else { | ||
119 | inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; | ||
120 | scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) | ||
121 | / native_mode->panel_xres + 1; | ||
122 | fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | | ||
123 | RADEON_HORZ_STRETCH_BLEND | | ||
124 | RADEON_HORZ_STRETCH_ENABLE | | ||
125 | ((native_mode->panel_xres/8-1) << 16)); | ||
126 | } | ||
127 | |||
128 | if (!vscale) | ||
129 | fp_vert_stretch |= ((yres-1) << 12); | ||
130 | else { | ||
131 | inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; | ||
132 | scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) | ||
133 | / native_mode->panel_yres + 1; | ||
134 | fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | | ||
135 | RADEON_VERT_STRETCH_ENABLE | | ||
136 | RADEON_VERT_STRETCH_BLEND | | ||
137 | ((native_mode->panel_yres-1) << 12)); | ||
138 | } | ||
139 | break; | ||
140 | case RMX_CENTER: | ||
141 | fp_horz_stretch |= ((xres/8-1) << 16); | ||
142 | fp_vert_stretch |= ((yres-1) << 12); | ||
143 | |||
144 | crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | | ||
145 | RADEON_CRTC_AUTO_VERT_CENTER_EN); | ||
146 | |||
147 | blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; | ||
148 | if (blank_width > 110) | ||
149 | blank_width = 110; | ||
150 | |||
151 | fp_crtc_h_total_disp = (((blank_width) & 0x3ff) | ||
152 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); | ||
153 | |||
154 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; | ||
155 | if (!hsync_wid) | ||
156 | hsync_wid = 1; | ||
157 | |||
158 | fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) | ||
159 | | ((hsync_wid & 0x3f) << 16) | ||
160 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) | ||
161 | ? RADEON_CRTC_H_SYNC_POL | ||
162 | : 0)); | ||
163 | |||
164 | fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) | ||
165 | | ((mode->crtc_vdisplay - 1) << 16)); | ||
166 | |||
167 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; | ||
168 | if (!vsync_wid) | ||
169 | vsync_wid = 1; | ||
170 | |||
171 | fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) | ||
172 | | ((vsync_wid & 0x1f) << 16) | ||
173 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) | ||
174 | ? RADEON_CRTC_V_SYNC_POL | ||
175 | : 0))); | ||
176 | |||
177 | fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) | | ||
178 | (((native_mode->panel_xres / 8) & 0x1ff) << 16)); | ||
179 | break; | ||
180 | case RMX_OFF: | ||
181 | default: | ||
182 | fp_horz_stretch |= ((xres/8-1) << 16); | ||
183 | fp_vert_stretch |= ((yres-1) << 12); | ||
184 | break; | ||
185 | } | ||
186 | |||
187 | WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); | ||
188 | WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); | ||
189 | WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); | ||
190 | WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); | ||
191 | WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); | ||
192 | WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); | ||
193 | WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); | ||
194 | WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); | ||
195 | } | ||
196 | |||
32 | void radeon_restore_common_regs(struct drm_device *dev) | 197 | void radeon_restore_common_regs(struct drm_device *dev) |
33 | { | 198 | { |
34 | /* don't need this yet */ | 199 | /* don't need this yet */ |
@@ -235,6 +400,7 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
235 | uint64_t base; | 400 | uint64_t base; |
236 | uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; | 401 | uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; |
237 | uint32_t crtc_pitch, pitch_pixels; | 402 | uint32_t crtc_pitch, pitch_pixels; |
403 | uint32_t tiling_flags; | ||
238 | 404 | ||
239 | DRM_DEBUG("\n"); | 405 | DRM_DEBUG("\n"); |
240 | 406 | ||
@@ -244,7 +410,12 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
244 | if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) { | 410 | if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) { |
245 | return -EINVAL; | 411 | return -EINVAL; |
246 | } | 412 | } |
247 | crtc_offset = (u32)base; | 413 | /* if scanout was in GTT this really wouldn't work */ |
414 | /* crtc offset is from display base addr not FB location */ | ||
415 | radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location; | ||
416 | |||
417 | base -= radeon_crtc->legacy_display_base_addr; | ||
418 | |||
248 | crtc_offset_cntl = 0; | 419 | crtc_offset_cntl = 0; |
249 | 420 | ||
250 | pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); | 421 | pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
@@ -253,8 +424,12 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
253 | (crtc->fb->bits_per_pixel * 8)); | 424 | (crtc->fb->bits_per_pixel * 8)); |
254 | crtc_pitch |= crtc_pitch << 16; | 425 | crtc_pitch |= crtc_pitch << 16; |
255 | 426 | ||
256 | /* TODO tiling */ | 427 | radeon_object_get_tiling_flags(obj->driver_private, |
257 | if (0) { | 428 | &tiling_flags, NULL); |
429 | if (tiling_flags & RADEON_TILING_MICRO) | ||
430 | DRM_ERROR("trying to scanout microtiled buffer\n"); | ||
431 | |||
432 | if (tiling_flags & RADEON_TILING_MACRO) { | ||
258 | if (ASIC_IS_R300(rdev)) | 433 | if (ASIC_IS_R300(rdev)) |
259 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | | 434 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | |
260 | R300_CRTC_MICRO_TILE_BUFFER_DIS | | 435 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
@@ -270,15 +445,13 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
270 | crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; | 445 | crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; |
271 | } | 446 | } |
272 | 447 | ||
273 | 448 | if (tiling_flags & RADEON_TILING_MACRO) { | |
274 | /* TODO more tiling */ | ||
275 | if (0) { | ||
276 | if (ASIC_IS_R300(rdev)) { | 449 | if (ASIC_IS_R300(rdev)) { |
277 | crtc_tile_x0_y0 = x | (y << 16); | 450 | crtc_tile_x0_y0 = x | (y << 16); |
278 | base &= ~0x7ff; | 451 | base &= ~0x7ff; |
279 | } else { | 452 | } else { |
280 | int byteshift = crtc->fb->bits_per_pixel >> 4; | 453 | int byteshift = crtc->fb->bits_per_pixel >> 4; |
281 | int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11; | 454 | int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; |
282 | base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); | 455 | base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); |
283 | crtc_offset_cntl |= (y % 16); | 456 | crtc_offset_cntl |= (y % 16); |
284 | } | 457 | } |
@@ -303,11 +476,9 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
303 | 476 | ||
304 | base &= ~7; | 477 | base &= ~7; |
305 | 478 | ||
306 | /* update sarea TODO */ | ||
307 | |||
308 | crtc_offset = (u32)base; | 479 | crtc_offset = (u32)base; |
309 | 480 | ||
310 | WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, rdev->mc.vram_location); | 481 | WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); |
311 | 482 | ||
312 | if (ASIC_IS_R300(rdev)) { | 483 | if (ASIC_IS_R300(rdev)) { |
313 | if (radeon_crtc->crtc_id) | 484 | if (radeon_crtc->crtc_id) |
@@ -751,6 +922,8 @@ static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, | |||
751 | struct drm_display_mode *mode, | 922 | struct drm_display_mode *mode, |
752 | struct drm_display_mode *adjusted_mode) | 923 | struct drm_display_mode *adjusted_mode) |
753 | { | 924 | { |
925 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) | ||
926 | return false; | ||
754 | return true; | 927 | return true; |
755 | } | 928 | } |
756 | 929 | ||
@@ -759,16 +932,25 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc, | |||
759 | struct drm_display_mode *adjusted_mode, | 932 | struct drm_display_mode *adjusted_mode, |
760 | int x, int y, struct drm_framebuffer *old_fb) | 933 | int x, int y, struct drm_framebuffer *old_fb) |
761 | { | 934 | { |
762 | 935 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
763 | DRM_DEBUG("\n"); | 936 | struct drm_device *dev = crtc->dev; |
937 | struct radeon_device *rdev = dev->dev_private; | ||
764 | 938 | ||
765 | /* TODO TV */ | 939 | /* TODO TV */ |
766 | |||
767 | radeon_crtc_set_base(crtc, x, y, old_fb); | 940 | radeon_crtc_set_base(crtc, x, y, old_fb); |
768 | radeon_set_crtc_timing(crtc, adjusted_mode); | 941 | radeon_set_crtc_timing(crtc, adjusted_mode); |
769 | radeon_set_pll(crtc, adjusted_mode); | 942 | radeon_set_pll(crtc, adjusted_mode); |
770 | radeon_init_disp_bandwidth(crtc->dev); | 943 | radeon_bandwidth_update(rdev); |
771 | 944 | if (radeon_crtc->crtc_id == 0) { | |
945 | radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode); | ||
946 | } else { | ||
947 | if (radeon_crtc->rmx_type != RMX_OFF) { | ||
948 | /* FIXME: only first crtc has rmx what should we | ||
949 | * do ? | ||
950 | */ | ||
951 | DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); | ||
952 | } | ||
953 | } | ||
772 | return 0; | 954 | return 0; |
773 | } | 955 | } |
774 | 956 | ||
@@ -799,478 +981,3 @@ void radeon_legacy_init_crtc(struct drm_device *dev, | |||
799 | radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; | 981 | radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; |
800 | drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); | 982 | drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); |
801 | } | 983 | } |
802 | |||
803 | void radeon_init_disp_bw_legacy(struct drm_device *dev, | ||
804 | struct drm_display_mode *mode1, | ||
805 | uint32_t pixel_bytes1, | ||
806 | struct drm_display_mode *mode2, | ||
807 | uint32_t pixel_bytes2) | ||
808 | { | ||
809 | struct radeon_device *rdev = dev->dev_private; | ||
810 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; | ||
811 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; | ||
812 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; | ||
813 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; | ||
814 | fixed20_12 memtcas_ff[8] = { | ||
815 | fixed_init(1), | ||
816 | fixed_init(2), | ||
817 | fixed_init(3), | ||
818 | fixed_init(0), | ||
819 | fixed_init_half(1), | ||
820 | fixed_init_half(2), | ||
821 | fixed_init(0), | ||
822 | }; | ||
823 | fixed20_12 memtcas_rs480_ff[8] = { | ||
824 | fixed_init(0), | ||
825 | fixed_init(1), | ||
826 | fixed_init(2), | ||
827 | fixed_init(3), | ||
828 | fixed_init(0), | ||
829 | fixed_init_half(1), | ||
830 | fixed_init_half(2), | ||
831 | fixed_init_half(3), | ||
832 | }; | ||
833 | fixed20_12 memtcas2_ff[8] = { | ||
834 | fixed_init(0), | ||
835 | fixed_init(1), | ||
836 | fixed_init(2), | ||
837 | fixed_init(3), | ||
838 | fixed_init(4), | ||
839 | fixed_init(5), | ||
840 | fixed_init(6), | ||
841 | fixed_init(7), | ||
842 | }; | ||
843 | fixed20_12 memtrbs[8] = { | ||
844 | fixed_init(1), | ||
845 | fixed_init_half(1), | ||
846 | fixed_init(2), | ||
847 | fixed_init_half(2), | ||
848 | fixed_init(3), | ||
849 | fixed_init_half(3), | ||
850 | fixed_init(4), | ||
851 | fixed_init_half(4) | ||
852 | }; | ||
853 | fixed20_12 memtrbs_r4xx[8] = { | ||
854 | fixed_init(4), | ||
855 | fixed_init(5), | ||
856 | fixed_init(6), | ||
857 | fixed_init(7), | ||
858 | fixed_init(8), | ||
859 | fixed_init(9), | ||
860 | fixed_init(10), | ||
861 | fixed_init(11) | ||
862 | }; | ||
863 | fixed20_12 min_mem_eff; | ||
864 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; | ||
865 | fixed20_12 cur_latency_mclk, cur_latency_sclk; | ||
866 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, | ||
867 | disp_drain_rate2, read_return_rate; | ||
868 | fixed20_12 time_disp1_drop_priority; | ||
869 | int c; | ||
870 | int cur_size = 16; /* in octawords */ | ||
871 | int critical_point = 0, critical_point2; | ||
872 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ | ||
873 | int stop_req, max_stop_req; | ||
874 | |||
875 | min_mem_eff.full = rfixed_const_8(0); | ||
876 | /* get modes */ | ||
877 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { | ||
878 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); | ||
879 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); | ||
880 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); | ||
881 | /* check crtc enables */ | ||
882 | if (mode2) | ||
883 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); | ||
884 | if (mode1) | ||
885 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); | ||
886 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); | ||
887 | } | ||
888 | |||
889 | /* | ||
890 | * determine is there is enough bw for current mode | ||
891 | */ | ||
892 | mclk_ff.full = rfixed_const(rdev->clock.default_mclk); | ||
893 | temp_ff.full = rfixed_const(100); | ||
894 | mclk_ff.full = rfixed_div(mclk_ff, temp_ff); | ||
895 | sclk_ff.full = rfixed_const(rdev->clock.default_sclk); | ||
896 | sclk_ff.full = rfixed_div(sclk_ff, temp_ff); | ||
897 | |||
898 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); | ||
899 | temp_ff.full = rfixed_const(temp); | ||
900 | mem_bw.full = rfixed_mul(mclk_ff, temp_ff); | ||
901 | |||
902 | pix_clk.full = 0; | ||
903 | pix_clk2.full = 0; | ||
904 | peak_disp_bw.full = 0; | ||
905 | if (mode1) { | ||
906 | temp_ff.full = rfixed_const(1000); | ||
907 | pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ | ||
908 | pix_clk.full = rfixed_div(pix_clk, temp_ff); | ||
909 | temp_ff.full = rfixed_const(pixel_bytes1); | ||
910 | peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); | ||
911 | } | ||
912 | if (mode2) { | ||
913 | temp_ff.full = rfixed_const(1000); | ||
914 | pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ | ||
915 | pix_clk2.full = rfixed_div(pix_clk2, temp_ff); | ||
916 | temp_ff.full = rfixed_const(pixel_bytes2); | ||
917 | peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); | ||
918 | } | ||
919 | |||
920 | mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); | ||
921 | if (peak_disp_bw.full >= mem_bw.full) { | ||
922 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" | ||
923 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); | ||
924 | } | ||
925 | |||
926 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ | ||
927 | temp = RREG32(RADEON_MEM_TIMING_CNTL); | ||
928 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ | ||
929 | mem_trcd = ((temp >> 2) & 0x3) + 1; | ||
930 | mem_trp = ((temp & 0x3)) + 1; | ||
931 | mem_tras = ((temp & 0x70) >> 4) + 1; | ||
932 | } else if (rdev->family == CHIP_R300 || | ||
933 | rdev->family == CHIP_R350) { /* r300, r350 */ | ||
934 | mem_trcd = (temp & 0x7) + 1; | ||
935 | mem_trp = ((temp >> 8) & 0x7) + 1; | ||
936 | mem_tras = ((temp >> 11) & 0xf) + 4; | ||
937 | } else if (rdev->family == CHIP_RV350 || | ||
938 | rdev->family <= CHIP_RV380) { | ||
939 | /* rv3x0 */ | ||
940 | mem_trcd = (temp & 0x7) + 3; | ||
941 | mem_trp = ((temp >> 8) & 0x7) + 3; | ||
942 | mem_tras = ((temp >> 11) & 0xf) + 6; | ||
943 | } else if (rdev->family == CHIP_R420 || | ||
944 | rdev->family == CHIP_R423 || | ||
945 | rdev->family == CHIP_RV410) { | ||
946 | /* r4xx */ | ||
947 | mem_trcd = (temp & 0xf) + 3; | ||
948 | if (mem_trcd > 15) | ||
949 | mem_trcd = 15; | ||
950 | mem_trp = ((temp >> 8) & 0xf) + 3; | ||
951 | if (mem_trp > 15) | ||
952 | mem_trp = 15; | ||
953 | mem_tras = ((temp >> 12) & 0x1f) + 6; | ||
954 | if (mem_tras > 31) | ||
955 | mem_tras = 31; | ||
956 | } else { /* RV200, R200 */ | ||
957 | mem_trcd = (temp & 0x7) + 1; | ||
958 | mem_trp = ((temp >> 8) & 0x7) + 1; | ||
959 | mem_tras = ((temp >> 12) & 0xf) + 4; | ||
960 | } | ||
961 | /* convert to FF */ | ||
962 | trcd_ff.full = rfixed_const(mem_trcd); | ||
963 | trp_ff.full = rfixed_const(mem_trp); | ||
964 | tras_ff.full = rfixed_const(mem_tras); | ||
965 | |||
966 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ | ||
967 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); | ||
968 | data = (temp & (7 << 20)) >> 20; | ||
969 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { | ||
970 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ | ||
971 | tcas_ff = memtcas_rs480_ff[data]; | ||
972 | else | ||
973 | tcas_ff = memtcas_ff[data]; | ||
974 | } else | ||
975 | tcas_ff = memtcas2_ff[data]; | ||
976 | |||
977 | if (rdev->family == CHIP_RS400 || | ||
978 | rdev->family == CHIP_RS480) { | ||
979 | /* extra cas latency stored in bits 23-25 0-4 clocks */ | ||
980 | data = (temp >> 23) & 0x7; | ||
981 | if (data < 5) | ||
982 | tcas_ff.full += rfixed_const(data); | ||
983 | } | ||
984 | |||
985 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { | ||
986 | /* on the R300, Tcas is included in Trbs. | ||
987 | */ | ||
988 | temp = RREG32(RADEON_MEM_CNTL); | ||
989 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); | ||
990 | if (data == 1) { | ||
991 | if (R300_MEM_USE_CD_CH_ONLY & temp) { | ||
992 | temp = RREG32(R300_MC_IND_INDEX); | ||
993 | temp &= ~R300_MC_IND_ADDR_MASK; | ||
994 | temp |= R300_MC_READ_CNTL_CD_mcind; | ||
995 | WREG32(R300_MC_IND_INDEX, temp); | ||
996 | temp = RREG32(R300_MC_IND_DATA); | ||
997 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); | ||
998 | } else { | ||
999 | temp = RREG32(R300_MC_READ_CNTL_AB); | ||
1000 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | ||
1001 | } | ||
1002 | } else { | ||
1003 | temp = RREG32(R300_MC_READ_CNTL_AB); | ||
1004 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | ||
1005 | } | ||
1006 | if (rdev->family == CHIP_RV410 || | ||
1007 | rdev->family == CHIP_R420 || | ||
1008 | rdev->family == CHIP_R423) | ||
1009 | trbs_ff = memtrbs_r4xx[data]; | ||
1010 | else | ||
1011 | trbs_ff = memtrbs[data]; | ||
1012 | tcas_ff.full += trbs_ff.full; | ||
1013 | } | ||
1014 | |||
1015 | sclk_eff_ff.full = sclk_ff.full; | ||
1016 | |||
1017 | if (rdev->flags & RADEON_IS_AGP) { | ||
1018 | fixed20_12 agpmode_ff; | ||
1019 | agpmode_ff.full = rfixed_const(radeon_agpmode); | ||
1020 | temp_ff.full = rfixed_const_666(16); | ||
1021 | sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff); | ||
1022 | } | ||
1023 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ | ||
1024 | |||
1025 | if (ASIC_IS_R300(rdev)) { | ||
1026 | sclk_delay_ff.full = rfixed_const(250); | ||
1027 | } else { | ||
1028 | if ((rdev->family == CHIP_RV100) || | ||
1029 | rdev->flags & RADEON_IS_IGP) { | ||
1030 | if (rdev->mc.vram_is_ddr) | ||
1031 | sclk_delay_ff.full = rfixed_const(41); | ||
1032 | else | ||
1033 | sclk_delay_ff.full = rfixed_const(33); | ||
1034 | } else { | ||
1035 | if (rdev->mc.vram_width == 128) | ||
1036 | sclk_delay_ff.full = rfixed_const(57); | ||
1037 | else | ||
1038 | sclk_delay_ff.full = rfixed_const(41); | ||
1039 | } | ||
1040 | } | ||
1041 | |||
1042 | mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff); | ||
1043 | |||
1044 | if (rdev->mc.vram_is_ddr) { | ||
1045 | if (rdev->mc.vram_width == 32) { | ||
1046 | k1.full = rfixed_const(40); | ||
1047 | c = 3; | ||
1048 | } else { | ||
1049 | k1.full = rfixed_const(20); | ||
1050 | c = 1; | ||
1051 | } | ||
1052 | } else { | ||
1053 | k1.full = rfixed_const(40); | ||
1054 | c = 3; | ||
1055 | } | ||
1056 | |||
1057 | temp_ff.full = rfixed_const(2); | ||
1058 | mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff); | ||
1059 | temp_ff.full = rfixed_const(c); | ||
1060 | mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff); | ||
1061 | temp_ff.full = rfixed_const(4); | ||
1062 | mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff); | ||
1063 | mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff); | ||
1064 | mc_latency_mclk.full += k1.full; | ||
1065 | |||
1066 | mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff); | ||
1067 | mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff); | ||
1068 | |||
1069 | /* | ||
1070 | HW cursor time assuming worst case of full size colour cursor. | ||
1071 | */ | ||
1072 | temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); | ||
1073 | temp_ff.full += trcd_ff.full; | ||
1074 | if (temp_ff.full < tras_ff.full) | ||
1075 | temp_ff.full = tras_ff.full; | ||
1076 | cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff); | ||
1077 | |||
1078 | temp_ff.full = rfixed_const(cur_size); | ||
1079 | cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff); | ||
1080 | /* | ||
1081 | Find the total latency for the display data. | ||
1082 | */ | ||
1083 | disp_latency_overhead.full = rfixed_const(80); | ||
1084 | disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff); | ||
1085 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; | ||
1086 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; | ||
1087 | |||
1088 | if (mc_latency_mclk.full > mc_latency_sclk.full) | ||
1089 | disp_latency.full = mc_latency_mclk.full; | ||
1090 | else | ||
1091 | disp_latency.full = mc_latency_sclk.full; | ||
1092 | |||
1093 | /* setup Max GRPH_STOP_REQ default value */ | ||
1094 | if (ASIC_IS_RV100(rdev)) | ||
1095 | max_stop_req = 0x5c; | ||
1096 | else | ||
1097 | max_stop_req = 0x7c; | ||
1098 | |||
1099 | if (mode1) { | ||
1100 | /* CRTC1 | ||
1101 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. | ||
1102 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] | ||
1103 | */ | ||
1104 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; | ||
1105 | |||
1106 | if (stop_req > max_stop_req) | ||
1107 | stop_req = max_stop_req; | ||
1108 | |||
1109 | /* | ||
1110 | Find the drain rate of the display buffer. | ||
1111 | */ | ||
1112 | temp_ff.full = rfixed_const((16/pixel_bytes1)); | ||
1113 | disp_drain_rate.full = rfixed_div(pix_clk, temp_ff); | ||
1114 | |||
1115 | /* | ||
1116 | Find the critical point of the display buffer. | ||
1117 | */ | ||
1118 | crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency); | ||
1119 | crit_point_ff.full += rfixed_const_half(0); | ||
1120 | |||
1121 | critical_point = rfixed_trunc(crit_point_ff); | ||
1122 | |||
1123 | if (rdev->disp_priority == 2) { | ||
1124 | critical_point = 0; | ||
1125 | } | ||
1126 | |||
1127 | /* | ||
1128 | The critical point should never be above max_stop_req-4. Setting | ||
1129 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. | ||
1130 | */ | ||
1131 | if (max_stop_req - critical_point < 4) | ||
1132 | critical_point = 0; | ||
1133 | |||
1134 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { | ||
1135 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ | ||
1136 | critical_point = 0x10; | ||
1137 | } | ||
1138 | |||
1139 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); | ||
1140 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); | ||
1141 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | ||
1142 | temp &= ~(RADEON_GRPH_START_REQ_MASK); | ||
1143 | if ((rdev->family == CHIP_R350) && | ||
1144 | (stop_req > 0x15)) { | ||
1145 | stop_req -= 0x10; | ||
1146 | } | ||
1147 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); | ||
1148 | temp |= RADEON_GRPH_BUFFER_SIZE; | ||
1149 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | | ||
1150 | RADEON_GRPH_CRITICAL_AT_SOF | | ||
1151 | RADEON_GRPH_STOP_CNTL); | ||
1152 | /* | ||
1153 | Write the result into the register. | ||
1154 | */ | ||
1155 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | | ||
1156 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | ||
1157 | |||
1158 | #if 0 | ||
1159 | if ((rdev->family == CHIP_RS400) || | ||
1160 | (rdev->family == CHIP_RS480)) { | ||
1161 | /* attempt to program RS400 disp regs correctly ??? */ | ||
1162 | temp = RREG32(RS400_DISP1_REG_CNTL); | ||
1163 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | | ||
1164 | RS400_DISP1_STOP_REQ_LEVEL_MASK); | ||
1165 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | | ||
1166 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | ||
1167 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | ||
1168 | temp = RREG32(RS400_DMIF_MEM_CNTL1); | ||
1169 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | | ||
1170 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); | ||
1171 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | | ||
1172 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | | ||
1173 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); | ||
1174 | } | ||
1175 | #endif | ||
1176 | |||
1177 | DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n", | ||
1178 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ | ||
1179 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); | ||
1180 | } | ||
1181 | |||
1182 | if (mode2) { | ||
1183 | u32 grph2_cntl; | ||
1184 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; | ||
1185 | |||
1186 | if (stop_req > max_stop_req) | ||
1187 | stop_req = max_stop_req; | ||
1188 | |||
1189 | /* | ||
1190 | Find the drain rate of the display buffer. | ||
1191 | */ | ||
1192 | temp_ff.full = rfixed_const((16/pixel_bytes2)); | ||
1193 | disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff); | ||
1194 | |||
1195 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); | ||
1196 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); | ||
1197 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | ||
1198 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); | ||
1199 | if ((rdev->family == CHIP_R350) && | ||
1200 | (stop_req > 0x15)) { | ||
1201 | stop_req -= 0x10; | ||
1202 | } | ||
1203 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); | ||
1204 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; | ||
1205 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | | ||
1206 | RADEON_GRPH_CRITICAL_AT_SOF | | ||
1207 | RADEON_GRPH_STOP_CNTL); | ||
1208 | |||
1209 | if ((rdev->family == CHIP_RS100) || | ||
1210 | (rdev->family == CHIP_RS200)) | ||
1211 | critical_point2 = 0; | ||
1212 | else { | ||
1213 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; | ||
1214 | temp_ff.full = rfixed_const(temp); | ||
1215 | temp_ff.full = rfixed_mul(mclk_ff, temp_ff); | ||
1216 | if (sclk_ff.full < temp_ff.full) | ||
1217 | temp_ff.full = sclk_ff.full; | ||
1218 | |||
1219 | read_return_rate.full = temp_ff.full; | ||
1220 | |||
1221 | if (mode1) { | ||
1222 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; | ||
1223 | time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff); | ||
1224 | } else { | ||
1225 | time_disp1_drop_priority.full = 0; | ||
1226 | } | ||
1227 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; | ||
1228 | crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2); | ||
1229 | crit_point_ff.full += rfixed_const_half(0); | ||
1230 | |||
1231 | critical_point2 = rfixed_trunc(crit_point_ff); | ||
1232 | |||
1233 | if (rdev->disp_priority == 2) { | ||
1234 | critical_point2 = 0; | ||
1235 | } | ||
1236 | |||
1237 | if (max_stop_req - critical_point2 < 4) | ||
1238 | critical_point2 = 0; | ||
1239 | |||
1240 | } | ||
1241 | |||
1242 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { | ||
1243 | /* some R300 cards have problem with this set to 0 */ | ||
1244 | critical_point2 = 0x10; | ||
1245 | } | ||
1246 | |||
1247 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | | ||
1248 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | ||
1249 | |||
1250 | if ((rdev->family == CHIP_RS400) || | ||
1251 | (rdev->family == CHIP_RS480)) { | ||
1252 | #if 0 | ||
1253 | /* attempt to program RS400 disp2 regs correctly ??? */ | ||
1254 | temp = RREG32(RS400_DISP2_REQ_CNTL1); | ||
1255 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | | ||
1256 | RS400_DISP2_STOP_REQ_LEVEL_MASK); | ||
1257 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | | ||
1258 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | ||
1259 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | ||
1260 | temp = RREG32(RS400_DISP2_REQ_CNTL2); | ||
1261 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | | ||
1262 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); | ||
1263 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | | ||
1264 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | | ||
1265 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); | ||
1266 | #endif | ||
1267 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); | ||
1268 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); | ||
1269 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); | ||
1270 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); | ||
1271 | } | ||
1272 | |||
1273 | DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", | ||
1274 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); | ||
1275 | } | ||
1276 | } | ||
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 2c2f42de1d4c..34d0f58eb944 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c | |||
@@ -30,170 +30,6 @@ | |||
30 | #include "atom.h" | 30 | #include "atom.h" |
31 | 31 | ||
32 | 32 | ||
33 | static void radeon_legacy_rmx_mode_set(struct drm_encoder *encoder, | ||
34 | struct drm_display_mode *mode, | ||
35 | struct drm_display_mode *adjusted_mode) | ||
36 | { | ||
37 | struct drm_device *dev = encoder->dev; | ||
38 | struct radeon_device *rdev = dev->dev_private; | ||
39 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | ||
40 | int xres = mode->hdisplay; | ||
41 | int yres = mode->vdisplay; | ||
42 | bool hscale = true, vscale = true; | ||
43 | int hsync_wid; | ||
44 | int vsync_wid; | ||
45 | int hsync_start; | ||
46 | uint32_t scale, inc; | ||
47 | uint32_t fp_horz_stretch, fp_vert_stretch, crtc_more_cntl, fp_horz_vert_active; | ||
48 | uint32_t fp_h_sync_strt_wid, fp_v_sync_strt_wid, fp_crtc_h_total_disp, fp_crtc_v_total_disp; | ||
49 | struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; | ||
50 | |||
51 | DRM_DEBUG("\n"); | ||
52 | |||
53 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & | ||
54 | (RADEON_VERT_STRETCH_RESERVED | | ||
55 | RADEON_VERT_AUTO_RATIO_INC); | ||
56 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & | ||
57 | (RADEON_HORZ_FP_LOOP_STRETCH | | ||
58 | RADEON_HORZ_AUTO_RATIO_INC); | ||
59 | |||
60 | crtc_more_cntl = 0; | ||
61 | if ((rdev->family == CHIP_RS100) || | ||
62 | (rdev->family == CHIP_RS200)) { | ||
63 | /* This is to workaround the asic bug for RMX, some versions | ||
64 | of BIOS dosen't have this register initialized correctly. */ | ||
65 | crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; | ||
66 | } | ||
67 | |||
68 | |||
69 | fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) | ||
70 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); | ||
71 | |||
72 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; | ||
73 | if (!hsync_wid) | ||
74 | hsync_wid = 1; | ||
75 | hsync_start = mode->crtc_hsync_start - 8; | ||
76 | |||
77 | fp_h_sync_strt_wid = ((hsync_start & 0x1fff) | ||
78 | | ((hsync_wid & 0x3f) << 16) | ||
79 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) | ||
80 | ? RADEON_CRTC_H_SYNC_POL | ||
81 | : 0)); | ||
82 | |||
83 | fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) | ||
84 | | ((mode->crtc_vdisplay - 1) << 16)); | ||
85 | |||
86 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; | ||
87 | if (!vsync_wid) | ||
88 | vsync_wid = 1; | ||
89 | |||
90 | fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) | ||
91 | | ((vsync_wid & 0x1f) << 16) | ||
92 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) | ||
93 | ? RADEON_CRTC_V_SYNC_POL | ||
94 | : 0)); | ||
95 | |||
96 | fp_horz_vert_active = 0; | ||
97 | |||
98 | if (native_mode->panel_xres == 0 || | ||
99 | native_mode->panel_yres == 0) { | ||
100 | hscale = false; | ||
101 | vscale = false; | ||
102 | } else { | ||
103 | if (xres > native_mode->panel_xres) | ||
104 | xres = native_mode->panel_xres; | ||
105 | if (yres > native_mode->panel_yres) | ||
106 | yres = native_mode->panel_yres; | ||
107 | |||
108 | if (xres == native_mode->panel_xres) | ||
109 | hscale = false; | ||
110 | if (yres == native_mode->panel_yres) | ||
111 | vscale = false; | ||
112 | } | ||
113 | |||
114 | if (radeon_encoder->flags & RADEON_USE_RMX) { | ||
115 | if (radeon_encoder->rmx_type != RMX_CENTER) { | ||
116 | if (!hscale) | ||
117 | fp_horz_stretch |= ((xres/8-1) << 16); | ||
118 | else { | ||
119 | inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; | ||
120 | scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) | ||
121 | / native_mode->panel_xres + 1; | ||
122 | fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | | ||
123 | RADEON_HORZ_STRETCH_BLEND | | ||
124 | RADEON_HORZ_STRETCH_ENABLE | | ||
125 | ((native_mode->panel_xres/8-1) << 16)); | ||
126 | } | ||
127 | |||
128 | if (!vscale) | ||
129 | fp_vert_stretch |= ((yres-1) << 12); | ||
130 | else { | ||
131 | inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; | ||
132 | scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) | ||
133 | / native_mode->panel_yres + 1; | ||
134 | fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | | ||
135 | RADEON_VERT_STRETCH_ENABLE | | ||
136 | RADEON_VERT_STRETCH_BLEND | | ||
137 | ((native_mode->panel_yres-1) << 12)); | ||
138 | } | ||
139 | } else if (radeon_encoder->rmx_type == RMX_CENTER) { | ||
140 | int blank_width; | ||
141 | |||
142 | fp_horz_stretch |= ((xres/8-1) << 16); | ||
143 | fp_vert_stretch |= ((yres-1) << 12); | ||
144 | |||
145 | crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | | ||
146 | RADEON_CRTC_AUTO_VERT_CENTER_EN); | ||
147 | |||
148 | blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; | ||
149 | if (blank_width > 110) | ||
150 | blank_width = 110; | ||
151 | |||
152 | fp_crtc_h_total_disp = (((blank_width) & 0x3ff) | ||
153 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); | ||
154 | |||
155 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; | ||
156 | if (!hsync_wid) | ||
157 | hsync_wid = 1; | ||
158 | |||
159 | fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) | ||
160 | | ((hsync_wid & 0x3f) << 16) | ||
161 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) | ||
162 | ? RADEON_CRTC_H_SYNC_POL | ||
163 | : 0)); | ||
164 | |||
165 | fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) | ||
166 | | ((mode->crtc_vdisplay - 1) << 16)); | ||
167 | |||
168 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; | ||
169 | if (!vsync_wid) | ||
170 | vsync_wid = 1; | ||
171 | |||
172 | fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) | ||
173 | | ((vsync_wid & 0x1f) << 16) | ||
174 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) | ||
175 | ? RADEON_CRTC_V_SYNC_POL | ||
176 | : 0))); | ||
177 | |||
178 | fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) | | ||
179 | (((native_mode->panel_xres / 8) & 0x1ff) << 16)); | ||
180 | } | ||
181 | } else { | ||
182 | fp_horz_stretch |= ((xres/8-1) << 16); | ||
183 | fp_vert_stretch |= ((yres-1) << 12); | ||
184 | } | ||
185 | |||
186 | WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); | ||
187 | WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); | ||
188 | WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); | ||
189 | WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); | ||
190 | WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); | ||
191 | WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); | ||
192 | WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); | ||
193 | WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); | ||
194 | |||
195 | } | ||
196 | |||
197 | static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) | 33 | static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) |
198 | { | 34 | { |
199 | struct drm_device *dev = encoder->dev; | 35 | struct drm_device *dev = encoder->dev; |
@@ -287,9 +123,6 @@ static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, | |||
287 | 123 | ||
288 | DRM_DEBUG("\n"); | 124 | DRM_DEBUG("\n"); |
289 | 125 | ||
290 | if (radeon_crtc->crtc_id == 0) | ||
291 | radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode); | ||
292 | |||
293 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); | 126 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
294 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; | 127 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; |
295 | 128 | ||
@@ -318,7 +151,7 @@ static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, | |||
318 | 151 | ||
319 | if (radeon_crtc->crtc_id == 0) { | 152 | if (radeon_crtc->crtc_id == 0) { |
320 | if (ASIC_IS_R300(rdev)) { | 153 | if (ASIC_IS_R300(rdev)) { |
321 | if (radeon_encoder->flags & RADEON_USE_RMX) | 154 | if (radeon_encoder->rmx_type != RMX_OFF) |
322 | lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; | 155 | lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; |
323 | } else | 156 | } else |
324 | lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; | 157 | lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; |
@@ -350,8 +183,6 @@ static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder, | |||
350 | 183 | ||
351 | drm_mode_set_crtcinfo(adjusted_mode, 0); | 184 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
352 | 185 | ||
353 | radeon_encoder->flags &= ~RADEON_USE_RMX; | ||
354 | |||
355 | if (radeon_encoder->rmx_type != RMX_OFF) | 186 | if (radeon_encoder->rmx_type != RMX_OFF) |
356 | radeon_rmx_mode_fixup(encoder, mode, adjusted_mode); | 187 | radeon_rmx_mode_fixup(encoder, mode, adjusted_mode); |
357 | 188 | ||
@@ -455,9 +286,6 @@ static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder, | |||
455 | 286 | ||
456 | DRM_DEBUG("\n"); | 287 | DRM_DEBUG("\n"); |
457 | 288 | ||
458 | if (radeon_crtc->crtc_id == 0) | ||
459 | radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode); | ||
460 | |||
461 | if (radeon_crtc->crtc_id == 0) { | 289 | if (radeon_crtc->crtc_id == 0) { |
462 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { | 290 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { |
463 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & | 291 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & |
@@ -653,9 +481,6 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, | |||
653 | 481 | ||
654 | DRM_DEBUG("\n"); | 482 | DRM_DEBUG("\n"); |
655 | 483 | ||
656 | if (radeon_crtc->crtc_id == 0) | ||
657 | radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode); | ||
658 | |||
659 | tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); | 484 | tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); |
660 | tmp &= 0xfffff; | 485 | tmp &= 0xfffff; |
661 | if (rdev->family == CHIP_RV280) { | 486 | if (rdev->family == CHIP_RV280) { |
@@ -711,7 +536,7 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, | |||
711 | if (radeon_crtc->crtc_id == 0) { | 536 | if (radeon_crtc->crtc_id == 0) { |
712 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { | 537 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { |
713 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; | 538 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; |
714 | if (radeon_encoder->flags & RADEON_USE_RMX) | 539 | if (radeon_encoder->rmx_type != RMX_OFF) |
715 | fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; | 540 | fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; |
716 | else | 541 | else |
717 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; | 542 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; |
@@ -820,9 +645,6 @@ static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, | |||
820 | 645 | ||
821 | DRM_DEBUG("\n"); | 646 | DRM_DEBUG("\n"); |
822 | 647 | ||
823 | if (radeon_crtc->crtc_id == 0) | ||
824 | radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode); | ||
825 | |||
826 | if (rdev->is_atom_bios) { | 648 | if (rdev->is_atom_bios) { |
827 | radeon_encoder->pixel_clock = adjusted_mode->clock; | 649 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
828 | atombios_external_tmds_setup(encoder, ATOM_ENABLE); | 650 | atombios_external_tmds_setup(encoder, ATOM_ENABLE); |
@@ -856,7 +678,7 @@ static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, | |||
856 | if (radeon_crtc->crtc_id == 0) { | 678 | if (radeon_crtc->crtc_id == 0) { |
857 | if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { | 679 | if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { |
858 | fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; | 680 | fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; |
859 | if (radeon_encoder->flags & RADEON_USE_RMX) | 681 | if (radeon_encoder->rmx_type != RMX_OFF) |
860 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; | 682 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; |
861 | else | 683 | else |
862 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; | 684 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; |
@@ -1014,9 +836,6 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, | |||
1014 | 836 | ||
1015 | DRM_DEBUG("\n"); | 837 | DRM_DEBUG("\n"); |
1016 | 838 | ||
1017 | if (radeon_crtc->crtc_id == 0) | ||
1018 | radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode); | ||
1019 | |||
1020 | if (rdev->family != CHIP_R200) { | 839 | if (rdev->family != CHIP_R200) { |
1021 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); | 840 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
1022 | if (rdev->family == CHIP_R420 || | 841 | if (rdev->family == CHIP_R420 || |
@@ -1243,6 +1062,7 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t | |||
1243 | 1062 | ||
1244 | radeon_encoder->encoder_id = encoder_id; | 1063 | radeon_encoder->encoder_id = encoder_id; |
1245 | radeon_encoder->devices = supported_device; | 1064 | radeon_encoder->devices = supported_device; |
1065 | radeon_encoder->rmx_type = RMX_OFF; | ||
1246 | 1066 | ||
1247 | switch (radeon_encoder->encoder_id) { | 1067 | switch (radeon_encoder->encoder_id) { |
1248 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | 1068 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 9173b687462b..3b09a1f2d8f9 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h | |||
@@ -36,6 +36,9 @@ | |||
36 | #include <linux/i2c.h> | 36 | #include <linux/i2c.h> |
37 | #include <linux/i2c-id.h> | 37 | #include <linux/i2c-id.h> |
38 | #include <linux/i2c-algo-bit.h> | 38 | #include <linux/i2c-algo-bit.h> |
39 | #include "radeon_fixed.h" | ||
40 | |||
41 | struct radeon_device; | ||
39 | 42 | ||
40 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) | 43 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
41 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) | 44 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
@@ -124,6 +127,7 @@ struct radeon_tmds_pll { | |||
124 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) | 127 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
125 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) | 128 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
126 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) | 129 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
130 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) | ||
127 | 131 | ||
128 | struct radeon_pll { | 132 | struct radeon_pll { |
129 | uint16_t reference_freq; | 133 | uint16_t reference_freq; |
@@ -170,6 +174,18 @@ struct radeon_mode_info { | |||
170 | struct atom_context *atom_context; | 174 | struct atom_context *atom_context; |
171 | enum radeon_connector_table connector_table; | 175 | enum radeon_connector_table connector_table; |
172 | bool mode_config_initialized; | 176 | bool mode_config_initialized; |
177 | struct radeon_crtc *crtcs[2]; | ||
178 | }; | ||
179 | |||
180 | struct radeon_native_mode { | ||
181 | /* preferred mode */ | ||
182 | uint32_t panel_xres, panel_yres; | ||
183 | uint32_t hoverplus, hsync_width; | ||
184 | uint32_t hblank; | ||
185 | uint32_t voverplus, vsync_width; | ||
186 | uint32_t vblank; | ||
187 | uint32_t dotclock; | ||
188 | uint32_t flags; | ||
173 | }; | 189 | }; |
174 | 190 | ||
175 | struct radeon_crtc { | 191 | struct radeon_crtc { |
@@ -185,19 +201,13 @@ struct radeon_crtc { | |||
185 | uint64_t cursor_addr; | 201 | uint64_t cursor_addr; |
186 | int cursor_width; | 202 | int cursor_width; |
187 | int cursor_height; | 203 | int cursor_height; |
188 | }; | 204 | uint32_t legacy_display_base_addr; |
189 | 205 | uint32_t legacy_cursor_offset; | |
190 | #define RADEON_USE_RMX 1 | 206 | enum radeon_rmx_type rmx_type; |
191 | 207 | uint32_t devices; | |
192 | struct radeon_native_mode { | 208 | fixed20_12 vsc; |
193 | /* preferred mode */ | 209 | fixed20_12 hsc; |
194 | uint32_t panel_xres, panel_yres; | 210 | struct radeon_native_mode native_mode; |
195 | uint32_t hoverplus, hsync_width; | ||
196 | uint32_t hblank; | ||
197 | uint32_t voverplus, vsync_width; | ||
198 | uint32_t vblank; | ||
199 | uint32_t dotclock; | ||
200 | uint32_t flags; | ||
201 | }; | 211 | }; |
202 | 212 | ||
203 | struct radeon_encoder_primary_dac { | 213 | struct radeon_encoder_primary_dac { |
@@ -383,16 +393,9 @@ void radeon_enc_destroy(struct drm_encoder *encoder); | |||
383 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); | 393 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
384 | void radeon_combios_asic_init(struct drm_device *dev); | 394 | void radeon_combios_asic_init(struct drm_device *dev); |
385 | extern int radeon_static_clocks_init(struct drm_device *dev); | 395 | extern int radeon_static_clocks_init(struct drm_device *dev); |
386 | void radeon_init_disp_bw_legacy(struct drm_device *dev, | 396 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
387 | struct drm_display_mode *mode1, | 397 | struct drm_display_mode *mode, |
388 | uint32_t pixel_bytes1, | 398 | struct drm_display_mode *adjusted_mode); |
389 | struct drm_display_mode *mode2, | 399 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev); |
390 | uint32_t pixel_bytes2); | ||
391 | void radeon_init_disp_bw_avivo(struct drm_device *dev, | ||
392 | struct drm_display_mode *mode1, | ||
393 | uint32_t pixel_bytes1, | ||
394 | struct drm_display_mode *mode2, | ||
395 | uint32_t pixel_bytes2); | ||
396 | void radeon_init_disp_bandwidth(struct drm_device *dev); | ||
397 | 400 | ||
398 | #endif | 401 | #endif |
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index bac0d06c52ac..dd9ac2fed6d6 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c | |||
@@ -44,6 +44,9 @@ struct radeon_object { | |||
44 | uint64_t gpu_addr; | 44 | uint64_t gpu_addr; |
45 | void *kptr; | 45 | void *kptr; |
46 | bool is_iomem; | 46 | bool is_iomem; |
47 | uint32_t tiling_flags; | ||
48 | uint32_t pitch; | ||
49 | int surface_reg; | ||
47 | }; | 50 | }; |
48 | 51 | ||
49 | int radeon_ttm_init(struct radeon_device *rdev); | 52 | int radeon_ttm_init(struct radeon_device *rdev); |
@@ -70,6 +73,7 @@ static void radeon_ttm_object_object_destroy(struct ttm_buffer_object *tobj) | |||
70 | 73 | ||
71 | robj = container_of(tobj, struct radeon_object, tobj); | 74 | robj = container_of(tobj, struct radeon_object, tobj); |
72 | list_del_init(&robj->list); | 75 | list_del_init(&robj->list); |
76 | radeon_object_clear_surface_reg(robj); | ||
73 | kfree(robj); | 77 | kfree(robj); |
74 | } | 78 | } |
75 | 79 | ||
@@ -99,16 +103,16 @@ static inline uint32_t radeon_object_flags_from_domain(uint32_t domain) | |||
99 | { | 103 | { |
100 | uint32_t flags = 0; | 104 | uint32_t flags = 0; |
101 | if (domain & RADEON_GEM_DOMAIN_VRAM) { | 105 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
102 | flags |= TTM_PL_FLAG_VRAM; | 106 | flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED; |
103 | } | 107 | } |
104 | if (domain & RADEON_GEM_DOMAIN_GTT) { | 108 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
105 | flags |= TTM_PL_FLAG_TT; | 109 | flags |= TTM_PL_FLAG_TT | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED; |
106 | } | 110 | } |
107 | if (domain & RADEON_GEM_DOMAIN_CPU) { | 111 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
108 | flags |= TTM_PL_FLAG_SYSTEM; | 112 | flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; |
109 | } | 113 | } |
110 | if (!flags) { | 114 | if (!flags) { |
111 | flags |= TTM_PL_FLAG_SYSTEM; | 115 | flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; |
112 | } | 116 | } |
113 | return flags; | 117 | return flags; |
114 | } | 118 | } |
@@ -141,6 +145,7 @@ int radeon_object_create(struct radeon_device *rdev, | |||
141 | } | 145 | } |
142 | robj->rdev = rdev; | 146 | robj->rdev = rdev; |
143 | robj->gobj = gobj; | 147 | robj->gobj = gobj; |
148 | robj->surface_reg = -1; | ||
144 | INIT_LIST_HEAD(&robj->list); | 149 | INIT_LIST_HEAD(&robj->list); |
145 | 150 | ||
146 | flags = radeon_object_flags_from_domain(domain); | 151 | flags = radeon_object_flags_from_domain(domain); |
@@ -304,7 +309,7 @@ int radeon_object_wait(struct radeon_object *robj) | |||
304 | } | 309 | } |
305 | spin_lock(&robj->tobj.lock); | 310 | spin_lock(&robj->tobj.lock); |
306 | if (robj->tobj.sync_obj) { | 311 | if (robj->tobj.sync_obj) { |
307 | r = ttm_bo_wait(&robj->tobj, true, false, false); | 312 | r = ttm_bo_wait(&robj->tobj, true, true, false); |
308 | } | 313 | } |
309 | spin_unlock(&robj->tobj.lock); | 314 | spin_unlock(&robj->tobj.lock); |
310 | radeon_object_unreserve(robj); | 315 | radeon_object_unreserve(robj); |
@@ -403,7 +408,6 @@ int radeon_object_list_validate(struct list_head *head, void *fence) | |||
403 | struct radeon_object *robj; | 408 | struct radeon_object *robj; |
404 | struct radeon_fence *old_fence = NULL; | 409 | struct radeon_fence *old_fence = NULL; |
405 | struct list_head *i; | 410 | struct list_head *i; |
406 | uint32_t flags; | ||
407 | int r; | 411 | int r; |
408 | 412 | ||
409 | r = radeon_object_list_reserve(head); | 413 | r = radeon_object_list_reserve(head); |
@@ -414,27 +418,25 @@ int radeon_object_list_validate(struct list_head *head, void *fence) | |||
414 | list_for_each(i, head) { | 418 | list_for_each(i, head) { |
415 | lobj = list_entry(i, struct radeon_object_list, list); | 419 | lobj = list_entry(i, struct radeon_object_list, list); |
416 | robj = lobj->robj; | 420 | robj = lobj->robj; |
417 | if (lobj->wdomain) { | ||
418 | flags = radeon_object_flags_from_domain(lobj->wdomain); | ||
419 | flags |= TTM_PL_FLAG_TT; | ||
420 | } else { | ||
421 | flags = radeon_object_flags_from_domain(lobj->rdomain); | ||
422 | flags |= TTM_PL_FLAG_TT; | ||
423 | flags |= TTM_PL_FLAG_VRAM; | ||
424 | } | ||
425 | if (!robj->pin_count) { | 421 | if (!robj->pin_count) { |
426 | robj->tobj.proposed_placement = flags | TTM_PL_MASK_CACHING; | 422 | if (lobj->wdomain) { |
423 | robj->tobj.proposed_placement = | ||
424 | radeon_object_flags_from_domain(lobj->wdomain); | ||
425 | } else { | ||
426 | robj->tobj.proposed_placement = | ||
427 | radeon_object_flags_from_domain(lobj->rdomain); | ||
428 | } | ||
427 | r = ttm_buffer_object_validate(&robj->tobj, | 429 | r = ttm_buffer_object_validate(&robj->tobj, |
428 | robj->tobj.proposed_placement, | 430 | robj->tobj.proposed_placement, |
429 | true, false); | 431 | true, false); |
430 | if (unlikely(r)) { | 432 | if (unlikely(r)) { |
431 | radeon_object_list_unreserve(head); | ||
432 | DRM_ERROR("radeon: failed to validate.\n"); | 433 | DRM_ERROR("radeon: failed to validate.\n"); |
433 | return r; | 434 | return r; |
434 | } | 435 | } |
435 | radeon_object_gpu_addr(robj); | 436 | radeon_object_gpu_addr(robj); |
436 | } | 437 | } |
437 | lobj->gpu_offset = robj->gpu_addr; | 438 | lobj->gpu_offset = robj->gpu_addr; |
439 | lobj->tiling_flags = robj->tiling_flags; | ||
438 | if (fence) { | 440 | if (fence) { |
439 | old_fence = (struct radeon_fence *)robj->tobj.sync_obj; | 441 | old_fence = (struct radeon_fence *)robj->tobj.sync_obj; |
440 | robj->tobj.sync_obj = radeon_fence_ref(fence); | 442 | robj->tobj.sync_obj = radeon_fence_ref(fence); |
@@ -479,3 +481,127 @@ unsigned long radeon_object_size(struct radeon_object *robj) | |||
479 | { | 481 | { |
480 | return robj->tobj.num_pages << PAGE_SHIFT; | 482 | return robj->tobj.num_pages << PAGE_SHIFT; |
481 | } | 483 | } |
484 | |||
485 | int radeon_object_get_surface_reg(struct radeon_object *robj) | ||
486 | { | ||
487 | struct radeon_device *rdev = robj->rdev; | ||
488 | struct radeon_surface_reg *reg; | ||
489 | struct radeon_object *old_object; | ||
490 | int steal; | ||
491 | int i; | ||
492 | |||
493 | if (!robj->tiling_flags) | ||
494 | return 0; | ||
495 | |||
496 | if (robj->surface_reg >= 0) { | ||
497 | reg = &rdev->surface_regs[robj->surface_reg]; | ||
498 | i = robj->surface_reg; | ||
499 | goto out; | ||
500 | } | ||
501 | |||
502 | steal = -1; | ||
503 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { | ||
504 | |||
505 | reg = &rdev->surface_regs[i]; | ||
506 | if (!reg->robj) | ||
507 | break; | ||
508 | |||
509 | old_object = reg->robj; | ||
510 | if (old_object->pin_count == 0) | ||
511 | steal = i; | ||
512 | } | ||
513 | |||
514 | /* if we are all out */ | ||
515 | if (i == RADEON_GEM_MAX_SURFACES) { | ||
516 | if (steal == -1) | ||
517 | return -ENOMEM; | ||
518 | /* find someone with a surface reg and nuke their BO */ | ||
519 | reg = &rdev->surface_regs[steal]; | ||
520 | old_object = reg->robj; | ||
521 | /* blow away the mapping */ | ||
522 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); | ||
523 | ttm_bo_unmap_virtual(&old_object->tobj); | ||
524 | old_object->surface_reg = -1; | ||
525 | i = steal; | ||
526 | } | ||
527 | |||
528 | robj->surface_reg = i; | ||
529 | reg->robj = robj; | ||
530 | |||
531 | out: | ||
532 | radeon_set_surface_reg(rdev, i, robj->tiling_flags, robj->pitch, | ||
533 | robj->tobj.mem.mm_node->start << PAGE_SHIFT, | ||
534 | robj->tobj.num_pages << PAGE_SHIFT); | ||
535 | return 0; | ||
536 | } | ||
537 | |||
538 | void radeon_object_clear_surface_reg(struct radeon_object *robj) | ||
539 | { | ||
540 | struct radeon_device *rdev = robj->rdev; | ||
541 | struct radeon_surface_reg *reg; | ||
542 | |||
543 | if (robj->surface_reg == -1) | ||
544 | return; | ||
545 | |||
546 | reg = &rdev->surface_regs[robj->surface_reg]; | ||
547 | radeon_clear_surface_reg(rdev, robj->surface_reg); | ||
548 | |||
549 | reg->robj = NULL; | ||
550 | robj->surface_reg = -1; | ||
551 | } | ||
552 | |||
553 | void radeon_object_set_tiling_flags(struct radeon_object *robj, | ||
554 | uint32_t tiling_flags, uint32_t pitch) | ||
555 | { | ||
556 | robj->tiling_flags = tiling_flags; | ||
557 | robj->pitch = pitch; | ||
558 | } | ||
559 | |||
560 | void radeon_object_get_tiling_flags(struct radeon_object *robj, | ||
561 | uint32_t *tiling_flags, | ||
562 | uint32_t *pitch) | ||
563 | { | ||
564 | if (tiling_flags) | ||
565 | *tiling_flags = robj->tiling_flags; | ||
566 | if (pitch) | ||
567 | *pitch = robj->pitch; | ||
568 | } | ||
569 | |||
570 | int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved, | ||
571 | bool force_drop) | ||
572 | { | ||
573 | if (!(robj->tiling_flags & RADEON_TILING_SURFACE)) | ||
574 | return 0; | ||
575 | |||
576 | if (force_drop) { | ||
577 | radeon_object_clear_surface_reg(robj); | ||
578 | return 0; | ||
579 | } | ||
580 | |||
581 | if (robj->tobj.mem.mem_type != TTM_PL_VRAM) { | ||
582 | if (!has_moved) | ||
583 | return 0; | ||
584 | |||
585 | if (robj->surface_reg >= 0) | ||
586 | radeon_object_clear_surface_reg(robj); | ||
587 | return 0; | ||
588 | } | ||
589 | |||
590 | if ((robj->surface_reg >= 0) && !has_moved) | ||
591 | return 0; | ||
592 | |||
593 | return radeon_object_get_surface_reg(robj); | ||
594 | } | ||
595 | |||
596 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | ||
597 | struct ttm_mem_reg *mem) | ||
598 | { | ||
599 | struct radeon_object *robj = container_of(bo, struct radeon_object, tobj); | ||
600 | radeon_object_check_tiling(robj, 0, 1); | ||
601 | } | ||
602 | |||
603 | void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) | ||
604 | { | ||
605 | struct radeon_object *robj = container_of(bo, struct radeon_object, tobj); | ||
606 | radeon_object_check_tiling(robj, 0, 0); | ||
607 | } | ||
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index a853261d1881..60d159308b88 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c | |||
@@ -126,32 +126,19 @@ static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib) | |||
126 | } | 126 | } |
127 | } | 127 | } |
128 | 128 | ||
129 | static void radeon_ib_cpu_flush(struct radeon_device *rdev, | ||
130 | struct radeon_ib *ib) | ||
131 | { | ||
132 | unsigned long tmp; | ||
133 | unsigned i; | ||
134 | |||
135 | /* To force CPU cache flush ugly but seems reliable */ | ||
136 | for (i = 0; i < ib->length_dw; i += (rdev->cp.align_mask + 1)) { | ||
137 | tmp = readl(&ib->ptr[i]); | ||
138 | } | ||
139 | } | ||
140 | |||
141 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) | 129 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) |
142 | { | 130 | { |
143 | int r = 0; | 131 | int r = 0; |
144 | 132 | ||
145 | mutex_lock(&rdev->ib_pool.mutex); | 133 | mutex_lock(&rdev->ib_pool.mutex); |
146 | radeon_ib_align(rdev, ib); | 134 | radeon_ib_align(rdev, ib); |
147 | radeon_ib_cpu_flush(rdev, ib); | ||
148 | if (!ib->length_dw || !rdev->cp.ready) { | 135 | if (!ib->length_dw || !rdev->cp.ready) { |
149 | /* TODO: Nothings in the ib we should report. */ | 136 | /* TODO: Nothings in the ib we should report. */ |
150 | mutex_unlock(&rdev->ib_pool.mutex); | 137 | mutex_unlock(&rdev->ib_pool.mutex); |
151 | DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx); | 138 | DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx); |
152 | return -EINVAL; | 139 | return -EINVAL; |
153 | } | 140 | } |
154 | /* 64 dwords should be enought for fence too */ | 141 | /* 64 dwords should be enough for fence too */ |
155 | r = radeon_ring_lock(rdev, 64); | 142 | r = radeon_ring_lock(rdev, 64); |
156 | if (r) { | 143 | if (r) { |
157 | DRM_ERROR("radeon: scheduling IB failled (%d).\n", r); | 144 | DRM_ERROR("radeon: scheduling IB failled (%d).\n", r); |
diff --git a/drivers/gpu/drm/radeon/radeon_share.h b/drivers/gpu/drm/radeon/radeon_share.h new file mode 100644 index 000000000000..63a773578f17 --- /dev/null +++ b/drivers/gpu/drm/radeon/radeon_share.h | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * Copyright 2008 Advanced Micro Devices, Inc. | ||
3 | * Copyright 2008 Red Hat Inc. | ||
4 | * Copyright 2009 Jerome Glisse. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
22 | * OTHER DEALINGS IN THE SOFTWARE. | ||
23 | * | ||
24 | * Authors: Dave Airlie | ||
25 | * Alex Deucher | ||
26 | * Jerome Glisse | ||
27 | */ | ||
28 | #ifndef __RADEON_SHARE_H__ | ||
29 | #define __RADEON_SHARE_H__ | ||
30 | |||
31 | void r100_vram_init_sizes(struct radeon_device *rdev); | ||
32 | |||
33 | void rs690_line_buffer_adjust(struct radeon_device *rdev, | ||
34 | struct drm_display_mode *mode1, | ||
35 | struct drm_display_mode *mode2); | ||
36 | |||
37 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev); | ||
38 | |||
39 | #endif | ||
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c new file mode 100644 index 000000000000..03c33cf4e14c --- /dev/null +++ b/drivers/gpu/drm/radeon/radeon_test.c | |||
@@ -0,0 +1,209 @@ | |||
1 | /* | ||
2 | * Copyright 2009 VMware, Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Michel Dänzer | ||
23 | */ | ||
24 | #include <drm/drmP.h> | ||
25 | #include <drm/radeon_drm.h> | ||
26 | #include "radeon_reg.h" | ||
27 | #include "radeon.h" | ||
28 | |||
29 | |||
30 | /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */ | ||
31 | void radeon_test_moves(struct radeon_device *rdev) | ||
32 | { | ||
33 | struct radeon_object *vram_obj = NULL; | ||
34 | struct radeon_object **gtt_obj = NULL; | ||
35 | struct radeon_fence *fence = NULL; | ||
36 | uint64_t gtt_addr, vram_addr; | ||
37 | unsigned i, n, size; | ||
38 | int r; | ||
39 | |||
40 | size = 1024 * 1024; | ||
41 | |||
42 | /* Number of tests = | ||
43 | * (Total GTT - IB pool - writeback page - ring buffer) / test size | ||
44 | */ | ||
45 | n = (rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - 4096 - | ||
46 | rdev->cp.ring_size) / size; | ||
47 | |||
48 | gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL); | ||
49 | if (!gtt_obj) { | ||
50 | DRM_ERROR("Failed to allocate %d pointers\n", n); | ||
51 | r = 1; | ||
52 | goto out_cleanup; | ||
53 | } | ||
54 | |||
55 | r = radeon_object_create(rdev, NULL, size, true, RADEON_GEM_DOMAIN_VRAM, | ||
56 | false, &vram_obj); | ||
57 | if (r) { | ||
58 | DRM_ERROR("Failed to create VRAM object\n"); | ||
59 | goto out_cleanup; | ||
60 | } | ||
61 | |||
62 | r = radeon_object_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr); | ||
63 | if (r) { | ||
64 | DRM_ERROR("Failed to pin VRAM object\n"); | ||
65 | goto out_cleanup; | ||
66 | } | ||
67 | |||
68 | for (i = 0; i < n; i++) { | ||
69 | void *gtt_map, *vram_map; | ||
70 | void **gtt_start, **gtt_end; | ||
71 | void **vram_start, **vram_end; | ||
72 | |||
73 | r = radeon_object_create(rdev, NULL, size, true, | ||
74 | RADEON_GEM_DOMAIN_GTT, false, gtt_obj + i); | ||
75 | if (r) { | ||
76 | DRM_ERROR("Failed to create GTT object %d\n", i); | ||
77 | goto out_cleanup; | ||
78 | } | ||
79 | |||
80 | r = radeon_object_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, >t_addr); | ||
81 | if (r) { | ||
82 | DRM_ERROR("Failed to pin GTT object %d\n", i); | ||
83 | goto out_cleanup; | ||
84 | } | ||
85 | |||
86 | r = radeon_object_kmap(gtt_obj[i], >t_map); | ||
87 | if (r) { | ||
88 | DRM_ERROR("Failed to map GTT object %d\n", i); | ||
89 | goto out_cleanup; | ||
90 | } | ||
91 | |||
92 | for (gtt_start = gtt_map, gtt_end = gtt_map + size; | ||
93 | gtt_start < gtt_end; | ||
94 | gtt_start++) | ||
95 | *gtt_start = gtt_start; | ||
96 | |||
97 | radeon_object_kunmap(gtt_obj[i]); | ||
98 | |||
99 | r = radeon_fence_create(rdev, &fence); | ||
100 | if (r) { | ||
101 | DRM_ERROR("Failed to create GTT->VRAM fence %d\n", i); | ||
102 | goto out_cleanup; | ||
103 | } | ||
104 | |||
105 | r = radeon_copy(rdev, gtt_addr, vram_addr, size / 4096, fence); | ||
106 | if (r) { | ||
107 | DRM_ERROR("Failed GTT->VRAM copy %d\n", i); | ||
108 | goto out_cleanup; | ||
109 | } | ||
110 | |||
111 | r = radeon_fence_wait(fence, false); | ||
112 | if (r) { | ||
113 | DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i); | ||
114 | goto out_cleanup; | ||
115 | } | ||
116 | |||
117 | radeon_fence_unref(&fence); | ||
118 | |||
119 | r = radeon_object_kmap(vram_obj, &vram_map); | ||
120 | if (r) { | ||
121 | DRM_ERROR("Failed to map VRAM object after copy %d\n", i); | ||
122 | goto out_cleanup; | ||
123 | } | ||
124 | |||
125 | for (gtt_start = gtt_map, gtt_end = gtt_map + size, | ||
126 | vram_start = vram_map, vram_end = vram_map + size; | ||
127 | vram_start < vram_end; | ||
128 | gtt_start++, vram_start++) { | ||
129 | if (*vram_start != gtt_start) { | ||
130 | DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, " | ||
131 | "expected 0x%p (GTT map 0x%p-0x%p)\n", | ||
132 | i, *vram_start, gtt_start, gtt_map, | ||
133 | gtt_end); | ||
134 | radeon_object_kunmap(vram_obj); | ||
135 | goto out_cleanup; | ||
136 | } | ||
137 | *vram_start = vram_start; | ||
138 | } | ||
139 | |||
140 | radeon_object_kunmap(vram_obj); | ||
141 | |||
142 | r = radeon_fence_create(rdev, &fence); | ||
143 | if (r) { | ||
144 | DRM_ERROR("Failed to create VRAM->GTT fence %d\n", i); | ||
145 | goto out_cleanup; | ||
146 | } | ||
147 | |||
148 | r = radeon_copy(rdev, vram_addr, gtt_addr, size / 4096, fence); | ||
149 | if (r) { | ||
150 | DRM_ERROR("Failed VRAM->GTT copy %d\n", i); | ||
151 | goto out_cleanup; | ||
152 | } | ||
153 | |||
154 | r = radeon_fence_wait(fence, false); | ||
155 | if (r) { | ||
156 | DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i); | ||
157 | goto out_cleanup; | ||
158 | } | ||
159 | |||
160 | radeon_fence_unref(&fence); | ||
161 | |||
162 | r = radeon_object_kmap(gtt_obj[i], >t_map); | ||
163 | if (r) { | ||
164 | DRM_ERROR("Failed to map GTT object after copy %d\n", i); | ||
165 | goto out_cleanup; | ||
166 | } | ||
167 | |||
168 | for (gtt_start = gtt_map, gtt_end = gtt_map + size, | ||
169 | vram_start = vram_map, vram_end = vram_map + size; | ||
170 | gtt_start < gtt_end; | ||
171 | gtt_start++, vram_start++) { | ||
172 | if (*gtt_start != vram_start) { | ||
173 | DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, " | ||
174 | "expected 0x%p (VRAM map 0x%p-0x%p)\n", | ||
175 | i, *gtt_start, vram_start, vram_map, | ||
176 | vram_end); | ||
177 | radeon_object_kunmap(gtt_obj[i]); | ||
178 | goto out_cleanup; | ||
179 | } | ||
180 | } | ||
181 | |||
182 | radeon_object_kunmap(gtt_obj[i]); | ||
183 | |||
184 | DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", | ||
185 | gtt_addr - rdev->mc.gtt_location); | ||
186 | } | ||
187 | |||
188 | out_cleanup: | ||
189 | if (vram_obj) { | ||
190 | radeon_object_unpin(vram_obj); | ||
191 | radeon_object_unref(&vram_obj); | ||
192 | } | ||
193 | if (gtt_obj) { | ||
194 | for (i = 0; i < n; i++) { | ||
195 | if (gtt_obj[i]) { | ||
196 | radeon_object_unpin(gtt_obj[i]); | ||
197 | radeon_object_unref(>t_obj[i]); | ||
198 | } | ||
199 | } | ||
200 | kfree(gtt_obj); | ||
201 | } | ||
202 | if (fence) { | ||
203 | radeon_fence_unref(&fence); | ||
204 | } | ||
205 | if (r) { | ||
206 | printk(KERN_WARNING "Error while testing BO move.\n"); | ||
207 | } | ||
208 | } | ||
209 | |||
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 1227a97f5169..15c3531377ed 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c | |||
@@ -355,23 +355,26 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, | |||
355 | if (!rdev->cp.ready) { | 355 | if (!rdev->cp.ready) { |
356 | /* use memcpy */ | 356 | /* use memcpy */ |
357 | DRM_ERROR("CP is not ready use memcpy.\n"); | 357 | DRM_ERROR("CP is not ready use memcpy.\n"); |
358 | return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); | 358 | goto memcpy; |
359 | } | 359 | } |
360 | 360 | ||
361 | if (old_mem->mem_type == TTM_PL_VRAM && | 361 | if (old_mem->mem_type == TTM_PL_VRAM && |
362 | new_mem->mem_type == TTM_PL_SYSTEM) { | 362 | new_mem->mem_type == TTM_PL_SYSTEM) { |
363 | return radeon_move_vram_ram(bo, evict, interruptible, | 363 | r = radeon_move_vram_ram(bo, evict, interruptible, |
364 | no_wait, new_mem); | 364 | no_wait, new_mem); |
365 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && | 365 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
366 | new_mem->mem_type == TTM_PL_VRAM) { | 366 | new_mem->mem_type == TTM_PL_VRAM) { |
367 | return radeon_move_ram_vram(bo, evict, interruptible, | 367 | r = radeon_move_ram_vram(bo, evict, interruptible, |
368 | no_wait, new_mem); | 368 | no_wait, new_mem); |
369 | } else { | 369 | } else { |
370 | r = radeon_move_blit(bo, evict, no_wait, new_mem, old_mem); | 370 | r = radeon_move_blit(bo, evict, no_wait, new_mem, old_mem); |
371 | if (unlikely(r)) { | ||
372 | return r; | ||
373 | } | ||
374 | } | 371 | } |
372 | |||
373 | if (r) { | ||
374 | memcpy: | ||
375 | r = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); | ||
376 | } | ||
377 | |||
375 | return r; | 378 | return r; |
376 | } | 379 | } |
377 | 380 | ||
@@ -429,6 +432,8 @@ static struct ttm_bo_driver radeon_bo_driver = { | |||
429 | .sync_obj_flush = &radeon_sync_obj_flush, | 432 | .sync_obj_flush = &radeon_sync_obj_flush, |
430 | .sync_obj_unref = &radeon_sync_obj_unref, | 433 | .sync_obj_unref = &radeon_sync_obj_unref, |
431 | .sync_obj_ref = &radeon_sync_obj_ref, | 434 | .sync_obj_ref = &radeon_sync_obj_ref, |
435 | .move_notify = &radeon_bo_move_notify, | ||
436 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, | ||
432 | }; | 437 | }; |
433 | 438 | ||
434 | int radeon_ttm_init(struct radeon_device *rdev) | 439 | int radeon_ttm_init(struct radeon_device *rdev) |
@@ -442,13 +447,14 @@ int radeon_ttm_init(struct radeon_device *rdev) | |||
442 | /* No others user of address space so set it to 0 */ | 447 | /* No others user of address space so set it to 0 */ |
443 | r = ttm_bo_device_init(&rdev->mman.bdev, | 448 | r = ttm_bo_device_init(&rdev->mman.bdev, |
444 | rdev->mman.mem_global_ref.object, | 449 | rdev->mman.mem_global_ref.object, |
445 | &radeon_bo_driver, DRM_FILE_PAGE_OFFSET); | 450 | &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, |
451 | rdev->need_dma32); | ||
446 | if (r) { | 452 | if (r) { |
447 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | 453 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); |
448 | return r; | 454 | return r; |
449 | } | 455 | } |
450 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 0, | 456 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 0, |
451 | ((rdev->mc.aper_size) >> PAGE_SHIFT)); | 457 | ((rdev->mc.real_vram_size) >> PAGE_SHIFT)); |
452 | if (r) { | 458 | if (r) { |
453 | DRM_ERROR("Failed initializing VRAM heap.\n"); | 459 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
454 | return r; | 460 | return r; |
@@ -465,7 +471,7 @@ int radeon_ttm_init(struct radeon_device *rdev) | |||
465 | return r; | 471 | return r; |
466 | } | 472 | } |
467 | DRM_INFO("radeon: %uM of VRAM memory ready\n", | 473 | DRM_INFO("radeon: %uM of VRAM memory ready\n", |
468 | rdev->mc.vram_size / (1024 * 1024)); | 474 | rdev->mc.real_vram_size / (1024 * 1024)); |
469 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0, | 475 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0, |
470 | ((rdev->mc.gtt_size) >> PAGE_SHIFT)); | 476 | ((rdev->mc.gtt_size) >> PAGE_SHIFT)); |
471 | if (r) { | 477 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index cc074b5a8f74..b29affd9c5d8 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <drm/drmP.h> | 29 | #include <drm/drmP.h> |
30 | #include "radeon_reg.h" | 30 | #include "radeon_reg.h" |
31 | #include "radeon.h" | 31 | #include "radeon.h" |
32 | #include "radeon_share.h" | ||
32 | 33 | ||
33 | /* rs400,rs480 depends on : */ | 34 | /* rs400,rs480 depends on : */ |
34 | void r100_hdp_reset(struct radeon_device *rdev); | 35 | void r100_hdp_reset(struct radeon_device *rdev); |
@@ -164,7 +165,9 @@ int rs400_gart_enable(struct radeon_device *rdev) | |||
164 | WREG32(RADEON_BUS_CNTL, tmp); | 165 | WREG32(RADEON_BUS_CNTL, tmp); |
165 | } | 166 | } |
166 | /* Table should be in 32bits address space so ignore bits above. */ | 167 | /* Table should be in 32bits address space so ignore bits above. */ |
167 | tmp = rdev->gart.table_addr & 0xfffff000; | 168 | tmp = (u32)rdev->gart.table_addr & 0xfffff000; |
169 | tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; | ||
170 | |||
168 | WREG32_MC(RS480_GART_BASE, tmp); | 171 | WREG32_MC(RS480_GART_BASE, tmp); |
169 | /* TODO: more tweaking here */ | 172 | /* TODO: more tweaking here */ |
170 | WREG32_MC(RS480_GART_FEATURE_ID, | 173 | WREG32_MC(RS480_GART_FEATURE_ID, |
@@ -201,10 +204,17 @@ void rs400_gart_disable(struct radeon_device *rdev) | |||
201 | 204 | ||
202 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | 205 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
203 | { | 206 | { |
207 | uint32_t entry; | ||
208 | |||
204 | if (i < 0 || i > rdev->gart.num_gpu_pages) { | 209 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
205 | return -EINVAL; | 210 | return -EINVAL; |
206 | } | 211 | } |
207 | rdev->gart.table.ram.ptr[i] = cpu_to_le32(((uint32_t)addr) | 0xC); | 212 | |
213 | entry = (lower_32_bits(addr) & PAGE_MASK) | | ||
214 | ((upper_32_bits(addr) & 0xff) << 4) | | ||
215 | 0xc; | ||
216 | entry = cpu_to_le32(entry); | ||
217 | rdev->gart.table.ram.ptr[i] = entry; | ||
208 | return 0; | 218 | return 0; |
209 | } | 219 | } |
210 | 220 | ||
@@ -223,10 +233,9 @@ int rs400_mc_init(struct radeon_device *rdev) | |||
223 | 233 | ||
224 | rs400_gpu_init(rdev); | 234 | rs400_gpu_init(rdev); |
225 | rs400_gart_disable(rdev); | 235 | rs400_gart_disable(rdev); |
226 | rdev->mc.gtt_location = rdev->mc.vram_size; | 236 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
227 | rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); | 237 | rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); |
228 | rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); | 238 | rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); |
229 | rdev->mc.vram_location = 0xFFFFFFFFUL; | ||
230 | r = radeon_mc_setup(rdev); | 239 | r = radeon_mc_setup(rdev); |
231 | if (r) { | 240 | if (r) { |
232 | return r; | 241 | return r; |
@@ -238,7 +247,7 @@ int rs400_mc_init(struct radeon_device *rdev) | |||
238 | "programming pipes. Bad things might happen.\n"); | 247 | "programming pipes. Bad things might happen.\n"); |
239 | } | 248 | } |
240 | 249 | ||
241 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; | 250 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
242 | tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16); | 251 | tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16); |
243 | tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16); | 252 | tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16); |
244 | WREG32(RADEON_MC_FB_LOCATION, tmp); | 253 | WREG32(RADEON_MC_FB_LOCATION, tmp); |
@@ -284,21 +293,12 @@ void rs400_gpu_init(struct radeon_device *rdev) | |||
284 | */ | 293 | */ |
285 | void rs400_vram_info(struct radeon_device *rdev) | 294 | void rs400_vram_info(struct radeon_device *rdev) |
286 | { | 295 | { |
287 | uint32_t tom; | ||
288 | |||
289 | rs400_gart_adjust_size(rdev); | 296 | rs400_gart_adjust_size(rdev); |
290 | /* DDR for all card after R300 & IGP */ | 297 | /* DDR for all card after R300 & IGP */ |
291 | rdev->mc.vram_is_ddr = true; | 298 | rdev->mc.vram_is_ddr = true; |
292 | rdev->mc.vram_width = 128; | 299 | rdev->mc.vram_width = 128; |
293 | 300 | ||
294 | /* read NB_TOM to get the amount of ram stolen for the GPU */ | 301 | r100_vram_init_sizes(rdev); |
295 | tom = RREG32(RADEON_NB_TOM); | ||
296 | rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); | ||
297 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); | ||
298 | |||
299 | /* Could aper size report 0 ? */ | ||
300 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | ||
301 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | ||
302 | } | 302 | } |
303 | 303 | ||
304 | 304 | ||
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index ab0c967553e6..bbea6dee4a94 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c | |||
@@ -223,7 +223,7 @@ int rs600_mc_init(struct radeon_device *rdev) | |||
223 | printk(KERN_WARNING "Failed to wait MC idle while " | 223 | printk(KERN_WARNING "Failed to wait MC idle while " |
224 | "programming pipes. Bad things might happen.\n"); | 224 | "programming pipes. Bad things might happen.\n"); |
225 | } | 225 | } |
226 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; | 226 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
227 | tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16); | 227 | tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16); |
228 | tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16); | 228 | tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16); |
229 | WREG32_MC(RS600_MC_FB_LOCATION, tmp); | 229 | WREG32_MC(RS600_MC_FB_LOCATION, tmp); |
@@ -301,6 +301,11 @@ void rs600_vram_info(struct radeon_device *rdev) | |||
301 | rdev->mc.vram_width = 128; | 301 | rdev->mc.vram_width = 128; |
302 | } | 302 | } |
303 | 303 | ||
304 | void rs600_bandwidth_update(struct radeon_device *rdev) | ||
305 | { | ||
306 | /* FIXME: implement, should this be like rs690 ? */ | ||
307 | } | ||
308 | |||
304 | 309 | ||
305 | /* | 310 | /* |
306 | * Indirect registers accessor | 311 | * Indirect registers accessor |
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index 79ba85042b5f..839595b00728 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c | |||
@@ -28,6 +28,9 @@ | |||
28 | #include "drmP.h" | 28 | #include "drmP.h" |
29 | #include "radeon_reg.h" | 29 | #include "radeon_reg.h" |
30 | #include "radeon.h" | 30 | #include "radeon.h" |
31 | #include "rs690r.h" | ||
32 | #include "atom.h" | ||
33 | #include "atom-bits.h" | ||
31 | 34 | ||
32 | /* rs690,rs740 depends on : */ | 35 | /* rs690,rs740 depends on : */ |
33 | void r100_hdp_reset(struct radeon_device *rdev); | 36 | void r100_hdp_reset(struct radeon_device *rdev); |
@@ -64,7 +67,7 @@ int rs690_mc_init(struct radeon_device *rdev) | |||
64 | rs400_gart_disable(rdev); | 67 | rs400_gart_disable(rdev); |
65 | 68 | ||
66 | /* Setup GPU memory space */ | 69 | /* Setup GPU memory space */ |
67 | rdev->mc.gtt_location = rdev->mc.vram_size; | 70 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
68 | rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); | 71 | rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); |
69 | rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); | 72 | rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); |
70 | rdev->mc.vram_location = 0xFFFFFFFFUL; | 73 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
@@ -79,7 +82,7 @@ int rs690_mc_init(struct radeon_device *rdev) | |||
79 | printk(KERN_WARNING "Failed to wait MC idle while " | 82 | printk(KERN_WARNING "Failed to wait MC idle while " |
80 | "programming pipes. Bad things might happen.\n"); | 83 | "programming pipes. Bad things might happen.\n"); |
81 | } | 84 | } |
82 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; | 85 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
83 | tmp = REG_SET(RS690_MC_FB_TOP, tmp >> 16); | 86 | tmp = REG_SET(RS690_MC_FB_TOP, tmp >> 16); |
84 | tmp |= REG_SET(RS690_MC_FB_START, rdev->mc.vram_location >> 16); | 87 | tmp |= REG_SET(RS690_MC_FB_START, rdev->mc.vram_location >> 16); |
85 | WREG32_MC(RS690_MCCFG_FB_LOCATION, tmp); | 88 | WREG32_MC(RS690_MCCFG_FB_LOCATION, tmp); |
@@ -138,9 +141,82 @@ void rs690_gpu_init(struct radeon_device *rdev) | |||
138 | /* | 141 | /* |
139 | * VRAM info. | 142 | * VRAM info. |
140 | */ | 143 | */ |
144 | void rs690_pm_info(struct radeon_device *rdev) | ||
145 | { | ||
146 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | ||
147 | struct _ATOM_INTEGRATED_SYSTEM_INFO *info; | ||
148 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2; | ||
149 | void *ptr; | ||
150 | uint16_t data_offset; | ||
151 | uint8_t frev, crev; | ||
152 | fixed20_12 tmp; | ||
153 | |||
154 | atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, | ||
155 | &frev, &crev, &data_offset); | ||
156 | ptr = rdev->mode_info.atom_context->bios + data_offset; | ||
157 | info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr; | ||
158 | info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr; | ||
159 | /* Get various system informations from bios */ | ||
160 | switch (crev) { | ||
161 | case 1: | ||
162 | tmp.full = rfixed_const(100); | ||
163 | rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock); | ||
164 | rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); | ||
165 | rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock)); | ||
166 | rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock)); | ||
167 | rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth); | ||
168 | break; | ||
169 | case 2: | ||
170 | tmp.full = rfixed_const(100); | ||
171 | rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock); | ||
172 | rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); | ||
173 | rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock); | ||
174 | rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); | ||
175 | rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq); | ||
176 | rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp); | ||
177 | rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth)); | ||
178 | break; | ||
179 | default: | ||
180 | tmp.full = rfixed_const(100); | ||
181 | /* We assume the slower possible clock ie worst case */ | ||
182 | /* DDR 333Mhz */ | ||
183 | rdev->pm.igp_sideport_mclk.full = rfixed_const(333); | ||
184 | /* FIXME: system clock ? */ | ||
185 | rdev->pm.igp_system_mclk.full = rfixed_const(100); | ||
186 | rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); | ||
187 | rdev->pm.igp_ht_link_clk.full = rfixed_const(200); | ||
188 | rdev->pm.igp_ht_link_width.full = rfixed_const(8); | ||
189 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); | ||
190 | break; | ||
191 | } | ||
192 | /* Compute various bandwidth */ | ||
193 | /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ | ||
194 | tmp.full = rfixed_const(4); | ||
195 | rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp); | ||
196 | /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 | ||
197 | * = ht_clk * ht_width / 5 | ||
198 | */ | ||
199 | tmp.full = rfixed_const(5); | ||
200 | rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk, | ||
201 | rdev->pm.igp_ht_link_width); | ||
202 | rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp); | ||
203 | if (tmp.full < rdev->pm.max_bandwidth.full) { | ||
204 | /* HT link is a limiting factor */ | ||
205 | rdev->pm.max_bandwidth.full = tmp.full; | ||
206 | } | ||
207 | /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 | ||
208 | * = (sideport_clk * 14) / 10 | ||
209 | */ | ||
210 | tmp.full = rfixed_const(14); | ||
211 | rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp); | ||
212 | tmp.full = rfixed_const(10); | ||
213 | rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp); | ||
214 | } | ||
215 | |||
141 | void rs690_vram_info(struct radeon_device *rdev) | 216 | void rs690_vram_info(struct radeon_device *rdev) |
142 | { | 217 | { |
143 | uint32_t tmp; | 218 | uint32_t tmp; |
219 | fixed20_12 a; | ||
144 | 220 | ||
145 | rs400_gart_adjust_size(rdev); | 221 | rs400_gart_adjust_size(rdev); |
146 | /* DDR for all card after R300 & IGP */ | 222 | /* DDR for all card after R300 & IGP */ |
@@ -152,12 +228,409 @@ void rs690_vram_info(struct radeon_device *rdev) | |||
152 | } else { | 228 | } else { |
153 | rdev->mc.vram_width = 64; | 229 | rdev->mc.vram_width = 64; |
154 | } | 230 | } |
155 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); | 231 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
232 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | ||
156 | 233 | ||
157 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | 234 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
158 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | 235 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
236 | rs690_pm_info(rdev); | ||
237 | /* FIXME: we should enforce default clock in case GPU is not in | ||
238 | * default setup | ||
239 | */ | ||
240 | a.full = rfixed_const(100); | ||
241 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); | ||
242 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | ||
243 | a.full = rfixed_const(16); | ||
244 | /* core_bandwidth = sclk(Mhz) * 16 */ | ||
245 | rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); | ||
246 | } | ||
247 | |||
248 | void rs690_line_buffer_adjust(struct radeon_device *rdev, | ||
249 | struct drm_display_mode *mode1, | ||
250 | struct drm_display_mode *mode2) | ||
251 | { | ||
252 | u32 tmp; | ||
253 | |||
254 | /* | ||
255 | * Line Buffer Setup | ||
256 | * There is a single line buffer shared by both display controllers. | ||
257 | * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between | ||
258 | * the display controllers. The paritioning can either be done | ||
259 | * manually or via one of four preset allocations specified in bits 1:0: | ||
260 | * 0 - line buffer is divided in half and shared between crtc | ||
261 | * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 | ||
262 | * 2 - D1 gets the whole buffer | ||
263 | * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 | ||
264 | * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual | ||
265 | * allocation mode. In manual allocation mode, D1 always starts at 0, | ||
266 | * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. | ||
267 | */ | ||
268 | tmp = RREG32(DC_LB_MEMORY_SPLIT) & ~DC_LB_MEMORY_SPLIT_MASK; | ||
269 | tmp &= ~DC_LB_MEMORY_SPLIT_SHIFT_MODE; | ||
270 | /* auto */ | ||
271 | if (mode1 && mode2) { | ||
272 | if (mode1->hdisplay > mode2->hdisplay) { | ||
273 | if (mode1->hdisplay > 2560) | ||
274 | tmp |= DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; | ||
275 | else | ||
276 | tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; | ||
277 | } else if (mode2->hdisplay > mode1->hdisplay) { | ||
278 | if (mode2->hdisplay > 2560) | ||
279 | tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; | ||
280 | else | ||
281 | tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; | ||
282 | } else | ||
283 | tmp |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; | ||
284 | } else if (mode1) { | ||
285 | tmp |= DC_LB_MEMORY_SPLIT_D1_ONLY; | ||
286 | } else if (mode2) { | ||
287 | tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; | ||
288 | } | ||
289 | WREG32(DC_LB_MEMORY_SPLIT, tmp); | ||
159 | } | 290 | } |
160 | 291 | ||
292 | struct rs690_watermark { | ||
293 | u32 lb_request_fifo_depth; | ||
294 | fixed20_12 num_line_pair; | ||
295 | fixed20_12 estimated_width; | ||
296 | fixed20_12 worst_case_latency; | ||
297 | fixed20_12 consumption_rate; | ||
298 | fixed20_12 active_time; | ||
299 | fixed20_12 dbpp; | ||
300 | fixed20_12 priority_mark_max; | ||
301 | fixed20_12 priority_mark; | ||
302 | fixed20_12 sclk; | ||
303 | }; | ||
304 | |||
305 | void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, | ||
306 | struct radeon_crtc *crtc, | ||
307 | struct rs690_watermark *wm) | ||
308 | { | ||
309 | struct drm_display_mode *mode = &crtc->base.mode; | ||
310 | fixed20_12 a, b, c; | ||
311 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; | ||
312 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; | ||
313 | /* FIXME: detect IGP with sideport memory, i don't think there is any | ||
314 | * such product available | ||
315 | */ | ||
316 | bool sideport = false; | ||
317 | |||
318 | if (!crtc->base.enabled) { | ||
319 | /* FIXME: wouldn't it better to set priority mark to maximum */ | ||
320 | wm->lb_request_fifo_depth = 4; | ||
321 | return; | ||
322 | } | ||
323 | |||
324 | if (crtc->vsc.full > rfixed_const(2)) | ||
325 | wm->num_line_pair.full = rfixed_const(2); | ||
326 | else | ||
327 | wm->num_line_pair.full = rfixed_const(1); | ||
328 | |||
329 | b.full = rfixed_const(mode->crtc_hdisplay); | ||
330 | c.full = rfixed_const(256); | ||
331 | a.full = rfixed_mul(wm->num_line_pair, b); | ||
332 | request_fifo_depth.full = rfixed_div(a, c); | ||
333 | if (a.full < rfixed_const(4)) { | ||
334 | wm->lb_request_fifo_depth = 4; | ||
335 | } else { | ||
336 | wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); | ||
337 | } | ||
338 | |||
339 | /* Determine consumption rate | ||
340 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) | ||
341 | * vtaps = number of vertical taps, | ||
342 | * vsc = vertical scaling ratio, defined as source/destination | ||
343 | * hsc = horizontal scaling ration, defined as source/destination | ||
344 | */ | ||
345 | a.full = rfixed_const(mode->clock); | ||
346 | b.full = rfixed_const(1000); | ||
347 | a.full = rfixed_div(a, b); | ||
348 | pclk.full = rfixed_div(b, a); | ||
349 | if (crtc->rmx_type != RMX_OFF) { | ||
350 | b.full = rfixed_const(2); | ||
351 | if (crtc->vsc.full > b.full) | ||
352 | b.full = crtc->vsc.full; | ||
353 | b.full = rfixed_mul(b, crtc->hsc); | ||
354 | c.full = rfixed_const(2); | ||
355 | b.full = rfixed_div(b, c); | ||
356 | consumption_time.full = rfixed_div(pclk, b); | ||
357 | } else { | ||
358 | consumption_time.full = pclk.full; | ||
359 | } | ||
360 | a.full = rfixed_const(1); | ||
361 | wm->consumption_rate.full = rfixed_div(a, consumption_time); | ||
362 | |||
363 | |||
364 | /* Determine line time | ||
365 | * LineTime = total time for one line of displayhtotal | ||
366 | * LineTime = total number of horizontal pixels | ||
367 | * pclk = pixel clock period(ns) | ||
368 | */ | ||
369 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); | ||
370 | line_time.full = rfixed_mul(a, pclk); | ||
371 | |||
372 | /* Determine active time | ||
373 | * ActiveTime = time of active region of display within one line, | ||
374 | * hactive = total number of horizontal active pixels | ||
375 | * htotal = total number of horizontal pixels | ||
376 | */ | ||
377 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); | ||
378 | b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | ||
379 | wm->active_time.full = rfixed_mul(line_time, b); | ||
380 | wm->active_time.full = rfixed_div(wm->active_time, a); | ||
381 | |||
382 | /* Maximun bandwidth is the minimun bandwidth of all component */ | ||
383 | rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; | ||
384 | if (sideport) { | ||
385 | if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && | ||
386 | rdev->pm.sideport_bandwidth.full) | ||
387 | rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; | ||
388 | read_delay_latency.full = rfixed_const(370 * 800 * 1000); | ||
389 | read_delay_latency.full = rfixed_div(read_delay_latency, | ||
390 | rdev->pm.igp_sideport_mclk); | ||
391 | } else { | ||
392 | if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && | ||
393 | rdev->pm.k8_bandwidth.full) | ||
394 | rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; | ||
395 | if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && | ||
396 | rdev->pm.ht_bandwidth.full) | ||
397 | rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; | ||
398 | read_delay_latency.full = rfixed_const(5000); | ||
399 | } | ||
400 | |||
401 | /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ | ||
402 | a.full = rfixed_const(16); | ||
403 | rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a); | ||
404 | a.full = rfixed_const(1000); | ||
405 | rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk); | ||
406 | /* Determine chunk time | ||
407 | * ChunkTime = the time it takes the DCP to send one chunk of data | ||
408 | * to the LB which consists of pipeline delay and inter chunk gap | ||
409 | * sclk = system clock(ns) | ||
410 | */ | ||
411 | a.full = rfixed_const(256 * 13); | ||
412 | chunk_time.full = rfixed_mul(rdev->pm.sclk, a); | ||
413 | a.full = rfixed_const(10); | ||
414 | chunk_time.full = rfixed_div(chunk_time, a); | ||
415 | |||
416 | /* Determine the worst case latency | ||
417 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) | ||
418 | * WorstCaseLatency = worst case time from urgent to when the MC starts | ||
419 | * to return data | ||
420 | * READ_DELAY_IDLE_MAX = constant of 1us | ||
421 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB | ||
422 | * which consists of pipeline delay and inter chunk gap | ||
423 | */ | ||
424 | if (rfixed_trunc(wm->num_line_pair) > 1) { | ||
425 | a.full = rfixed_const(3); | ||
426 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); | ||
427 | wm->worst_case_latency.full += read_delay_latency.full; | ||
428 | } else { | ||
429 | a.full = rfixed_const(2); | ||
430 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); | ||
431 | wm->worst_case_latency.full += read_delay_latency.full; | ||
432 | } | ||
433 | |||
434 | /* Determine the tolerable latency | ||
435 | * TolerableLatency = Any given request has only 1 line time | ||
436 | * for the data to be returned | ||
437 | * LBRequestFifoDepth = Number of chunk requests the LB can | ||
438 | * put into the request FIFO for a display | ||
439 | * LineTime = total time for one line of display | ||
440 | * ChunkTime = the time it takes the DCP to send one chunk | ||
441 | * of data to the LB which consists of | ||
442 | * pipeline delay and inter chunk gap | ||
443 | */ | ||
444 | if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { | ||
445 | tolerable_latency.full = line_time.full; | ||
446 | } else { | ||
447 | tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); | ||
448 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; | ||
449 | tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); | ||
450 | tolerable_latency.full = line_time.full - tolerable_latency.full; | ||
451 | } | ||
452 | /* We assume worst case 32bits (4 bytes) */ | ||
453 | wm->dbpp.full = rfixed_const(4 * 8); | ||
454 | |||
455 | /* Determine the maximum priority mark | ||
456 | * width = viewport width in pixels | ||
457 | */ | ||
458 | a.full = rfixed_const(16); | ||
459 | wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | ||
460 | wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); | ||
461 | |||
462 | /* Determine estimated width */ | ||
463 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; | ||
464 | estimated_width.full = rfixed_div(estimated_width, consumption_time); | ||
465 | if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { | ||
466 | wm->priority_mark.full = rfixed_const(10); | ||
467 | } else { | ||
468 | a.full = rfixed_const(16); | ||
469 | wm->priority_mark.full = rfixed_div(estimated_width, a); | ||
470 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; | ||
471 | } | ||
472 | } | ||
473 | |||
474 | void rs690_bandwidth_update(struct radeon_device *rdev) | ||
475 | { | ||
476 | struct drm_display_mode *mode0 = NULL; | ||
477 | struct drm_display_mode *mode1 = NULL; | ||
478 | struct rs690_watermark wm0; | ||
479 | struct rs690_watermark wm1; | ||
480 | u32 tmp; | ||
481 | fixed20_12 priority_mark02, priority_mark12, fill_rate; | ||
482 | fixed20_12 a, b; | ||
483 | |||
484 | if (rdev->mode_info.crtcs[0]->base.enabled) | ||
485 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | ||
486 | if (rdev->mode_info.crtcs[1]->base.enabled) | ||
487 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | ||
488 | /* | ||
489 | * Set display0/1 priority up in the memory controller for | ||
490 | * modes if the user specifies HIGH for displaypriority | ||
491 | * option. | ||
492 | */ | ||
493 | if (rdev->disp_priority == 2) { | ||
494 | tmp = RREG32_MC(MC_INIT_MISC_LAT_TIMER); | ||
495 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; | ||
496 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; | ||
497 | if (mode1) | ||
498 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); | ||
499 | if (mode0) | ||
500 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); | ||
501 | WREG32_MC(MC_INIT_MISC_LAT_TIMER, tmp); | ||
502 | } | ||
503 | rs690_line_buffer_adjust(rdev, mode0, mode1); | ||
504 | |||
505 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) | ||
506 | WREG32(DCP_CONTROL, 0); | ||
507 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) | ||
508 | WREG32(DCP_CONTROL, 2); | ||
509 | |||
510 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); | ||
511 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); | ||
512 | |||
513 | tmp = (wm0.lb_request_fifo_depth - 1); | ||
514 | tmp |= (wm1.lb_request_fifo_depth - 1) << 16; | ||
515 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); | ||
516 | |||
517 | if (mode0 && mode1) { | ||
518 | if (rfixed_trunc(wm0.dbpp) > 64) | ||
519 | a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); | ||
520 | else | ||
521 | a.full = wm0.num_line_pair.full; | ||
522 | if (rfixed_trunc(wm1.dbpp) > 64) | ||
523 | b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); | ||
524 | else | ||
525 | b.full = wm1.num_line_pair.full; | ||
526 | a.full += b.full; | ||
527 | fill_rate.full = rfixed_div(wm0.sclk, a); | ||
528 | if (wm0.consumption_rate.full > fill_rate.full) { | ||
529 | b.full = wm0.consumption_rate.full - fill_rate.full; | ||
530 | b.full = rfixed_mul(b, wm0.active_time); | ||
531 | a.full = rfixed_mul(wm0.worst_case_latency, | ||
532 | wm0.consumption_rate); | ||
533 | a.full = a.full + b.full; | ||
534 | b.full = rfixed_const(16 * 1000); | ||
535 | priority_mark02.full = rfixed_div(a, b); | ||
536 | } else { | ||
537 | a.full = rfixed_mul(wm0.worst_case_latency, | ||
538 | wm0.consumption_rate); | ||
539 | b.full = rfixed_const(16 * 1000); | ||
540 | priority_mark02.full = rfixed_div(a, b); | ||
541 | } | ||
542 | if (wm1.consumption_rate.full > fill_rate.full) { | ||
543 | b.full = wm1.consumption_rate.full - fill_rate.full; | ||
544 | b.full = rfixed_mul(b, wm1.active_time); | ||
545 | a.full = rfixed_mul(wm1.worst_case_latency, | ||
546 | wm1.consumption_rate); | ||
547 | a.full = a.full + b.full; | ||
548 | b.full = rfixed_const(16 * 1000); | ||
549 | priority_mark12.full = rfixed_div(a, b); | ||
550 | } else { | ||
551 | a.full = rfixed_mul(wm1.worst_case_latency, | ||
552 | wm1.consumption_rate); | ||
553 | b.full = rfixed_const(16 * 1000); | ||
554 | priority_mark12.full = rfixed_div(a, b); | ||
555 | } | ||
556 | if (wm0.priority_mark.full > priority_mark02.full) | ||
557 | priority_mark02.full = wm0.priority_mark.full; | ||
558 | if (rfixed_trunc(priority_mark02) < 0) | ||
559 | priority_mark02.full = 0; | ||
560 | if (wm0.priority_mark_max.full > priority_mark02.full) | ||
561 | priority_mark02.full = wm0.priority_mark_max.full; | ||
562 | if (wm1.priority_mark.full > priority_mark12.full) | ||
563 | priority_mark12.full = wm1.priority_mark.full; | ||
564 | if (rfixed_trunc(priority_mark12) < 0) | ||
565 | priority_mark12.full = 0; | ||
566 | if (wm1.priority_mark_max.full > priority_mark12.full) | ||
567 | priority_mark12.full = wm1.priority_mark_max.full; | ||
568 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); | ||
569 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); | ||
570 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); | ||
571 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); | ||
572 | } else if (mode0) { | ||
573 | if (rfixed_trunc(wm0.dbpp) > 64) | ||
574 | a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); | ||
575 | else | ||
576 | a.full = wm0.num_line_pair.full; | ||
577 | fill_rate.full = rfixed_div(wm0.sclk, a); | ||
578 | if (wm0.consumption_rate.full > fill_rate.full) { | ||
579 | b.full = wm0.consumption_rate.full - fill_rate.full; | ||
580 | b.full = rfixed_mul(b, wm0.active_time); | ||
581 | a.full = rfixed_mul(wm0.worst_case_latency, | ||
582 | wm0.consumption_rate); | ||
583 | a.full = a.full + b.full; | ||
584 | b.full = rfixed_const(16 * 1000); | ||
585 | priority_mark02.full = rfixed_div(a, b); | ||
586 | } else { | ||
587 | a.full = rfixed_mul(wm0.worst_case_latency, | ||
588 | wm0.consumption_rate); | ||
589 | b.full = rfixed_const(16 * 1000); | ||
590 | priority_mark02.full = rfixed_div(a, b); | ||
591 | } | ||
592 | if (wm0.priority_mark.full > priority_mark02.full) | ||
593 | priority_mark02.full = wm0.priority_mark.full; | ||
594 | if (rfixed_trunc(priority_mark02) < 0) | ||
595 | priority_mark02.full = 0; | ||
596 | if (wm0.priority_mark_max.full > priority_mark02.full) | ||
597 | priority_mark02.full = wm0.priority_mark_max.full; | ||
598 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); | ||
599 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); | ||
600 | WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); | ||
601 | WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | ||
602 | } else { | ||
603 | if (rfixed_trunc(wm1.dbpp) > 64) | ||
604 | a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); | ||
605 | else | ||
606 | a.full = wm1.num_line_pair.full; | ||
607 | fill_rate.full = rfixed_div(wm1.sclk, a); | ||
608 | if (wm1.consumption_rate.full > fill_rate.full) { | ||
609 | b.full = wm1.consumption_rate.full - fill_rate.full; | ||
610 | b.full = rfixed_mul(b, wm1.active_time); | ||
611 | a.full = rfixed_mul(wm1.worst_case_latency, | ||
612 | wm1.consumption_rate); | ||
613 | a.full = a.full + b.full; | ||
614 | b.full = rfixed_const(16 * 1000); | ||
615 | priority_mark12.full = rfixed_div(a, b); | ||
616 | } else { | ||
617 | a.full = rfixed_mul(wm1.worst_case_latency, | ||
618 | wm1.consumption_rate); | ||
619 | b.full = rfixed_const(16 * 1000); | ||
620 | priority_mark12.full = rfixed_div(a, b); | ||
621 | } | ||
622 | if (wm1.priority_mark.full > priority_mark12.full) | ||
623 | priority_mark12.full = wm1.priority_mark.full; | ||
624 | if (rfixed_trunc(priority_mark12) < 0) | ||
625 | priority_mark12.full = 0; | ||
626 | if (wm1.priority_mark_max.full > priority_mark12.full) | ||
627 | priority_mark12.full = wm1.priority_mark_max.full; | ||
628 | WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); | ||
629 | WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | ||
630 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); | ||
631 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); | ||
632 | } | ||
633 | } | ||
161 | 634 | ||
162 | /* | 635 | /* |
163 | * Indirect registers accessor | 636 | * Indirect registers accessor |
diff --git a/drivers/gpu/drm/radeon/rs690r.h b/drivers/gpu/drm/radeon/rs690r.h new file mode 100644 index 000000000000..c0d9faa2175b --- /dev/null +++ b/drivers/gpu/drm/radeon/rs690r.h | |||
@@ -0,0 +1,99 @@ | |||
1 | /* | ||
2 | * Copyright 2008 Advanced Micro Devices, Inc. | ||
3 | * Copyright 2008 Red Hat Inc. | ||
4 | * Copyright 2009 Jerome Glisse. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
22 | * OTHER DEALINGS IN THE SOFTWARE. | ||
23 | * | ||
24 | * Authors: Dave Airlie | ||
25 | * Alex Deucher | ||
26 | * Jerome Glisse | ||
27 | */ | ||
28 | #ifndef RS690R_H | ||
29 | #define RS690R_H | ||
30 | |||
31 | /* RS690/RS740 registers */ | ||
32 | #define MC_INDEX 0x0078 | ||
33 | # define MC_INDEX_MASK 0x1FF | ||
34 | # define MC_INDEX_WR_EN (1 << 9) | ||
35 | # define MC_INDEX_WR_ACK 0x7F | ||
36 | #define MC_DATA 0x007C | ||
37 | #define HDP_FB_LOCATION 0x0134 | ||
38 | #define DC_LB_MEMORY_SPLIT 0x6520 | ||
39 | #define DC_LB_MEMORY_SPLIT_MASK 0x00000003 | ||
40 | #define DC_LB_MEMORY_SPLIT_SHIFT 0 | ||
41 | #define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 | ||
42 | #define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 | ||
43 | #define DC_LB_MEMORY_SPLIT_D1_ONLY 2 | ||
44 | #define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 | ||
45 | #define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) | ||
46 | #define DC_LB_DISP1_END_ADR_SHIFT 4 | ||
47 | #define DC_LB_DISP1_END_ADR_MASK 0x00007FF0 | ||
48 | #define D1MODE_PRIORITY_A_CNT 0x6548 | ||
49 | #define MODE_PRIORITY_MARK_MASK 0x00007FFF | ||
50 | #define MODE_PRIORITY_OFF (1 << 16) | ||
51 | #define MODE_PRIORITY_ALWAYS_ON (1 << 20) | ||
52 | #define MODE_PRIORITY_FORCE_MASK (1 << 24) | ||
53 | #define D1MODE_PRIORITY_B_CNT 0x654C | ||
54 | #define LB_MAX_REQ_OUTSTANDING 0x6D58 | ||
55 | #define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F | ||
56 | #define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 | ||
57 | #define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000 | ||
58 | #define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 | ||
59 | #define DCP_CONTROL 0x6C9C | ||
60 | #define D2MODE_PRIORITY_A_CNT 0x6D48 | ||
61 | #define D2MODE_PRIORITY_B_CNT 0x6D4C | ||
62 | |||
63 | /* MC indirect registers */ | ||
64 | #define MC_STATUS_IDLE (1 << 0) | ||
65 | #define MC_MISC_CNTL 0x18 | ||
66 | #define DISABLE_GTW (1 << 1) | ||
67 | #define GART_INDEX_REG_EN (1 << 12) | ||
68 | #define BLOCK_GFX_D3_EN (1 << 14) | ||
69 | #define GART_FEATURE_ID 0x2B | ||
70 | #define HANG_EN (1 << 11) | ||
71 | #define TLB_ENABLE (1 << 18) | ||
72 | #define P2P_ENABLE (1 << 19) | ||
73 | #define GTW_LAC_EN (1 << 25) | ||
74 | #define LEVEL2_GART (0 << 30) | ||
75 | #define LEVEL1_GART (1 << 30) | ||
76 | #define PDC_EN (1 << 31) | ||
77 | #define GART_BASE 0x2C | ||
78 | #define GART_CACHE_CNTRL 0x2E | ||
79 | # define GART_CACHE_INVALIDATE (1 << 0) | ||
80 | #define MC_STATUS 0x90 | ||
81 | #define MCCFG_FB_LOCATION 0x100 | ||
82 | #define MC_FB_START_MASK 0x0000FFFF | ||
83 | #define MC_FB_START_SHIFT 0 | ||
84 | #define MC_FB_TOP_MASK 0xFFFF0000 | ||
85 | #define MC_FB_TOP_SHIFT 16 | ||
86 | #define MCCFG_AGP_LOCATION 0x101 | ||
87 | #define MC_AGP_START_MASK 0x0000FFFF | ||
88 | #define MC_AGP_START_SHIFT 0 | ||
89 | #define MC_AGP_TOP_MASK 0xFFFF0000 | ||
90 | #define MC_AGP_TOP_SHIFT 16 | ||
91 | #define MCCFG_AGP_BASE 0x102 | ||
92 | #define MCCFG_AGP_BASE_2 0x103 | ||
93 | #define MC_INIT_MISC_LAT_TIMER 0x104 | ||
94 | #define MC_DISP0R_INIT_LAT_SHIFT 8 | ||
95 | #define MC_DISP0R_INIT_LAT_MASK 0x00000F00 | ||
96 | #define MC_DISP1R_INIT_LAT_SHIFT 12 | ||
97 | #define MC_DISP1R_INIT_LAT_MASK 0x0000F000 | ||
98 | |||
99 | #endif | ||
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index ffea37b1b3e2..551e608702e4 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c | |||
@@ -27,8 +27,9 @@ | |||
27 | */ | 27 | */ |
28 | #include <linux/seq_file.h> | 28 | #include <linux/seq_file.h> |
29 | #include "drmP.h" | 29 | #include "drmP.h" |
30 | #include "radeon_reg.h" | 30 | #include "rv515r.h" |
31 | #include "radeon.h" | 31 | #include "radeon.h" |
32 | #include "radeon_share.h" | ||
32 | 33 | ||
33 | /* rv515 depends on : */ | 34 | /* rv515 depends on : */ |
34 | void r100_hdp_reset(struct radeon_device *rdev); | 35 | void r100_hdp_reset(struct radeon_device *rdev); |
@@ -99,26 +100,26 @@ int rv515_mc_init(struct radeon_device *rdev) | |||
99 | "programming pipes. Bad things might happen.\n"); | 100 | "programming pipes. Bad things might happen.\n"); |
100 | } | 101 | } |
101 | /* Write VRAM size in case we are limiting it */ | 102 | /* Write VRAM size in case we are limiting it */ |
102 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); | 103 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
103 | tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16); | 104 | tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); |
104 | WREG32(0x134, tmp); | 105 | WREG32(0x134, tmp); |
105 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; | 106 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
106 | tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16); | 107 | tmp = REG_SET(MC_FB_TOP, tmp >> 16); |
107 | tmp |= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16); | 108 | tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); |
108 | WREG32_MC(RV515_MC_FB_LOCATION, tmp); | 109 | WREG32_MC(MC_FB_LOCATION, tmp); |
109 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); | 110 | WREG32(HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
110 | WREG32(0x310, rdev->mc.vram_location); | 111 | WREG32(0x310, rdev->mc.vram_location); |
111 | if (rdev->flags & RADEON_IS_AGP) { | 112 | if (rdev->flags & RADEON_IS_AGP) { |
112 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; | 113 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
113 | tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16); | 114 | tmp = REG_SET(MC_AGP_TOP, tmp >> 16); |
114 | tmp |= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16); | 115 | tmp |= REG_SET(MC_AGP_START, rdev->mc.gtt_location >> 16); |
115 | WREG32_MC(RV515_MC_AGP_LOCATION, tmp); | 116 | WREG32_MC(MC_AGP_LOCATION, tmp); |
116 | WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base); | 117 | WREG32_MC(MC_AGP_BASE, rdev->mc.agp_base); |
117 | WREG32_MC(RV515_MC_AGP_BASE_2, 0); | 118 | WREG32_MC(MC_AGP_BASE_2, 0); |
118 | } else { | 119 | } else { |
119 | WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF); | 120 | WREG32_MC(MC_AGP_LOCATION, 0x0FFFFFFF); |
120 | WREG32_MC(RV515_MC_AGP_BASE, 0); | 121 | WREG32_MC(MC_AGP_BASE, 0); |
121 | WREG32_MC(RV515_MC_AGP_BASE_2, 0); | 122 | WREG32_MC(MC_AGP_BASE_2, 0); |
122 | } | 123 | } |
123 | return 0; | 124 | return 0; |
124 | } | 125 | } |
@@ -136,95 +137,67 @@ void rv515_mc_fini(struct radeon_device *rdev) | |||
136 | */ | 137 | */ |
137 | void rv515_ring_start(struct radeon_device *rdev) | 138 | void rv515_ring_start(struct radeon_device *rdev) |
138 | { | 139 | { |
139 | unsigned gb_tile_config; | ||
140 | int r; | 140 | int r; |
141 | 141 | ||
142 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ | ||
143 | gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16; | ||
144 | switch (rdev->num_gb_pipes) { | ||
145 | case 2: | ||
146 | gb_tile_config |= R300_PIPE_COUNT_R300; | ||
147 | break; | ||
148 | case 3: | ||
149 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; | ||
150 | break; | ||
151 | case 4: | ||
152 | gb_tile_config |= R300_PIPE_COUNT_R420; | ||
153 | break; | ||
154 | case 1: | ||
155 | default: | ||
156 | gb_tile_config |= R300_PIPE_COUNT_RV350; | ||
157 | break; | ||
158 | } | ||
159 | |||
160 | r = radeon_ring_lock(rdev, 64); | 142 | r = radeon_ring_lock(rdev, 64); |
161 | if (r) { | 143 | if (r) { |
162 | return; | 144 | return; |
163 | } | 145 | } |
164 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); | 146 | radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0)); |
165 | radeon_ring_write(rdev, | ||
166 | RADEON_ISYNC_ANY2D_IDLE3D | | ||
167 | RADEON_ISYNC_ANY3D_IDLE2D | | ||
168 | RADEON_ISYNC_WAIT_IDLEGUI | | ||
169 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); | ||
170 | radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); | ||
171 | radeon_ring_write(rdev, gb_tile_config); | ||
172 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); | ||
173 | radeon_ring_write(rdev, | 147 | radeon_ring_write(rdev, |
174 | RADEON_WAIT_2D_IDLECLEAN | | 148 | ISYNC_ANY2D_IDLE3D | |
175 | RADEON_WAIT_3D_IDLECLEAN); | 149 | ISYNC_ANY3D_IDLE2D | |
150 | ISYNC_WAIT_IDLEGUI | | ||
151 | ISYNC_CPSCRATCH_IDLEGUI); | ||
152 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); | ||
153 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); | ||
176 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); | 154 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
177 | radeon_ring_write(rdev, 1 << 31); | 155 | radeon_ring_write(rdev, 1 << 31); |
178 | radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); | 156 | radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); |
179 | radeon_ring_write(rdev, 0); | 157 | radeon_ring_write(rdev, 0); |
180 | radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); | 158 | radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); |
181 | radeon_ring_write(rdev, 0); | 159 | radeon_ring_write(rdev, 0); |
182 | radeon_ring_write(rdev, PACKET0(0x42C8, 0)); | 160 | radeon_ring_write(rdev, PACKET0(0x42C8, 0)); |
183 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); | 161 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); |
184 | radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0)); | 162 | radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); |
185 | radeon_ring_write(rdev, 0); | 163 | radeon_ring_write(rdev, 0); |
186 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | 164 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
187 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); | 165 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); |
188 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | 166 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
189 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); | 167 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); |
190 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); | 168 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); |
191 | radeon_ring_write(rdev, | 169 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
192 | RADEON_WAIT_2D_IDLECLEAN | | 170 | radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0)); |
193 | RADEON_WAIT_3D_IDLECLEAN); | ||
194 | radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); | ||
195 | radeon_ring_write(rdev, 0); | 171 | radeon_ring_write(rdev, 0); |
196 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | 172 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
197 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); | 173 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); |
198 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | 174 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
199 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); | 175 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); |
200 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); | 176 | radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0)); |
201 | radeon_ring_write(rdev, | ||
202 | ((6 << R300_MS_X0_SHIFT) | | ||
203 | (6 << R300_MS_Y0_SHIFT) | | ||
204 | (6 << R300_MS_X1_SHIFT) | | ||
205 | (6 << R300_MS_Y1_SHIFT) | | ||
206 | (6 << R300_MS_X2_SHIFT) | | ||
207 | (6 << R300_MS_Y2_SHIFT) | | ||
208 | (6 << R300_MSBD0_Y_SHIFT) | | ||
209 | (6 << R300_MSBD0_X_SHIFT))); | ||
210 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); | ||
211 | radeon_ring_write(rdev, | 177 | radeon_ring_write(rdev, |
212 | ((6 << R300_MS_X3_SHIFT) | | 178 | ((6 << MS_X0_SHIFT) | |
213 | (6 << R300_MS_Y3_SHIFT) | | 179 | (6 << MS_Y0_SHIFT) | |
214 | (6 << R300_MS_X4_SHIFT) | | 180 | (6 << MS_X1_SHIFT) | |
215 | (6 << R300_MS_Y4_SHIFT) | | 181 | (6 << MS_Y1_SHIFT) | |
216 | (6 << R300_MS_X5_SHIFT) | | 182 | (6 << MS_X2_SHIFT) | |
217 | (6 << R300_MS_Y5_SHIFT) | | 183 | (6 << MS_Y2_SHIFT) | |
218 | (6 << R300_MSBD1_SHIFT))); | 184 | (6 << MSBD0_Y_SHIFT) | |
219 | radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); | 185 | (6 << MSBD0_X_SHIFT))); |
220 | radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); | 186 | radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0)); |
221 | radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); | ||
222 | radeon_ring_write(rdev, | 187 | radeon_ring_write(rdev, |
223 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); | 188 | ((6 << MS_X3_SHIFT) | |
224 | radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); | 189 | (6 << MS_Y3_SHIFT) | |
225 | radeon_ring_write(rdev, | 190 | (6 << MS_X4_SHIFT) | |
226 | R300_GEOMETRY_ROUND_NEAREST | | 191 | (6 << MS_Y4_SHIFT) | |
227 | R300_COLOR_ROUND_NEAREST); | 192 | (6 << MS_X5_SHIFT) | |
193 | (6 << MS_Y5_SHIFT) | | ||
194 | (6 << MSBD1_SHIFT))); | ||
195 | radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0)); | ||
196 | radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); | ||
197 | radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0)); | ||
198 | radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); | ||
199 | radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); | ||
200 | radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); | ||
228 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); | 201 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
229 | radeon_ring_write(rdev, 0); | 202 | radeon_ring_write(rdev, 0); |
230 | radeon_ring_unlock_commit(rdev); | 203 | radeon_ring_unlock_commit(rdev); |
@@ -242,8 +215,8 @@ int rv515_mc_wait_for_idle(struct radeon_device *rdev) | |||
242 | 215 | ||
243 | for (i = 0; i < rdev->usec_timeout; i++) { | 216 | for (i = 0; i < rdev->usec_timeout; i++) { |
244 | /* read MC_STATUS */ | 217 | /* read MC_STATUS */ |
245 | tmp = RREG32_MC(RV515_MC_STATUS); | 218 | tmp = RREG32_MC(MC_STATUS); |
246 | if (tmp & RV515_MC_STATUS_IDLE) { | 219 | if (tmp & MC_STATUS_IDLE) { |
247 | return 0; | 220 | return 0; |
248 | } | 221 | } |
249 | DRM_UDELAY(1); | 222 | DRM_UDELAY(1); |
@@ -291,33 +264,33 @@ int rv515_ga_reset(struct radeon_device *rdev) | |||
291 | reinit_cp = rdev->cp.ready; | 264 | reinit_cp = rdev->cp.ready; |
292 | rdev->cp.ready = false; | 265 | rdev->cp.ready = false; |
293 | for (i = 0; i < rdev->usec_timeout; i++) { | 266 | for (i = 0; i < rdev->usec_timeout; i++) { |
294 | WREG32(RADEON_CP_CSQ_MODE, 0); | 267 | WREG32(CP_CSQ_MODE, 0); |
295 | WREG32(RADEON_CP_CSQ_CNTL, 0); | 268 | WREG32(CP_CSQ_CNTL, 0); |
296 | WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); | 269 | WREG32(RBBM_SOFT_RESET, 0x32005); |
297 | (void)RREG32(RADEON_RBBM_SOFT_RESET); | 270 | (void)RREG32(RBBM_SOFT_RESET); |
298 | udelay(200); | 271 | udelay(200); |
299 | WREG32(RADEON_RBBM_SOFT_RESET, 0); | 272 | WREG32(RBBM_SOFT_RESET, 0); |
300 | /* Wait to prevent race in RBBM_STATUS */ | 273 | /* Wait to prevent race in RBBM_STATUS */ |
301 | mdelay(1); | 274 | mdelay(1); |
302 | tmp = RREG32(RADEON_RBBM_STATUS); | 275 | tmp = RREG32(RBBM_STATUS); |
303 | if (tmp & ((1 << 20) | (1 << 26))) { | 276 | if (tmp & ((1 << 20) | (1 << 26))) { |
304 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp); | 277 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp); |
305 | /* GA still busy soft reset it */ | 278 | /* GA still busy soft reset it */ |
306 | WREG32(0x429C, 0x200); | 279 | WREG32(0x429C, 0x200); |
307 | WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); | 280 | WREG32(VAP_PVS_STATE_FLUSH_REG, 0); |
308 | WREG32(0x43E0, 0); | 281 | WREG32(0x43E0, 0); |
309 | WREG32(0x43E4, 0); | 282 | WREG32(0x43E4, 0); |
310 | WREG32(0x24AC, 0); | 283 | WREG32(0x24AC, 0); |
311 | } | 284 | } |
312 | /* Wait to prevent race in RBBM_STATUS */ | 285 | /* Wait to prevent race in RBBM_STATUS */ |
313 | mdelay(1); | 286 | mdelay(1); |
314 | tmp = RREG32(RADEON_RBBM_STATUS); | 287 | tmp = RREG32(RBBM_STATUS); |
315 | if (!(tmp & ((1 << 20) | (1 << 26)))) { | 288 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
316 | break; | 289 | break; |
317 | } | 290 | } |
318 | } | 291 | } |
319 | for (i = 0; i < rdev->usec_timeout; i++) { | 292 | for (i = 0; i < rdev->usec_timeout; i++) { |
320 | tmp = RREG32(RADEON_RBBM_STATUS); | 293 | tmp = RREG32(RBBM_STATUS); |
321 | if (!(tmp & ((1 << 20) | (1 << 26)))) { | 294 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
322 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", | 295 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
323 | tmp); | 296 | tmp); |
@@ -331,7 +304,7 @@ int rv515_ga_reset(struct radeon_device *rdev) | |||
331 | } | 304 | } |
332 | DRM_UDELAY(1); | 305 | DRM_UDELAY(1); |
333 | } | 306 | } |
334 | tmp = RREG32(RADEON_RBBM_STATUS); | 307 | tmp = RREG32(RBBM_STATUS); |
335 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); | 308 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
336 | return -1; | 309 | return -1; |
337 | } | 310 | } |
@@ -341,7 +314,7 @@ int rv515_gpu_reset(struct radeon_device *rdev) | |||
341 | uint32_t status; | 314 | uint32_t status; |
342 | 315 | ||
343 | /* reset order likely matter */ | 316 | /* reset order likely matter */ |
344 | status = RREG32(RADEON_RBBM_STATUS); | 317 | status = RREG32(RBBM_STATUS); |
345 | /* reset HDP */ | 318 | /* reset HDP */ |
346 | r100_hdp_reset(rdev); | 319 | r100_hdp_reset(rdev); |
347 | /* reset rb2d */ | 320 | /* reset rb2d */ |
@@ -353,12 +326,12 @@ int rv515_gpu_reset(struct radeon_device *rdev) | |||
353 | rv515_ga_reset(rdev); | 326 | rv515_ga_reset(rdev); |
354 | } | 327 | } |
355 | /* reset CP */ | 328 | /* reset CP */ |
356 | status = RREG32(RADEON_RBBM_STATUS); | 329 | status = RREG32(RBBM_STATUS); |
357 | if (status & (1 << 16)) { | 330 | if (status & (1 << 16)) { |
358 | r100_cp_reset(rdev); | 331 | r100_cp_reset(rdev); |
359 | } | 332 | } |
360 | /* Check if GPU is idle */ | 333 | /* Check if GPU is idle */ |
361 | status = RREG32(RADEON_RBBM_STATUS); | 334 | status = RREG32(RBBM_STATUS); |
362 | if (status & (1 << 31)) { | 335 | if (status & (1 << 31)) { |
363 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); | 336 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
364 | return -1; | 337 | return -1; |
@@ -377,8 +350,7 @@ static void rv515_vram_get_type(struct radeon_device *rdev) | |||
377 | 350 | ||
378 | rdev->mc.vram_width = 128; | 351 | rdev->mc.vram_width = 128; |
379 | rdev->mc.vram_is_ddr = true; | 352 | rdev->mc.vram_is_ddr = true; |
380 | tmp = RREG32_MC(RV515_MC_CNTL); | 353 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
381 | tmp &= RV515_MEM_NUM_CHANNELS_MASK; | ||
382 | switch (tmp) { | 354 | switch (tmp) { |
383 | case 0: | 355 | case 0: |
384 | rdev->mc.vram_width = 64; | 356 | rdev->mc.vram_width = 64; |
@@ -394,11 +366,16 @@ static void rv515_vram_get_type(struct radeon_device *rdev) | |||
394 | 366 | ||
395 | void rv515_vram_info(struct radeon_device *rdev) | 367 | void rv515_vram_info(struct radeon_device *rdev) |
396 | { | 368 | { |
369 | fixed20_12 a; | ||
370 | |||
397 | rv515_vram_get_type(rdev); | 371 | rv515_vram_get_type(rdev); |
398 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); | ||
399 | 372 | ||
400 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | 373 | /* FIXME: we should enforce default clock in case GPU is not in |
401 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | 374 | * default setup |
375 | */ | ||
376 | a.full = rfixed_const(100); | ||
377 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); | ||
378 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | ||
402 | } | 379 | } |
403 | 380 | ||
404 | 381 | ||
@@ -409,35 +386,35 @@ uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) | |||
409 | { | 386 | { |
410 | uint32_t r; | 387 | uint32_t r; |
411 | 388 | ||
412 | WREG32(R520_MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); | 389 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
413 | r = RREG32(R520_MC_IND_DATA); | 390 | r = RREG32(MC_IND_DATA); |
414 | WREG32(R520_MC_IND_INDEX, 0); | 391 | WREG32(MC_IND_INDEX, 0); |
415 | return r; | 392 | return r; |
416 | } | 393 | } |
417 | 394 | ||
418 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | 395 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
419 | { | 396 | { |
420 | WREG32(R520_MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); | 397 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
421 | WREG32(R520_MC_IND_DATA, (v)); | 398 | WREG32(MC_IND_DATA, (v)); |
422 | WREG32(R520_MC_IND_INDEX, 0); | 399 | WREG32(MC_IND_INDEX, 0); |
423 | } | 400 | } |
424 | 401 | ||
425 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | 402 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
426 | { | 403 | { |
427 | uint32_t r; | 404 | uint32_t r; |
428 | 405 | ||
429 | WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff)); | 406 | WREG32(PCIE_INDEX, ((reg) & 0x7ff)); |
430 | (void)RREG32(RADEON_PCIE_INDEX); | 407 | (void)RREG32(PCIE_INDEX); |
431 | r = RREG32(RADEON_PCIE_DATA); | 408 | r = RREG32(PCIE_DATA); |
432 | return r; | 409 | return r; |
433 | } | 410 | } |
434 | 411 | ||
435 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | 412 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
436 | { | 413 | { |
437 | WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff)); | 414 | WREG32(PCIE_INDEX, ((reg) & 0x7ff)); |
438 | (void)RREG32(RADEON_PCIE_INDEX); | 415 | (void)RREG32(PCIE_INDEX); |
439 | WREG32(RADEON_PCIE_DATA, (v)); | 416 | WREG32(PCIE_DATA, (v)); |
440 | (void)RREG32(RADEON_PCIE_DATA); | 417 | (void)RREG32(PCIE_DATA); |
441 | } | 418 | } |
442 | 419 | ||
443 | 420 | ||
@@ -452,13 +429,13 @@ static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) | |||
452 | struct radeon_device *rdev = dev->dev_private; | 429 | struct radeon_device *rdev = dev->dev_private; |
453 | uint32_t tmp; | 430 | uint32_t tmp; |
454 | 431 | ||
455 | tmp = RREG32(R400_GB_PIPE_SELECT); | 432 | tmp = RREG32(GB_PIPE_SELECT); |
456 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); | 433 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
457 | tmp = RREG32(R500_SU_REG_DEST); | 434 | tmp = RREG32(SU_REG_DEST); |
458 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); | 435 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
459 | tmp = RREG32(R300_GB_TILE_CONFIG); | 436 | tmp = RREG32(GB_TILE_CONFIG); |
460 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); | 437 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
461 | tmp = RREG32(R300_DST_PIPE_CONFIG); | 438 | tmp = RREG32(DST_PIPE_CONFIG); |
462 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); | 439 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
463 | return 0; | 440 | return 0; |
464 | } | 441 | } |
@@ -509,9 +486,9 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev) | |||
509 | /* | 486 | /* |
510 | * Asic initialization | 487 | * Asic initialization |
511 | */ | 488 | */ |
512 | static const unsigned r500_reg_safe_bm[159] = { | 489 | static const unsigned r500_reg_safe_bm[219] = { |
490 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
513 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | 491 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
514 | 0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF, | ||
515 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | 492 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
516 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | 493 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
517 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | 494 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
@@ -549,14 +526,575 @@ static const unsigned r500_reg_safe_bm[159] = { | |||
549 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | 526 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
550 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF, | 527 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF, |
551 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, | 528 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
552 | 0x0003FC01, 0x3FFFFCF8, 0xFE800B19, | 529 | 0x0003FC01, 0x3FFFFCF8, 0xFE800B19, 0xFFFFFFFF, |
530 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
531 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
532 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
533 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
534 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
535 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
536 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
537 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
538 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
539 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
540 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
541 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
542 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
543 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
544 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, | ||
553 | }; | 545 | }; |
554 | 546 | ||
555 | |||
556 | |||
557 | int rv515_init(struct radeon_device *rdev) | 547 | int rv515_init(struct radeon_device *rdev) |
558 | { | 548 | { |
559 | rdev->config.r300.reg_safe_bm = r500_reg_safe_bm; | 549 | rdev->config.r300.reg_safe_bm = r500_reg_safe_bm; |
560 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm); | 550 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm); |
561 | return 0; | 551 | return 0; |
562 | } | 552 | } |
553 | |||
554 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev) | ||
555 | { | ||
556 | |||
557 | WREG32(0x659C, 0x0); | ||
558 | WREG32(0x6594, 0x705); | ||
559 | WREG32(0x65A4, 0x10001); | ||
560 | WREG32(0x65D8, 0x0); | ||
561 | WREG32(0x65B0, 0x0); | ||
562 | WREG32(0x65C0, 0x0); | ||
563 | WREG32(0x65D4, 0x0); | ||
564 | WREG32(0x6578, 0x0); | ||
565 | WREG32(0x657C, 0x841880A8); | ||
566 | WREG32(0x6578, 0x1); | ||
567 | WREG32(0x657C, 0x84208680); | ||
568 | WREG32(0x6578, 0x2); | ||
569 | WREG32(0x657C, 0xBFF880B0); | ||
570 | WREG32(0x6578, 0x100); | ||
571 | WREG32(0x657C, 0x83D88088); | ||
572 | WREG32(0x6578, 0x101); | ||
573 | WREG32(0x657C, 0x84608680); | ||
574 | WREG32(0x6578, 0x102); | ||
575 | WREG32(0x657C, 0xBFF080D0); | ||
576 | WREG32(0x6578, 0x200); | ||
577 | WREG32(0x657C, 0x83988068); | ||
578 | WREG32(0x6578, 0x201); | ||
579 | WREG32(0x657C, 0x84A08680); | ||
580 | WREG32(0x6578, 0x202); | ||
581 | WREG32(0x657C, 0xBFF080F8); | ||
582 | WREG32(0x6578, 0x300); | ||
583 | WREG32(0x657C, 0x83588058); | ||
584 | WREG32(0x6578, 0x301); | ||
585 | WREG32(0x657C, 0x84E08660); | ||
586 | WREG32(0x6578, 0x302); | ||
587 | WREG32(0x657C, 0xBFF88120); | ||
588 | WREG32(0x6578, 0x400); | ||
589 | WREG32(0x657C, 0x83188040); | ||
590 | WREG32(0x6578, 0x401); | ||
591 | WREG32(0x657C, 0x85008660); | ||
592 | WREG32(0x6578, 0x402); | ||
593 | WREG32(0x657C, 0xBFF88150); | ||
594 | WREG32(0x6578, 0x500); | ||
595 | WREG32(0x657C, 0x82D88030); | ||
596 | WREG32(0x6578, 0x501); | ||
597 | WREG32(0x657C, 0x85408640); | ||
598 | WREG32(0x6578, 0x502); | ||
599 | WREG32(0x657C, 0xBFF88180); | ||
600 | WREG32(0x6578, 0x600); | ||
601 | WREG32(0x657C, 0x82A08018); | ||
602 | WREG32(0x6578, 0x601); | ||
603 | WREG32(0x657C, 0x85808620); | ||
604 | WREG32(0x6578, 0x602); | ||
605 | WREG32(0x657C, 0xBFF081B8); | ||
606 | WREG32(0x6578, 0x700); | ||
607 | WREG32(0x657C, 0x82608010); | ||
608 | WREG32(0x6578, 0x701); | ||
609 | WREG32(0x657C, 0x85A08600); | ||
610 | WREG32(0x6578, 0x702); | ||
611 | WREG32(0x657C, 0x800081F0); | ||
612 | WREG32(0x6578, 0x800); | ||
613 | WREG32(0x657C, 0x8228BFF8); | ||
614 | WREG32(0x6578, 0x801); | ||
615 | WREG32(0x657C, 0x85E085E0); | ||
616 | WREG32(0x6578, 0x802); | ||
617 | WREG32(0x657C, 0xBFF88228); | ||
618 | WREG32(0x6578, 0x10000); | ||
619 | WREG32(0x657C, 0x82A8BF00); | ||
620 | WREG32(0x6578, 0x10001); | ||
621 | WREG32(0x657C, 0x82A08CC0); | ||
622 | WREG32(0x6578, 0x10002); | ||
623 | WREG32(0x657C, 0x8008BEF8); | ||
624 | WREG32(0x6578, 0x10100); | ||
625 | WREG32(0x657C, 0x81F0BF28); | ||
626 | WREG32(0x6578, 0x10101); | ||
627 | WREG32(0x657C, 0x83608CA0); | ||
628 | WREG32(0x6578, 0x10102); | ||
629 | WREG32(0x657C, 0x8018BED0); | ||
630 | WREG32(0x6578, 0x10200); | ||
631 | WREG32(0x657C, 0x8148BF38); | ||
632 | WREG32(0x6578, 0x10201); | ||
633 | WREG32(0x657C, 0x84408C80); | ||
634 | WREG32(0x6578, 0x10202); | ||
635 | WREG32(0x657C, 0x8008BEB8); | ||
636 | WREG32(0x6578, 0x10300); | ||
637 | WREG32(0x657C, 0x80B0BF78); | ||
638 | WREG32(0x6578, 0x10301); | ||
639 | WREG32(0x657C, 0x85008C20); | ||
640 | WREG32(0x6578, 0x10302); | ||
641 | WREG32(0x657C, 0x8020BEA0); | ||
642 | WREG32(0x6578, 0x10400); | ||
643 | WREG32(0x657C, 0x8028BF90); | ||
644 | WREG32(0x6578, 0x10401); | ||
645 | WREG32(0x657C, 0x85E08BC0); | ||
646 | WREG32(0x6578, 0x10402); | ||
647 | WREG32(0x657C, 0x8018BE90); | ||
648 | WREG32(0x6578, 0x10500); | ||
649 | WREG32(0x657C, 0xBFB8BFB0); | ||
650 | WREG32(0x6578, 0x10501); | ||
651 | WREG32(0x657C, 0x86C08B40); | ||
652 | WREG32(0x6578, 0x10502); | ||
653 | WREG32(0x657C, 0x8010BE90); | ||
654 | WREG32(0x6578, 0x10600); | ||
655 | WREG32(0x657C, 0xBF58BFC8); | ||
656 | WREG32(0x6578, 0x10601); | ||
657 | WREG32(0x657C, 0x87A08AA0); | ||
658 | WREG32(0x6578, 0x10602); | ||
659 | WREG32(0x657C, 0x8010BE98); | ||
660 | WREG32(0x6578, 0x10700); | ||
661 | WREG32(0x657C, 0xBF10BFF0); | ||
662 | WREG32(0x6578, 0x10701); | ||
663 | WREG32(0x657C, 0x886089E0); | ||
664 | WREG32(0x6578, 0x10702); | ||
665 | WREG32(0x657C, 0x8018BEB0); | ||
666 | WREG32(0x6578, 0x10800); | ||
667 | WREG32(0x657C, 0xBED8BFE8); | ||
668 | WREG32(0x6578, 0x10801); | ||
669 | WREG32(0x657C, 0x89408940); | ||
670 | WREG32(0x6578, 0x10802); | ||
671 | WREG32(0x657C, 0xBFE8BED8); | ||
672 | WREG32(0x6578, 0x20000); | ||
673 | WREG32(0x657C, 0x80008000); | ||
674 | WREG32(0x6578, 0x20001); | ||
675 | WREG32(0x657C, 0x90008000); | ||
676 | WREG32(0x6578, 0x20002); | ||
677 | WREG32(0x657C, 0x80008000); | ||
678 | WREG32(0x6578, 0x20003); | ||
679 | WREG32(0x657C, 0x80008000); | ||
680 | WREG32(0x6578, 0x20100); | ||
681 | WREG32(0x657C, 0x80108000); | ||
682 | WREG32(0x6578, 0x20101); | ||
683 | WREG32(0x657C, 0x8FE0BF70); | ||
684 | WREG32(0x6578, 0x20102); | ||
685 | WREG32(0x657C, 0xBFE880C0); | ||
686 | WREG32(0x6578, 0x20103); | ||
687 | WREG32(0x657C, 0x80008000); | ||
688 | WREG32(0x6578, 0x20200); | ||
689 | WREG32(0x657C, 0x8018BFF8); | ||
690 | WREG32(0x6578, 0x20201); | ||
691 | WREG32(0x657C, 0x8F80BF08); | ||
692 | WREG32(0x6578, 0x20202); | ||
693 | WREG32(0x657C, 0xBFD081A0); | ||
694 | WREG32(0x6578, 0x20203); | ||
695 | WREG32(0x657C, 0xBFF88000); | ||
696 | WREG32(0x6578, 0x20300); | ||
697 | WREG32(0x657C, 0x80188000); | ||
698 | WREG32(0x6578, 0x20301); | ||
699 | WREG32(0x657C, 0x8EE0BEC0); | ||
700 | WREG32(0x6578, 0x20302); | ||
701 | WREG32(0x657C, 0xBFB082A0); | ||
702 | WREG32(0x6578, 0x20303); | ||
703 | WREG32(0x657C, 0x80008000); | ||
704 | WREG32(0x6578, 0x20400); | ||
705 | WREG32(0x657C, 0x80188000); | ||
706 | WREG32(0x6578, 0x20401); | ||
707 | WREG32(0x657C, 0x8E00BEA0); | ||
708 | WREG32(0x6578, 0x20402); | ||
709 | WREG32(0x657C, 0xBF8883C0); | ||
710 | WREG32(0x6578, 0x20403); | ||
711 | WREG32(0x657C, 0x80008000); | ||
712 | WREG32(0x6578, 0x20500); | ||
713 | WREG32(0x657C, 0x80188000); | ||
714 | WREG32(0x6578, 0x20501); | ||
715 | WREG32(0x657C, 0x8D00BE90); | ||
716 | WREG32(0x6578, 0x20502); | ||
717 | WREG32(0x657C, 0xBF588500); | ||
718 | WREG32(0x6578, 0x20503); | ||
719 | WREG32(0x657C, 0x80008008); | ||
720 | WREG32(0x6578, 0x20600); | ||
721 | WREG32(0x657C, 0x80188000); | ||
722 | WREG32(0x6578, 0x20601); | ||
723 | WREG32(0x657C, 0x8BC0BE98); | ||
724 | WREG32(0x6578, 0x20602); | ||
725 | WREG32(0x657C, 0xBF308660); | ||
726 | WREG32(0x6578, 0x20603); | ||
727 | WREG32(0x657C, 0x80008008); | ||
728 | WREG32(0x6578, 0x20700); | ||
729 | WREG32(0x657C, 0x80108000); | ||
730 | WREG32(0x6578, 0x20701); | ||
731 | WREG32(0x657C, 0x8A80BEB0); | ||
732 | WREG32(0x6578, 0x20702); | ||
733 | WREG32(0x657C, 0xBF0087C0); | ||
734 | WREG32(0x6578, 0x20703); | ||
735 | WREG32(0x657C, 0x80008008); | ||
736 | WREG32(0x6578, 0x20800); | ||
737 | WREG32(0x657C, 0x80108000); | ||
738 | WREG32(0x6578, 0x20801); | ||
739 | WREG32(0x657C, 0x8920BED0); | ||
740 | WREG32(0x6578, 0x20802); | ||
741 | WREG32(0x657C, 0xBED08920); | ||
742 | WREG32(0x6578, 0x20803); | ||
743 | WREG32(0x657C, 0x80008010); | ||
744 | WREG32(0x6578, 0x30000); | ||
745 | WREG32(0x657C, 0x90008000); | ||
746 | WREG32(0x6578, 0x30001); | ||
747 | WREG32(0x657C, 0x80008000); | ||
748 | WREG32(0x6578, 0x30100); | ||
749 | WREG32(0x657C, 0x8FE0BF90); | ||
750 | WREG32(0x6578, 0x30101); | ||
751 | WREG32(0x657C, 0xBFF880A0); | ||
752 | WREG32(0x6578, 0x30200); | ||
753 | WREG32(0x657C, 0x8F60BF40); | ||
754 | WREG32(0x6578, 0x30201); | ||
755 | WREG32(0x657C, 0xBFE88180); | ||
756 | WREG32(0x6578, 0x30300); | ||
757 | WREG32(0x657C, 0x8EC0BF00); | ||
758 | WREG32(0x6578, 0x30301); | ||
759 | WREG32(0x657C, 0xBFC88280); | ||
760 | WREG32(0x6578, 0x30400); | ||
761 | WREG32(0x657C, 0x8DE0BEE0); | ||
762 | WREG32(0x6578, 0x30401); | ||
763 | WREG32(0x657C, 0xBFA083A0); | ||
764 | WREG32(0x6578, 0x30500); | ||
765 | WREG32(0x657C, 0x8CE0BED0); | ||
766 | WREG32(0x6578, 0x30501); | ||
767 | WREG32(0x657C, 0xBF7884E0); | ||
768 | WREG32(0x6578, 0x30600); | ||
769 | WREG32(0x657C, 0x8BA0BED8); | ||
770 | WREG32(0x6578, 0x30601); | ||
771 | WREG32(0x657C, 0xBF508640); | ||
772 | WREG32(0x6578, 0x30700); | ||
773 | WREG32(0x657C, 0x8A60BEE8); | ||
774 | WREG32(0x6578, 0x30701); | ||
775 | WREG32(0x657C, 0xBF2087A0); | ||
776 | WREG32(0x6578, 0x30800); | ||
777 | WREG32(0x657C, 0x8900BF00); | ||
778 | WREG32(0x6578, 0x30801); | ||
779 | WREG32(0x657C, 0xBF008900); | ||
780 | } | ||
781 | |||
782 | struct rv515_watermark { | ||
783 | u32 lb_request_fifo_depth; | ||
784 | fixed20_12 num_line_pair; | ||
785 | fixed20_12 estimated_width; | ||
786 | fixed20_12 worst_case_latency; | ||
787 | fixed20_12 consumption_rate; | ||
788 | fixed20_12 active_time; | ||
789 | fixed20_12 dbpp; | ||
790 | fixed20_12 priority_mark_max; | ||
791 | fixed20_12 priority_mark; | ||
792 | fixed20_12 sclk; | ||
793 | }; | ||
794 | |||
795 | void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, | ||
796 | struct radeon_crtc *crtc, | ||
797 | struct rv515_watermark *wm) | ||
798 | { | ||
799 | struct drm_display_mode *mode = &crtc->base.mode; | ||
800 | fixed20_12 a, b, c; | ||
801 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; | ||
802 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; | ||
803 | |||
804 | if (!crtc->base.enabled) { | ||
805 | /* FIXME: wouldn't it better to set priority mark to maximum */ | ||
806 | wm->lb_request_fifo_depth = 4; | ||
807 | return; | ||
808 | } | ||
809 | |||
810 | if (crtc->vsc.full > rfixed_const(2)) | ||
811 | wm->num_line_pair.full = rfixed_const(2); | ||
812 | else | ||
813 | wm->num_line_pair.full = rfixed_const(1); | ||
814 | |||
815 | b.full = rfixed_const(mode->crtc_hdisplay); | ||
816 | c.full = rfixed_const(256); | ||
817 | a.full = rfixed_mul(wm->num_line_pair, b); | ||
818 | request_fifo_depth.full = rfixed_div(a, c); | ||
819 | if (a.full < rfixed_const(4)) { | ||
820 | wm->lb_request_fifo_depth = 4; | ||
821 | } else { | ||
822 | wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); | ||
823 | } | ||
824 | |||
825 | /* Determine consumption rate | ||
826 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) | ||
827 | * vtaps = number of vertical taps, | ||
828 | * vsc = vertical scaling ratio, defined as source/destination | ||
829 | * hsc = horizontal scaling ration, defined as source/destination | ||
830 | */ | ||
831 | a.full = rfixed_const(mode->clock); | ||
832 | b.full = rfixed_const(1000); | ||
833 | a.full = rfixed_div(a, b); | ||
834 | pclk.full = rfixed_div(b, a); | ||
835 | if (crtc->rmx_type != RMX_OFF) { | ||
836 | b.full = rfixed_const(2); | ||
837 | if (crtc->vsc.full > b.full) | ||
838 | b.full = crtc->vsc.full; | ||
839 | b.full = rfixed_mul(b, crtc->hsc); | ||
840 | c.full = rfixed_const(2); | ||
841 | b.full = rfixed_div(b, c); | ||
842 | consumption_time.full = rfixed_div(pclk, b); | ||
843 | } else { | ||
844 | consumption_time.full = pclk.full; | ||
845 | } | ||
846 | a.full = rfixed_const(1); | ||
847 | wm->consumption_rate.full = rfixed_div(a, consumption_time); | ||
848 | |||
849 | |||
850 | /* Determine line time | ||
851 | * LineTime = total time for one line of displayhtotal | ||
852 | * LineTime = total number of horizontal pixels | ||
853 | * pclk = pixel clock period(ns) | ||
854 | */ | ||
855 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); | ||
856 | line_time.full = rfixed_mul(a, pclk); | ||
857 | |||
858 | /* Determine active time | ||
859 | * ActiveTime = time of active region of display within one line, | ||
860 | * hactive = total number of horizontal active pixels | ||
861 | * htotal = total number of horizontal pixels | ||
862 | */ | ||
863 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); | ||
864 | b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | ||
865 | wm->active_time.full = rfixed_mul(line_time, b); | ||
866 | wm->active_time.full = rfixed_div(wm->active_time, a); | ||
867 | |||
868 | /* Determine chunk time | ||
869 | * ChunkTime = the time it takes the DCP to send one chunk of data | ||
870 | * to the LB which consists of pipeline delay and inter chunk gap | ||
871 | * sclk = system clock(Mhz) | ||
872 | */ | ||
873 | a.full = rfixed_const(600 * 1000); | ||
874 | chunk_time.full = rfixed_div(a, rdev->pm.sclk); | ||
875 | read_delay_latency.full = rfixed_const(1000); | ||
876 | |||
877 | /* Determine the worst case latency | ||
878 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) | ||
879 | * WorstCaseLatency = worst case time from urgent to when the MC starts | ||
880 | * to return data | ||
881 | * READ_DELAY_IDLE_MAX = constant of 1us | ||
882 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB | ||
883 | * which consists of pipeline delay and inter chunk gap | ||
884 | */ | ||
885 | if (rfixed_trunc(wm->num_line_pair) > 1) { | ||
886 | a.full = rfixed_const(3); | ||
887 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); | ||
888 | wm->worst_case_latency.full += read_delay_latency.full; | ||
889 | } else { | ||
890 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; | ||
891 | } | ||
892 | |||
893 | /* Determine the tolerable latency | ||
894 | * TolerableLatency = Any given request has only 1 line time | ||
895 | * for the data to be returned | ||
896 | * LBRequestFifoDepth = Number of chunk requests the LB can | ||
897 | * put into the request FIFO for a display | ||
898 | * LineTime = total time for one line of display | ||
899 | * ChunkTime = the time it takes the DCP to send one chunk | ||
900 | * of data to the LB which consists of | ||
901 | * pipeline delay and inter chunk gap | ||
902 | */ | ||
903 | if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { | ||
904 | tolerable_latency.full = line_time.full; | ||
905 | } else { | ||
906 | tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); | ||
907 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; | ||
908 | tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); | ||
909 | tolerable_latency.full = line_time.full - tolerable_latency.full; | ||
910 | } | ||
911 | /* We assume worst case 32bits (4 bytes) */ | ||
912 | wm->dbpp.full = rfixed_const(2 * 16); | ||
913 | |||
914 | /* Determine the maximum priority mark | ||
915 | * width = viewport width in pixels | ||
916 | */ | ||
917 | a.full = rfixed_const(16); | ||
918 | wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | ||
919 | wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); | ||
920 | |||
921 | /* Determine estimated width */ | ||
922 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; | ||
923 | estimated_width.full = rfixed_div(estimated_width, consumption_time); | ||
924 | if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { | ||
925 | wm->priority_mark.full = rfixed_const(10); | ||
926 | } else { | ||
927 | a.full = rfixed_const(16); | ||
928 | wm->priority_mark.full = rfixed_div(estimated_width, a); | ||
929 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; | ||
930 | } | ||
931 | } | ||
932 | |||
933 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | ||
934 | { | ||
935 | struct drm_display_mode *mode0 = NULL; | ||
936 | struct drm_display_mode *mode1 = NULL; | ||
937 | struct rv515_watermark wm0; | ||
938 | struct rv515_watermark wm1; | ||
939 | u32 tmp; | ||
940 | fixed20_12 priority_mark02, priority_mark12, fill_rate; | ||
941 | fixed20_12 a, b; | ||
942 | |||
943 | if (rdev->mode_info.crtcs[0]->base.enabled) | ||
944 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | ||
945 | if (rdev->mode_info.crtcs[1]->base.enabled) | ||
946 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | ||
947 | rs690_line_buffer_adjust(rdev, mode0, mode1); | ||
948 | |||
949 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); | ||
950 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); | ||
951 | |||
952 | tmp = wm0.lb_request_fifo_depth; | ||
953 | tmp |= wm1.lb_request_fifo_depth << 16; | ||
954 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); | ||
955 | |||
956 | if (mode0 && mode1) { | ||
957 | if (rfixed_trunc(wm0.dbpp) > 64) | ||
958 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); | ||
959 | else | ||
960 | a.full = wm0.num_line_pair.full; | ||
961 | if (rfixed_trunc(wm1.dbpp) > 64) | ||
962 | b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); | ||
963 | else | ||
964 | b.full = wm1.num_line_pair.full; | ||
965 | a.full += b.full; | ||
966 | fill_rate.full = rfixed_div(wm0.sclk, a); | ||
967 | if (wm0.consumption_rate.full > fill_rate.full) { | ||
968 | b.full = wm0.consumption_rate.full - fill_rate.full; | ||
969 | b.full = rfixed_mul(b, wm0.active_time); | ||
970 | a.full = rfixed_const(16); | ||
971 | b.full = rfixed_div(b, a); | ||
972 | a.full = rfixed_mul(wm0.worst_case_latency, | ||
973 | wm0.consumption_rate); | ||
974 | priority_mark02.full = a.full + b.full; | ||
975 | } else { | ||
976 | a.full = rfixed_mul(wm0.worst_case_latency, | ||
977 | wm0.consumption_rate); | ||
978 | b.full = rfixed_const(16 * 1000); | ||
979 | priority_mark02.full = rfixed_div(a, b); | ||
980 | } | ||
981 | if (wm1.consumption_rate.full > fill_rate.full) { | ||
982 | b.full = wm1.consumption_rate.full - fill_rate.full; | ||
983 | b.full = rfixed_mul(b, wm1.active_time); | ||
984 | a.full = rfixed_const(16); | ||
985 | b.full = rfixed_div(b, a); | ||
986 | a.full = rfixed_mul(wm1.worst_case_latency, | ||
987 | wm1.consumption_rate); | ||
988 | priority_mark12.full = a.full + b.full; | ||
989 | } else { | ||
990 | a.full = rfixed_mul(wm1.worst_case_latency, | ||
991 | wm1.consumption_rate); | ||
992 | b.full = rfixed_const(16 * 1000); | ||
993 | priority_mark12.full = rfixed_div(a, b); | ||
994 | } | ||
995 | if (wm0.priority_mark.full > priority_mark02.full) | ||
996 | priority_mark02.full = wm0.priority_mark.full; | ||
997 | if (rfixed_trunc(priority_mark02) < 0) | ||
998 | priority_mark02.full = 0; | ||
999 | if (wm0.priority_mark_max.full > priority_mark02.full) | ||
1000 | priority_mark02.full = wm0.priority_mark_max.full; | ||
1001 | if (wm1.priority_mark.full > priority_mark12.full) | ||
1002 | priority_mark12.full = wm1.priority_mark.full; | ||
1003 | if (rfixed_trunc(priority_mark12) < 0) | ||
1004 | priority_mark12.full = 0; | ||
1005 | if (wm1.priority_mark_max.full > priority_mark12.full) | ||
1006 | priority_mark12.full = wm1.priority_mark_max.full; | ||
1007 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); | ||
1008 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); | ||
1009 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); | ||
1010 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); | ||
1011 | } else if (mode0) { | ||
1012 | if (rfixed_trunc(wm0.dbpp) > 64) | ||
1013 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); | ||
1014 | else | ||
1015 | a.full = wm0.num_line_pair.full; | ||
1016 | fill_rate.full = rfixed_div(wm0.sclk, a); | ||
1017 | if (wm0.consumption_rate.full > fill_rate.full) { | ||
1018 | b.full = wm0.consumption_rate.full - fill_rate.full; | ||
1019 | b.full = rfixed_mul(b, wm0.active_time); | ||
1020 | a.full = rfixed_const(16); | ||
1021 | b.full = rfixed_div(b, a); | ||
1022 | a.full = rfixed_mul(wm0.worst_case_latency, | ||
1023 | wm0.consumption_rate); | ||
1024 | priority_mark02.full = a.full + b.full; | ||
1025 | } else { | ||
1026 | a.full = rfixed_mul(wm0.worst_case_latency, | ||
1027 | wm0.consumption_rate); | ||
1028 | b.full = rfixed_const(16); | ||
1029 | priority_mark02.full = rfixed_div(a, b); | ||
1030 | } | ||
1031 | if (wm0.priority_mark.full > priority_mark02.full) | ||
1032 | priority_mark02.full = wm0.priority_mark.full; | ||
1033 | if (rfixed_trunc(priority_mark02) < 0) | ||
1034 | priority_mark02.full = 0; | ||
1035 | if (wm0.priority_mark_max.full > priority_mark02.full) | ||
1036 | priority_mark02.full = wm0.priority_mark_max.full; | ||
1037 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); | ||
1038 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); | ||
1039 | WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); | ||
1040 | WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | ||
1041 | } else { | ||
1042 | if (rfixed_trunc(wm1.dbpp) > 64) | ||
1043 | a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); | ||
1044 | else | ||
1045 | a.full = wm1.num_line_pair.full; | ||
1046 | fill_rate.full = rfixed_div(wm1.sclk, a); | ||
1047 | if (wm1.consumption_rate.full > fill_rate.full) { | ||
1048 | b.full = wm1.consumption_rate.full - fill_rate.full; | ||
1049 | b.full = rfixed_mul(b, wm1.active_time); | ||
1050 | a.full = rfixed_const(16); | ||
1051 | b.full = rfixed_div(b, a); | ||
1052 | a.full = rfixed_mul(wm1.worst_case_latency, | ||
1053 | wm1.consumption_rate); | ||
1054 | priority_mark12.full = a.full + b.full; | ||
1055 | } else { | ||
1056 | a.full = rfixed_mul(wm1.worst_case_latency, | ||
1057 | wm1.consumption_rate); | ||
1058 | b.full = rfixed_const(16 * 1000); | ||
1059 | priority_mark12.full = rfixed_div(a, b); | ||
1060 | } | ||
1061 | if (wm1.priority_mark.full > priority_mark12.full) | ||
1062 | priority_mark12.full = wm1.priority_mark.full; | ||
1063 | if (rfixed_trunc(priority_mark12) < 0) | ||
1064 | priority_mark12.full = 0; | ||
1065 | if (wm1.priority_mark_max.full > priority_mark12.full) | ||
1066 | priority_mark12.full = wm1.priority_mark_max.full; | ||
1067 | WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); | ||
1068 | WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | ||
1069 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); | ||
1070 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); | ||
1071 | } | ||
1072 | } | ||
1073 | |||
1074 | void rv515_bandwidth_update(struct radeon_device *rdev) | ||
1075 | { | ||
1076 | uint32_t tmp; | ||
1077 | struct drm_display_mode *mode0 = NULL; | ||
1078 | struct drm_display_mode *mode1 = NULL; | ||
1079 | |||
1080 | if (rdev->mode_info.crtcs[0]->base.enabled) | ||
1081 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | ||
1082 | if (rdev->mode_info.crtcs[1]->base.enabled) | ||
1083 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | ||
1084 | /* | ||
1085 | * Set display0/1 priority up in the memory controller for | ||
1086 | * modes if the user specifies HIGH for displaypriority | ||
1087 | * option. | ||
1088 | */ | ||
1089 | if (rdev->disp_priority == 2) { | ||
1090 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); | ||
1091 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; | ||
1092 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; | ||
1093 | if (mode1) | ||
1094 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); | ||
1095 | if (mode0) | ||
1096 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); | ||
1097 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); | ||
1098 | } | ||
1099 | rv515_bandwidth_avivo_update(rdev); | ||
1100 | } | ||
diff --git a/drivers/gpu/drm/radeon/rv515r.h b/drivers/gpu/drm/radeon/rv515r.h new file mode 100644 index 000000000000..f3cf84039906 --- /dev/null +++ b/drivers/gpu/drm/radeon/rv515r.h | |||
@@ -0,0 +1,170 @@ | |||
1 | /* | ||
2 | * Copyright 2008 Advanced Micro Devices, Inc. | ||
3 | * Copyright 2008 Red Hat Inc. | ||
4 | * Copyright 2009 Jerome Glisse. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
22 | * OTHER DEALINGS IN THE SOFTWARE. | ||
23 | * | ||
24 | * Authors: Dave Airlie | ||
25 | * Alex Deucher | ||
26 | * Jerome Glisse | ||
27 | */ | ||
28 | #ifndef RV515R_H | ||
29 | #define RV515R_H | ||
30 | |||
31 | /* RV515 registers */ | ||
32 | #define PCIE_INDEX 0x0030 | ||
33 | #define PCIE_DATA 0x0034 | ||
34 | #define MC_IND_INDEX 0x0070 | ||
35 | #define MC_IND_WR_EN (1 << 24) | ||
36 | #define MC_IND_DATA 0x0074 | ||
37 | #define RBBM_SOFT_RESET 0x00F0 | ||
38 | #define CONFIG_MEMSIZE 0x00F8 | ||
39 | #define HDP_FB_LOCATION 0x0134 | ||
40 | #define CP_CSQ_CNTL 0x0740 | ||
41 | #define CP_CSQ_MODE 0x0744 | ||
42 | #define CP_CSQ_ADDR 0x07F0 | ||
43 | #define CP_CSQ_DATA 0x07F4 | ||
44 | #define CP_CSQ_STAT 0x07F8 | ||
45 | #define CP_CSQ2_STAT 0x07FC | ||
46 | #define RBBM_STATUS 0x0E40 | ||
47 | #define DST_PIPE_CONFIG 0x170C | ||
48 | #define WAIT_UNTIL 0x1720 | ||
49 | #define WAIT_2D_IDLE (1 << 14) | ||
50 | #define WAIT_3D_IDLE (1 << 15) | ||
51 | #define WAIT_2D_IDLECLEAN (1 << 16) | ||
52 | #define WAIT_3D_IDLECLEAN (1 << 17) | ||
53 | #define ISYNC_CNTL 0x1724 | ||
54 | #define ISYNC_ANY2D_IDLE3D (1 << 0) | ||
55 | #define ISYNC_ANY3D_IDLE2D (1 << 1) | ||
56 | #define ISYNC_TRIG2D_IDLE3D (1 << 2) | ||
57 | #define ISYNC_TRIG3D_IDLE2D (1 << 3) | ||
58 | #define ISYNC_WAIT_IDLEGUI (1 << 4) | ||
59 | #define ISYNC_CPSCRATCH_IDLEGUI (1 << 5) | ||
60 | #define VAP_INDEX_OFFSET 0x208C | ||
61 | #define VAP_PVS_STATE_FLUSH_REG 0x2284 | ||
62 | #define GB_ENABLE 0x4008 | ||
63 | #define GB_MSPOS0 0x4010 | ||
64 | #define MS_X0_SHIFT 0 | ||
65 | #define MS_Y0_SHIFT 4 | ||
66 | #define MS_X1_SHIFT 8 | ||
67 | #define MS_Y1_SHIFT 12 | ||
68 | #define MS_X2_SHIFT 16 | ||
69 | #define MS_Y2_SHIFT 20 | ||
70 | #define MSBD0_Y_SHIFT 24 | ||
71 | #define MSBD0_X_SHIFT 28 | ||
72 | #define GB_MSPOS1 0x4014 | ||
73 | #define MS_X3_SHIFT 0 | ||
74 | #define MS_Y3_SHIFT 4 | ||
75 | #define MS_X4_SHIFT 8 | ||
76 | #define MS_Y4_SHIFT 12 | ||
77 | #define MS_X5_SHIFT 16 | ||
78 | #define MS_Y5_SHIFT 20 | ||
79 | #define MSBD1_SHIFT 24 | ||
80 | #define GB_TILE_CONFIG 0x4018 | ||
81 | #define ENABLE_TILING (1 << 0) | ||
82 | #define PIPE_COUNT_MASK 0x0000000E | ||
83 | #define PIPE_COUNT_SHIFT 1 | ||
84 | #define TILE_SIZE_8 (0 << 4) | ||
85 | #define TILE_SIZE_16 (1 << 4) | ||
86 | #define TILE_SIZE_32 (2 << 4) | ||
87 | #define SUBPIXEL_1_12 (0 << 16) | ||
88 | #define SUBPIXEL_1_16 (1 << 16) | ||
89 | #define GB_SELECT 0x401C | ||
90 | #define GB_AA_CONFIG 0x4020 | ||
91 | #define GB_PIPE_SELECT 0x402C | ||
92 | #define GA_ENHANCE 0x4274 | ||
93 | #define GA_DEADLOCK_CNTL (1 << 0) | ||
94 | #define GA_FASTSYNC_CNTL (1 << 1) | ||
95 | #define GA_POLY_MODE 0x4288 | ||
96 | #define FRONT_PTYPE_POINT (0 << 4) | ||
97 | #define FRONT_PTYPE_LINE (1 << 4) | ||
98 | #define FRONT_PTYPE_TRIANGE (2 << 4) | ||
99 | #define BACK_PTYPE_POINT (0 << 7) | ||
100 | #define BACK_PTYPE_LINE (1 << 7) | ||
101 | #define BACK_PTYPE_TRIANGE (2 << 7) | ||
102 | #define GA_ROUND_MODE 0x428C | ||
103 | #define GEOMETRY_ROUND_TRUNC (0 << 0) | ||
104 | #define GEOMETRY_ROUND_NEAREST (1 << 0) | ||
105 | #define COLOR_ROUND_TRUNC (0 << 2) | ||
106 | #define COLOR_ROUND_NEAREST (1 << 2) | ||
107 | #define SU_REG_DEST 0x42C8 | ||
108 | #define RB3D_DSTCACHE_CTLSTAT 0x4E4C | ||
109 | #define RB3D_DC_FLUSH (2 << 0) | ||
110 | #define RB3D_DC_FREE (2 << 2) | ||
111 | #define RB3D_DC_FINISH (1 << 4) | ||
112 | #define ZB_ZCACHE_CTLSTAT 0x4F18 | ||
113 | #define ZC_FLUSH (1 << 0) | ||
114 | #define ZC_FREE (1 << 1) | ||
115 | #define DC_LB_MEMORY_SPLIT 0x6520 | ||
116 | #define DC_LB_MEMORY_SPLIT_MASK 0x00000003 | ||
117 | #define DC_LB_MEMORY_SPLIT_SHIFT 0 | ||
118 | #define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 | ||
119 | #define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 | ||
120 | #define DC_LB_MEMORY_SPLIT_D1_ONLY 2 | ||
121 | #define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 | ||
122 | #define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) | ||
123 | #define DC_LB_DISP1_END_ADR_SHIFT 4 | ||
124 | #define DC_LB_DISP1_END_ADR_MASK 0x00007FF0 | ||
125 | #define D1MODE_PRIORITY_A_CNT 0x6548 | ||
126 | #define MODE_PRIORITY_MARK_MASK 0x00007FFF | ||
127 | #define MODE_PRIORITY_OFF (1 << 16) | ||
128 | #define MODE_PRIORITY_ALWAYS_ON (1 << 20) | ||
129 | #define MODE_PRIORITY_FORCE_MASK (1 << 24) | ||
130 | #define D1MODE_PRIORITY_B_CNT 0x654C | ||
131 | #define LB_MAX_REQ_OUTSTANDING 0x6D58 | ||
132 | #define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F | ||
133 | #define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 | ||
134 | #define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000 | ||
135 | #define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 | ||
136 | #define D2MODE_PRIORITY_A_CNT 0x6D48 | ||
137 | #define D2MODE_PRIORITY_B_CNT 0x6D4C | ||
138 | |||
139 | /* ix[MC] registers */ | ||
140 | #define MC_FB_LOCATION 0x01 | ||
141 | #define MC_FB_START_MASK 0x0000FFFF | ||
142 | #define MC_FB_START_SHIFT 0 | ||
143 | #define MC_FB_TOP_MASK 0xFFFF0000 | ||
144 | #define MC_FB_TOP_SHIFT 16 | ||
145 | #define MC_AGP_LOCATION 0x02 | ||
146 | #define MC_AGP_START_MASK 0x0000FFFF | ||
147 | #define MC_AGP_START_SHIFT 0 | ||
148 | #define MC_AGP_TOP_MASK 0xFFFF0000 | ||
149 | #define MC_AGP_TOP_SHIFT 16 | ||
150 | #define MC_AGP_BASE 0x03 | ||
151 | #define MC_AGP_BASE_2 0x04 | ||
152 | #define MC_CNTL 0x5 | ||
153 | #define MEM_NUM_CHANNELS_MASK 0x00000003 | ||
154 | #define MC_STATUS 0x08 | ||
155 | #define MC_STATUS_IDLE (1 << 4) | ||
156 | #define MC_MISC_LAT_TIMER 0x09 | ||
157 | #define MC_CPR_INIT_LAT_MASK 0x0000000F | ||
158 | #define MC_VF_INIT_LAT_MASK 0x000000F0 | ||
159 | #define MC_DISP0R_INIT_LAT_MASK 0x00000F00 | ||
160 | #define MC_DISP0R_INIT_LAT_SHIFT 8 | ||
161 | #define MC_DISP1R_INIT_LAT_MASK 0x0000F000 | ||
162 | #define MC_DISP1R_INIT_LAT_SHIFT 12 | ||
163 | #define MC_FIXED_INIT_LAT_MASK 0x000F0000 | ||
164 | #define MC_E2R_INIT_LAT_MASK 0x00F00000 | ||
165 | #define SAME_PAGE_PRIO_MASK 0x0F000000 | ||
166 | #define MC_GLOBW_INIT_LAT_MASK 0xF0000000 | ||
167 | |||
168 | |||
169 | #endif | ||
170 | |||
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index da50cc51ede3..21d8ffd57308 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -67,7 +67,7 @@ int rv770_mc_init(struct radeon_device *rdev) | |||
67 | "programming pipes. Bad things might happen.\n"); | 67 | "programming pipes. Bad things might happen.\n"); |
68 | } | 68 | } |
69 | 69 | ||
70 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; | 70 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
71 | tmp = REG_SET(R700_MC_FB_TOP, tmp >> 24); | 71 | tmp = REG_SET(R700_MC_FB_TOP, tmp >> 24); |
72 | tmp |= REG_SET(R700_MC_FB_BASE, rdev->mc.vram_location >> 24); | 72 | tmp |= REG_SET(R700_MC_FB_BASE, rdev->mc.vram_location >> 24); |
73 | WREG32(R700_MC_VM_FB_LOCATION, tmp); | 73 | WREG32(R700_MC_VM_FB_LOCATION, tmp); |
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index c1c407f7cca3..6538d4236989 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c | |||
@@ -43,7 +43,6 @@ | |||
43 | #define TTM_BO_HASH_ORDER 13 | 43 | #define TTM_BO_HASH_ORDER 13 |
44 | 44 | ||
45 | static int ttm_bo_setup_vm(struct ttm_buffer_object *bo); | 45 | static int ttm_bo_setup_vm(struct ttm_buffer_object *bo); |
46 | static void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo); | ||
47 | static int ttm_bo_swapout(struct ttm_mem_shrink *shrink); | 46 | static int ttm_bo_swapout(struct ttm_mem_shrink *shrink); |
48 | 47 | ||
49 | static inline uint32_t ttm_bo_type_flags(unsigned type) | 48 | static inline uint32_t ttm_bo_type_flags(unsigned type) |
@@ -224,6 +223,9 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) | |||
224 | TTM_ASSERT_LOCKED(&bo->mutex); | 223 | TTM_ASSERT_LOCKED(&bo->mutex); |
225 | bo->ttm = NULL; | 224 | bo->ttm = NULL; |
226 | 225 | ||
226 | if (bdev->need_dma32) | ||
227 | page_flags |= TTM_PAGE_FLAG_DMA32; | ||
228 | |||
227 | switch (bo->type) { | 229 | switch (bo->type) { |
228 | case ttm_bo_type_device: | 230 | case ttm_bo_type_device: |
229 | if (zero_alloc) | 231 | if (zero_alloc) |
@@ -304,6 +306,9 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, | |||
304 | 306 | ||
305 | } | 307 | } |
306 | 308 | ||
309 | if (bdev->driver->move_notify) | ||
310 | bdev->driver->move_notify(bo, mem); | ||
311 | |||
307 | if (!(old_man->flags & TTM_MEMTYPE_FLAG_FIXED) && | 312 | if (!(old_man->flags & TTM_MEMTYPE_FLAG_FIXED) && |
308 | !(new_man->flags & TTM_MEMTYPE_FLAG_FIXED)) | 313 | !(new_man->flags & TTM_MEMTYPE_FLAG_FIXED)) |
309 | ret = ttm_bo_move_ttm(bo, evict, no_wait, mem); | 314 | ret = ttm_bo_move_ttm(bo, evict, no_wait, mem); |
@@ -655,31 +660,52 @@ retry_pre_get: | |||
655 | return 0; | 660 | return 0; |
656 | } | 661 | } |
657 | 662 | ||
663 | static uint32_t ttm_bo_select_caching(struct ttm_mem_type_manager *man, | ||
664 | uint32_t cur_placement, | ||
665 | uint32_t proposed_placement) | ||
666 | { | ||
667 | uint32_t caching = proposed_placement & TTM_PL_MASK_CACHING; | ||
668 | uint32_t result = proposed_placement & ~TTM_PL_MASK_CACHING; | ||
669 | |||
670 | /** | ||
671 | * Keep current caching if possible. | ||
672 | */ | ||
673 | |||
674 | if ((cur_placement & caching) != 0) | ||
675 | result |= (cur_placement & caching); | ||
676 | else if ((man->default_caching & caching) != 0) | ||
677 | result |= man->default_caching; | ||
678 | else if ((TTM_PL_FLAG_CACHED & caching) != 0) | ||
679 | result |= TTM_PL_FLAG_CACHED; | ||
680 | else if ((TTM_PL_FLAG_WC & caching) != 0) | ||
681 | result |= TTM_PL_FLAG_WC; | ||
682 | else if ((TTM_PL_FLAG_UNCACHED & caching) != 0) | ||
683 | result |= TTM_PL_FLAG_UNCACHED; | ||
684 | |||
685 | return result; | ||
686 | } | ||
687 | |||
688 | |||
658 | static bool ttm_bo_mt_compatible(struct ttm_mem_type_manager *man, | 689 | static bool ttm_bo_mt_compatible(struct ttm_mem_type_manager *man, |
659 | bool disallow_fixed, | 690 | bool disallow_fixed, |
660 | uint32_t mem_type, | 691 | uint32_t mem_type, |
661 | uint32_t mask, uint32_t *res_mask) | 692 | uint32_t proposed_placement, |
693 | uint32_t *masked_placement) | ||
662 | { | 694 | { |
663 | uint32_t cur_flags = ttm_bo_type_flags(mem_type); | 695 | uint32_t cur_flags = ttm_bo_type_flags(mem_type); |
664 | 696 | ||
665 | if ((man->flags & TTM_MEMTYPE_FLAG_FIXED) && disallow_fixed) | 697 | if ((man->flags & TTM_MEMTYPE_FLAG_FIXED) && disallow_fixed) |
666 | return false; | 698 | return false; |
667 | 699 | ||
668 | if ((cur_flags & mask & TTM_PL_MASK_MEM) == 0) | 700 | if ((cur_flags & proposed_placement & TTM_PL_MASK_MEM) == 0) |
669 | return false; | 701 | return false; |
670 | 702 | ||
671 | if ((mask & man->available_caching) == 0) | 703 | if ((proposed_placement & man->available_caching) == 0) |
672 | return false; | 704 | return false; |
673 | if (mask & man->default_caching) | ||
674 | cur_flags |= man->default_caching; | ||
675 | else if (mask & TTM_PL_FLAG_CACHED) | ||
676 | cur_flags |= TTM_PL_FLAG_CACHED; | ||
677 | else if (mask & TTM_PL_FLAG_WC) | ||
678 | cur_flags |= TTM_PL_FLAG_WC; | ||
679 | else | ||
680 | cur_flags |= TTM_PL_FLAG_UNCACHED; | ||
681 | 705 | ||
682 | *res_mask = cur_flags; | 706 | cur_flags |= (proposed_placement & man->available_caching); |
707 | |||
708 | *masked_placement = cur_flags; | ||
683 | return true; | 709 | return true; |
684 | } | 710 | } |
685 | 711 | ||
@@ -723,6 +749,9 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, | |||
723 | if (!type_ok) | 749 | if (!type_ok) |
724 | continue; | 750 | continue; |
725 | 751 | ||
752 | cur_flags = ttm_bo_select_caching(man, bo->mem.placement, | ||
753 | cur_flags); | ||
754 | |||
726 | if (mem_type == TTM_PL_SYSTEM) | 755 | if (mem_type == TTM_PL_SYSTEM) |
727 | break; | 756 | break; |
728 | 757 | ||
@@ -779,6 +808,9 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, | |||
779 | proposed_placement, &cur_flags)) | 808 | proposed_placement, &cur_flags)) |
780 | continue; | 809 | continue; |
781 | 810 | ||
811 | cur_flags = ttm_bo_select_caching(man, bo->mem.placement, | ||
812 | cur_flags); | ||
813 | |||
782 | ret = ttm_bo_mem_force_space(bdev, mem, mem_type, | 814 | ret = ttm_bo_mem_force_space(bdev, mem, mem_type, |
783 | interruptible, no_wait); | 815 | interruptible, no_wait); |
784 | 816 | ||
@@ -1305,7 +1337,8 @@ EXPORT_SYMBOL(ttm_bo_device_release); | |||
1305 | 1337 | ||
1306 | int ttm_bo_device_init(struct ttm_bo_device *bdev, | 1338 | int ttm_bo_device_init(struct ttm_bo_device *bdev, |
1307 | struct ttm_mem_global *mem_glob, | 1339 | struct ttm_mem_global *mem_glob, |
1308 | struct ttm_bo_driver *driver, uint64_t file_page_offset) | 1340 | struct ttm_bo_driver *driver, uint64_t file_page_offset, |
1341 | bool need_dma32) | ||
1309 | { | 1342 | { |
1310 | int ret = -EINVAL; | 1343 | int ret = -EINVAL; |
1311 | 1344 | ||
@@ -1342,6 +1375,7 @@ int ttm_bo_device_init(struct ttm_bo_device *bdev, | |||
1342 | INIT_LIST_HEAD(&bdev->ddestroy); | 1375 | INIT_LIST_HEAD(&bdev->ddestroy); |
1343 | INIT_LIST_HEAD(&bdev->swap_lru); | 1376 | INIT_LIST_HEAD(&bdev->swap_lru); |
1344 | bdev->dev_mapping = NULL; | 1377 | bdev->dev_mapping = NULL; |
1378 | bdev->need_dma32 = need_dma32; | ||
1345 | ttm_mem_init_shrink(&bdev->shrink, ttm_bo_swapout); | 1379 | ttm_mem_init_shrink(&bdev->shrink, ttm_bo_swapout); |
1346 | ret = ttm_mem_register_shrink(mem_glob, &bdev->shrink); | 1380 | ret = ttm_mem_register_shrink(mem_glob, &bdev->shrink); |
1347 | if (unlikely(ret != 0)) { | 1381 | if (unlikely(ret != 0)) { |
@@ -1419,6 +1453,7 @@ void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo) | |||
1419 | 1453 | ||
1420 | unmap_mapping_range(bdev->dev_mapping, offset, holelen, 1); | 1454 | unmap_mapping_range(bdev->dev_mapping, offset, holelen, 1); |
1421 | } | 1455 | } |
1456 | EXPORT_SYMBOL(ttm_bo_unmap_virtual); | ||
1422 | 1457 | ||
1423 | static void ttm_bo_vm_insert_rb(struct ttm_buffer_object *bo) | 1458 | static void ttm_bo_vm_insert_rb(struct ttm_buffer_object *bo) |
1424 | { | 1459 | { |
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index bdec583901eb..ce2e6f38ea01 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c | |||
@@ -136,7 +136,8 @@ static int ttm_copy_io_page(void *dst, void *src, unsigned long page) | |||
136 | } | 136 | } |
137 | 137 | ||
138 | static int ttm_copy_io_ttm_page(struct ttm_tt *ttm, void *src, | 138 | static int ttm_copy_io_ttm_page(struct ttm_tt *ttm, void *src, |
139 | unsigned long page) | 139 | unsigned long page, |
140 | pgprot_t prot) | ||
140 | { | 141 | { |
141 | struct page *d = ttm_tt_get_page(ttm, page); | 142 | struct page *d = ttm_tt_get_page(ttm, page); |
142 | void *dst; | 143 | void *dst; |
@@ -145,17 +146,35 @@ static int ttm_copy_io_ttm_page(struct ttm_tt *ttm, void *src, | |||
145 | return -ENOMEM; | 146 | return -ENOMEM; |
146 | 147 | ||
147 | src = (void *)((unsigned long)src + (page << PAGE_SHIFT)); | 148 | src = (void *)((unsigned long)src + (page << PAGE_SHIFT)); |
148 | dst = kmap(d); | 149 | |
150 | #ifdef CONFIG_X86 | ||
151 | dst = kmap_atomic_prot(d, KM_USER0, prot); | ||
152 | #else | ||
153 | if (prot != PAGE_KERNEL) | ||
154 | dst = vmap(&d, 1, 0, prot); | ||
155 | else | ||
156 | dst = kmap(d); | ||
157 | #endif | ||
149 | if (!dst) | 158 | if (!dst) |
150 | return -ENOMEM; | 159 | return -ENOMEM; |
151 | 160 | ||
152 | memcpy_fromio(dst, src, PAGE_SIZE); | 161 | memcpy_fromio(dst, src, PAGE_SIZE); |
153 | kunmap(d); | 162 | |
163 | #ifdef CONFIG_X86 | ||
164 | kunmap_atomic(dst, KM_USER0); | ||
165 | #else | ||
166 | if (prot != PAGE_KERNEL) | ||
167 | vunmap(dst); | ||
168 | else | ||
169 | kunmap(d); | ||
170 | #endif | ||
171 | |||
154 | return 0; | 172 | return 0; |
155 | } | 173 | } |
156 | 174 | ||
157 | static int ttm_copy_ttm_io_page(struct ttm_tt *ttm, void *dst, | 175 | static int ttm_copy_ttm_io_page(struct ttm_tt *ttm, void *dst, |
158 | unsigned long page) | 176 | unsigned long page, |
177 | pgprot_t prot) | ||
159 | { | 178 | { |
160 | struct page *s = ttm_tt_get_page(ttm, page); | 179 | struct page *s = ttm_tt_get_page(ttm, page); |
161 | void *src; | 180 | void *src; |
@@ -164,12 +183,28 @@ static int ttm_copy_ttm_io_page(struct ttm_tt *ttm, void *dst, | |||
164 | return -ENOMEM; | 183 | return -ENOMEM; |
165 | 184 | ||
166 | dst = (void *)((unsigned long)dst + (page << PAGE_SHIFT)); | 185 | dst = (void *)((unsigned long)dst + (page << PAGE_SHIFT)); |
167 | src = kmap(s); | 186 | #ifdef CONFIG_X86 |
187 | src = kmap_atomic_prot(s, KM_USER0, prot); | ||
188 | #else | ||
189 | if (prot != PAGE_KERNEL) | ||
190 | src = vmap(&s, 1, 0, prot); | ||
191 | else | ||
192 | src = kmap(s); | ||
193 | #endif | ||
168 | if (!src) | 194 | if (!src) |
169 | return -ENOMEM; | 195 | return -ENOMEM; |
170 | 196 | ||
171 | memcpy_toio(dst, src, PAGE_SIZE); | 197 | memcpy_toio(dst, src, PAGE_SIZE); |
172 | kunmap(s); | 198 | |
199 | #ifdef CONFIG_X86 | ||
200 | kunmap_atomic(src, KM_USER0); | ||
201 | #else | ||
202 | if (prot != PAGE_KERNEL) | ||
203 | vunmap(src); | ||
204 | else | ||
205 | kunmap(s); | ||
206 | #endif | ||
207 | |||
173 | return 0; | 208 | return 0; |
174 | } | 209 | } |
175 | 210 | ||
@@ -214,11 +249,17 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo, | |||
214 | 249 | ||
215 | for (i = 0; i < new_mem->num_pages; ++i) { | 250 | for (i = 0; i < new_mem->num_pages; ++i) { |
216 | page = i * dir + add; | 251 | page = i * dir + add; |
217 | if (old_iomap == NULL) | 252 | if (old_iomap == NULL) { |
218 | ret = ttm_copy_ttm_io_page(ttm, new_iomap, page); | 253 | pgprot_t prot = ttm_io_prot(old_mem->placement, |
219 | else if (new_iomap == NULL) | 254 | PAGE_KERNEL); |
220 | ret = ttm_copy_io_ttm_page(ttm, old_iomap, page); | 255 | ret = ttm_copy_ttm_io_page(ttm, new_iomap, page, |
221 | else | 256 | prot); |
257 | } else if (new_iomap == NULL) { | ||
258 | pgprot_t prot = ttm_io_prot(new_mem->placement, | ||
259 | PAGE_KERNEL); | ||
260 | ret = ttm_copy_io_ttm_page(ttm, old_iomap, page, | ||
261 | prot); | ||
262 | } else | ||
222 | ret = ttm_copy_io_page(new_iomap, old_iomap, page); | 263 | ret = ttm_copy_io_page(new_iomap, old_iomap, page); |
223 | if (ret) | 264 | if (ret) |
224 | goto out1; | 265 | goto out1; |
@@ -509,8 +550,8 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo, | |||
509 | if (evict) { | 550 | if (evict) { |
510 | ret = ttm_bo_wait(bo, false, false, false); | 551 | ret = ttm_bo_wait(bo, false, false, false); |
511 | spin_unlock(&bo->lock); | 552 | spin_unlock(&bo->lock); |
512 | driver->sync_obj_unref(&bo->sync_obj); | 553 | if (tmp_obj) |
513 | 554 | driver->sync_obj_unref(&tmp_obj); | |
514 | if (ret) | 555 | if (ret) |
515 | return ret; | 556 | return ret; |
516 | 557 | ||
@@ -532,6 +573,8 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo, | |||
532 | 573 | ||
533 | set_bit(TTM_BO_PRIV_FLAG_MOVING, &bo->priv_flags); | 574 | set_bit(TTM_BO_PRIV_FLAG_MOVING, &bo->priv_flags); |
534 | spin_unlock(&bo->lock); | 575 | spin_unlock(&bo->lock); |
576 | if (tmp_obj) | ||
577 | driver->sync_obj_unref(&tmp_obj); | ||
535 | 578 | ||
536 | ret = ttm_buffer_object_transfer(bo, &ghost_obj); | 579 | ret = ttm_buffer_object_transfer(bo, &ghost_obj); |
537 | if (ret) | 580 | if (ret) |
diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index fe949a12fe40..33de7637c0c6 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c | |||
@@ -101,6 +101,9 @@ static int ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |||
101 | return VM_FAULT_NOPAGE; | 101 | return VM_FAULT_NOPAGE; |
102 | } | 102 | } |
103 | 103 | ||
104 | if (bdev->driver->fault_reserve_notify) | ||
105 | bdev->driver->fault_reserve_notify(bo); | ||
106 | |||
104 | /* | 107 | /* |
105 | * Wait for buffer data in transit, due to a pipelined | 108 | * Wait for buffer data in transit, due to a pipelined |
106 | * move. | 109 | * move. |
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 75dc8bd24592..b8b6c4a5f983 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c | |||
@@ -86,10 +86,16 @@ void ttm_tt_cache_flush(struct page *pages[], unsigned long num_pages) | |||
86 | unsigned long i; | 86 | unsigned long i; |
87 | 87 | ||
88 | for (i = 0; i < num_pages; ++i) { | 88 | for (i = 0; i < num_pages; ++i) { |
89 | if (pages[i]) { | 89 | struct page *page = pages[i]; |
90 | unsigned long start = (unsigned long)page_address(pages[i]); | 90 | void *page_virtual; |
91 | flush_dcache_range(start, start + PAGE_SIZE); | 91 | |
92 | } | 92 | if (unlikely(page == NULL)) |
93 | continue; | ||
94 | |||
95 | page_virtual = kmap_atomic(page, KM_USER0); | ||
96 | flush_dcache_range((unsigned long) page_virtual, | ||
97 | (unsigned long) page_virtual + PAGE_SIZE); | ||
98 | kunmap_atomic(page_virtual, KM_USER0); | ||
93 | } | 99 | } |
94 | #else | 100 | #else |
95 | if (on_each_cpu(ttm_tt_ipi_handler, NULL, 1) != 0) | 101 | if (on_each_cpu(ttm_tt_ipi_handler, NULL, 1) != 0) |
@@ -131,10 +137,17 @@ static void ttm_tt_free_page_directory(struct ttm_tt *ttm) | |||
131 | 137 | ||
132 | static struct page *ttm_tt_alloc_page(unsigned page_flags) | 138 | static struct page *ttm_tt_alloc_page(unsigned page_flags) |
133 | { | 139 | { |
140 | gfp_t gfp_flags = GFP_USER; | ||
141 | |||
134 | if (page_flags & TTM_PAGE_FLAG_ZERO_ALLOC) | 142 | if (page_flags & TTM_PAGE_FLAG_ZERO_ALLOC) |
135 | return alloc_page(GFP_HIGHUSER | __GFP_ZERO); | 143 | gfp_flags |= __GFP_ZERO; |
144 | |||
145 | if (page_flags & TTM_PAGE_FLAG_DMA32) | ||
146 | gfp_flags |= __GFP_DMA32; | ||
147 | else | ||
148 | gfp_flags |= __GFP_HIGHMEM; | ||
136 | 149 | ||
137 | return alloc_page(GFP_HIGHUSER); | 150 | return alloc_page(gfp_flags); |
138 | } | 151 | } |
139 | 152 | ||
140 | static void ttm_tt_free_user_pages(struct ttm_tt *ttm) | 153 | static void ttm_tt_free_user_pages(struct ttm_tt *ttm) |