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-rw-r--r--drivers/gpu/drm/i915/intel_display.c24
1 files changed, 16 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3bc6ab56cf8b..841f0397288b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1516,8 +1516,10 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1516 1516
1517 reg = PIPECONF(pipe); 1517 reg = PIPECONF(pipe);
1518 val = I915_READ(reg); 1518 val = I915_READ(reg);
1519 val |= PIPECONF_ENABLE; 1519 if (val & PIPECONF_ENABLE)
1520 I915_WRITE(reg, val); 1520 return;
1521
1522 I915_WRITE(reg, val | PIPECONF_ENABLE);
1521 intel_wait_for_vblank(dev_priv->dev, pipe); 1523 intel_wait_for_vblank(dev_priv->dev, pipe);
1522} 1524}
1523 1525
@@ -1551,8 +1553,10 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1551 1553
1552 reg = PIPECONF(pipe); 1554 reg = PIPECONF(pipe);
1553 val = I915_READ(reg); 1555 val = I915_READ(reg);
1554 val &= ~PIPECONF_ENABLE; 1556 if ((val & PIPECONF_ENABLE) == 0)
1555 I915_WRITE(reg, val); 1557 return;
1558
1559 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1556 intel_wait_for_pipe_off(dev_priv->dev, pipe); 1560 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1557} 1561}
1558 1562
@@ -1575,8 +1579,10 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv,
1575 1579
1576 reg = DSPCNTR(plane); 1580 reg = DSPCNTR(plane);
1577 val = I915_READ(reg); 1581 val = I915_READ(reg);
1578 val |= DISPLAY_PLANE_ENABLE; 1582 if (val & DISPLAY_PLANE_ENABLE)
1579 I915_WRITE(reg, val); 1583 return;
1584
1585 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1580 intel_wait_for_vblank(dev_priv->dev, pipe); 1586 intel_wait_for_vblank(dev_priv->dev, pipe);
1581} 1587}
1582 1588
@@ -1607,8 +1613,10 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv,
1607 1613
1608 reg = DSPCNTR(plane); 1614 reg = DSPCNTR(plane);
1609 val = I915_READ(reg); 1615 val = I915_READ(reg);
1610 val &= ~DISPLAY_PLANE_ENABLE; 1616 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1611 I915_WRITE(reg, val); 1617 return;
1618
1619 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1612 intel_flush_display_plane(dev_priv, plane); 1620 intel_flush_display_plane(dev_priv, plane);
1613 intel_wait_for_vblank(dev_priv->dev, pipe); 1621 intel_wait_for_vblank(dev_priv->dev, pipe);
1614} 1622}