102 files changed, 1846 insertions, 995 deletions

diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 03711d00aaae..8218078b6133 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -419,8 +419,9 @@ long drm_ioctl(struct file *filp,
                         retcode = -EFAULT;
                         goto err_i1;
                 }
-        } else
+        } else if (cmd & IOC_OUT) {
                 memset(kdata, 0, usize);
+        }
 
         if (ioctl->flags & DRM_UNLOCKED)
                 retcode = func(dev, kdata, file_priv);
diff --git a/drivers/gpu/drm/drm_modeset_lock.c b/drivers/gpu/drm/drm_modeset_lock.c
index 7c2497dea1e9..0dc57d5ecd10 100644
--- a/drivers/gpu/drm/drm_modeset_lock.c
+++ b/drivers/gpu/drm/drm_modeset_lock.c
@@ -64,6 +64,7 @@
 void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx,
                 uint32_t flags)
 {
+        memset(ctx, 0, sizeof(*ctx));
         ww_acquire_init(&ctx->ww_ctx, &crtc_ww_class);
         INIT_LIST_HEAD(&ctx->locked);
 }
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dpi.c b/drivers/gpu/drm/exynos/exynos_drm_dpi.c
index 482127f633c5..9e530f205ad2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dpi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dpi.c
@@ -40,7 +40,7 @@ exynos_dpi_detect(struct drm_connector *connector, bool force)
 {
         struct exynos_dpi *ctx = connector_to_dpi(connector);
 
-        if (!ctx->panel->connector)
+        if (ctx->panel && !ctx->panel->connector)
                 drm_panel_attach(ctx->panel, &ctx->connector);
 
         return connector_status_connected;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index d91f27777537..ab7d182063c3 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -765,24 +765,24 @@ static int exynos_drm_init(void)
 
         return 0;
 
-err_unregister_pd:
-        platform_device_unregister(exynos_drm_pdev);
-
 err_remove_vidi:
 #ifdef CONFIG_DRM_EXYNOS_VIDI
         exynos_drm_remove_vidi();
+
+err_unregister_pd:
 #endif
+        platform_device_unregister(exynos_drm_pdev);
 
         return ret;
 }
 
 static void exynos_drm_exit(void)
 {
+        platform_driver_unregister(&exynos_drm_platform_driver);
 #ifdef CONFIG_DRM_EXYNOS_VIDI
         exynos_drm_remove_vidi();
 #endif
         platform_device_unregister(exynos_drm_pdev);
-        platform_driver_unregister(&exynos_drm_platform_driver);
 }
 
 module_init(exynos_drm_init);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 36535f398848..06cde4506278 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -343,7 +343,7 @@ struct exynos_drm_display * exynos_dpi_probe(struct device *dev);
 int exynos_dpi_remove(struct device *dev);
 #else
 static inline struct exynos_drm_display *
-exynos_dpi_probe(struct device *dev) { return 0; }
+exynos_dpi_probe(struct device *dev) { return NULL; }
 static inline int exynos_dpi_remove(struct device *dev) { return 0; }
 #endif
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index bb45ab2e7384..33161ad38201 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -741,6 +741,8 @@ static void fimd_apply(struct exynos_drm_manager *mgr)
                 win_data = &ctx->win_data[i];
                 if (win_data->enabled)
                         fimd_win_commit(mgr, i);
+                else
+                        fimd_win_disable(mgr, i);
         }
 
         fimd_commit(mgr);
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index c104d0c9b385..aa259b0a873a 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -2090,6 +2090,11 @@ out:
 
 static void hdmi_dpms(struct exynos_drm_display *display, int mode)
 {
+        struct hdmi_context *hdata = display->ctx;
+        struct drm_encoder *encoder = hdata->encoder;
+        struct drm_crtc *crtc = encoder->crtc;
+        struct drm_crtc_helper_funcs *funcs = NULL;
+
         DRM_DEBUG_KMS("mode %d\n", mode);
 
         switch (mode) {
@@ -2099,6 +2104,20 @@ static void hdmi_dpms(struct exynos_drm_display *display, int mode)
         case DRM_MODE_DPMS_STANDBY:
         case DRM_MODE_DPMS_SUSPEND:
         case DRM_MODE_DPMS_OFF:
+                /*
+                 * The SFRs of VP and Mixer are updated by Vertical Sync of
+                 * Timing generator which is a part of HDMI so the sequence
+                 * to disable TV Subsystem should be as following,
+                 *      VP -> Mixer -> HDMI
+                 *
+                 * Below codes will try to disable Mixer and VP(if used)
+                 * prior to disabling HDMI.
+                 */
+                if (crtc)
+                        funcs = crtc->helper_private;
+                if (funcs && funcs->dpms)
+                        (*funcs->dpms)(crtc, mode);
+
                 hdmi_poweroff(display);
                 break;
         default:
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 4c5aed7e54c8..7529946d0a74 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -377,6 +377,20 @@ static void mixer_run(struct mixer_context *ctx)
         mixer_regs_dump(ctx);
 }
 
+static void mixer_stop(struct mixer_context *ctx)
+{
+        struct mixer_resources *res = &ctx->mixer_res;
+        int timeout = 20;
+
+        mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN);
+
+        while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
+                        --timeout)
+                usleep_range(10000, 12000);
+
+        mixer_regs_dump(ctx);
+}
+
 static void vp_video_buffer(struct mixer_context *ctx, int win)
 {
         struct mixer_resources *res = &ctx->mixer_res;
@@ -497,13 +511,8 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
 static void mixer_layer_update(struct mixer_context *ctx)
 {
         struct mixer_resources *res = &ctx->mixer_res;
-        u32 val;
-
-        val = mixer_reg_read(res, MXR_CFG);
 
-        /* allow one update per vsync only */
-        if (!(val & MXR_CFG_LAYER_UPDATE_COUNT_MASK))
-                mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
+        mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
 }
 
 static void mixer_graph_buffer(struct mixer_context *ctx, int win)
@@ -1010,6 +1019,8 @@ static void mixer_wait_for_vblank(struct exynos_drm_manager *mgr)
         }
         mutex_unlock(&mixer_ctx->mixer_mutex);
 
+        drm_vblank_get(mgr->crtc->dev, mixer_ctx->pipe);
+
         atomic_set(&mixer_ctx->wait_vsync_event, 1);
 
         /*
@@ -1020,6 +1031,8 @@ static void mixer_wait_for_vblank(struct exynos_drm_manager *mgr)
                                 !atomic_read(&mixer_ctx->wait_vsync_event),
                                 HZ/20))
                 DRM_DEBUG_KMS("vblank wait timed out.\n");
+
+        drm_vblank_put(mgr->crtc->dev, mixer_ctx->pipe);
 }
 
 static void mixer_window_suspend(struct exynos_drm_manager *mgr)
@@ -1061,7 +1074,7 @@ static void mixer_poweron(struct exynos_drm_manager *mgr)
                 mutex_unlock(&ctx->mixer_mutex);
                 return;
         }
-        ctx->powered = true;
+
         mutex_unlock(&ctx->mixer_mutex);
 
         pm_runtime_get_sync(ctx->dev);
@@ -1072,6 +1085,12 @@ static void mixer_poweron(struct exynos_drm_manager *mgr)
                 clk_prepare_enable(res->sclk_mixer);
         }
 
+        mutex_lock(&ctx->mixer_mutex);
+        ctx->powered = true;
+        mutex_unlock(&ctx->mixer_mutex);
+
+        mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
+
         mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
         mixer_win_reset(ctx);
 
@@ -1084,14 +1103,21 @@ static void mixer_poweroff(struct exynos_drm_manager *mgr)
         struct mixer_resources *res = &ctx->mixer_res;
 
         mutex_lock(&ctx->mixer_mutex);
-        if (!ctx->powered)
-                goto out;
+        if (!ctx->powered) {
+                mutex_unlock(&ctx->mixer_mutex);
+                return;
+        }
         mutex_unlock(&ctx->mixer_mutex);
 
+        mixer_stop(ctx);
         mixer_window_suspend(mgr);
 
         ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
 
+        mutex_lock(&ctx->mixer_mutex);
+        ctx->powered = false;
+        mutex_unlock(&ctx->mixer_mutex);
+
         clk_disable_unprepare(res->mixer);
         if (ctx->vp_enabled) {
                 clk_disable_unprepare(res->vp);
@@ -1099,12 +1125,6 @@ static void mixer_poweroff(struct exynos_drm_manager *mgr)
         }
 
         pm_runtime_put_sync(ctx->dev);
-
-        mutex_lock(&ctx->mixer_mutex);
-        ctx->powered = false;
-
-out:
-        mutex_unlock(&ctx->mixer_mutex);
 }
 
 static void mixer_dpms(struct exynos_drm_manager *mgr, int mode)
diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h
index 4537026bc385..5f32e1a29411 100644
--- a/drivers/gpu/drm/exynos/regs-mixer.h
+++ b/drivers/gpu/drm/exynos/regs-mixer.h
@@ -78,6 +78,7 @@
 #define MXR_STATUS_BIG_ENDIAN           (1 << 3)
 #define MXR_STATUS_ENDIAN_MASK          (1 << 3)
 #define MXR_STATUS_SYNC_ENABLE          (1 << 2)
+#define MXR_STATUS_REG_IDLE             (1 << 1)
 #define MXR_STATUS_REG_RUN              (1 << 0)
 
 /* bits for MXR_CFG */
diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
index 240c331405b9..ac357b02bd35 100644
--- a/drivers/gpu/drm/i2c/tda998x_drv.c
+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
@@ -810,6 +810,12 @@ static int
 tda998x_encoder_mode_valid(struct drm_encoder *encoder,
                           struct drm_display_mode *mode)
 {
+        if (mode->clock > 150000)
+                return MODE_CLOCK_HIGH;
+        if (mode->htotal >= BIT(13))
+                return MODE_BAD_HVALUE;
+        if (mode->vtotal >= BIT(11))
+                return MODE_BAD_VVALUE;
         return MODE_OK;
 }
 
@@ -1048,8 +1054,8 @@ read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk)
                         return i;
                 }
         } else {
-                for (i = 10; i > 0; i--) {
-                        msleep(10);
+                for (i = 100; i > 0; i--) {
+                        msleep(1);
                         ret = reg_read(priv, REG_INT_FLAGS_2);
                         if (ret < 0)
                                 return ret;
@@ -1183,7 +1189,6 @@ static void
 tda998x_encoder_destroy(struct drm_encoder *encoder)
 {
         struct tda998x_priv *priv = to_tda998x_priv(encoder);
-        drm_i2c_encoder_destroy(encoder);
 
         /* disable all IRQs and free the IRQ handler */
         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
@@ -1193,6 +1198,7 @@ tda998x_encoder_destroy(struct drm_encoder *encoder)
 
         if (priv->cec)
                 i2c_unregister_device(priv->cec);
+        drm_i2c_encoder_destroy(encoder);
         kfree(priv);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 601caa88c092..b8c689202c40 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -446,7 +446,9 @@ static int i915_gem_object_info(struct seq_file *m, void* data)
 
                 memset(&stats, 0, sizeof(stats));
                 stats.file_priv = file->driver_priv;
+                spin_lock(&file->table_lock);
                 idr_for_each(&file->object_idr, per_file_stats, &stats);
+                spin_unlock(&file->table_lock);
                 /*
                  * Although we have a valid reference on file->pid, that does
                  * not guarantee that the task_struct who called get_pid() is
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4c22a5b7f4c5..d44344140627 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -36,6 +36,8 @@
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include <linux/pci.h>
+#include <linux/console.h>
+#include <linux/vt.h>
 #include <linux/vgaarb.h>
 #include <linux/acpi.h>
 #include <linux/pnp.h>
@@ -1386,7 +1388,6 @@ cleanup_gem:
         i915_gem_context_fini(dev);
         mutex_unlock(&dev->struct_mutex);
         WARN_ON(dev_priv->mm.aliasing_ppgtt);
-        drm_mm_takedown(&dev_priv->gtt.base.mm);
 cleanup_irq:
         drm_irq_uninstall(dev);
 cleanup_gem_stolen:
@@ -1450,6 +1451,39 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 }
 #endif
 
+#if !defined(CONFIG_VGA_CONSOLE)
+static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
+{
+        return 0;
+}
+#elif !defined(CONFIG_DUMMY_CONSOLE)
+static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
+{
+        return -ENODEV;
+}
+#else
+static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
+{
+        int ret = 0;
+
+        DRM_INFO("Replacing VGA console driver\n");
+
+        console_lock();
+        if (con_is_bound(&vga_con))
+                ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
+        if (ret == 0) {
+                ret = do_unregister_con_driver(&vga_con);
+
+                /* Ignore "already unregistered". */
+                if (ret == -ENODEV)
+                        ret = 0;
+        }
+        console_unlock();
+
+        return ret;
+}
+#endif
+
 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 {
         const struct intel_device_info *info = &dev_priv->info;
@@ -1623,8 +1657,15 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
         if (ret)
                 goto out_regs;
 
-        if (drm_core_check_feature(dev, DRIVER_MODESET))
+        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+                ret = i915_kick_out_vgacon(dev_priv);
+                if (ret) {
+                        DRM_ERROR("failed to remove conflicting VGA console\n");
+                        goto out_gtt;
+                }
+
                 i915_kick_out_firmware_fb(dev_priv);
+        }
 
         pci_set_master(dev->pdev);
 
@@ -1756,8 +1797,6 @@ out_mtrrfree:
         arch_phys_wc_del(dev_priv->gtt.mtrr);
         io_mapping_free(dev_priv->gtt.mappable);
 out_gtt:
-        list_del(&dev_priv->gtt.base.global_link);
-        drm_mm_takedown(&dev_priv->gtt.base.mm);
         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
 out_regs:
         intel_uncore_fini(dev);
@@ -1846,7 +1885,6 @@ int i915_driver_unload(struct drm_device *dev)
                         i915_free_hws(dev);
         }
 
-        list_del(&dev_priv->gtt.base.global_link);
         WARN_ON(!list_empty(&dev_priv->vm_list));
 
         drm_vblank_cleanup(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 49414d30e8d4..374f964323ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -656,6 +656,7 @@ enum intel_sbi_destination {
 #define QUIRK_PIPEA_FORCE (1<<0)
 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
+#define QUIRK_BACKLIGHT_PRESENT (1<<3)
 
 struct intel_fbdev;
 struct intel_fbc_work;
@@ -977,6 +978,8 @@ struct i915_power_well {
         bool always_on;
         /* power well enable/disable usage count */
         int count;
+        /* cached hw enabled state */
+        bool hw_enabled;
         unsigned long domains;
         unsigned long data;
         const struct i915_power_well_ops *ops;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 3ffe308d5893..a5ddf3bce9c3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -598,6 +598,7 @@ static int do_switch(struct intel_engine_cs *ring,
         struct intel_context *from = ring->last_context;
         struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(to);
         u32 hw_flags = 0;
+        bool uninitialized = false;
         int ret, i;
 
         if (from != NULL && ring == &dev_priv->ring[RCS]) {
@@ -696,19 +697,20 @@ static int do_switch(struct intel_engine_cs *ring,
                 i915_gem_context_unreference(from);
         }
 
+        uninitialized = !to->is_initialized && from == NULL;
+        to->is_initialized = true;
+
 done:
         i915_gem_context_reference(to);
         ring->last_context = to;
         to->last_ring = ring;
 
-        if (ring->id == RCS && !to->is_initialized && from == NULL) {
+        if (uninitialized) {
                 ret = i915_gem_render_state_init(ring);
                 if (ret)
                         DRM_ERROR("init render state: %d\n", ret);
         }
 
-        to->is_initialized = true;
-
         return 0;
 
 unpin_out:
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eec820aec022..8b3cde703364 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1992,7 +1992,10 @@ static void gen6_gmch_remove(struct i915_address_space *vm)
 
         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
 
-        drm_mm_takedown(&vm->mm);
+        if (drm_mm_initialized(&vm->mm)) {
+                drm_mm_takedown(&vm->mm);
+                list_del(&vm->global_link);
+        }
         iounmap(gtt->gsm);
         teardown_scratch_page(vm->dev);
 }
@@ -2025,6 +2028,10 @@ static int i915_gmch_probe(struct drm_device *dev,
 
 static void i915_gmch_remove(struct i915_address_space *vm)
 {
+        if (drm_mm_initialized(&vm->mm)) {
+                drm_mm_takedown(&vm->mm);
+                list_del(&vm->global_link);
+        }
         intel_gmch_remove();
 }
 
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 62ef55ba061c..7465ab0fd396 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -74,6 +74,50 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
         if (base == 0)
                 return 0;
 
+        /* make sure we don't clobber the GTT if it's within stolen memory */
+        if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) {
+                struct {
+                        u32 start, end;
+                } stolen[2] = {
+                        { .start = base, .end = base + dev_priv->gtt.stolen_size, },
+                        { .start = base, .end = base + dev_priv->gtt.stolen_size, },
+                };
+                u64 gtt_start, gtt_end;
+
+                gtt_start = I915_READ(PGTBL_CTL);
+                if (IS_GEN4(dev))
+                        gtt_start = (gtt_start & PGTBL_ADDRESS_LO_MASK) |
+                                (gtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
+                else
+                        gtt_start &= PGTBL_ADDRESS_LO_MASK;
+                gtt_end = gtt_start + gtt_total_entries(dev_priv->gtt) * 4;
+
+                if (gtt_start >= stolen[0].start && gtt_start < stolen[0].end)
+                        stolen[0].end = gtt_start;
+                if (gtt_end > stolen[1].start && gtt_end <= stolen[1].end)
+                        stolen[1].start = gtt_end;
+
+                /* pick the larger of the two chunks */
+                if (stolen[0].end - stolen[0].start >
+                    stolen[1].end - stolen[1].start) {
+                        base = stolen[0].start;
+                        dev_priv->gtt.stolen_size = stolen[0].end - stolen[0].start;
+                } else {
+                        base = stolen[1].start;
+                        dev_priv->gtt.stolen_size = stolen[1].end - stolen[1].start;
+                }
+
+                if (stolen[0].start != stolen[1].start ||
+                    stolen[0].end != stolen[1].end) {
+                        DRM_DEBUG_KMS("GTT within stolen memory at 0x%llx-0x%llx\n",
+                                      (unsigned long long) gtt_start,
+                                      (unsigned long long) gtt_end - 1);
+                        DRM_DEBUG_KMS("Stolen memory adjusted to 0x%x-0x%x\n",
+                                      base, base + (u32) dev_priv->gtt.stolen_size - 1);
+                }
+        }
+
+
         /* Verify that nothing else uses this physical address. Stolen
          * memory should be reserved by the BIOS and hidden from the
          * kernel. So if the region is already marked as busy, something
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 87ec60e181a7..66cf41765bf9 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -888,6 +888,8 @@ static void i915_gem_record_rings(struct drm_device *dev,
         for (i = 0; i < I915_NUM_RINGS; i++) {
                 struct intel_engine_cs *ring = &dev_priv->ring[i];
 
+                error->ring[i].pid = -1;
+
                 if (ring->dev == NULL)
                         continue;
 
@@ -895,7 +897,6 @@ static void i915_gem_record_rings(struct drm_device *dev,
 
                 i915_record_ring_state(dev, ring, &error->ring[i]);
 
-                error->ring[i].pid = -1;
                 request = i915_gem_find_active_request(ring);
                 if (request) {
                         /* We need to copy these to an anonymous buffer
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6f8017a7e937..267f069765ad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2847,10 +2847,14 @@ static int semaphore_passed(struct intel_engine_cs *ring)
         struct intel_engine_cs *signaller;
         u32 seqno, ctl;
 
-        ring->hangcheck.deadlock = true;
+        ring->hangcheck.deadlock++;
 
         signaller = semaphore_waits_for(ring, &seqno);
-        if (signaller == NULL || signaller->hangcheck.deadlock)
+        if (signaller == NULL)
+                return -1;
+
+        /* Prevent pathological recursion due to driver bugs */
+        if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
                 return -1;
 
         /* cursory check for an unkickable deadlock */
@@ -2858,7 +2862,13 @@ static int semaphore_passed(struct intel_engine_cs *ring)
         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
                 return -1;
 
-        return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
+        if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
+                return 1;
+
+        if (signaller->hangcheck.deadlock)
+                return -1;
+
+        return 0;
 }
 
 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
@@ -2867,7 +2877,7 @@ static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
         int i;
 
         for_each_ring(ring, dev_priv, i)
-                ring->hangcheck.deadlock = false;
+                ring->hangcheck.deadlock = 0;
 }
 
 static enum intel_ring_hangcheck_action
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e691b30b2817..a5bab61bfc00 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -942,6 +942,9 @@ enum punit_power_well {
 /*
  * Instruction and interrupt control regs
  */
+#define PGTBL_CTL       0x02020
+#define   PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
+#define   PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
 #define PGTBL_ER        0x02024
 #define RENDER_RING_BASE        0x02000
 #define BSD_RING_BASE           0x04000
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 1ee98f121a00..827498e081df 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -315,9 +315,6 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
         const struct bdb_lfp_backlight_data *backlight_data;
         const struct bdb_lfp_backlight_data_entry *entry;
 
-        /* Err to enabling backlight if no backlight block. */
-        dev_priv->vbt.backlight.present = true;
-
         backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
         if (!backlight_data)
                 return;
@@ -1088,6 +1085,9 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
 
         dev_priv->vbt.crt_ddc_pin = GMBUS_PORT_VGADDC;
 
+        /* Default to having backlight */
+        dev_priv->vbt.backlight.present = true;
+
         /* LFP panel data */
         dev_priv->vbt.lvds_dither = 1;
         dev_priv->vbt.lvds_vbt = 0;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index efd3cf50cb0f..e27e7804c0b9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2087,6 +2087,7 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
                                           enum plane plane, enum pipe pipe)
 {
+        struct drm_device *dev = dev_priv->dev;
         struct intel_crtc *intel_crtc =
                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
         int reg;
@@ -2106,6 +2107,14 @@ static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
 
         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
         intel_flush_primary_plane(dev_priv, plane);
+
+        /*
+         * BDW signals flip done immediately if the plane
+         * is disabled, even if the plane enable is already
+         * armed to occur at the next vblank :(
+         */
+        if (IS_BROADWELL(dev))
+                intel_wait_for_vblank(dev, intel_crtc->pipe);
 }
 
 /**
@@ -4564,7 +4573,10 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
         if (intel_crtc->active)
                 return;
 
-        vlv_prepare_pll(intel_crtc);
+        is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
+
+        if (!is_dsi && !IS_CHERRYVIEW(dev))
+                vlv_prepare_pll(intel_crtc);
 
         /* Set up the display plane register */
         dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4598,8 +4610,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
                 if (encoder->pre_pll_enable)
                         encoder->pre_pll_enable(encoder);
 
-        is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
-
         if (!is_dsi) {
                 if (IS_CHERRYVIEW(dev))
                         chv_enable_pll(intel_crtc);
@@ -11087,6 +11097,22 @@ const char *intel_output_name(int output)
         return names[output];
 }
 
+static bool intel_crt_present(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        if (IS_ULT(dev))
+                return false;
+
+        if (IS_CHERRYVIEW(dev))
+                return false;
+
+        if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
+                return false;
+
+        return true;
+}
+
 static void intel_setup_outputs(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -11095,7 +11121,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 
         intel_lvds_init(dev);
 
-        if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
+        if (intel_crt_present(dev))
                 intel_crt_init(dev);
 
         if (HAS_DDI(dev)) {
@@ -11565,6 +11591,14 @@ static void quirk_invert_brightness(struct drm_device *dev)
         DRM_INFO("applying inverted panel brightness quirk\n");
 }
 
+/* Some VBT's incorrectly indicate no backlight is present */
+static void quirk_backlight_present(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
+        DRM_INFO("applying backlight present quirk\n");
+}
+
 struct intel_quirk {
         int device;
         int subsystem_vendor;
@@ -11633,6 +11667,12 @@ static struct intel_quirk intel_quirks[] = {
 
         /* Acer Aspire 5336 */
         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
+
+        /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
+        { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
+
+        /* Toshiba CB35 Chromebook (Celeron 2955U) */
+        { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
 };
 
 static void intel_init_quirks(struct drm_device *dev)
@@ -12411,8 +12451,8 @@ intel_display_capture_error_state(struct drm_device *dev)
 
         for_each_pipe(i) {
                 error->pipe[i].power_domain_on =
-                        intel_display_power_enabled_sw(dev_priv,
-                                                       POWER_DOMAIN_PIPE(i));
+                        intel_display_power_enabled_unlocked(dev_priv,
+                                                           POWER_DOMAIN_PIPE(i));
                 if (!error->pipe[i].power_domain_on)
                         continue;
 
@@ -12447,7 +12487,7 @@ intel_display_capture_error_state(struct drm_device *dev)
                 enum transcoder cpu_transcoder = transcoders[i];
 
                 error->transcoder[i].power_domain_on =
-                        intel_display_power_enabled_sw(dev_priv,
+                        intel_display_power_enabled_unlocked(dev_priv,
                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
                 if (!error->transcoder[i].power_domain_on)
                         continue;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 52fda950fd2a..075170d1844f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -28,6 +28,8 @@
 #include <linux/i2c.h>
 #include <linux/slab.h>
 #include <linux/export.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
@@ -336,6 +338,37 @@ static u32 _pp_stat_reg(struct intel_dp *intel_dp)
                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 }
 
+/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
+   This function only applicable when panel PM state is not to be tracked */
+static int edp_notify_handler(struct notifier_block *this, unsigned long code,
+                              void *unused)
+{
+        struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
+                                                 edp_notifier);
+        struct drm_device *dev = intel_dp_to_dev(intel_dp);
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 pp_div;
+        u32 pp_ctrl_reg, pp_div_reg;
+        enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+
+        if (!is_edp(intel_dp) || code != SYS_RESTART)
+                return 0;
+
+        if (IS_VALLEYVIEW(dev)) {
+                pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
+                pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
+                pp_div = I915_READ(pp_div_reg);
+                pp_div &= PP_REFERENCE_DIVIDER_MASK;
+
+                /* 0x1F write to PP_DIV_REG sets max cycle delay */
+                I915_WRITE(pp_div_reg, pp_div | 0x1F);
+                I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+                msleep(intel_dp->panel_power_cycle_delay);
+        }
+
+        return 0;
+}
+
 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -3707,6 +3740,10 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
                 edp_panel_vdd_off_sync(intel_dp);
                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
+                if (intel_dp->edp_notifier.notifier_call) {
+                        unregister_reboot_notifier(&intel_dp->edp_notifier);
+                        intel_dp->edp_notifier.notifier_call = NULL;
+                }
         }
         kfree(intel_dig_port);
 }
@@ -4184,6 +4221,11 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
         }
         mutex_unlock(&dev->mode_config.mutex);
 
+        if (IS_VALLEYVIEW(dev)) {
+                intel_dp->edp_notifier.notifier_call = edp_notify_handler;
+                register_reboot_notifier(&intel_dp->edp_notifier);
+        }
+
         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
         intel_panel_setup_backlight(connector);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bda0ae3d80cc..f67340ed2c12 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -538,6 +538,8 @@ struct intel_dp {
         unsigned long last_power_on;
         unsigned long last_backlight_off;
         bool psr_setup_done;
+        struct notifier_block edp_notifier;
+
         bool use_tps3;
         struct intel_connector *attached_connector;
 
@@ -950,8 +952,8 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_remove(struct drm_i915_private *);
 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
                                  enum intel_display_power_domain domain);
-bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
-                                    enum intel_display_power_domain domain);
+bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
+                                          enum intel_display_power_domain domain);
 void intel_display_power_get(struct drm_i915_private *dev_priv,
                              enum intel_display_power_domain domain);
 void intel_display_power_put(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 02f99d768d49..3fd082933c87 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -117,17 +117,18 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
         /* bandgap reset is needed after everytime we do power gate */
         band_gap_reset(dev_priv);
 
+        I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
+        usleep_range(2500, 3000);
+
         val = I915_READ(MIPI_PORT_CTRL(pipe));
         I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
         usleep_range(1000, 1500);
-        I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
-        usleep_range(2000, 2500);
-        I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
-        usleep_range(2000, 2500);
-        I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
-        usleep_range(2000, 2500);
+
+        I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
+        usleep_range(2500, 3000);
+
         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
-        usleep_range(2000, 2500);
+        usleep_range(2500, 3000);
 }
 
 static void intel_dsi_enable(struct intel_encoder *encoder)
@@ -271,23 +272,23 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 
         DRM_DEBUG_KMS("\n");
 
-        I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
+        I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
         usleep_range(2000, 2500);
 
-        I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
+        I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
         usleep_range(2000, 2500);
 
-        I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
+        I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
         usleep_range(2000, 2500);
 
-        val = I915_READ(MIPI_PORT_CTRL(pipe));
-        I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
-        usleep_range(1000, 1500);
-
         if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
                                         == 0x00000), 30))
                 DRM_ERROR("DSI LP not going Low\n");
 
+        val = I915_READ(MIPI_PORT_CTRL(pipe));
+        I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
+        usleep_range(1000, 1500);
+
         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
         usleep_range(2000, 2500);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 3eeb21b9fddf..933c86305237 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -404,12 +404,6 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
         else
                 cmd |= DPI_LP_MODE;
 
-        /* DPI virtual channel?! */
-
-        mask = DPI_FIFO_EMPTY;
-        if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
-                DRM_ERROR("Timeout waiting for DPI FIFO empty.\n");
-
         /* clear bit */
         I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);
 
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 2e2c71fcc9ed..4f6b53998d79 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -403,6 +403,15 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
 
         DRM_DEBUG_DRIVER("bclp = 0x%08x\n", bclp);
 
+        /*
+         * If the acpi_video interface is not supposed to be used, don't
+         * bother processing backlight level change requests from firmware.
+         */
+        if (!acpi_video_verify_backlight_support()) {
+                DRM_DEBUG_KMS("opregion backlight request ignored\n");
+                return 0;
+        }
+
         if (!(bclp & ASLE_BCLP_VALID))
                 return ASLC_BACKLIGHT_FAILED;
 
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 5e6c888b4928..628cd8938274 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -798,9 +798,6 @@ static void i965_enable_backlight(struct intel_connector *connector)
         ctl = freq << 16;
         I915_WRITE(BLC_PWM_CTL, ctl);
 
-        /* XXX: combine this into above write? */
-        intel_panel_actually_set_backlight(connector, panel->backlight.level);
-
         ctl2 = BLM_PIPE(pipe);
         if (panel->backlight.combination_mode)
                 ctl2 |= BLM_COMBINATION_MODE;
@@ -809,6 +806,8 @@ static void i965_enable_backlight(struct intel_connector *connector)
         I915_WRITE(BLC_PWM_CTL2, ctl2);
         POSTING_READ(BLC_PWM_CTL2);
         I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);
+
+        intel_panel_actually_set_backlight(connector, panel->backlight.level);
 }
 
 static void vlv_enable_backlight(struct intel_connector *connector)
@@ -1119,8 +1118,12 @@ int intel_panel_setup_backlight(struct drm_connector *connector)
         int ret;
 
         if (!dev_priv->vbt.backlight.present) {
-                DRM_DEBUG_KMS("native backlight control not available per VBT\n");
-                return 0;
+                if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
+                        DRM_DEBUG_KMS("no backlight present per VBT, but present per quirk\n");
+                } else {
+                        DRM_DEBUG_KMS("no backlight present per VBT\n");
+                        return 0;
+                }
         }
 
         /* set level and max in panel struct */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1e53abec1b5..ee72807069e4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -511,8 +511,7 @@ void intel_update_fbc(struct drm_device *dev)
         obj = intel_fb->obj;
         adjusted_mode = &intel_crtc->config.adjusted_mode;
 
-        if (i915.enable_fbc < 0 &&
-            INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
+        if (i915.enable_fbc < 0) {
                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
                         DRM_DEBUG_KMS("disabled per chip default\n");
                 goto out_disable;
@@ -3210,6 +3209,14 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
 */
 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
 {
+        struct drm_device *dev = dev_priv->dev;
+
+        /* Latest VLV doesn't need to force the gfx clock */
+        if (dev->pdev->revision >= 0xd) {
+                valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
+                return;
+        }
+
         /*
          * When we are idle.  Drop to min voltage state.
          */
@@ -3506,15 +3513,11 @@ static void gen8_enable_rps(struct drm_device *dev)
 
         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 
-        /* WaDisablePwrmtrEvent:chv (pre-production hw) */
-        I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
-        I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
-
         /* 5: Enable RPS */
         I915_WRITE(GEN6_RP_CONTROL,
                    GEN6_RP_MEDIA_TURBO |
                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
-                   GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
+                   GEN6_RP_MEDIA_IS_GFX |
                    GEN6_RP_ENABLE |
                    GEN6_RP_UP_BUSY_AVG |
                    GEN6_RP_DOWN_IDLE_AVG);
@@ -5608,8 +5611,8 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 }
 
-bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
-                                    enum intel_display_power_domain domain)
+bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
+                                          enum intel_display_power_domain domain)
 {
         struct i915_power_domains *power_domains;
         struct i915_power_well *power_well;
@@ -5620,16 +5623,19 @@ bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
                 return false;
 
         power_domains = &dev_priv->power_domains;
+
         is_enabled = true;
+
         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
                 if (power_well->always_on)
                         continue;
 
-                if (!power_well->count) {
+                if (!power_well->hw_enabled) {
                         is_enabled = false;
                         break;
                 }
         }
+
         return is_enabled;
 }
 
@@ -5637,30 +5643,15 @@ bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
                                  enum intel_display_power_domain domain)
 {
         struct i915_power_domains *power_domains;
-        struct i915_power_well *power_well;
-        bool is_enabled;
-        int i;
-
-        if (dev_priv->pm.suspended)
-                return false;
+        bool ret;
 
         power_domains = &dev_priv->power_domains;
 
-        is_enabled = true;
-
         mutex_lock(&power_domains->lock);
-        for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
-                if (power_well->always_on)
-                        continue;
-
-                if (!power_well->ops->is_enabled(dev_priv, power_well)) {
-                        is_enabled = false;
-                        break;
-                }
-        }
+        ret = intel_display_power_enabled_unlocked(dev_priv, domain);
         mutex_unlock(&power_domains->lock);
 
-        return is_enabled;
+        return ret;
 }
 
 /*
@@ -5981,6 +5972,7 @@ void intel_display_power_get(struct drm_i915_private *dev_priv,
                 if (!power_well->count++) {
                         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
                         power_well->ops->enable(dev_priv, power_well);
+                        power_well->hw_enabled = true;
                 }
 
                 check_power_well_state(dev_priv, power_well);
@@ -6010,6 +6002,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 
                 if (!--power_well->count && i915.disable_power_well) {
                         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
+                        power_well->hw_enabled = false;
                         power_well->ops->disable(dev_priv, power_well);
                 }
 
@@ -6024,33 +6017,56 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 static struct i915_power_domains *hsw_pwr;
 
 /* Display audio driver power well request */
-void i915_request_power_well(void)
+int i915_request_power_well(void)
 {
         struct drm_i915_private *dev_priv;
 
-        if (WARN_ON(!hsw_pwr))
-                return;
+        if (!hsw_pwr)
+                return -ENODEV;
 
         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
                                 power_domains);
         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(i915_request_power_well);
 
 /* Display audio driver power well release */
-void i915_release_power_well(void)
+int i915_release_power_well(void)
 {
         struct drm_i915_private *dev_priv;
 
-        if (WARN_ON(!hsw_pwr))
-                return;
+        if (!hsw_pwr)
+                return -ENODEV;
 
         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
                                 power_domains);
         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(i915_release_power_well);
 
+/*
+ * Private interface for the audio driver to get CDCLK in kHz.
+ *
+ * Caller must request power well using i915_request_power_well() prior to
+ * making the call.
+ */
+int i915_get_cdclk_freq(void)
+{
+        struct drm_i915_private *dev_priv;
+
+        if (!hsw_pwr)
+                return -ENODEV;
+
+        dev_priv = container_of(hsw_pwr, struct drm_i915_private,
+                                power_domains);
+
+        return intel_ddi_get_cdclk_freq(dev_priv);
+}
+EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
+
+
 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
 
 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
@@ -6270,8 +6286,11 @@ static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
         int i;
 
         mutex_lock(&power_domains->lock);
-        for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
+        for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
                 power_well->ops->sync_hw(dev_priv, power_well);
+                power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
+                                                                     power_well);
+        }
         mutex_unlock(&power_domains->lock);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 910c83cf7d44..e72017bdcd7f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -55,7 +55,7 @@ struct intel_ring_hangcheck {
         u32 seqno;
         int score;
         enum intel_ring_hangcheck_action action;
-        bool deadlock;
+        int deadlock;
 };
 
 struct intel_ringbuffer {
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 6a4d5bc17697..20375cc7f82d 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1385,7 +1385,9 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
                          >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
         }
 
-        dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier;
+        dotclock = pipe_config->port_clock;
+        if (pipe_config->pixel_multiplier)
+                dotclock /= pipe_config->pixel_multiplier;
 
         if (HAS_PCH_SPLIT(dev))
                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 1b66ddcdfb33..9a17b4e92ef4 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -691,6 +691,14 @@ intel_post_enable_primary(struct drm_crtc *crtc)
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
         /*
+         * BDW signals flip done immediately if the plane
+         * is disabled, even if the plane enable is already
+         * armed to occur at the next vblank :(
+         */
+        if (IS_BROADWELL(dev))
+                intel_wait_for_vblank(dev, intel_crtc->pipe);
+
+        /*
          * FIXME IPS should be fine as long as one plane is
          * enabled, but in practice it seems to have problems
          * when going from primary only to sprite only and vice
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 79cba593df0d..4f6fef7ac069 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -320,7 +320,8 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long irqflags;
 
-        del_timer_sync(&dev_priv->uncore.force_wake_timer);
+        if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
+                gen6_force_wake_timer((unsigned long)dev_priv);
 
         /* Hold uncore.lock across reset to prevent any register access
          * with forcewake not set correctly
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index ae750f6928c1..7f7aadef8a82 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -277,6 +277,7 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data)
         static const char *hpd_reg_names[] = {"hpd-gdsc", "hpd-5v"};
         static const char *pwr_reg_names[] = {"core-vdda", "core-vcc"};
         static const char *hpd_clk_names[] = {"iface_clk", "core_clk", "mdp_core_clk"};
+        static unsigned long hpd_clk_freq[] = {0, 19200000, 0};
         static const char *pwr_clk_names[] = {"extp_clk", "alt_iface_clk"};
 
         config.phy_init      = hdmi_phy_8x74_init;
@@ -286,6 +287,7 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data)
         config.pwr_reg_names = pwr_reg_names;
         config.pwr_reg_cnt   = ARRAY_SIZE(pwr_reg_names);
         config.hpd_clk_names = hpd_clk_names;
+        config.hpd_freq      = hpd_clk_freq;
         config.hpd_clk_cnt   = ARRAY_SIZE(hpd_clk_names);
         config.pwr_clk_names = pwr_clk_names;
         config.pwr_clk_cnt   = ARRAY_SIZE(pwr_clk_names);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 9fafee6a3e43..9d7723c6528a 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -87,6 +87,7 @@ struct hdmi_platform_config {
 
         /* clks that need to be on for hpd: */
         const char **hpd_clk_names;
+        const long unsigned *hpd_freq;
         int hpd_clk_cnt;
 
         /* clks that need to be on for screen pwr (ie pixel clk): */
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index e56a6196867c..28f7e3ec6c28 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -127,6 +127,14 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
         }
 
         for (i = 0; i < config->hpd_clk_cnt; i++) {
+                if (config->hpd_freq && config->hpd_freq[i]) {
+                        ret = clk_set_rate(hdmi->hpd_clks[i],
+                                        config->hpd_freq[i]);
+                        if (ret)
+                                dev_warn(dev->dev, "failed to set clk %s (%d)\n",
+                                                config->hpd_clk_names[i], ret);
+                }
+
                 ret = clk_prepare_enable(hdmi->hpd_clks[i]);
                 if (ret) {
                         dev_err(dev->dev, "failed to enable hpd clk: %s (%d)\n",
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 42caf7fcb0b9..71510ee26e96 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -20,6 +20,10 @@
 #include "msm_mmu.h"
 #include "mdp5_kms.h"
 
+static const char *iommu_ports[] = {
+                "mdp_0",
+};
+
 static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev);
 
 static int mdp5_hw_init(struct msm_kms *kms)
@@ -104,6 +108,12 @@ static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file)
 static void mdp5_destroy(struct msm_kms *kms)
 {
         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
+        struct msm_mmu *mmu = mdp5_kms->mmu;
+
+        if (mmu) {
+                mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
+                mmu->funcs->destroy(mmu);
+        }
         kfree(mdp5_kms);
 }
 
@@ -216,10 +226,6 @@ fail:
         return ret;
 }
 
-static const char *iommu_ports[] = {
-                "mdp_0",
-};
-
 static int get_clk(struct platform_device *pdev, struct clk **clkp,
                 const char *name)
 {
@@ -317,17 +323,23 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
                 mmu = msm_iommu_new(dev, config->iommu);
                 if (IS_ERR(mmu)) {
                         ret = PTR_ERR(mmu);
+                        dev_err(dev->dev, "failed to init iommu: %d\n", ret);
                         goto fail;
                 }
+
                 ret = mmu->funcs->attach(mmu, iommu_ports,
                                 ARRAY_SIZE(iommu_ports));
-                if (ret)
+                if (ret) {
+                        dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
+                        mmu->funcs->destroy(mmu);
                         goto fail;
+                }
         } else {
                 dev_info(dev->dev, "no iommu, fallback to phys "
                                 "contig buffers for scanout\n");
                 mmu = NULL;
         }
+        mdp5_kms->mmu = mmu;
 
         mdp5_kms->id = msm_register_mmu(dev, mmu);
         if (mdp5_kms->id < 0) {
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
index c8b1a2522c25..6e981b692d1d 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
@@ -33,6 +33,7 @@ struct mdp5_kms {
 
         /* mapper-id used to request GEM buffer mapped for scanout: */
         int id;
+        struct msm_mmu *mmu;
 
         /* for tracking smp allocation amongst pipes: */
         mdp5_smp_state_t smp_state;
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 0d2562fb681e..9a5d87db5c23 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -159,7 +159,7 @@ static int msm_unload(struct drm_device *dev)
 static int get_mdp_ver(struct platform_device *pdev)
 {
 #ifdef CONFIG_OF
-        const static struct of_device_id match_types[] = { {
+        static const struct of_device_id match_types[] = { {
                 .compatible = "qcom,mdss_mdp",
                 .data   = (void *)5,
         }, {
diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c
index a752ab83b810..5107fc4826bc 100644
--- a/drivers/gpu/drm/msm/msm_fbdev.c
+++ b/drivers/gpu/drm/msm/msm_fbdev.c
@@ -59,7 +59,7 @@ static int msm_fbdev_create(struct drm_fb_helper *helper,
         struct drm_framebuffer *fb = NULL;
         struct fb_info *fbi = NULL;
         struct drm_mode_fb_cmd2 mode_cmd = {0};
-        dma_addr_t paddr;
+        uint32_t paddr;
         int ret, size;
 
         sizes->surface_bpp = 32;
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index bb8026daebc9..690d7e7b6d1e 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -278,6 +278,7 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
                 uint32_t *iova)
 {
         struct msm_gem_object *msm_obj = to_msm_bo(obj);
+        struct drm_device *dev = obj->dev;
         int ret = 0;
 
         if (!msm_obj->domain[id].iova) {
@@ -285,6 +286,11 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
                 struct msm_mmu *mmu = priv->mmus[id];
                 struct page **pages = get_pages(obj);
 
+                if (!mmu) {
+                        dev_err(dev->dev, "null MMU pointer\n");
+                        return -EINVAL;
+                }
+
                 if (IS_ERR(pages))
                         return PTR_ERR(pages);
 
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index 92b745986231..4b2ad9181edf 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -28,7 +28,7 @@ static int msm_fault_handler(struct iommu_domain *iommu, struct device *dev,
                 unsigned long iova, int flags, void *arg)
 {
         DBG("*** fault: iova=%08lx, flags=%d", iova, flags);
-        return 0;
+        return -ENOSYS;
 }
 
 static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt)
@@ -40,8 +40,10 @@ static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt)
         for (i = 0; i < cnt; i++) {
                 struct device *msm_iommu_get_ctx(const char *ctx_name);
                 struct device *ctx = msm_iommu_get_ctx(names[i]);
-                if (IS_ERR_OR_NULL(ctx))
+                if (IS_ERR_OR_NULL(ctx)) {
+                        dev_warn(dev->dev, "couldn't get %s context", names[i]);
                         continue;
+                }
                 ret = iommu_attach_device(iommu->domain, ctx);
                 if (ret) {
                         dev_warn(dev->dev, "could not attach iommu to %s", names[i]);
@@ -52,6 +54,20 @@ static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt)
         return 0;
 }
 
+static void msm_iommu_detach(struct msm_mmu *mmu, const char **names, int cnt)
+{
+        struct msm_iommu *iommu = to_msm_iommu(mmu);
+        int i;
+
+        for (i = 0; i < cnt; i++) {
+                struct device *msm_iommu_get_ctx(const char *ctx_name);
+                struct device *ctx = msm_iommu_get_ctx(names[i]);
+                if (IS_ERR_OR_NULL(ctx))
+                        continue;
+                iommu_detach_device(iommu->domain, ctx);
+        }
+}
+
 static int msm_iommu_map(struct msm_mmu *mmu, uint32_t iova,
                 struct sg_table *sgt, unsigned len, int prot)
 {
@@ -110,7 +126,7 @@ static int msm_iommu_unmap(struct msm_mmu *mmu, uint32_t iova,
 
                 VERB("unmap[%d]: %08x(%x)", i, iova, bytes);
 
-                BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE));
+                BUG_ON(!PAGE_ALIGNED(bytes));
 
                 da += bytes;
         }
@@ -127,6 +143,7 @@ static void msm_iommu_destroy(struct msm_mmu *mmu)
 
 static const struct msm_mmu_funcs funcs = {
                 .attach = msm_iommu_attach,
+                .detach = msm_iommu_detach,
                 .map = msm_iommu_map,
                 .unmap = msm_iommu_unmap,
                 .destroy = msm_iommu_destroy,
diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h
index 030324482b4a..21da6d154f71 100644
--- a/drivers/gpu/drm/msm/msm_mmu.h
+++ b/drivers/gpu/drm/msm/msm_mmu.h
@@ -22,6 +22,7 @@
 
 struct msm_mmu_funcs {
         int (*attach)(struct msm_mmu *mmu, const char **names, int cnt);
+        void (*detach)(struct msm_mmu *mmu, const char **names, int cnt);
         int (*map)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt,
                         unsigned len, int prot);
         int (*unmap)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt,
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 2b6156d0e4b5..8b307e143632 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -140,6 +140,7 @@ nouveau-y += core/subdev/i2c/nv4e.o
 nouveau-y += core/subdev/i2c/nv50.o
 nouveau-y += core/subdev/i2c/nv94.o
 nouveau-y += core/subdev/i2c/nvd0.o
+nouveau-y += core/subdev/i2c/gf117.o
 nouveau-y += core/subdev/i2c/nve0.o
 nouveau-y += core/subdev/ibus/nvc0.o
 nouveau-y += core/subdev/ibus/nve0.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index f199957995fa..8d55ed633b19 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -314,7 +314,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->cname = "GF117";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nvd0_gpio_oclass;
-                device->oclass[NVDEV_SUBDEV_I2C    ] =  nvd0_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_I2C    ] =  gf117_i2c_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/base.c b/drivers/gpu/drm/nouveau/core/engine/disp/base.c
index c41f656abe64..9c38c5e40500 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/base.c
@@ -99,8 +99,10 @@ _nouveau_disp_dtor(struct nouveau_object *object)
 
         nouveau_event_destroy(&disp->vblank);
 
-        list_for_each_entry_safe(outp, outt, &disp->outp, head) {
-                nouveau_object_ref(NULL, (struct nouveau_object **)&outp);
+        if (disp->outp.next) {
+                list_for_each_entry_safe(outp, outt, &disp->outp, head) {
+                        nouveau_object_ref(NULL, (struct nouveau_object **)&outp);
+                }
         }
 
         nouveau_engine_destroy(&disp->base);
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
index 39562d48101d..5a5b59b21130 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
@@ -241,7 +241,9 @@ dp_link_train_eq(struct dp_state *dp)
                 dp_set_training_pattern(dp, 2);
 
         do {
-                if (dp_link_train_update(dp, dp->pc2, 400))
+                if ((tries &&
+                    dp_link_train_commit(dp, dp->pc2)) ||
+                    dp_link_train_update(dp, dp->pc2, 400))
                         break;
 
                 eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
@@ -253,9 +255,6 @@ dp_link_train_eq(struct dp_state *dp)
                             !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
                                 eq_done = false;
                 }
-
-                if (dp_link_train_commit(dp, dp->pc2))
-                        break;
         } while (!eq_done && cr_done && ++tries <= 5);
 
         return eq_done ? 0 : -1;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 1e85f36c705f..2283c442a10d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -1270,7 +1270,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf)
         i--;
 
         outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1);
-        if (!data)
+        if (!outp)
                 return NULL;
 
         if (outp->info.location == 0) {
@@ -1516,11 +1516,11 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
                 }
 
                 switch ((ctrl & 0x000f0000) >> 16) {
-                case 6: datarate = pclk * 30 / 8; break;
-                case 5: datarate = pclk * 24 / 8; break;
+                case 6: datarate = pclk * 30; break;
+                case 5: datarate = pclk * 24; break;
                 case 2:
                 default:
-                        datarate = pclk * 18 / 8;
+                        datarate = pclk * 18;
                         break;
                 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index 48aa38a87e3f..fa30d8196f35 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -1159,11 +1159,11 @@ nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
         if (outp->info.type == DCB_OUTPUT_DP) {
                 u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300));
                 switch ((sync & 0x000003c0) >> 6) {
-                case 6: pclk = pclk * 30 / 8; break;
-                case 5: pclk = pclk * 24 / 8; break;
+                case 6: pclk = pclk * 30; break;
+                case 5: pclk = pclk * 24; break;
                 case 2:
                 default:
-                        pclk = pclk * 18 / 8;
+                        pclk = pclk * 18;
                         break;
                 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c
index 52c299c3d300..eb2d7789555d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c
@@ -34,7 +34,7 @@ nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait)
         struct nvkm_output_dp *outp = (void *)base;
         bool retrain = true;
         u8 link[2], stat[3];
-        u32 rate;
+        u32 linkrate;
         int ret, i;
 
         /* check that the link is trained at a high enough rate */
@@ -44,8 +44,10 @@ nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait)
                 goto done;
         }
 
-        rate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET);
-        if (rate < ((datarate / 8) * 10)) {
+        linkrate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET);
+        linkrate = (linkrate * 8) / 10; /* 8B/10B coding overhead */
+        datarate = (datarate + 9) / 10; /* -> decakilobits */
+        if (linkrate < datarate) {
                 DBG("link not trained at sufficient rate\n");
                 goto done;
         }
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
index e1832778e8b6..7a1ebdfa9e1b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
@@ -87,6 +87,7 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
                         struct nvkm_output_dp *outpdp = (void *)outp;
                         switch (data) {
                         case NV94_DISP_SOR_DP_PWR_STATE_OFF:
+                                nouveau_event_put(outpdp->irq);
                                 ((struct nvkm_output_dp_impl *)nv_oclass(outp))
                                         ->lnk_pwr(outpdp, 0);
                                 atomic_set(&outpdp->lt.done, 0);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
index 2f7345f7fe07..7445f12b1d9e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
@@ -54,7 +54,7 @@ mmio_list_base:
 #ifdef INCLUDE_CODE
 // reports an exception to the host
 //
-// In: $r15 error code (see nvc0.fuc)
+// In: $r15 error code (see os.h)
 //
 error:
         push $r14
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
index c8ddb8d71b91..b4ad18bf5a26 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
@@ -49,7 +49,7 @@ hub_mmio_list_next:
 #ifdef INCLUDE_CODE
 // reports an exception to the host
 //
-// In: $r15 error code (see nvc0.fuc)
+// In: $r15 error code (see os.h)
 //
 error:
         nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15)
@@ -343,13 +343,25 @@ ih:
         ih_no_ctxsw:
         and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD
         bra e #ih_no_fwmthd
-                // none we handle, ack, and fall-through to unhandled
+                // none we handle; report to host and ack
+                nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO)
+                nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15)
+                nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR)
+                nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15)
+                extr $r14 $r15 16:18
+                shl b32 $r14 $r14 2
+                imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0))
+                add b32 $r14 $r15
+                call(nv_rd32)
+                nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15)
+                mov $r15 E_BAD_FWMTHD
+                call(error)
                 mov $r11 0x100
                 nv_wr32(0x400144, $r11)
 
         // anything we didn't handle, bring it to the host's attention
         ih_no_fwmthd:
-        mov $r11 0x104 // FIFO | CHSW
+        mov $r11 0x504 // FIFO | CHSW | FWMTHD
         not b32 $r11
         and $r11 $r10 $r11
         bra e #ih_no_other
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h
index 214dd16ec566..5f953c5c20b7 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h
@@ -478,10 +478,10 @@ uint32_t gm107_grhub_code[] = {
         0x01040080,
         0xbd0001f6,
         0x01004104,
-        0x627e020f,
-        0x717e0006,
+        0xa87e020f,
+        0xb77e0006,
         0x100f0006,
-        0x0006b37e,
+        0x0006f97e,
         0x98000e98,
         0x207e010f,
         0x14950001,
@@ -523,8 +523,8 @@ uint32_t gm107_grhub_code[] = {
         0x800040b7,
         0xf40132b6,
         0x000fb41b,
-        0x0006b37e,
-        0x627e000f,
+        0x0006f97e,
+        0xa87e000f,
         0x00800006,
         0x01f60201,
         0xbd04bd00,
@@ -554,7 +554,7 @@ uint32_t gm107_grhub_code[] = {
         0x0009f602,
         0x32f404bd,
         0x0231f401,
-        0x0008367e,
+        0x00087c7e,
         0x99f094bd,
         0x17008007,
         0x0009f602,
@@ -563,7 +563,7 @@ uint32_t gm107_grhub_code[] = {
         0x37008006,
         0x0009f602,
         0x31f404bd,
-        0x08367e01,
+        0x087c7e01,
         0xf094bd00,
         0x00800699,
         0x09f60217,
@@ -572,7 +572,7 @@ uint32_t gm107_grhub_code[] = {
         0x20f92f0e,
         0x32f412b2,
         0x0232f401,
-        0x0008367e,
+        0x00087c7e,
         0x008020fc,
         0x02f602c0,
         0xf404bd00,
@@ -580,7 +580,7 @@ uint32_t gm107_grhub_code[] = {
         0x23c8130e,
         0x0d0bf41f,
         0xf40131f4,
-        0x367e0232,
+        0x7c7e0232,
 /* 0x054e: chsw_done */
         0x01020008,
         0x02c30080,
@@ -593,7 +593,7 @@ uint32_t gm107_grhub_code[] = {
         0xb0ff2a0e,
         0x1bf401e4,
         0x7ef2b20c,
-        0xf40007d6,
+        0xf400081c,
 /* 0x057a: main_not_ctx_chan */
         0xe4b0400e,
         0x2c1bf402,
@@ -602,7 +602,7 @@ uint32_t gm107_grhub_code[] = {
         0x0009f602,
         0x32f404bd,
         0x0232f401,
-        0x0008367e,
+        0x00087c7e,
         0x99f094bd,
         0x17008007,
         0x0009f602,
@@ -642,238 +642,238 @@ uint32_t gm107_grhub_code[] = {
 /* 0x061a: ih_no_ctxsw */
         0xabe40000,
         0x0bf40400,
-        0x01004b10,
-        0x448ebfb2,
-        0x8f7e4001,
-/* 0x062e: ih_no_fwmthd */
-        0x044b0000,
-        0xffb0bd01,
-        0x0bf4b4ab,
-        0x0700800c,
-        0x000bf603,
-/* 0x0642: ih_no_other */
-        0x004004bd,
-        0x000af601,
-        0xf0fc04bd,
-        0xd0fce0fc,
-        0xa0fcb0fc,
-        0x80fc90fc,
-        0xfc0088fe,
-        0x0032f480,
-/* 0x0662: ctx_4170s */
-        0xf5f001f8,
-        0x8effb210,
-        0x7e404170,
-        0xf800008f,
-/* 0x0671: ctx_4170w */
-        0x41708e00,
+        0x07088e56,
         0x00657e40,
-        0xf0ffb200,
-        0x1bf410f4,
-/* 0x0683: ctx_redswitch */
-        0x4e00f8f3,
-        0xe5f00200,
-        0x20e5f040,
-        0x8010e5f0,
-        0xf6018500,
-        0x04bd000e,
-/* 0x069a: ctx_redswitch_delay */
-        0xf2b6080f,
-        0xfd1bf401,
-        0x0400e5f1,
-        0x0100e5f1,
-        0x01850080,
-        0xbd000ef6,
-/* 0x06b3: ctx_86c */
-        0x8000f804,
-        0xf6022300,
+        0x80ffb200,
+        0xf6020400,
         0x04bd000f,
-        0x148effb2,
-        0x8f7e408a,
-        0xffb20000,
-        0x41a88c8e,
+        0x4007048e,
+        0x0000657e,
+        0x0080ffb2,
+        0x0ff60203,
+        0xc704bd00,
+        0xee9450fe,
+        0x07008f02,
+        0x00efbb40,
+        0x0000657e,
+        0x02020080,
+        0xbd000ff6,
+        0x7e030f04,
+        0x4b0002f8,
+        0xbfb20100,
+        0x4001448e,
         0x00008f7e,
-/* 0x06d2: ctx_mem */
-        0x008000f8,
-        0x0ff60284,
-/* 0x06db: ctx_mem_wait */
-        0x8f04bd00,
-        0xcf028400,
-        0xfffd00ff,
-        0xf61bf405,
-/* 0x06ea: ctx_load */
-        0x94bd00f8,
-        0x800599f0,
-        0xf6023700,
-        0x04bd0009,
-        0xb87e0c0a,
-        0xf4bd0000,
-        0x02890080,
+/* 0x0674: ih_no_fwmthd */
+        0xbd05044b,
+        0xb4abffb0,
+        0x800c0bf4,
+        0xf6030700,
+        0x04bd000b,
+/* 0x0688: ih_no_other */
+        0xf6010040,
+        0x04bd000a,
+        0xe0fcf0fc,
+        0xb0fcd0fc,
+        0x90fca0fc,
+        0x88fe80fc,
+        0xf480fc00,
+        0x01f80032,
+/* 0x06a8: ctx_4170s */
+        0xb210f5f0,
+        0x41708eff,
+        0x008f7e40,
+/* 0x06b7: ctx_4170w */
+        0x8e00f800,
+        0x7e404170,
+        0xb2000065,
+        0x10f4f0ff,
+        0xf8f31bf4,
+/* 0x06c9: ctx_redswitch */
+        0x02004e00,
+        0xf040e5f0,
+        0xe5f020e5,
+        0x85008010,
+        0x000ef601,
+        0x080f04bd,
+/* 0x06e0: ctx_redswitch_delay */
+        0xf401f2b6,
+        0xe5f1fd1b,
+        0xe5f10400,
+        0x00800100,
+        0x0ef60185,
+        0xf804bd00,
+/* 0x06f9: ctx_86c */
+        0x23008000,
+        0x000ff602,
+        0xffb204bd,
+        0x408a148e,
+        0x00008f7e,
+        0x8c8effb2,
+        0x8f7e41a8,
+        0x00f80000,
+/* 0x0718: ctx_mem */
+        0x02840080,
         0xbd000ff6,
-        0xc1008004,
-        0x0002f602,
-        0x008004bd,
-        0x02f60283,
-        0x0f04bd00,
-        0x06d27e07,
-        0xc0008000,
-        0x0002f602,
-        0x0bfe04bd,
-        0x1f2af000,
-        0xb60424b6,
-        0x94bd0220,
-        0x800899f0,
-        0xf6023700,
-        0x04bd0009,
-        0x02810080,
-        0xbd0002f6,
-        0x0000d204,
-        0x25f08000,
-        0x88008002,
-        0x0002f602,
-        0x100104bd,
-        0xf0020042,
-        0x12fa0223,
-        0xbd03f805,
-        0x0899f094,
-        0x02170080,
-        0xbd0009f6,
-        0x81019804,
-        0x981814b6,
-        0x25b68002,
-        0x0512fd08,
-        0xbd1601b5,
-        0x0999f094,
-        0x02370080,
-        0xbd0009f6,
-        0x81008004,
-        0x0001f602,
-        0x010204bd,
-        0x02880080,
+/* 0x0721: ctx_mem_wait */
+        0x84008f04,
+        0x00ffcf02,
+        0xf405fffd,
+        0x00f8f61b,
+/* 0x0730: ctx_load */
+        0x99f094bd,
+        0x37008005,
+        0x0009f602,
+        0x0c0a04bd,
+        0x0000b87e,
+        0x0080f4bd,
+        0x0ff60289,
+        0x8004bd00,
+        0xf602c100,
+        0x04bd0002,
+        0x02830080,
         0xbd0002f6,
-        0x01004104,
-        0xfa0613f0,
-        0x03f80501,
+        0x7e070f04,
+        0x80000718,
+        0xf602c000,
+        0x04bd0002,
+        0xf0000bfe,
+        0x24b61f2a,
+        0x0220b604,
         0x99f094bd,
-        0x17008009,
+        0x37008008,
         0x0009f602,
-        0x94bd04bd,
-        0x800599f0,
+        0x008004bd,
+        0x02f60281,
+        0xd204bd00,
+        0x80000000,
+        0x800225f0,
+        0xf6028800,
+        0x04bd0002,
+        0x00421001,
+        0x0223f002,
+        0xf80512fa,
+        0xf094bd03,
+        0x00800899,
+        0x09f60217,
+        0x9804bd00,
+        0x14b68101,
+        0x80029818,
+        0xfd0825b6,
+        0x01b50512,
+        0xf094bd16,
+        0x00800999,
+        0x09f60237,
+        0x8004bd00,
+        0xf6028100,
+        0x04bd0001,
+        0x00800102,
+        0x02f60288,
+        0x4104bd00,
+        0x13f00100,
+        0x0501fa06,
+        0x94bd03f8,
+        0x800999f0,
         0xf6021700,
         0x04bd0009,
-/* 0x07d6: ctx_chan */
-        0xea7e00f8,
-        0x0c0a0006,
-        0x0000b87e,
-        0xd27e050f,
-        0x00f80006,
-/* 0x07e8: ctx_mmio_exec */
-        0x80410398,
+        0x99f094bd,
+        0x17008005,
+        0x0009f602,
+        0x00f804bd,
+/* 0x081c: ctx_chan */
+        0x0007307e,
+        0xb87e0c0a,
+        0x050f0000,
+        0x0007187e,
+/* 0x082e: ctx_mmio_exec */
+        0x039800f8,
+        0x81008041,
+        0x0003f602,
+        0x34bd04bd,
+/* 0x083c: ctx_mmio_loop */
+        0xf4ff34c4,
+        0x00450e1b,
+        0x0653f002,
+        0xf80535fa,
+/* 0x084d: ctx_mmio_pull */
+        0x804e9803,
+        0x7e814f98,
+        0xb600008f,
+        0x12b60830,
+        0xdf1bf401,
+/* 0x0860: ctx_mmio_done */
+        0x80160398,
         0xf6028100,
         0x04bd0003,
-/* 0x07f6: ctx_mmio_loop */
-        0x34c434bd,
-        0x0e1bf4ff,
-        0xf0020045,
-        0x35fa0653,
-/* 0x0807: ctx_mmio_pull */
-        0x9803f805,
-        0x4f98804e,
-        0x008f7e81,
-        0x0830b600,
-        0xf40112b6,
-/* 0x081a: ctx_mmio_done */
-        0x0398df1b,
-        0x81008016,
-        0x0003f602,
-        0x00b504bd,
-        0x01004140,
-        0xfa0613f0,
-        0x03f80601,
-/* 0x0836: ctx_xfer */
-        0x040e00f8,
-        0x03020080,
-        0xbd000ef6,
-/* 0x0841: ctx_xfer_idle */
-        0x00008e04,
-        0x00eecf03,
-        0x2000e4f1,
-        0xf4f51bf4,
-        0x02f40611,
-/* 0x0855: ctx_xfer_pre */
-        0x7e100f0c,
-        0xf40006b3,
-/* 0x085e: ctx_xfer_pre_load */
-        0x020f1b11,
-        0x0006627e,
-        0x0006717e,
-        0x0006837e,
-        0x627ef4bd,
-        0xea7e0006,
-/* 0x0876: ctx_xfer_exec */
-        0x01980006,
-        0x8024bd16,
-        0xf6010500,
-        0x04bd0002,
-        0x008e1fb2,
-        0x8f7e41a5,
-        0xfcf00000,
-        0x022cf001,
-        0xfd0124b6,
-        0xffb205f2,
-        0x41a5048e,
+        0x414000b5,
+        0x13f00100,
+        0x0601fa06,
+        0x00f803f8,
+/* 0x087c: ctx_xfer */
+        0x0080040e,
+        0x0ef60302,
+/* 0x0887: ctx_xfer_idle */
+        0x8e04bd00,
+        0xcf030000,
+        0xe4f100ee,
+        0x1bf42000,
+        0x0611f4f5,
+/* 0x089b: ctx_xfer_pre */
+        0x0f0c02f4,
+        0x06f97e10,
+        0x1b11f400,
+/* 0x08a4: ctx_xfer_pre_load */
+        0xa87e020f,
+        0xb77e0006,
+        0xc97e0006,
+        0xf4bd0006,
+        0x0006a87e,
+        0x0007307e,
+/* 0x08bc: ctx_xfer_exec */
+        0xbd160198,
+        0x05008024,
+        0x0002f601,
+        0x1fb204bd,
+        0x41a5008e,
         0x00008f7e,
-        0x0002167e,
-        0xfc8024bd,
-        0x02f60247,
-        0xf004bd00,
-        0x20b6012c,
-        0x4afc8003,
-        0x0002f602,
-        0xacf004bd,
-        0x06a5f001,
-        0x0c98000b,
-        0x010d9800,
-        0x3d7e000e,
-        0x080a0001,
-        0x0000ec7e,
-        0x00020a7e,
-        0x0a1201f4,
-        0x00b87e0c,
-        0x7e050f00,
-        0xf40006d2,
-/* 0x08f2: ctx_xfer_post */
-        0x020f2d02,
-        0x0006627e,
-        0xb37ef4bd,
-        0x277e0006,
-        0x717e0002,
+        0xf001fcf0,
+        0x24b6022c,
+        0x05f2fd01,
+        0x048effb2,
+        0x8f7e41a5,
+        0x167e0000,
+        0x24bd0002,
+        0x0247fc80,
+        0xbd0002f6,
+        0x012cf004,
+        0x800320b6,
+        0xf6024afc,
+        0x04bd0002,
+        0xf001acf0,
+        0x000b06a5,
+        0x98000c98,
+        0x000e010d,
+        0x00013d7e,
+        0xec7e080a,
+        0x0a7e0000,
+        0x01f40002,
+        0x7e0c0a12,
+        0x0f0000b8,
+        0x07187e05,
+        0x2d02f400,
+/* 0x0938: ctx_xfer_post */
+        0xa87e020f,
         0xf4bd0006,
-        0x0006627e,
-        0x981011f4,
-        0x11fd4001,
-        0x070bf405,
-        0x0007e87e,
-/* 0x091c: ctx_xfer_no_post_mmio */
-/* 0x091c: ctx_xfer_done */
-        0x000000f8,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
+        0x0006f97e,
+        0x0002277e,
+        0x0006b77e,
+        0xa87ef4bd,
+        0x11f40006,
+        0x40019810,
+        0xf40511fd,
+        0x2e7e070b,
+/* 0x0962: ctx_xfer_no_post_mmio */
+/* 0x0962: ctx_xfer_done */
+        0x00f80008,
         0x00000000,
         0x00000000,
         0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h
index 64dfd75192bf..e49b5a877ae4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h
@@ -478,10 +478,10 @@ uint32_t nv108_grhub_code[] = {
         0x01040080,
         0xbd0001f6,
         0x01004104,
-        0x627e020f,
-        0x717e0006,
+        0xa87e020f,
+        0xb77e0006,
         0x100f0006,
-        0x0006b37e,
+        0x0006f97e,
         0x98000e98,
         0x207e010f,
         0x14950001,
@@ -523,8 +523,8 @@ uint32_t nv108_grhub_code[] = {
         0x800040b7,
         0xf40132b6,
         0x000fb41b,
-        0x0006b37e,
-        0x627e000f,
+        0x0006f97e,
+        0xa87e000f,
         0x00800006,
         0x01f60201,
         0xbd04bd00,
@@ -554,7 +554,7 @@ uint32_t nv108_grhub_code[] = {
         0x0009f602,
         0x32f404bd,
         0x0231f401,
-        0x0008367e,
+        0x00087c7e,
         0x99f094bd,
         0x17008007,
         0x0009f602,
@@ -563,7 +563,7 @@ uint32_t nv108_grhub_code[] = {
         0x37008006,
         0x0009f602,
         0x31f404bd,
-        0x08367e01,
+        0x087c7e01,
         0xf094bd00,
         0x00800699,
         0x09f60217,
@@ -572,7 +572,7 @@ uint32_t nv108_grhub_code[] = {
         0x20f92f0e,
         0x32f412b2,
         0x0232f401,
-        0x0008367e,
+        0x00087c7e,
         0x008020fc,
         0x02f602c0,
         0xf404bd00,
@@ -580,7 +580,7 @@ uint32_t nv108_grhub_code[] = {
         0x23c8130e,
         0x0d0bf41f,
         0xf40131f4,
-        0x367e0232,
+        0x7c7e0232,
 /* 0x054e: chsw_done */
         0x01020008,
         0x02c30080,
@@ -593,7 +593,7 @@ uint32_t nv108_grhub_code[] = {
         0xb0ff2a0e,
         0x1bf401e4,
         0x7ef2b20c,
-        0xf40007d6,
+        0xf400081c,
 /* 0x057a: main_not_ctx_chan */
         0xe4b0400e,
         0x2c1bf402,
@@ -602,7 +602,7 @@ uint32_t nv108_grhub_code[] = {
         0x0009f602,
         0x32f404bd,
         0x0232f401,
-        0x0008367e,
+        0x00087c7e,
         0x99f094bd,
         0x17008007,
         0x0009f602,
@@ -642,238 +642,238 @@ uint32_t nv108_grhub_code[] = {
 /* 0x061a: ih_no_ctxsw */
         0xabe40000,
         0x0bf40400,
-        0x01004b10,
-        0x448ebfb2,
-        0x8f7e4001,
-/* 0x062e: ih_no_fwmthd */
-        0x044b0000,
-        0xffb0bd01,
-        0x0bf4b4ab,
-        0x0700800c,
-        0x000bf603,
-/* 0x0642: ih_no_other */
-        0x004004bd,
-        0x000af601,
-        0xf0fc04bd,
-        0xd0fce0fc,
-        0xa0fcb0fc,
-        0x80fc90fc,
-        0xfc0088fe,
-        0x0032f480,
-/* 0x0662: ctx_4170s */
-        0xf5f001f8,
-        0x8effb210,
-        0x7e404170,
-        0xf800008f,
-/* 0x0671: ctx_4170w */
-        0x41708e00,
+        0x07088e56,
         0x00657e40,
-        0xf0ffb200,
-        0x1bf410f4,
-/* 0x0683: ctx_redswitch */
-        0x4e00f8f3,
-        0xe5f00200,
-        0x20e5f040,
-        0x8010e5f0,
-        0xf6018500,
-        0x04bd000e,
-/* 0x069a: ctx_redswitch_delay */
-        0xf2b6080f,
-        0xfd1bf401,
-        0x0400e5f1,
-        0x0100e5f1,
-        0x01850080,
-        0xbd000ef6,
-/* 0x06b3: ctx_86c */
-        0x8000f804,
-        0xf6022300,
+        0x80ffb200,
+        0xf6020400,
         0x04bd000f,
-        0x148effb2,
-        0x8f7e408a,
-        0xffb20000,
-        0x41a88c8e,
+        0x4007048e,
+        0x0000657e,
+        0x0080ffb2,
+        0x0ff60203,
+        0xc704bd00,
+        0xee9450fe,
+        0x07008f02,
+        0x00efbb40,
+        0x0000657e,
+        0x02020080,
+        0xbd000ff6,
+        0x7e030f04,
+        0x4b0002f8,
+        0xbfb20100,
+        0x4001448e,
         0x00008f7e,
-/* 0x06d2: ctx_mem */
-        0x008000f8,
-        0x0ff60284,
-/* 0x06db: ctx_mem_wait */
-        0x8f04bd00,
-        0xcf028400,
-        0xfffd00ff,
-        0xf61bf405,
-/* 0x06ea: ctx_load */
-        0x94bd00f8,
-        0x800599f0,
-        0xf6023700,
-        0x04bd0009,
-        0xb87e0c0a,
-        0xf4bd0000,
-        0x02890080,
+/* 0x0674: ih_no_fwmthd */
+        0xbd05044b,
+        0xb4abffb0,
+        0x800c0bf4,
+        0xf6030700,
+        0x04bd000b,
+/* 0x0688: ih_no_other */
+        0xf6010040,
+        0x04bd000a,
+        0xe0fcf0fc,
+        0xb0fcd0fc,
+        0x90fca0fc,
+        0x88fe80fc,
+        0xf480fc00,
+        0x01f80032,
+/* 0x06a8: ctx_4170s */
+        0xb210f5f0,
+        0x41708eff,
+        0x008f7e40,
+/* 0x06b7: ctx_4170w */
+        0x8e00f800,
+        0x7e404170,
+        0xb2000065,
+        0x10f4f0ff,
+        0xf8f31bf4,
+/* 0x06c9: ctx_redswitch */
+        0x02004e00,
+        0xf040e5f0,
+        0xe5f020e5,
+        0x85008010,
+        0x000ef601,
+        0x080f04bd,
+/* 0x06e0: ctx_redswitch_delay */
+        0xf401f2b6,
+        0xe5f1fd1b,
+        0xe5f10400,
+        0x00800100,
+        0x0ef60185,
+        0xf804bd00,
+/* 0x06f9: ctx_86c */
+        0x23008000,
+        0x000ff602,
+        0xffb204bd,
+        0x408a148e,
+        0x00008f7e,
+        0x8c8effb2,
+        0x8f7e41a8,
+        0x00f80000,
+/* 0x0718: ctx_mem */
+        0x02840080,
         0xbd000ff6,
-        0xc1008004,
-        0x0002f602,
-        0x008004bd,
-        0x02f60283,
-        0x0f04bd00,
-        0x06d27e07,
-        0xc0008000,
-        0x0002f602,
-        0x0bfe04bd,
-        0x1f2af000,
-        0xb60424b6,
-        0x94bd0220,
-        0x800899f0,
-        0xf6023700,
-        0x04bd0009,
-        0x02810080,
-        0xbd0002f6,
-        0x0000d204,
-        0x25f08000,
-        0x88008002,
-        0x0002f602,
-        0x100104bd,
-        0xf0020042,
-        0x12fa0223,
-        0xbd03f805,
-        0x0899f094,
-        0x02170080,
-        0xbd0009f6,
-        0x81019804,
-        0x981814b6,
-        0x25b68002,
-        0x0512fd08,
-        0xbd1601b5,
-        0x0999f094,
-        0x02370080,
-        0xbd0009f6,
-        0x81008004,
-        0x0001f602,
-        0x010204bd,
-        0x02880080,
+/* 0x0721: ctx_mem_wait */
+        0x84008f04,
+        0x00ffcf02,
+        0xf405fffd,
+        0x00f8f61b,
+/* 0x0730: ctx_load */
+        0x99f094bd,
+        0x37008005,
+        0x0009f602,
+        0x0c0a04bd,
+        0x0000b87e,
+        0x0080f4bd,
+        0x0ff60289,
+        0x8004bd00,
+        0xf602c100,
+        0x04bd0002,
+        0x02830080,
         0xbd0002f6,
-        0x01004104,
-        0xfa0613f0,
-        0x03f80501,
+        0x7e070f04,
+        0x80000718,
+        0xf602c000,
+        0x04bd0002,
+        0xf0000bfe,
+        0x24b61f2a,
+        0x0220b604,
         0x99f094bd,
-        0x17008009,
+        0x37008008,
         0x0009f602,
-        0x94bd04bd,
-        0x800599f0,
+        0x008004bd,
+        0x02f60281,
+        0xd204bd00,
+        0x80000000,
+        0x800225f0,
+        0xf6028800,
+        0x04bd0002,
+        0x00421001,
+        0x0223f002,
+        0xf80512fa,
+        0xf094bd03,
+        0x00800899,
+        0x09f60217,
+        0x9804bd00,
+        0x14b68101,
+        0x80029818,
+        0xfd0825b6,
+        0x01b50512,
+        0xf094bd16,
+        0x00800999,
+        0x09f60237,
+        0x8004bd00,
+        0xf6028100,
+        0x04bd0001,
+        0x00800102,
+        0x02f60288,
+        0x4104bd00,
+        0x13f00100,
+        0x0501fa06,
+        0x94bd03f8,
+        0x800999f0,
         0xf6021700,
         0x04bd0009,
-/* 0x07d6: ctx_chan */
-        0xea7e00f8,
-        0x0c0a0006,
-        0x0000b87e,
-        0xd27e050f,
-        0x00f80006,
-/* 0x07e8: ctx_mmio_exec */
-        0x80410398,
+        0x99f094bd,
+        0x17008005,
+        0x0009f602,
+        0x00f804bd,
+/* 0x081c: ctx_chan */
+        0x0007307e,
+        0xb87e0c0a,
+        0x050f0000,
+        0x0007187e,
+/* 0x082e: ctx_mmio_exec */
+        0x039800f8,
+        0x81008041,
+        0x0003f602,
+        0x34bd04bd,
+/* 0x083c: ctx_mmio_loop */
+        0xf4ff34c4,
+        0x00450e1b,
+        0x0653f002,
+        0xf80535fa,
+/* 0x084d: ctx_mmio_pull */
+        0x804e9803,
+        0x7e814f98,
+        0xb600008f,
+        0x12b60830,
+        0xdf1bf401,
+/* 0x0860: ctx_mmio_done */
+        0x80160398,
         0xf6028100,
         0x04bd0003,
-/* 0x07f6: ctx_mmio_loop */
-        0x34c434bd,
-        0x0e1bf4ff,
-        0xf0020045,
-        0x35fa0653,
-/* 0x0807: ctx_mmio_pull */
-        0x9803f805,
-        0x4f98804e,
-        0x008f7e81,
-        0x0830b600,
-        0xf40112b6,
-/* 0x081a: ctx_mmio_done */
-        0x0398df1b,
-        0x81008016,
-        0x0003f602,
-        0x00b504bd,
-        0x01004140,
-        0xfa0613f0,
-        0x03f80601,
-/* 0x0836: ctx_xfer */
-        0x040e00f8,
-        0x03020080,
-        0xbd000ef6,
-/* 0x0841: ctx_xfer_idle */
-        0x00008e04,
-        0x00eecf03,
-        0x2000e4f1,
-        0xf4f51bf4,
-        0x02f40611,
-/* 0x0855: ctx_xfer_pre */
-        0x7e100f0c,
-        0xf40006b3,
-/* 0x085e: ctx_xfer_pre_load */
-        0x020f1b11,
-        0x0006627e,
-        0x0006717e,
-        0x0006837e,
-        0x627ef4bd,
-        0xea7e0006,
-/* 0x0876: ctx_xfer_exec */
-        0x01980006,
-        0x8024bd16,
-        0xf6010500,
-        0x04bd0002,
-        0x008e1fb2,
-        0x8f7e41a5,
-        0xfcf00000,
-        0x022cf001,
-        0xfd0124b6,
-        0xffb205f2,
-        0x41a5048e,
+        0x414000b5,
+        0x13f00100,
+        0x0601fa06,
+        0x00f803f8,
+/* 0x087c: ctx_xfer */
+        0x0080040e,
+        0x0ef60302,
+/* 0x0887: ctx_xfer_idle */
+        0x8e04bd00,
+        0xcf030000,
+        0xe4f100ee,
+        0x1bf42000,
+        0x0611f4f5,
+/* 0x089b: ctx_xfer_pre */
+        0x0f0c02f4,
+        0x06f97e10,
+        0x1b11f400,
+/* 0x08a4: ctx_xfer_pre_load */
+        0xa87e020f,
+        0xb77e0006,
+        0xc97e0006,
+        0xf4bd0006,
+        0x0006a87e,
+        0x0007307e,
+/* 0x08bc: ctx_xfer_exec */
+        0xbd160198,
+        0x05008024,
+        0x0002f601,
+        0x1fb204bd,
+        0x41a5008e,
         0x00008f7e,
-        0x0002167e,
-        0xfc8024bd,
-        0x02f60247,
-        0xf004bd00,
-        0x20b6012c,
-        0x4afc8003,
-        0x0002f602,
-        0xacf004bd,
-        0x06a5f001,
-        0x0c98000b,
-        0x010d9800,
-        0x3d7e000e,
-        0x080a0001,
-        0x0000ec7e,
-        0x00020a7e,
-        0x0a1201f4,
-        0x00b87e0c,
-        0x7e050f00,
-        0xf40006d2,
-/* 0x08f2: ctx_xfer_post */
-        0x020f2d02,
-        0x0006627e,
-        0xb37ef4bd,
-        0x277e0006,
-        0x717e0002,
+        0xf001fcf0,
+        0x24b6022c,
+        0x05f2fd01,
+        0x048effb2,
+        0x8f7e41a5,
+        0x167e0000,
+        0x24bd0002,
+        0x0247fc80,
+        0xbd0002f6,
+        0x012cf004,
+        0x800320b6,
+        0xf6024afc,
+        0x04bd0002,
+        0xf001acf0,
+        0x000b06a5,
+        0x98000c98,
+        0x000e010d,
+        0x00013d7e,
+        0xec7e080a,
+        0x0a7e0000,
+        0x01f40002,
+        0x7e0c0a12,
+        0x0f0000b8,
+        0x07187e05,
+        0x2d02f400,
+/* 0x0938: ctx_xfer_post */
+        0xa87e020f,
         0xf4bd0006,
-        0x0006627e,
-        0x981011f4,
-        0x11fd4001,
-        0x070bf405,
-        0x0007e87e,
-/* 0x091c: ctx_xfer_no_post_mmio */
-/* 0x091c: ctx_xfer_done */
-        0x000000f8,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
+        0x0006f97e,
+        0x0002277e,
+        0x0006b77e,
+        0xa87ef4bd,
+        0x11f40006,
+        0x40019810,
+        0xf40511fd,
+        0x2e7e070b,
+/* 0x0962: ctx_xfer_no_post_mmio */
+/* 0x0962: ctx_xfer_done */
+        0x00f80008,
         0x00000000,
         0x00000000,
         0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
index f8f7b278a13f..92dfe6a4ac87 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
@@ -528,10 +528,10 @@ uint32_t nvc0_grhub_code[] = {
         0x0001d001,
         0x17f104bd,
         0xf7f00100,
-        0xb521f502,
-        0xc721f507,
-        0x10f7f007,
-        0x081421f5,
+        0x0d21f502,
+        0x1f21f508,
+        0x10f7f008,
+        0x086c21f5,
         0x98000e98,
         0x21f5010f,
         0x14950150,
@@ -574,9 +574,9 @@ uint32_t nvc0_grhub_code[] = {
         0xb6800040,
         0x1bf40132,
         0x00f7f0be,
-        0x081421f5,
+        0x086c21f5,
         0xf500f7f0,
-        0xf107b521,
+        0xf1080d21,
         0xf0010007,
         0x01d00203,
         0xbd04bd00,
@@ -610,8 +610,8 @@ uint32_t nvc0_grhub_code[] = {
         0x09d00203,
         0xf404bd00,
         0x31f40132,
-        0xe821f502,
-        0xf094bd09,
+        0x4021f502,
+        0xf094bd0a,
         0x07f10799,
         0x03f01700,
         0x0009d002,
@@ -621,7 +621,7 @@ uint32_t nvc0_grhub_code[] = {
         0x0203f00f,
         0xbd0009d0,
         0x0131f404,
-        0x09e821f5,
+        0x0a4021f5,
         0x99f094bd,
         0x0007f106,
         0x0203f017,
@@ -631,7 +631,7 @@ uint32_t nvc0_grhub_code[] = {
         0x12b920f9,
         0x0132f402,
         0xf50232f4,
-        0xfc09e821,
+        0xfc0a4021,
         0x0007f120,
         0x0203f0c0,
         0xbd0002d0,
@@ -640,7 +640,7 @@ uint32_t nvc0_grhub_code[] = {
         0xf41f23c8,
         0x31f40d0b,
         0x0232f401,
-        0x09e821f5,
+        0x0a4021f5,
 /* 0x063c: chsw_done */
         0xf10127f0,
         0xf0c30007,
@@ -654,7 +654,7 @@ uint32_t nvc0_grhub_code[] = {
 /* 0x0660: main_not_ctx_switch */
         0xf401e4b0,
         0xf2b90d1b,
-        0x7821f502,
+        0xd021f502,
         0x460ef409,
 /* 0x0670: main_not_ctx_chan */
         0xf402e4b0,
@@ -664,8 +664,8 @@ uint32_t nvc0_grhub_code[] = {
         0x09d00203,
         0xf404bd00,
         0x32f40132,
-        0xe821f502,
-        0xf094bd09,
+        0x4021f502,
+        0xf094bd0a,
         0x07f10799,
         0x03f01700,
         0x0009d002,
@@ -710,18 +710,40 @@ uint32_t nvc0_grhub_code[] = {
 /* 0x072b: ih_no_ctxsw */
         0xe40421f4,
         0xf40400ab,
-        0xb7f1140b,
+        0xe7f16c0b,
+        0xe3f00708,
+        0x6821f440,
+        0xf102ffb9,
+        0xf0040007,
+        0x0fd00203,
+        0xf104bd00,
+        0xf00704e7,
+        0x21f440e3,
+        0x02ffb968,
+        0x030007f1,
+        0xd00203f0,
+        0x04bd000f,
+        0x9450fec7,
+        0xf7f102ee,
+        0xf3f00700,
+        0x00efbb40,
+        0xf16821f4,
+        0xf0020007,
+        0x0fd00203,
+        0xf004bd00,
+        0x21f503f7,
+        0xb7f1037e,
         0xbfb90100,
         0x44e7f102,
         0x40e3f001,
-/* 0x0743: ih_no_fwmthd */
+/* 0x079b: ih_no_fwmthd */
         0xf19d21f4,
-        0xbd0104b7,
+        0xbd0504b7,
         0xb4abffb0,
         0xf10f0bf4,
         0xf0070007,
         0x0bd00303,
-/* 0x075b: ih_no_other */
+/* 0x07b3: ih_no_other */
         0xf104bd00,
         0xf0010007,
         0x0ad00003,
@@ -731,36 +753,36 @@ uint32_t nvc0_grhub_code[] = {
         0xfc90fca0,
         0x0088fe80,
         0x32f480fc,
-/* 0x077f: ctx_4160s */
+/* 0x07d7: ctx_4160s */
         0xf001f800,
         0xffb901f7,
         0x60e7f102,
         0x40e3f041,
-/* 0x078f: ctx_4160s_wait */
+/* 0x07e7: ctx_4160s_wait */
         0xf19d21f4,
         0xf04160e7,
         0x21f440e3,
         0x02ffb968,
         0xf404ffc8,
         0x00f8f00b,
-/* 0x07a4: ctx_4160c */
+/* 0x07fc: ctx_4160c */
         0xffb9f4bd,
         0x60e7f102,
         0x40e3f041,
         0xf89d21f4,
-/* 0x07b5: ctx_4170s */
+/* 0x080d: ctx_4170s */
         0x10f5f000,
         0xf102ffb9,
         0xf04170e7,
         0x21f440e3,
-/* 0x07c7: ctx_4170w */
+/* 0x081f: ctx_4170w */
         0xf100f89d,
         0xf04170e7,
         0x21f440e3,
         0x02ffb968,
         0xf410f4f0,
         0x00f8f01b,
-/* 0x07dc: ctx_redswitch */
+/* 0x0834: ctx_redswitch */
         0x0200e7f1,
         0xf040e5f0,
         0xe5f020e5,
@@ -768,7 +790,7 @@ uint32_t nvc0_grhub_code[] = {
         0x0103f085,
         0xbd000ed0,
         0x08f7f004,
-/* 0x07f8: ctx_redswitch_delay */
+/* 0x0850: ctx_redswitch_delay */
         0xf401f2b6,
         0xe5f1fd1b,
         0xe5f10400,
@@ -776,7 +798,7 @@ uint32_t nvc0_grhub_code[] = {
         0x03f08500,
         0x000ed001,
         0x00f804bd,
-/* 0x0814: ctx_86c */
+/* 0x086c: ctx_86c */
         0x1b0007f1,
         0xd00203f0,
         0x04bd000f,
@@ -787,16 +809,16 @@ uint32_t nvc0_grhub_code[] = {
         0xa86ce7f1,
         0xf441e3f0,
         0x00f89d21,
-/* 0x083c: ctx_mem */
+/* 0x0894: ctx_mem */
         0x840007f1,
         0xd00203f0,
         0x04bd000f,
-/* 0x0848: ctx_mem_wait */
+/* 0x08a0: ctx_mem_wait */
         0x8400f7f1,
         0xcf02f3f0,
         0xfffd00ff,
         0xf31bf405,
-/* 0x085a: ctx_load */
+/* 0x08b2: ctx_load */
         0x94bd00f8,
         0xf10599f0,
         0xf00f0007,
@@ -814,7 +836,7 @@ uint32_t nvc0_grhub_code[] = {
         0x02d00203,
         0xf004bd00,
         0x21f507f7,
-        0x07f1083c,
+        0x07f10894,
         0x03f0c000,
         0x0002d002,
         0x0bfe04bd,
@@ -869,31 +891,31 @@ uint32_t nvc0_grhub_code[] = {
         0x03f01700,
         0x0009d002,
         0x00f804bd,
-/* 0x0978: ctx_chan */
-        0x077f21f5,
-        0x085a21f5,
+/* 0x09d0: ctx_chan */
+        0x07d721f5,
+        0x08b221f5,
         0xf40ca7f0,
         0xf7f0d021,
-        0x3c21f505,
-        0xa421f508,
-/* 0x0993: ctx_mmio_exec */
+        0x9421f505,
+        0xfc21f508,
+/* 0x09eb: ctx_mmio_exec */
         0x9800f807,
         0x07f14103,
         0x03f08100,
         0x0003d002,
         0x34bd04bd,
-/* 0x09a4: ctx_mmio_loop */
+/* 0x09fc: ctx_mmio_loop */
         0xf4ff34c4,
         0x57f10f1b,
         0x53f00200,
         0x0535fa06,
-/* 0x09b6: ctx_mmio_pull */
+/* 0x0a0e: ctx_mmio_pull */
         0x4e9803f8,
         0x814f9880,
         0xb69d21f4,
         0x12b60830,
         0xdf1bf401,
-/* 0x09c8: ctx_mmio_done */
+/* 0x0a20: ctx_mmio_done */
         0xf1160398,
         0xf0810007,
         0x03d00203,
@@ -902,30 +924,30 @@ uint32_t nvc0_grhub_code[] = {
         0x13f00100,
         0x0601fa06,
         0x00f803f8,
-/* 0x09e8: ctx_xfer */
+/* 0x0a40: ctx_xfer */
         0xf104e7f0,
         0xf0020007,
         0x0ed00303,
-/* 0x09f7: ctx_xfer_idle */
+/* 0x0a4f: ctx_xfer_idle */
         0xf104bd00,
         0xf00000e7,
         0xeecf03e3,
         0x00e4f100,
         0xf21bf420,
         0xf40611f4,
-/* 0x0a0e: ctx_xfer_pre */
+/* 0x0a66: ctx_xfer_pre */
         0xf7f01102,
-        0x1421f510,
-        0x7f21f508,
+        0x6c21f510,
+        0xd721f508,
         0x1c11f407,
-/* 0x0a1c: ctx_xfer_pre_load */
+/* 0x0a74: ctx_xfer_pre_load */
         0xf502f7f0,
-        0xf507b521,
-        0xf507c721,
-        0xbd07dc21,
-        0xb521f5f4,
-        0x5a21f507,
-/* 0x0a35: ctx_xfer_exec */
+        0xf5080d21,
+        0xf5081f21,
+        0xbd083421,
+        0x0d21f5f4,
+        0xb221f508,
+/* 0x0a8d: ctx_xfer_exec */
         0x16019808,
         0x07f124bd,
         0x03f00500,
@@ -960,23 +982,65 @@ uint32_t nvc0_grhub_code[] = {
         0x1301f402,
         0xf40ca7f0,
         0xf7f0d021,
-        0x3c21f505,
+        0x9421f505,
         0x3202f408,
-/* 0x0ac4: ctx_xfer_post */
+/* 0x0b1c: ctx_xfer_post */
         0xf502f7f0,
-        0xbd07b521,
-        0x1421f5f4,
+        0xbd080d21,
+        0x6c21f5f4,
         0x7f21f508,
-        0xc721f502,
-        0xf5f4bd07,
-        0xf407b521,
+        0x1f21f502,
+        0xf5f4bd08,
+        0xf4080d21,
         0x01981011,
         0x0511fd40,
         0xf5070bf4,
-/* 0x0aef: ctx_xfer_no_post_mmio */
-        0xf5099321,
-/* 0x0af3: ctx_xfer_done */
-        0xf807a421,
+/* 0x0b47: ctx_xfer_no_post_mmio */
+        0xf509eb21,
+/* 0x0b4b: ctx_xfer_done */
+        0xf807fc21,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
         0x00000000,
         0x00000000,
         0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
index 624215a005b0..62b0c7601d8b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
@@ -528,10 +528,10 @@ uint32_t nvd7_grhub_code[] = {
         0x0001d001,
         0x17f104bd,
         0xf7f00100,
-        0xb521f502,
-        0xc721f507,
-        0x10f7f007,
-        0x081421f5,
+        0x0d21f502,
+        0x1f21f508,
+        0x10f7f008,
+        0x086c21f5,
         0x98000e98,
         0x21f5010f,
         0x14950150,
@@ -574,9 +574,9 @@ uint32_t nvd7_grhub_code[] = {
         0xb6800040,
         0x1bf40132,
         0x00f7f0be,
-        0x081421f5,
+        0x086c21f5,
         0xf500f7f0,
-        0xf107b521,
+        0xf1080d21,
         0xf0010007,
         0x01d00203,
         0xbd04bd00,
@@ -610,8 +610,8 @@ uint32_t nvd7_grhub_code[] = {
         0x09d00203,
         0xf404bd00,
         0x31f40132,
-        0xe821f502,
-        0xf094bd09,
+        0x4021f502,
+        0xf094bd0a,
         0x07f10799,
         0x03f01700,
         0x0009d002,
@@ -621,7 +621,7 @@ uint32_t nvd7_grhub_code[] = {
         0x0203f00f,
         0xbd0009d0,
         0x0131f404,
-        0x09e821f5,
+        0x0a4021f5,
         0x99f094bd,
         0x0007f106,
         0x0203f017,
@@ -631,7 +631,7 @@ uint32_t nvd7_grhub_code[] = {
         0x12b920f9,
         0x0132f402,
         0xf50232f4,
-        0xfc09e821,
+        0xfc0a4021,
         0x0007f120,
         0x0203f0c0,
         0xbd0002d0,
@@ -640,7 +640,7 @@ uint32_t nvd7_grhub_code[] = {
         0xf41f23c8,
         0x31f40d0b,
         0x0232f401,
-        0x09e821f5,
+        0x0a4021f5,
 /* 0x063c: chsw_done */
         0xf10127f0,
         0xf0c30007,
@@ -654,7 +654,7 @@ uint32_t nvd7_grhub_code[] = {
 /* 0x0660: main_not_ctx_switch */
         0xf401e4b0,
         0xf2b90d1b,
-        0x7821f502,
+        0xd021f502,
         0x460ef409,
 /* 0x0670: main_not_ctx_chan */
         0xf402e4b0,
@@ -664,8 +664,8 @@ uint32_t nvd7_grhub_code[] = {
         0x09d00203,
         0xf404bd00,
         0x32f40132,
-        0xe821f502,
-        0xf094bd09,
+        0x4021f502,
+        0xf094bd0a,
         0x07f10799,
         0x03f01700,
         0x0009d002,
@@ -710,18 +710,40 @@ uint32_t nvd7_grhub_code[] = {
 /* 0x072b: ih_no_ctxsw */
         0xe40421f4,
         0xf40400ab,
-        0xb7f1140b,
+        0xe7f16c0b,
+        0xe3f00708,
+        0x6821f440,
+        0xf102ffb9,
+        0xf0040007,
+        0x0fd00203,
+        0xf104bd00,
+        0xf00704e7,
+        0x21f440e3,
+        0x02ffb968,
+        0x030007f1,
+        0xd00203f0,
+        0x04bd000f,
+        0x9450fec7,
+        0xf7f102ee,
+        0xf3f00700,
+        0x00efbb40,
+        0xf16821f4,
+        0xf0020007,
+        0x0fd00203,
+        0xf004bd00,
+        0x21f503f7,
+        0xb7f1037e,
         0xbfb90100,
         0x44e7f102,
         0x40e3f001,
-/* 0x0743: ih_no_fwmthd */
+/* 0x079b: ih_no_fwmthd */
         0xf19d21f4,
-        0xbd0104b7,
+        0xbd0504b7,
         0xb4abffb0,
         0xf10f0bf4,
         0xf0070007,
         0x0bd00303,
-/* 0x075b: ih_no_other */
+/* 0x07b3: ih_no_other */
         0xf104bd00,
         0xf0010007,
         0x0ad00003,
@@ -731,36 +753,36 @@ uint32_t nvd7_grhub_code[] = {
         0xfc90fca0,
         0x0088fe80,
         0x32f480fc,
-/* 0x077f: ctx_4160s */
+/* 0x07d7: ctx_4160s */
         0xf001f800,
         0xffb901f7,
         0x60e7f102,
         0x40e3f041,
-/* 0x078f: ctx_4160s_wait */
+/* 0x07e7: ctx_4160s_wait */
         0xf19d21f4,
         0xf04160e7,
         0x21f440e3,
         0x02ffb968,
         0xf404ffc8,
         0x00f8f00b,
-/* 0x07a4: ctx_4160c */
+/* 0x07fc: ctx_4160c */
         0xffb9f4bd,
         0x60e7f102,
         0x40e3f041,
         0xf89d21f4,
-/* 0x07b5: ctx_4170s */
+/* 0x080d: ctx_4170s */
         0x10f5f000,
         0xf102ffb9,
         0xf04170e7,
         0x21f440e3,
-/* 0x07c7: ctx_4170w */
+/* 0x081f: ctx_4170w */
         0xf100f89d,
         0xf04170e7,
         0x21f440e3,
         0x02ffb968,
         0xf410f4f0,
         0x00f8f01b,
-/* 0x07dc: ctx_redswitch */
+/* 0x0834: ctx_redswitch */
         0x0200e7f1,
         0xf040e5f0,
         0xe5f020e5,
@@ -768,7 +790,7 @@ uint32_t nvd7_grhub_code[] = {
         0x0103f085,
         0xbd000ed0,
         0x08f7f004,
-/* 0x07f8: ctx_redswitch_delay */
+/* 0x0850: ctx_redswitch_delay */
         0xf401f2b6,
         0xe5f1fd1b,
         0xe5f10400,
@@ -776,7 +798,7 @@ uint32_t nvd7_grhub_code[] = {
         0x03f08500,
         0x000ed001,
         0x00f804bd,
-/* 0x0814: ctx_86c */
+/* 0x086c: ctx_86c */
         0x1b0007f1,
         0xd00203f0,
         0x04bd000f,
@@ -787,16 +809,16 @@ uint32_t nvd7_grhub_code[] = {
         0xa86ce7f1,
         0xf441e3f0,
         0x00f89d21,
-/* 0x083c: ctx_mem */
+/* 0x0894: ctx_mem */
         0x840007f1,
         0xd00203f0,
         0x04bd000f,
-/* 0x0848: ctx_mem_wait */
+/* 0x08a0: ctx_mem_wait */
         0x8400f7f1,
         0xcf02f3f0,
         0xfffd00ff,
         0xf31bf405,
-/* 0x085a: ctx_load */
+/* 0x08b2: ctx_load */
         0x94bd00f8,
         0xf10599f0,
         0xf00f0007,
@@ -814,7 +836,7 @@ uint32_t nvd7_grhub_code[] = {
         0x02d00203,
         0xf004bd00,
         0x21f507f7,
-        0x07f1083c,
+        0x07f10894,
         0x03f0c000,
         0x0002d002,
         0x0bfe04bd,
@@ -869,31 +891,31 @@ uint32_t nvd7_grhub_code[] = {
         0x03f01700,
         0x0009d002,
         0x00f804bd,
-/* 0x0978: ctx_chan */
-        0x077f21f5,
-        0x085a21f5,
+/* 0x09d0: ctx_chan */
+        0x07d721f5,
+        0x08b221f5,
         0xf40ca7f0,
         0xf7f0d021,
-        0x3c21f505,
-        0xa421f508,
-/* 0x0993: ctx_mmio_exec */
+        0x9421f505,
+        0xfc21f508,
+/* 0x09eb: ctx_mmio_exec */
         0x9800f807,
         0x07f14103,
         0x03f08100,
         0x0003d002,
         0x34bd04bd,
-/* 0x09a4: ctx_mmio_loop */
+/* 0x09fc: ctx_mmio_loop */
         0xf4ff34c4,
         0x57f10f1b,
         0x53f00200,
         0x0535fa06,
-/* 0x09b6: ctx_mmio_pull */
+/* 0x0a0e: ctx_mmio_pull */
         0x4e9803f8,
         0x814f9880,
         0xb69d21f4,
         0x12b60830,
         0xdf1bf401,
-/* 0x09c8: ctx_mmio_done */
+/* 0x0a20: ctx_mmio_done */
         0xf1160398,
         0xf0810007,
         0x03d00203,
@@ -902,30 +924,30 @@ uint32_t nvd7_grhub_code[] = {
         0x13f00100,
         0x0601fa06,
         0x00f803f8,
-/* 0x09e8: ctx_xfer */
+/* 0x0a40: ctx_xfer */
         0xf104e7f0,
         0xf0020007,
         0x0ed00303,
-/* 0x09f7: ctx_xfer_idle */
+/* 0x0a4f: ctx_xfer_idle */
         0xf104bd00,
         0xf00000e7,
         0xeecf03e3,
         0x00e4f100,
         0xf21bf420,
         0xf40611f4,
-/* 0x0a0e: ctx_xfer_pre */
+/* 0x0a66: ctx_xfer_pre */
         0xf7f01102,
-        0x1421f510,
-        0x7f21f508,
+        0x6c21f510,
+        0xd721f508,
         0x1c11f407,
-/* 0x0a1c: ctx_xfer_pre_load */
+/* 0x0a74: ctx_xfer_pre_load */
         0xf502f7f0,
-        0xf507b521,
-        0xf507c721,
-        0xbd07dc21,
-        0xb521f5f4,
-        0x5a21f507,
-/* 0x0a35: ctx_xfer_exec */
+        0xf5080d21,
+        0xf5081f21,
+        0xbd083421,
+        0x0d21f5f4,
+        0xb221f508,
+/* 0x0a8d: ctx_xfer_exec */
         0x16019808,
         0x07f124bd,
         0x03f00500,
@@ -960,23 +982,65 @@ uint32_t nvd7_grhub_code[] = {
         0x1301f402,
         0xf40ca7f0,
         0xf7f0d021,
-        0x3c21f505,
+        0x9421f505,
         0x3202f408,
-/* 0x0ac4: ctx_xfer_post */
+/* 0x0b1c: ctx_xfer_post */
         0xf502f7f0,
-        0xbd07b521,
-        0x1421f5f4,
+        0xbd080d21,
+        0x6c21f5f4,
         0x7f21f508,
-        0xc721f502,
-        0xf5f4bd07,
-        0xf407b521,
+        0x1f21f502,
+        0xf5f4bd08,
+        0xf4080d21,
         0x01981011,
         0x0511fd40,
         0xf5070bf4,
-/* 0x0aef: ctx_xfer_no_post_mmio */
-        0xf5099321,
-/* 0x0af3: ctx_xfer_done */
-        0xf807a421,
+/* 0x0b47: ctx_xfer_no_post_mmio */
+        0xf509eb21,
+/* 0x0b4b: ctx_xfer_done */
+        0xf807fc21,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
         0x00000000,
         0x00000000,
         0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
index 6547b3dfc7ed..51c3797d8537 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
@@ -528,10 +528,10 @@ uint32_t nve0_grhub_code[] = {
         0x0001d001,
         0x17f104bd,
         0xf7f00100,
-        0x7f21f502,
-        0x9121f507,
+        0xd721f502,
+        0xe921f507,
         0x10f7f007,
-        0x07de21f5,
+        0x083621f5,
         0x98000e98,
         0x21f5010f,
         0x14950150,
@@ -574,9 +574,9 @@ uint32_t nve0_grhub_code[] = {
         0xb6800040,
         0x1bf40132,
         0x00f7f0be,
-        0x07de21f5,
+        0x083621f5,
         0xf500f7f0,
-        0xf1077f21,
+        0xf107d721,
         0xf0010007,
         0x01d00203,
         0xbd04bd00,
@@ -610,8 +610,8 @@ uint32_t nve0_grhub_code[] = {
         0x09d00203,
         0xf404bd00,
         0x31f40132,
-        0xaa21f502,
-        0xf094bd09,
+        0x0221f502,
+        0xf094bd0a,
         0x07f10799,
         0x03f01700,
         0x0009d002,
@@ -621,7 +621,7 @@ uint32_t nve0_grhub_code[] = {
         0x0203f00f,
         0xbd0009d0,
         0x0131f404,
-        0x09aa21f5,
+        0x0a0221f5,
         0x99f094bd,
         0x0007f106,
         0x0203f017,
@@ -631,7 +631,7 @@ uint32_t nve0_grhub_code[] = {
         0x12b920f9,
         0x0132f402,
         0xf50232f4,
-        0xfc09aa21,
+        0xfc0a0221,
         0x0007f120,
         0x0203f0c0,
         0xbd0002d0,
@@ -640,7 +640,7 @@ uint32_t nve0_grhub_code[] = {
         0xf41f23c8,
         0x31f40d0b,
         0x0232f401,
-        0x09aa21f5,
+        0x0a0221f5,
 /* 0x063c: chsw_done */
         0xf10127f0,
         0xf0c30007,
@@ -654,7 +654,7 @@ uint32_t nve0_grhub_code[] = {
 /* 0x0660: main_not_ctx_switch */
         0xf401e4b0,
         0xf2b90d1b,
-        0x4221f502,
+        0x9a21f502,
         0x460ef409,
 /* 0x0670: main_not_ctx_chan */
         0xf402e4b0,
@@ -664,8 +664,8 @@ uint32_t nve0_grhub_code[] = {
         0x09d00203,
         0xf404bd00,
         0x32f40132,
-        0xaa21f502,
-        0xf094bd09,
+        0x0221f502,
+        0xf094bd0a,
         0x07f10799,
         0x03f01700,
         0x0009d002,
@@ -710,18 +710,40 @@ uint32_t nve0_grhub_code[] = {
 /* 0x072b: ih_no_ctxsw */
         0xe40421f4,
         0xf40400ab,
-        0xb7f1140b,
+        0xe7f16c0b,
+        0xe3f00708,
+        0x6821f440,
+        0xf102ffb9,
+        0xf0040007,
+        0x0fd00203,
+        0xf104bd00,
+        0xf00704e7,
+        0x21f440e3,
+        0x02ffb968,
+        0x030007f1,
+        0xd00203f0,
+        0x04bd000f,
+        0x9450fec7,
+        0xf7f102ee,
+        0xf3f00700,
+        0x00efbb40,
+        0xf16821f4,
+        0xf0020007,
+        0x0fd00203,
+        0xf004bd00,
+        0x21f503f7,
+        0xb7f1037e,
         0xbfb90100,
         0x44e7f102,
         0x40e3f001,
-/* 0x0743: ih_no_fwmthd */
+/* 0x079b: ih_no_fwmthd */
         0xf19d21f4,
-        0xbd0104b7,
+        0xbd0504b7,
         0xb4abffb0,
         0xf10f0bf4,
         0xf0070007,
         0x0bd00303,
-/* 0x075b: ih_no_other */
+/* 0x07b3: ih_no_other */
         0xf104bd00,
         0xf0010007,
         0x0ad00003,
@@ -731,19 +753,19 @@ uint32_t nve0_grhub_code[] = {
         0xfc90fca0,
         0x0088fe80,
         0x32f480fc,
-/* 0x077f: ctx_4170s */
+/* 0x07d7: ctx_4170s */
         0xf001f800,
         0xffb910f5,
         0x70e7f102,
         0x40e3f041,
         0xf89d21f4,
-/* 0x0791: ctx_4170w */
+/* 0x07e9: ctx_4170w */
         0x70e7f100,
         0x40e3f041,
         0xb96821f4,
         0xf4f002ff,
         0xf01bf410,
-/* 0x07a6: ctx_redswitch */
+/* 0x07fe: ctx_redswitch */
         0xe7f100f8,
         0xe5f00200,
         0x20e5f040,
@@ -751,7 +773,7 @@ uint32_t nve0_grhub_code[] = {
         0xf0850007,
         0x0ed00103,
         0xf004bd00,
-/* 0x07c2: ctx_redswitch_delay */
+/* 0x081a: ctx_redswitch_delay */
         0xf2b608f7,
         0xfd1bf401,
         0x0400e5f1,
@@ -759,7 +781,7 @@ uint32_t nve0_grhub_code[] = {
         0x850007f1,
         0xd00103f0,
         0x04bd000e,
-/* 0x07de: ctx_86c */
+/* 0x0836: ctx_86c */
         0x07f100f8,
         0x03f01b00,
         0x000fd002,
@@ -770,17 +792,17 @@ uint32_t nve0_grhub_code[] = {
         0xe7f102ff,
         0xe3f0a86c,
         0x9d21f441,
-/* 0x0806: ctx_mem */
+/* 0x085e: ctx_mem */
         0x07f100f8,
         0x03f08400,
         0x000fd002,
-/* 0x0812: ctx_mem_wait */
+/* 0x086a: ctx_mem_wait */
         0xf7f104bd,
         0xf3f08400,
         0x00ffcf02,
         0xf405fffd,
         0x00f8f31b,
-/* 0x0824: ctx_load */
+/* 0x087c: ctx_load */
         0x99f094bd,
         0x0007f105,
         0x0203f00f,
@@ -797,7 +819,7 @@ uint32_t nve0_grhub_code[] = {
         0x0203f083,
         0xbd0002d0,
         0x07f7f004,
-        0x080621f5,
+        0x085e21f5,
         0xc00007f1,
         0xd00203f0,
         0x04bd0002,
@@ -852,29 +874,29 @@ uint32_t nve0_grhub_code[] = {
         0x170007f1,
         0xd00203f0,
         0x04bd0009,
-/* 0x0942: ctx_chan */
+/* 0x099a: ctx_chan */
         0x21f500f8,
-        0xa7f00824,
+        0xa7f0087c,
         0xd021f40c,
         0xf505f7f0,
-        0xf8080621,
-/* 0x0955: ctx_mmio_exec */
+        0xf8085e21,
+/* 0x09ad: ctx_mmio_exec */
         0x41039800,
         0x810007f1,
         0xd00203f0,
         0x04bd0003,
-/* 0x0966: ctx_mmio_loop */
+/* 0x09be: ctx_mmio_loop */
         0x34c434bd,
         0x0f1bf4ff,
         0x020057f1,
         0xfa0653f0,
         0x03f80535,
-/* 0x0978: ctx_mmio_pull */
+/* 0x09d0: ctx_mmio_pull */
         0x98804e98,
         0x21f4814f,
         0x0830b69d,
         0xf40112b6,
-/* 0x098a: ctx_mmio_done */
+/* 0x09e2: ctx_mmio_done */
         0x0398df1b,
         0x0007f116,
         0x0203f081,
@@ -883,30 +905,30 @@ uint32_t nve0_grhub_code[] = {
         0x010017f1,
         0xfa0613f0,
         0x03f80601,
-/* 0x09aa: ctx_xfer */
+/* 0x0a02: ctx_xfer */
         0xe7f000f8,
         0x0007f104,
         0x0303f002,
         0xbd000ed0,
-/* 0x09b9: ctx_xfer_idle */
+/* 0x0a11: ctx_xfer_idle */
         0x00e7f104,
         0x03e3f000,
         0xf100eecf,
         0xf42000e4,
         0x11f4f21b,
         0x0d02f406,
-/* 0x09d0: ctx_xfer_pre */
+/* 0x0a28: ctx_xfer_pre */
         0xf510f7f0,
-        0xf407de21,
-/* 0x09da: ctx_xfer_pre_load */
+        0xf4083621,
+/* 0x0a32: ctx_xfer_pre_load */
         0xf7f01c11,
-        0x7f21f502,
-        0x9121f507,
-        0xa621f507,
+        0xd721f502,
+        0xe921f507,
+        0xfe21f507,
         0xf5f4bd07,
-        0xf5077f21,
-/* 0x09f3: ctx_xfer_exec */
-        0x98082421,
+        0xf507d721,
+/* 0x0a4b: ctx_xfer_exec */
+        0x98087c21,
         0x24bd1601,
         0x050007f1,
         0xd00103f0,
@@ -941,21 +963,21 @@ uint32_t nve0_grhub_code[] = {
         0xa7f01301,
         0xd021f40c,
         0xf505f7f0,
-        0xf4080621,
-/* 0x0a82: ctx_xfer_post */
+        0xf4085e21,
+/* 0x0ada: ctx_xfer_post */
         0xf7f02e02,
-        0x7f21f502,
+        0xd721f502,
         0xf5f4bd07,
-        0xf507de21,
+        0xf5083621,
         0xf5027f21,
-        0xbd079121,
-        0x7f21f5f4,
+        0xbd07e921,
+        0xd721f5f4,
         0x1011f407,
         0xfd400198,
         0x0bf40511,
-        0x5521f507,
-/* 0x0aad: ctx_xfer_no_post_mmio */
-/* 0x0aad: ctx_xfer_done */
+        0xad21f507,
+/* 0x0b05: ctx_xfer_no_post_mmio */
+/* 0x0b05: ctx_xfer_done */
         0x0000f809,
         0x00000000,
         0x00000000,
@@ -977,4 +999,46 @@ uint32_t nve0_grhub_code[] = {
         0x00000000,
         0x00000000,
         0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
 };
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
index a5aee5a4302f..a0af4b703a8e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
@@ -528,10 +528,10 @@ uint32_t nvf0_grhub_code[] = {
         0x0001d001,
         0x17f104bd,
         0xf7f00100,
-        0x7f21f502,
-        0x9121f507,
+        0xd721f502,
+        0xe921f507,
         0x10f7f007,
-        0x07de21f5,
+        0x083621f5,
         0x98000e98,
         0x21f5010f,
         0x14950150,
@@ -574,9 +574,9 @@ uint32_t nvf0_grhub_code[] = {
         0xb6800040,
         0x1bf40132,
         0x00f7f0be,
-        0x07de21f5,
+        0x083621f5,
         0xf500f7f0,
-        0xf1077f21,
+        0xf107d721,
         0xf0010007,
         0x01d00203,
         0xbd04bd00,
@@ -610,8 +610,8 @@ uint32_t nvf0_grhub_code[] = {
         0x09d00203,
         0xf404bd00,
         0x31f40132,
-        0xaa21f502,
-        0xf094bd09,
+        0x0221f502,
+        0xf094bd0a,
         0x07f10799,
         0x03f01700,
         0x0009d002,
@@ -621,7 +621,7 @@ uint32_t nvf0_grhub_code[] = {
         0x0203f037,
         0xbd0009d0,
         0x0131f404,
-        0x09aa21f5,
+        0x0a0221f5,
         0x99f094bd,
         0x0007f106,
         0x0203f017,
@@ -631,7 +631,7 @@ uint32_t nvf0_grhub_code[] = {
         0x12b920f9,
         0x0132f402,
         0xf50232f4,
-        0xfc09aa21,
+        0xfc0a0221,
         0x0007f120,
         0x0203f0c0,
         0xbd0002d0,
@@ -640,7 +640,7 @@ uint32_t nvf0_grhub_code[] = {
         0xf41f23c8,
         0x31f40d0b,
         0x0232f401,
-        0x09aa21f5,
+        0x0a0221f5,
 /* 0x063c: chsw_done */
         0xf10127f0,
         0xf0c30007,
@@ -654,7 +654,7 @@ uint32_t nvf0_grhub_code[] = {
 /* 0x0660: main_not_ctx_switch */
         0xf401e4b0,
         0xf2b90d1b,
-        0x4221f502,
+        0x9a21f502,
         0x460ef409,
 /* 0x0670: main_not_ctx_chan */
         0xf402e4b0,
@@ -664,8 +664,8 @@ uint32_t nvf0_grhub_code[] = {
         0x09d00203,
         0xf404bd00,
         0x32f40132,
-        0xaa21f502,
-        0xf094bd09,
+        0x0221f502,
+        0xf094bd0a,
         0x07f10799,
         0x03f01700,
         0x0009d002,
@@ -710,18 +710,40 @@ uint32_t nvf0_grhub_code[] = {
 /* 0x072b: ih_no_ctxsw */
         0xe40421f4,
         0xf40400ab,
-        0xb7f1140b,
+        0xe7f16c0b,
+        0xe3f00708,
+        0x6821f440,
+        0xf102ffb9,
+        0xf0040007,
+        0x0fd00203,
+        0xf104bd00,
+        0xf00704e7,
+        0x21f440e3,
+        0x02ffb968,
+        0x030007f1,
+        0xd00203f0,
+        0x04bd000f,
+        0x9450fec7,
+        0xf7f102ee,
+        0xf3f00700,
+        0x00efbb40,
+        0xf16821f4,
+        0xf0020007,
+        0x0fd00203,
+        0xf004bd00,
+        0x21f503f7,
+        0xb7f1037e,
         0xbfb90100,
         0x44e7f102,
         0x40e3f001,
-/* 0x0743: ih_no_fwmthd */
+/* 0x079b: ih_no_fwmthd */
         0xf19d21f4,
-        0xbd0104b7,
+        0xbd0504b7,
         0xb4abffb0,
         0xf10f0bf4,
         0xf0070007,
         0x0bd00303,
-/* 0x075b: ih_no_other */
+/* 0x07b3: ih_no_other */
         0xf104bd00,
         0xf0010007,
         0x0ad00003,
@@ -731,19 +753,19 @@ uint32_t nvf0_grhub_code[] = {
         0xfc90fca0,
         0x0088fe80,
         0x32f480fc,
-/* 0x077f: ctx_4170s */
+/* 0x07d7: ctx_4170s */
         0xf001f800,
         0xffb910f5,
         0x70e7f102,
         0x40e3f041,
         0xf89d21f4,
-/* 0x0791: ctx_4170w */
+/* 0x07e9: ctx_4170w */
         0x70e7f100,
         0x40e3f041,
         0xb96821f4,
         0xf4f002ff,
         0xf01bf410,
-/* 0x07a6: ctx_redswitch */
+/* 0x07fe: ctx_redswitch */
         0xe7f100f8,
         0xe5f00200,
         0x20e5f040,
@@ -751,7 +773,7 @@ uint32_t nvf0_grhub_code[] = {
         0xf0850007,
         0x0ed00103,
         0xf004bd00,
-/* 0x07c2: ctx_redswitch_delay */
+/* 0x081a: ctx_redswitch_delay */
         0xf2b608f7,
         0xfd1bf401,
         0x0400e5f1,
@@ -759,7 +781,7 @@ uint32_t nvf0_grhub_code[] = {
         0x850007f1,
         0xd00103f0,
         0x04bd000e,
-/* 0x07de: ctx_86c */
+/* 0x0836: ctx_86c */
         0x07f100f8,
         0x03f02300,
         0x000fd002,
@@ -770,17 +792,17 @@ uint32_t nvf0_grhub_code[] = {
         0xe7f102ff,
         0xe3f0a88c,
         0x9d21f441,
-/* 0x0806: ctx_mem */
+/* 0x085e: ctx_mem */
         0x07f100f8,
         0x03f08400,
         0x000fd002,
-/* 0x0812: ctx_mem_wait */
+/* 0x086a: ctx_mem_wait */
         0xf7f104bd,
         0xf3f08400,
         0x00ffcf02,
         0xf405fffd,
         0x00f8f31b,
-/* 0x0824: ctx_load */
+/* 0x087c: ctx_load */
         0x99f094bd,
         0x0007f105,
         0x0203f037,
@@ -797,7 +819,7 @@ uint32_t nvf0_grhub_code[] = {
         0x0203f083,
         0xbd0002d0,
         0x07f7f004,
-        0x080621f5,
+        0x085e21f5,
         0xc00007f1,
         0xd00203f0,
         0x04bd0002,
@@ -852,29 +874,29 @@ uint32_t nvf0_grhub_code[] = {
         0x170007f1,
         0xd00203f0,
         0x04bd0009,
-/* 0x0942: ctx_chan */
+/* 0x099a: ctx_chan */
         0x21f500f8,
-        0xa7f00824,
+        0xa7f0087c,
         0xd021f40c,
         0xf505f7f0,
-        0xf8080621,
-/* 0x0955: ctx_mmio_exec */
+        0xf8085e21,
+/* 0x09ad: ctx_mmio_exec */
         0x41039800,
         0x810007f1,
         0xd00203f0,
         0x04bd0003,
-/* 0x0966: ctx_mmio_loop */
+/* 0x09be: ctx_mmio_loop */
         0x34c434bd,
         0x0f1bf4ff,
         0x020057f1,
         0xfa0653f0,
         0x03f80535,
-/* 0x0978: ctx_mmio_pull */
+/* 0x09d0: ctx_mmio_pull */
         0x98804e98,
         0x21f4814f,
         0x0830b69d,
         0xf40112b6,
-/* 0x098a: ctx_mmio_done */
+/* 0x09e2: ctx_mmio_done */
         0x0398df1b,
         0x0007f116,
         0x0203f081,
@@ -883,30 +905,30 @@ uint32_t nvf0_grhub_code[] = {
         0x010017f1,
         0xfa0613f0,
         0x03f80601,
-/* 0x09aa: ctx_xfer */
+/* 0x0a02: ctx_xfer */
         0xe7f000f8,
         0x0007f104,
         0x0303f002,
         0xbd000ed0,
-/* 0x09b9: ctx_xfer_idle */
+/* 0x0a11: ctx_xfer_idle */
         0x00e7f104,
         0x03e3f000,
         0xf100eecf,
         0xf42000e4,
         0x11f4f21b,
         0x0d02f406,
-/* 0x09d0: ctx_xfer_pre */
+/* 0x0a28: ctx_xfer_pre */
         0xf510f7f0,
-        0xf407de21,
-/* 0x09da: ctx_xfer_pre_load */
+        0xf4083621,
+/* 0x0a32: ctx_xfer_pre_load */
         0xf7f01c11,
-        0x7f21f502,
-        0x9121f507,
-        0xa621f507,
+        0xd721f502,
+        0xe921f507,
+        0xfe21f507,
         0xf5f4bd07,
-        0xf5077f21,
-/* 0x09f3: ctx_xfer_exec */
-        0x98082421,
+        0xf507d721,
+/* 0x0a4b: ctx_xfer_exec */
+        0x98087c21,
         0x24bd1601,
         0x050007f1,
         0xd00103f0,
@@ -941,21 +963,21 @@ uint32_t nvf0_grhub_code[] = {
         0xa7f01301,
         0xd021f40c,
         0xf505f7f0,
-        0xf4080621,
-/* 0x0a82: ctx_xfer_post */
+        0xf4085e21,
+/* 0x0ada: ctx_xfer_post */
         0xf7f02e02,
-        0x7f21f502,
+        0xd721f502,
         0xf5f4bd07,
-        0xf507de21,
+        0xf5083621,
         0xf5027f21,
-        0xbd079121,
-        0x7f21f5f4,
+        0xbd07e921,
+        0xd721f5f4,
         0x1011f407,
         0xfd400198,
         0x0bf40511,
-        0x5521f507,
-/* 0x0aad: ctx_xfer_no_post_mmio */
-/* 0x0aad: ctx_xfer_done */
+        0xad21f507,
+/* 0x0b05: ctx_xfer_no_post_mmio */
+/* 0x0b05: ctx_xfer_done */
         0x0000f809,
         0x00000000,
         0x00000000,
@@ -977,4 +999,46 @@ uint32_t nvf0_grhub_code[] = {
         0x00000000,
         0x00000000,
         0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
 };
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
index a47d49db5232..2a0b0f844299 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
@@ -30,6 +30,12 @@
 #define GK110 0xf0
 #define GK208 0x108
 
+#define NV_PGRAPH_TRAPPED_ADDR                                         0x400704
+#define NV_PGRAPH_TRAPPED_DATA_LO                                      0x400708
+#define NV_PGRAPH_TRAPPED_DATA_HI                                      0x40070c
+
+#define NV_PGRAPH_FE_OBJECT_TABLE(n)                        ((n) * 4 + 0x400700)
+
 #define NV_PGRAPH_FECS_INTR_ACK                                        0x409004
 #define NV_PGRAPH_FECS_INTR                                            0x409008
 #define NV_PGRAPH_FECS_INTR_FWMTHD                                   0x00000400
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h
index fd1d380de094..1718ae4e8224 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h
@@ -3,5 +3,6 @@
 
 #define E_BAD_COMMAND  0x00000001
 #define E_CMD_OVERFLOW 0x00000002
+#define E_BAD_FWMTHD   0x00000003
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
index 1a2d56493cf6..20665c21d80e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -976,7 +976,6 @@ nv50_graph_init(struct nouveau_object *object)
                 break;
         case 0xa0:
         default:
-                nv_wr32(priv, 0x402cc0, 0x00000000);
                 if (nv_device(priv)->chipset == 0xa0 ||
                     nv_device(priv)->chipset == 0xaa ||
                     nv_device(priv)->chipset == 0xac) {
@@ -991,10 +990,10 @@ nv50_graph_init(struct nouveau_object *object)
 
         /* zero out zcull regions */
         for (i = 0; i < 8; i++) {
-                nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000);
-                nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000);
-                nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000);
-                nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000);
+                nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000);
+                nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000);
+                nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000);
+                nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000);
         }
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index bf7bdb1f291e..aa0838916354 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -789,17 +789,40 @@ nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv)
 static void
 nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
 {
-        u32 ustat = nv_rd32(priv, 0x409c18);
+        u32 stat = nv_rd32(priv, 0x409c18);
 
-        if (ustat & 0x00000001)
-                nv_error(priv, "CTXCTL ucode error\n");
-        if (ustat & 0x00080000)
-                nv_error(priv, "CTXCTL watchdog timeout\n");
-        if (ustat & ~0x00080001)
-                nv_error(priv, "CTXCTL 0x%08x\n", ustat);
+        if (stat & 0x00000001) {
+                u32 code = nv_rd32(priv, 0x409814);
+                if (code == E_BAD_FWMTHD) {
+                        u32 class = nv_rd32(priv, 0x409808);
+                        u32  addr = nv_rd32(priv, 0x40980c);
+                        u32  subc = (addr & 0x00070000) >> 16;
+                        u32  mthd = (addr & 0x00003ffc);
+                        u32  data = nv_rd32(priv, 0x409810);
+
+                        nv_error(priv, "FECS MTHD subc %d class 0x%04x "
+                                       "mthd 0x%04x data 0x%08x\n",
+                                 subc, class, mthd, data);
 
-        nvc0_graph_ctxctl_debug(priv);
-        nv_wr32(priv, 0x409c20, ustat);
+                        nv_wr32(priv, 0x409c20, 0x00000001);
+                        stat &= ~0x00000001;
+                } else {
+                        nv_error(priv, "FECS ucode error %d\n", code);
+                }
+        }
+
+        if (stat & 0x00080000) {
+                nv_error(priv, "FECS watchdog timeout\n");
+                nvc0_graph_ctxctl_debug(priv);
+                nv_wr32(priv, 0x409c20, 0x00080000);
+                stat &= ~0x00080000;
+        }
+
+        if (stat) {
+                nv_error(priv, "FECS 0x%08x\n", stat);
+                nvc0_graph_ctxctl_debug(priv);
+                nv_wr32(priv, 0x409c20, stat);
+        }
 }
 
 static void
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
index 75203a99d902..ffc289198dd8 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
@@ -38,6 +38,8 @@
 #include <engine/fifo.h>
 #include <engine/graph.h>
 
+#include "fuc/os.h"
+
 #define GPC_MAX 32
 #define TPC_MAX (GPC_MAX * 8)
 
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h b/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
index db1b39d08013..825f7bb46b67 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
@@ -84,6 +84,7 @@ extern struct nouveau_oclass *nv4e_i2c_oclass;
 extern struct nouveau_oclass *nv50_i2c_oclass;
 extern struct nouveau_oclass *nv94_i2c_oclass;
 extern struct nouveau_oclass *nvd0_i2c_oclass;
+extern struct nouveau_oclass *gf117_i2c_oclass;
 extern struct nouveau_oclass *nve0_i2c_oclass;
 
 static inline int
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c
index 4ac1aa30ea11..0e62a3240144 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c
@@ -307,7 +307,6 @@ calc_clk(struct nve0_clock_priv *priv,
                 info->dsrc = src0;
                 if (div0) {
                         info->ddiv |= 0x80000000;
-                        info->ddiv |= div0 << 8;
                         info->ddiv |= div0;
                 }
                 if (div1D) {
@@ -352,7 +351,7 @@ nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk)
 {
         struct nve0_clock_info *info = &priv->eng[clk];
         if (!info->ssel) {
-                nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
+                nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv);
                 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
         }
 }
@@ -389,7 +388,10 @@ static void
 nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk)
 {
         struct nve0_clock_info *info = &priv->eng[clk];
-        nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
+        if (info->ssel)
+                nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv);
+        else
+                nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv);
 }
 
 static void
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h
index 0f57fcfe0bbf..2af9cfd2c60f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h
@@ -26,7 +26,7 @@ ramfuc_reg2(u32 addr1, u32 addr2)
         };
 }
 
-static inline struct ramfuc_reg
+static noinline struct ramfuc_reg
 ramfuc_reg(u32 addr)
 {
         return ramfuc_reg2(addr, addr);
@@ -107,7 +107,7 @@ ramfuc_nsec(struct ramfuc *ram, u32 nsec)
 
 #define ram_init(s,p)       ramfuc_init(&(s)->base, (p))
 #define ram_exec(s,e)       ramfuc_exec(&(s)->base, (e))
-#define ram_have(s,r)       ((s)->r_##r.addr != 0x000000)
+#define ram_have(s,r)       ((s)->r_##r.addr[0] != 0x000000)
 #define ram_rd32(s,r)       ramfuc_rd32(&(s)->base, &(s)->r_##r)
 #define ram_wr32(s,r,d)     ramfuc_wr32(&(s)->base, &(s)->r_##r, (d))
 #define ram_nuke(s,r)       ramfuc_nuke(&(s)->base, &(s)->r_##r)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
index 84c7efbc4f38..c5b46e302319 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
@@ -200,6 +200,7 @@ r1373f4_init(struct nve0_ramfuc *fuc)
         /* (re)program mempll, if required */
         if (ram->mode == 2) {
                 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
+                ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
                 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
                 ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
                 ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
@@ -262,8 +263,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
         struct nve0_ram *ram = (void *)pfb->ram;
         struct nve0_ramfuc *fuc = &ram->fuc;
         struct nouveau_ram_data *next = ram->base.next;
-        int vc = !(next->bios.ramcfg_11_02_08);
-        int mv = !(next->bios.ramcfg_11_02_04);
+        int vc = !next->bios.ramcfg_11_02_08;
+        int mv = !next->bios.ramcfg_11_02_04;
         u32 mask, data;
 
         ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
@@ -370,8 +371,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
                 }
         }
 
-        if ( (next->bios.ramcfg_11_02_40) ||
-             (next->bios.ramcfg_11_07_10)) {
+        if (next->bios.ramcfg_11_02_40 ||
+            next->bios.ramcfg_11_07_10) {
                 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
                 ram_nsec(fuc, 20000);
         }
@@ -417,7 +418,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
                 ram_mask(fuc, 0x10f694, 0xff00ff00, data);
         }
 
-        if (ram->mode == 2 && (next->bios.ramcfg_11_08_10))
+        if (ram->mode == 2 && next->bios.ramcfg_11_08_10)
                 data = 0x00000080;
         else
                 data = 0x00000000;
@@ -425,13 +426,13 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
 
         mask = 0x00070000;
         data = 0x00000000;
-        if (!(next->bios.ramcfg_11_02_80))
+        if (!next->bios.ramcfg_11_02_80)
                 data |= 0x03000000;
-        if (!(next->bios.ramcfg_11_02_40))
+        if (!next->bios.ramcfg_11_02_40)
                 data |= 0x00002000;
-        if (!(next->bios.ramcfg_11_07_10))
+        if (!next->bios.ramcfg_11_07_10)
                 data |= 0x00004000;
-        if (!(next->bios.ramcfg_11_07_08))
+        if (!next->bios.ramcfg_11_07_08)
                 data |= 0x00000003;
         else
                 data |= 0x74000000;
@@ -486,7 +487,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
 
         data = mask = 0x00000000;
         if (NOTE00(ramcfg_02_03 != 0)) {
-                data |= (next->bios.ramcfg_11_02_03) << 8;
+                data |= next->bios.ramcfg_11_02_03 << 8;
                 mask |= 0x00000300;
         }
         if (NOTE00(ramcfg_01_10)) {
@@ -498,7 +499,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
 
         data = mask = 0x00000000;
         if (NOTE00(timing_30_07 != 0)) {
-                data |= (next->bios.timing_20_30_07) << 28;
+                data |= next->bios.timing_20_30_07 << 28;
                 mask |= 0x70000000;
         }
         if (NOTE00(ramcfg_01_01)) {
@@ -510,7 +511,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
 
         data = mask = 0x00000000;
         if (NOTE00(timing_30_07 != 0)) {
-                data |= (next->bios.timing_20_30_07) << 28;
+                data |= next->bios.timing_20_30_07 << 28;
                 mask |= 0x70000000;
         }
         if (NOTE00(ramcfg_01_02)) {
@@ -522,16 +523,16 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
 
         mask = 0x33f00000;
         data = 0x00000000;
-        if (!(next->bios.ramcfg_11_01_04))
+        if (!next->bios.ramcfg_11_01_04)
                 data |= 0x20200000;
-        if (!(next->bios.ramcfg_11_07_80))
+        if (!next->bios.ramcfg_11_07_80)
                 data |= 0x12800000;
         /*XXX: see note above about there probably being some condition
          *     for the 10f824 stuff that uses ramcfg 3...
          */
-        if ( (next->bios.ramcfg_11_03_f0)) {
+        if (next->bios.ramcfg_11_03_f0) {
                 if (next->bios.rammap_11_08_0c) {
-                        if (!(next->bios.ramcfg_11_07_80))
+                        if (!next->bios.ramcfg_11_07_80)
                                 mask |= 0x00000020;
                         else
                                 data |= 0x00000020;
@@ -563,7 +564,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
                 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
         }
 
-        data = (next->bios.timing_20_30_07) << 8;
+        data = next->bios.timing_20_30_07 << 8;
         if (next->bios.ramcfg_11_01_01)
                 data |= 0x80000000;
         ram_mask(fuc, 0x100778, 0x00000700, data);
@@ -588,7 +589,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
         ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
         ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
 
-        if ((next->bios.ramcfg_11_08_10) && (ram->mode == 2) /*XXX*/) {
+        if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
                 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
                 nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
                 ram_nsec(fuc, 1000);
@@ -621,8 +622,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
         data  = ram_rd32(fuc, 0x10f978);
         data &= ~0x00046144;
         data |=  0x0000000b;
-        if (!(next->bios.ramcfg_11_07_08)) {
-                if (!(next->bios.ramcfg_11_07_04))
+        if (!next->bios.ramcfg_11_07_08) {
+                if (!next->bios.ramcfg_11_07_04)
                         data |= 0x0000200c;
                 else
                         data |= 0x00000000;
@@ -636,11 +637,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
                 ram_wr32(fuc, 0x10f830, data);
         }
 
-        if (!(next->bios.ramcfg_11_07_08)) {
+        if (!next->bios.ramcfg_11_07_08) {
                 data = 0x88020000;
-                if ( (next->bios.ramcfg_11_07_04))
+                if ( next->bios.ramcfg_11_07_04)
                         data |= 0x10000000;
-                if (!(next->bios.rammap_11_08_10))
+                if (!next->bios.rammap_11_08_10)
                         data |= 0x00080000;
         } else {
                 data = 0xa40e0000;
@@ -689,8 +690,8 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
         const u32 runk0 = ram->fN1 << 16;
         const u32 runk1 = ram->fN1;
         struct nouveau_ram_data *next = ram->base.next;
-        int vc = !(next->bios.ramcfg_11_02_08);
-        int mv = !(next->bios.ramcfg_11_02_04);
+        int vc = !next->bios.ramcfg_11_02_08;
+        int mv = !next->bios.ramcfg_11_02_04;
         u32 mask, data;
 
         ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
@@ -705,7 +706,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
         }
 
         ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
-        if ((next->bios.ramcfg_11_03_f0))
+        if (next->bios.ramcfg_11_03_f0)
                 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
 
         ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
@@ -761,7 +762,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
 
         ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
         data  = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
-        data |= (next->bios.ramcfg_11_03_30) << 12;
+        data |= next->bios.ramcfg_11_03_30 << 16;
         ram_wr32(fuc, 0x1373ec, data);
         ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
         ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
@@ -793,8 +794,8 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
                 }
         }
 
-        if ( (next->bios.ramcfg_11_02_40) ||
-             (next->bios.ramcfg_11_07_10)) {
+        if (next->bios.ramcfg_11_02_40 ||
+            next->bios.ramcfg_11_07_10) {
                 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
                 ram_nsec(fuc, 20000);
         }
@@ -810,13 +811,13 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
 
         mask = 0x00010000;
         data = 0x00000000;
-        if (!(next->bios.ramcfg_11_02_80))
+        if (!next->bios.ramcfg_11_02_80)
                 data |= 0x03000000;
-        if (!(next->bios.ramcfg_11_02_40))
+        if (!next->bios.ramcfg_11_02_40)
                 data |= 0x00002000;
-        if (!(next->bios.ramcfg_11_07_10))
+        if (!next->bios.ramcfg_11_07_10)
                 data |= 0x00004000;
-        if (!(next->bios.ramcfg_11_07_08))
+        if (!next->bios.ramcfg_11_07_08)
                 data |= 0x00000003;
         else
                 data |= 0x14000000;
@@ -844,16 +845,16 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
 
         mask = 0x33f00000;
         data = 0x00000000;
-        if (!(next->bios.ramcfg_11_01_04))
+        if (!next->bios.ramcfg_11_01_04)
                 data |= 0x20200000;
-        if (!(next->bios.ramcfg_11_07_80))
+        if (!next->bios.ramcfg_11_07_80)
                 data |= 0x12800000;
         /*XXX: see note above about there probably being some condition
          *     for the 10f824 stuff that uses ramcfg 3...
          */
-        if ( (next->bios.ramcfg_11_03_f0)) {
+        if (next->bios.ramcfg_11_03_f0) {
                 if (next->bios.rammap_11_08_0c) {
-                        if (!(next->bios.ramcfg_11_07_80))
+                        if (!next->bios.ramcfg_11_07_80)
                                 mask |= 0x00000020;
                         else
                                 data |= 0x00000020;
@@ -876,7 +877,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
                 data = next->bios.timing_20_2c_1fc0;
         ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
 
-        ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8);
+        ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
 
         ram_wr32(fuc, 0x10f090, 0x4000007f);
         ram_nsec(fuc, 1000);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c
new file mode 100644
index 000000000000..fa891c39866b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "nv50.h"
+
+struct nouveau_oclass *
+gf117_i2c_oclass = &(struct nouveau_i2c_impl) {
+        .base.handle = NV_SUBDEV(I2C, 0xd7),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = _nouveau_i2c_ctor,
+                .dtor = _nouveau_i2c_dtor,
+                .init = _nouveau_i2c_init,
+                .fini = _nouveau_i2c_fini,
+        },
+        .sclass = nvd0_i2c_sclass,
+        .pad_x = &nv04_i2c_pad_oclass,
+        .pad_s = &nv04_i2c_pad_oclass,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c
index 7120124dceac..ebef970a0645 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c
@@ -95,6 +95,23 @@ nve0_ibus_intr(struct nouveau_subdev *subdev)
 }
 
 static int
+nve0_ibus_init(struct nouveau_object *object)
+{
+        struct nve0_ibus_priv *priv = (void *)object;
+        int ret = nouveau_ibus_init(&priv->base);
+        if (ret == 0) {
+                nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000);
+                nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200);
+                nv_mask(priv, 0x122310, 0x0003ffff, 0x00000800);
+                nv_mask(priv, 0x122348, 0x0003ffff, 0x00000100);
+                nv_mask(priv, 0x1223b0, 0x0003ffff, 0x00000fff);
+                nv_mask(priv, 0x122348, 0x0003ffff, 0x00000200);
+                nv_mask(priv, 0x122358, 0x0003ffff, 0x00002880);
+        }
+        return ret;
+}
+
+static int
 nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                struct nouveau_oclass *oclass, void *data, u32 size,
                struct nouveau_object **pobject)
@@ -117,7 +134,7 @@ nve0_ibus_oclass = {
         .ofuncs = &(struct nouveau_ofuncs) {
                 .ctor = nve0_ibus_ctor,
                 .dtor = _nouveau_ibus_dtor,
-                .init = _nouveau_ibus_init,
+                .init = nve0_ibus_init,
                 .fini = _nouveau_ibus_fini,
         },
 };
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
index 2284ecb1c9b8..c2bb616a8da5 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
@@ -83,7 +83,7 @@ host_send:
                 // increment GET
                 add b32 $r1 0x1
                 and $r14 $r1 #fifo_qmaskf
-                nv_iowr(NV_PPWR_FIFO_GET(0), $r1)
+                nv_iowr(NV_PPWR_FIFO_GET(0), $r14)
                 bra #host_send
         host_send_done:
         ret
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
index 4bd43a99fdcc..39a5dc150a05 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
@@ -1018,7 +1018,7 @@ uint32_t nv108_pwr_code[] = {
         0xb600023f,
         0x1ec40110,
         0x04b0400f,
-        0xbd0001f6,
+        0xbd000ef6,
         0xc70ef404,
 /* 0x0328: host_send_done */
 /* 0x032a: host_recv */
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
index 5a73fa620978..254205cd5166 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
@@ -1124,7 +1124,7 @@ uint32_t nva3_pwr_code[] = {
         0x0f1ec401,
         0x04b007f1,
         0xd00604b6,
-        0x04bd0001,
+        0x04bd000e,
 /* 0x03cb: host_send_done */
         0xf8ba0ef4,
 /* 0x03cd: host_recv */
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
index 4dba00d2dd1a..7ac87405d01b 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
@@ -1124,7 +1124,7 @@ uint32_t nvc0_pwr_code[] = {
         0x0f1ec401,
         0x04b007f1,
         0xd00604b6,
-        0x04bd0001,
+        0x04bd000e,
 /* 0x03cb: host_send_done */
         0xf8ba0ef4,
 /* 0x03cd: host_recv */
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
index 5e24c6bc041d..cd9ff1a73284 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
@@ -1033,7 +1033,7 @@ uint32_t nvd0_pwr_code[] = {
         0xb6026b21,
         0x1ec40110,
         0xb007f10f,
-        0x0001d004,
+        0x000ed004,
         0x0ef404bd,
 /* 0x0365: host_send_done */
 /* 0x0367: host_recv */
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 26b5647188ef..47ad74255bf1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -736,6 +736,9 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                   fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y,
                   new_bo->bo.offset };
 
+        /* Keep vblanks on during flip, for the target crtc of this flip */
+        drm_vblank_get(dev, nouveau_crtc(crtc)->index);
+
         /* Emit a page flip */
         if (nv_device(drm->device)->card_type >= NV_50) {
                 ret = nv50_display_flip_next(crtc, fb, chan, swap_interval);
@@ -779,6 +782,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
         return 0;
 
 fail_unreserve:
+        drm_vblank_put(dev, nouveau_crtc(crtc)->index);
         ttm_bo_unreserve(&old_bo->bo);
 fail_unpin:
         mutex_unlock(&chan->cli->mutex);
@@ -817,6 +821,9 @@ nouveau_finish_page_flip(struct nouveau_channel *chan,
                 drm_send_vblank_event(dev, crtcid, s->event);
         }
 
+        /* Give up ownership of vblank for page-flipped crtc */
+        drm_vblank_put(dev, s->crtc);
+
         list_del(&s->head);
         if (ps)
                 *ps = *s;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index ddd83756b9a2..5425ffe3931d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -652,12 +652,12 @@ int nouveau_pmops_resume(struct device *dev)
         ret = nouveau_do_resume(drm_dev);
         if (ret)
                 return ret;
-        if (drm_dev->mode_config.num_crtc)
-                nouveau_fbcon_set_suspend(drm_dev, 0);
 
-        nouveau_fbcon_zfill_all(drm_dev);
-        if (drm_dev->mode_config.num_crtc)
+        if (drm_dev->mode_config.num_crtc) {
                 nouveau_display_resume(drm_dev);
+                nouveau_fbcon_set_suspend(drm_dev, 0);
+        }
+
         return 0;
 }
 
@@ -683,11 +683,12 @@ static int nouveau_pmops_thaw(struct device *dev)
         ret = nouveau_do_resume(drm_dev);
         if (ret)
                 return ret;
-        if (drm_dev->mode_config.num_crtc)
-                nouveau_fbcon_set_suspend(drm_dev, 0);
-        nouveau_fbcon_zfill_all(drm_dev);
-        if (drm_dev->mode_config.num_crtc)
+
+        if (drm_dev->mode_config.num_crtc) {
                 nouveau_display_resume(drm_dev);
+                nouveau_fbcon_set_suspend(drm_dev, 0);
+        }
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 64a42cfd3717..191665ee7f52 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -531,17 +531,10 @@ nouveau_fbcon_set_suspend(struct drm_device *dev, int state)
                 if (state == 1)
                         nouveau_fbcon_save_disable_accel(dev);
                 fb_set_suspend(drm->fbcon->helper.fbdev, state);
-                if (state == 0)
+                if (state == 0) {
                         nouveau_fbcon_restore_accel(dev);
+                        nouveau_fbcon_zfill(dev, drm->fbcon);
+                }
                 console_unlock();
         }
 }
-
-void
-nouveau_fbcon_zfill_all(struct drm_device *dev)
-{
-        struct nouveau_drm *drm = nouveau_drm(dev);
-        if (drm->fbcon) {
-                nouveau_fbcon_zfill(dev, drm->fbcon);
-        }
-}
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
index fdfc0c94fbcc..fcff797d2084 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
@@ -61,7 +61,6 @@ void nouveau_fbcon_gpu_lockup(struct fb_info *info);
 int nouveau_fbcon_init(struct drm_device *dev);
 void nouveau_fbcon_fini(struct drm_device *dev);
 void nouveau_fbcon_set_suspend(struct drm_device *dev, int state);
-void nouveau_fbcon_zfill_all(struct drm_device *dev);
 void nouveau_fbcon_save_disable_accel(struct drm_device *dev);
 void nouveau_fbcon_restore_accel(struct drm_device *dev);
 
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index afdf607df3e6..4c534b7b04da 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -1741,7 +1741,8 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
                 }
         }
 
-        mthd  = (ffs(nv_encoder->dcb->sorconf.link) - 1) << 2;
+        mthd  = (ffs(nv_encoder->dcb->heads) - 1) << 3;
+        mthd |= (ffs(nv_encoder->dcb->sorconf.link) - 1) << 2;
         mthd |= nv_encoder->or;
 
         if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 26c12a3fe430..a03c73411a56 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1052,7 +1052,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
 
         /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
-        if (ASIC_IS_DCE5(rdev) && !ASIC_IS_DCE8(rdev) &&
+        if (ASIC_IS_DCE5(rdev) &&
             (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
             (radeon_crtc->bpc > 8))
                 clock = radeon_crtc->adjusted_clock;
@@ -1136,6 +1136,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
         u32 tmp, viewport_w, viewport_h;
         int r;
+        bool bypass_lut = false;
 
         /* no fb bound */
         if (!atomic && !crtc->primary->fb) {
@@ -1174,33 +1175,73 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
         radeon_bo_unreserve(rbo);
 
-        switch (target_fb->bits_per_pixel) {
-        case 8:
+        switch (target_fb->pixel_format) {
+        case DRM_FORMAT_C8:
                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
                 break;
-        case 15:
+        case DRM_FORMAT_XRGB4444:
+        case DRM_FORMAT_ARGB4444:
+                fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
+                             EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
+#ifdef __BIG_ENDIAN
+                fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
+#endif
+                break;
+        case DRM_FORMAT_XRGB1555:
+        case DRM_FORMAT_ARGB1555:
                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
+#ifdef __BIG_ENDIAN
+                fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
+#endif
+                break;
+        case DRM_FORMAT_BGRX5551:
+        case DRM_FORMAT_BGRA5551:
+                fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
+                             EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
+#ifdef __BIG_ENDIAN
+                fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
+#endif
                 break;
-        case 16:
+        case DRM_FORMAT_RGB565:
                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
 #ifdef __BIG_ENDIAN
                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
 #endif
                 break;
-        case 24:
-        case 32:
+        case DRM_FORMAT_XRGB8888:
+        case DRM_FORMAT_ARGB8888:
                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
 #ifdef __BIG_ENDIAN
                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
 #endif
                 break;
+        case DRM_FORMAT_XRGB2101010:
+        case DRM_FORMAT_ARGB2101010:
+                fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
+                             EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
+#ifdef __BIG_ENDIAN
+                fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
+#endif
+                /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
+                bypass_lut = true;
+                break;
+        case DRM_FORMAT_BGRX1010102:
+        case DRM_FORMAT_BGRA1010102:
+                fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
+                             EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
+#ifdef __BIG_ENDIAN
+                fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
+#endif
+                /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
+                bypass_lut = true;
+                break;
         default:
-                DRM_ERROR("Unsupported screen depth %d\n",
-                          target_fb->bits_per_pixel);
+                DRM_ERROR("Unsupported screen format %s\n",
+                          drm_get_format_name(target_fb->pixel_format));
                 return -EINVAL;
         }
 
@@ -1329,6 +1370,18 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
         WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
 
+        /*
+         * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
+         * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
+         * retain the full precision throughout the pipeline.
+         */
+        WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
+                 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
+                 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
+
+        if (bypass_lut)
+                DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
+
         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
@@ -1396,6 +1449,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
         u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
         u32 tmp, viewport_w, viewport_h;
         int r;
+        bool bypass_lut = false;
 
         /* no fb bound */
         if (!atomic && !crtc->primary->fb) {
@@ -1433,18 +1487,30 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
         radeon_bo_unreserve(rbo);
 
-        switch (target_fb->bits_per_pixel) {
-        case 8:
+        switch (target_fb->pixel_format) {
+        case DRM_FORMAT_C8:
                 fb_format =
                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
                 break;
-        case 15:
+        case DRM_FORMAT_XRGB4444:
+        case DRM_FORMAT_ARGB4444:
+                fb_format =
+                    AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
+                    AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
+#ifdef __BIG_ENDIAN
+                fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
+#endif
+                break;
+        case DRM_FORMAT_XRGB1555:
                 fb_format =
                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
+#ifdef __BIG_ENDIAN
+                fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
+#endif
                 break;
-        case 16:
+        case DRM_FORMAT_RGB565:
                 fb_format =
                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
@@ -1452,8 +1518,8 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
 #endif
                 break;
-        case 24:
-        case 32:
+        case DRM_FORMAT_XRGB8888:
+        case DRM_FORMAT_ARGB8888:
                 fb_format =
                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
@@ -1461,9 +1527,20 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
 #endif
                 break;
+        case DRM_FORMAT_XRGB2101010:
+        case DRM_FORMAT_ARGB2101010:
+                fb_format =
+                    AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
+                    AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
+#ifdef __BIG_ENDIAN
+                fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
+#endif
+                /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
+                bypass_lut = true;
+                break;
         default:
-                DRM_ERROR("Unsupported screen depth %d\n",
-                          target_fb->bits_per_pixel);
+                DRM_ERROR("Unsupported screen format %s\n",
+                          drm_get_format_name(target_fb->pixel_format));
                 return -EINVAL;
         }
 
@@ -1502,6 +1579,13 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
         if (rdev->family >= CHIP_R600)
                 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
 
+        /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
+        WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
+                 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
+
+        if (bypass_lut)
+                DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
+
         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index c5b1f2da3954..b1e11f8434e2 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -127,7 +127,7 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
         /* flags not zero */
         if (args.v1.ucReplyStatus == 2) {
                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
-                r = -EBUSY;
+                r = -EIO;
                 goto done;
         }
 
@@ -403,16 +403,18 @@ bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 {
         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
         u8 msg[DP_DPCD_SIZE];
-        int ret, i;
+        int ret;
+
+        char dpcd_hex_dump[DP_DPCD_SIZE * 3];
 
         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
                                DP_DPCD_SIZE);
         if (ret > 0) {
                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
-                DRM_DEBUG_KMS("DPCD: ");
-                for (i = 0; i < DP_DPCD_SIZE; i++)
-                        DRM_DEBUG_KMS("%02x ", msg[i]);
-                DRM_DEBUG_KMS("\n");
+
+                hex_dump_to_buffer(dig_connector->dpcd, sizeof(dig_connector->dpcd),
+                                   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
+                DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
 
                 radeon_dp_probe_oui(radeon_connector);
 
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 10dae4106c08..584090ac3eb9 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -1179,7 +1179,7 @@ static int ci_stop_dpm(struct radeon_device *rdev)
         tmp &= ~GLOBAL_PWRMGT_EN;
         WREG32_SMC(GENERAL_PWRMGT, tmp);
 
-        tmp = RREG32(SCLK_PWRMGT_CNTL);
+        tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
         tmp &= ~DYNAMIC_PM_EN;
         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
 
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index dcd4518a9b08..0b2471107137 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7676,14 +7676,16 @@ restart_ih:
                         addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
                         status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
                         mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
+                        /* reset addr and status */
+                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
+                        if (addr == 0x0 && status == 0x0)
+                                break;
                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                                 addr);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
                                 status);
                         cik_vm_decode_fault(rdev, status, addr, mc_client);
-                        /* reset addr and status */
-                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
                         break;
                 case 167: /* VCE */
                         DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index ae88660f34ea..0c6e1b55d968 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -1752,12 +1752,12 @@
 #define         EOP_TC_WB_ACTION_EN                     (1 << 15) /* L2 */
 #define         EOP_TCL1_ACTION_EN                      (1 << 16)
 #define         EOP_TC_ACTION_EN                        (1 << 17) /* L2 */
+#define         EOP_TCL2_VOLATILE                       (1 << 24)
 #define         EOP_CACHE_POLICY(x)                     ((x) << 25)
                 /* 0 - LRU
                  * 1 - Stream
                  * 2 - Bypass
                  */
-#define         EOP_TCL2_VOLATILE                       (1 << 27)
 #define         DATA_SEL(x)                             ((x) << 29)
                 /* 0 - discard
                  * 1 - send low 32bit data
diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c
index 5a9a5f4d7888..47d31e915758 100644
--- a/drivers/gpu/drm/radeon/cypress_dpm.c
+++ b/drivers/gpu/drm/radeon/cypress_dpm.c
@@ -1551,7 +1551,7 @@ int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,
 
                 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
                 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
-                        cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
+                        cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
         }
 
         return 0;
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e2f605224e8c..f7ece0ff431b 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -189,7 +189,7 @@ static const u32 evergreen_golden_registers[] =
         0x8c1c, 0xffffffff, 0x00001010,
         0x28350, 0xffffffff, 0x00000000,
         0xa008, 0xffffffff, 0x00010000,
-        0x5cc, 0xffffffff, 0x00000001,
+        0x5c4, 0xffffffff, 0x00000001,
         0x9508, 0xffffffff, 0x00000002,
         0x913c, 0x0000000f, 0x0000000a
 };
@@ -476,7 +476,7 @@ static const u32 cedar_golden_registers[] =
         0x8c1c, 0xffffffff, 0x00001010,
         0x28350, 0xffffffff, 0x00000000,
         0xa008, 0xffffffff, 0x00010000,
-        0x5cc, 0xffffffff, 0x00000001,
+        0x5c4, 0xffffffff, 0x00000001,
         0x9508, 0xffffffff, 0x00000002
 };
 
@@ -635,7 +635,7 @@ static const u32 juniper_mgcg_init[] =
 static const u32 supersumo_golden_registers[] =
 {
         0x5eb4, 0xffffffff, 0x00000002,
-        0x5cc, 0xffffffff, 0x00000001,
+        0x5c4, 0xffffffff, 0x00000001,
         0x7030, 0xffffffff, 0x00000011,
         0x7c30, 0xffffffff, 0x00000011,
         0x6104, 0x01000300, 0x00000000,
@@ -719,7 +719,7 @@ static const u32 sumo_golden_registers[] =
 static const u32 wrestler_golden_registers[] =
 {
         0x5eb4, 0xffffffff, 0x00000002,
-        0x5cc, 0xffffffff, 0x00000001,
+        0x5c4, 0xffffffff, 0x00000001,
         0x7030, 0xffffffff, 0x00000011,
         0x7c30, 0xffffffff, 0x00000011,
         0x6104, 0x01000300, 0x00000000,
@@ -5066,14 +5066,16 @@ restart_ih:
                 case 147:
                         addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
                         status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
+                        /* reset addr and status */
+                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
+                        if (addr == 0x0 && status == 0x0)
+                                break;
                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                                 addr);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
                                 status);
                         cayman_vm_decode_fault(rdev, status, addr);
-                        /* reset addr and status */
-                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
                         break;
                 case 176: /* CP_INT in ring buffer */
                 case 177: /* CP_INT in IB1 */
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
index a0f63ff5a5e9..333d143fca2c 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -116,6 +116,8 @@
 #       define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED      1
 #       define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1      2
 #       define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1      4
+#define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL         0x6808
+#       define EVERGREEN_LUT_10BIT_BYPASS_EN            (1 << 8)
 #define EVERGREEN_GRPH_SWAP_CONTROL                     0x680c
 #       define EVERGREEN_GRPH_ENDIAN_SWAP(x)            (((x) & 0x3) << 0)
 #       define EVERGREEN_GRPH_ENDIAN_NONE               0
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index 3f6e817d97ee..9ef8c38f2d66 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -2726,7 +2726,7 @@ int kv_dpm_init(struct radeon_device *rdev)
         pi->caps_sclk_ds = true;
         pi->enable_auto_thermal_throttling = true;
         pi->disable_nb_ps3_in_battery = false;
-        pi->bapm_enable = false;
+        pi->bapm_enable = true;
         pi->voltage_drop_t = 0;
         pi->caps_sclk_throttle_low_notification = false;
         pi->caps_fps = false; /* true? */
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 004c931606c4..01fc4888e6fe 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -1315,7 +1315,7 @@ static void ni_populate_smc_voltage_tables(struct radeon_device *rdev,
 
                 table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0;
                 table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] =
-                        cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
+                        cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
         }
 }
 
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index 1dd0d32993d5..136b7bc7cd20 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -402,6 +402,7 @@
  * block and vice versa.  This applies to GRPH, CUR, etc.
  */
 #define AVIVO_D1GRPH_LUT_SEL                                    0x6108
+#       define AVIVO_LUT_10BIT_BYPASS_EN                        (1 << 8)
 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS                    0x6110
 #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x6914
 #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x6114
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 4b0bbf88d5c0..29d9cc04c04e 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -102,6 +102,7 @@ extern int radeon_runtime_pm;
 extern int radeon_hard_reset;
 extern int radeon_vm_size;
 extern int radeon_vm_block_size;
+extern int radeon_deep_color;
 
 /*
  * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -749,10 +750,6 @@ union radeon_irq_stat_regs {
         struct cik_irq_stat_regs cik;
 };
 
-#define RADEON_MAX_HPD_PINS 7
-#define RADEON_MAX_CRTCS 6
-#define RADEON_MAX_AFMT_BLOCKS 7
-
 struct radeon_irq {
         bool                            installed;
         spinlock_t                      lock;
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 30844814c25a..173f378428a9 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1227,11 +1227,19 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
                         rdev->clock.default_dispclk =
                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
                         if (rdev->clock.default_dispclk == 0) {
-                                if (ASIC_IS_DCE5(rdev))
+                                if (ASIC_IS_DCE6(rdev))
+                                        rdev->clock.default_dispclk = 60000; /* 600 Mhz */
+                                else if (ASIC_IS_DCE5(rdev))
                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
                                 else
                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
                         }
+                        /* set a reasonable default for DP */
+                        if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
+                                DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
+                                         rdev->clock.default_dispclk / 100);
+                                rdev->clock.default_dispclk = 60000;
+                        }
                         rdev->clock.dp_extclk =
                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
                         rdev->clock.current_dispclk = rdev->clock.default_dispclk;
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 933c5c39654d..44831197e82e 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -199,6 +199,9 @@ int radeon_get_monitor_bpc(struct drm_connector *connector)
                 }
         }
 
+        if ((radeon_deep_color == 0) && (bpc > 8))
+                bpc = 8;
+
         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
                           connector->name, connector->display_info.bpc, bpc);
 
@@ -1288,17 +1291,15 @@ static int radeon_dvi_mode_valid(struct drm_connector *connector,
                     (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
                     (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
                         return MODE_OK;
-                else if (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_A) {
-                        if (ASIC_IS_DCE6(rdev)) {
-                                /* HDMI 1.3+ supports max clock of 340 Mhz */
-                                if (mode->clock > 340000)
-                                        return MODE_CLOCK_HIGH;
-                                else
-                                        return MODE_OK;
-                        } else
+                else if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) {
+                        /* HDMI 1.3+ supports max clock of 340 Mhz */
+                        if (mode->clock > 340000)
                                 return MODE_CLOCK_HIGH;
-                } else
+                        else
+                                return MODE_OK;
+                } else {
                         return MODE_CLOCK_HIGH;
+                }
         }
 
         /* check against the max pixel clock */
@@ -1549,6 +1550,8 @@ out:
 static int radeon_dp_mode_valid(struct drm_connector *connector,
                                   struct drm_display_mode *mode)
 {
+        struct drm_device *dev = connector->dev;
+        struct radeon_device *rdev = dev->dev_private;
         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
         struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
 
@@ -1579,14 +1582,23 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
                                         return MODE_PANEL;
                         }
                 }
-                return MODE_OK;
         } else {
                 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
-                    (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
+                    (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
                         return radeon_dp_mode_valid_helper(connector, mode);
-                else
-                        return MODE_OK;
+                } else {
+                        if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) {
+                                /* HDMI 1.3+ supports max clock of 340 Mhz */
+                                if (mode->clock > 340000)
+                                        return MODE_CLOCK_HIGH;
+                        } else {
+                                if (mode->clock > 165000)
+                                        return MODE_CLOCK_HIGH;
+                        }
+                }
         }
+
+        return MODE_OK;
 }
 
 static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = {
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 5ed617056b9c..13896edcf0b6 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -66,7 +66,8 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
                              (radeon_crtc->lut_b[i] << 0));
         }
 
-        WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
+        /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
+        WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
 }
 
 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
@@ -284,7 +285,6 @@ static void radeon_unpin_work_func(struct work_struct *__work)
 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
 {
         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
-        struct radeon_flip_work *work;
         unsigned long flags;
         u32 update_pending;
         int vpos, hpos;
@@ -294,8 +294,11 @@ void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
                 return;
 
         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
-        work = radeon_crtc->flip_work;
-        if (work == NULL) {
+        if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
+                DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
+                                 "RADEON_FLIP_SUBMITTED(%d)\n",
+                                 radeon_crtc->flip_status,
+                                 RADEON_FLIP_SUBMITTED);
                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
                 return;
         }
@@ -343,12 +346,17 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 
         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
         work = radeon_crtc->flip_work;
-        if (work == NULL) {
+        if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
+                DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
+                                 "RADEON_FLIP_SUBMITTED(%d)\n",
+                                 radeon_crtc->flip_status,
+                                 RADEON_FLIP_SUBMITTED);
                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
                 return;
         }
 
         /* Pageflip completed. Clean up. */
+        radeon_crtc->flip_status = RADEON_FLIP_NONE;
         radeon_crtc->flip_work = NULL;
 
         /* wakeup userspace */
@@ -357,8 +365,9 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 
         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 
+        drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
         radeon_fence_unref(&work->fence);
-        radeon_irq_kms_pflip_irq_get(rdev, work->crtc_id);
+        radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
         queue_work(radeon_crtc->flip_queue, &work->unpin_work);
 }
 
@@ -459,6 +468,12 @@ static void radeon_flip_work_func(struct work_struct *__work)
                 base &= ~7;
         }
 
+        r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
+        if (r) {
+                DRM_ERROR("failed to get vblank before flip\n");
+                goto pflip_cleanup;
+        }
+
         /* We borrow the event spin lock for protecting flip_work */
         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 
@@ -468,11 +483,22 @@ static void radeon_flip_work_func(struct work_struct *__work)
         /* do the flip (mmio) */
         radeon_page_flip(rdev, radeon_crtc->crtc_id, base);
 
+        radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
         up_read(&rdev->exclusive_lock);
 
         return;
 
+pflip_cleanup:
+        if (unlikely(radeon_bo_reserve(work->new_rbo, false) != 0)) {
+                DRM_ERROR("failed to reserve new rbo in error path\n");
+                goto cleanup;
+        }
+        if (unlikely(radeon_bo_unpin(work->new_rbo) != 0)) {
+                DRM_ERROR("failed to unpin new rbo in error path\n");
+        }
+        radeon_bo_unreserve(work->new_rbo);
+
 cleanup:
         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
         radeon_fence_unref(&work->fence);
@@ -526,7 +552,7 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
         /* We borrow the event spin lock for protecting flip_work */
         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 
-        if (radeon_crtc->flip_work) {
+        if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
                 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
@@ -534,6 +560,7 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
                 kfree(work);
                 return -EBUSY;
         }
+        radeon_crtc->flip_status = RADEON_FLIP_PENDING;
         radeon_crtc->flip_work = work;
 
         /* update crtc fb */
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 6e3017413386..cb1421369e3a 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -175,6 +175,7 @@ int radeon_runtime_pm = -1;
 int radeon_hard_reset = 0;
 int radeon_vm_size = 4096;
 int radeon_vm_block_size = 9;
+int radeon_deep_color = 0;
 
 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -248,6 +249,9 @@ module_param_named(vm_size, radeon_vm_size, int, 0444);
 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)");
 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
 
+MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
+module_param_named(deep_color, radeon_deep_color, int, 0444);
+
 static struct pci_device_id pciidlist[] = {
         radeon_PCI_IDS
 };
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index ad0e4b8cc7e3..0592ddb0904b 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -46,6 +46,10 @@ struct radeon_device;
 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
 
+#define RADEON_MAX_HPD_PINS 7
+#define RADEON_MAX_CRTCS 6
+#define RADEON_MAX_AFMT_BLOCKS 7
+
 enum radeon_rmx_type {
         RMX_OFF,
         RMX_FULL,
@@ -233,8 +237,8 @@ struct radeon_mode_info {
         struct card_info *atom_card_info;
         enum radeon_connector_table connector_table;
         bool mode_config_initialized;
-        struct radeon_crtc *crtcs[6];
-        struct radeon_afmt *afmt[7];
+        struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
+        struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
         /* DVI-I properties */
         struct drm_property *coherent_mode_property;
         /* DAC enable load detect */
@@ -302,6 +306,12 @@ struct radeon_atom_ss {
         uint16_t amount;
 };
 
+enum radeon_flip_status {
+        RADEON_FLIP_NONE,
+        RADEON_FLIP_PENDING,
+        RADEON_FLIP_SUBMITTED
+};
+
 struct radeon_crtc {
         struct drm_crtc base;
         int crtc_id;
@@ -327,6 +337,7 @@ struct radeon_crtc {
         /* page flipping */
         struct workqueue_struct *flip_queue;
         struct radeon_flip_work *flip_work;
+        enum radeon_flip_status flip_status;
         /* pll sharing */
         struct radeon_atom_ss ss;
         bool ss_enabled;
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 12c663e86ca1..e447e390d09a 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -73,8 +73,10 @@ void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
                         rdev->pm.dpm.ac_power = true;
                 else
                         rdev->pm.dpm.ac_power = false;
-                if (rdev->asic->dpm.enable_bapm)
-                        radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
+                if (rdev->family == CHIP_ARUBA) {
+                        if (rdev->asic->dpm.enable_bapm)
+                                radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
+                }
                 mutex_unlock(&rdev->pm.mutex);
         } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
index 899d9126cad6..eecff6bbd341 100644
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -495,7 +495,7 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
                 mutex_unlock(&vm->mutex);
 
                 r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
-                                     RADEON_GPU_PAGE_SIZE, false, 
+                                     RADEON_GPU_PAGE_SIZE, true,
                                      RADEON_GEM_DOMAIN_VRAM, NULL, &pt);
                 if (r)
                         return r;
@@ -992,7 +992,7 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
                 return -ENOMEM;
         }
 
-        r = radeon_bo_create(rdev, pd_size, align, false,
+        r = radeon_bo_create(rdev, pd_size, align, true,
                              RADEON_GEM_DOMAIN_VRAM, NULL,
                              &vm->page_directory);
         if (r)
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index da041a43d82e..3c76e1dcdf04 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -2329,12 +2329,6 @@ void rv770_get_engine_memory_ss(struct radeon_device *rdev)
         pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
                                                        ASIC_INTERNAL_MEMORY_SS, 0);
 
-        /* disable ss, causes hangs on some cayman boards */
-        if (rdev->family == CHIP_CAYMAN) {
-                pi->sclk_ss = false;
-                pi->mclk_ss = false;
-        }
-
         if (pi->sclk_ss || pi->mclk_ss)
                 pi->dynamic_ss = true;
         else
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 730cee2c34cf..eba0225259a4 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -6376,14 +6376,16 @@ restart_ih:
                 case 147:
                         addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
                         status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
+                        /* reset addr and status */
+                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
+                        if (addr == 0x0 && status == 0x0)
+                                break;
                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                                 addr);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
                                 status);
                         si_vm_decode_fault(rdev, status, addr);
-                        /* reset addr and status */
-                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
                         break;
                 case 176: /* RINGID0 CP_INT */
                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c
index 2a2822c03329..20da6ff183df 100644
--- a/drivers/gpu/drm/radeon/trinity_dpm.c
+++ b/drivers/gpu/drm/radeon/trinity_dpm.c
@@ -1874,7 +1874,15 @@ int trinity_dpm_init(struct radeon_device *rdev)
         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
                 pi->at[i] = TRINITY_AT_DFLT;
 
-        pi->enable_bapm = false;
+        /* There are stability issues reported on latops with
+         * bapm installed when switching between AC and battery
+         * power.  At the same time, some desktop boards hang
+         * if it's not enabled and dpm is enabled.
+         */
+        if (rdev->flags & RADEON_IS_MOBILITY)
+                pi->enable_bapm = false;
+        else
+                pi->enable_bapm = true;
         pi->enable_nbps_policy = true;
         pi->enable_sclk_ds = true;
         pi->enable_gfx_power_gating = true;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
index a89ad938eacf..b031b48dbb3c 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
@@ -179,7 +179,6 @@ static int vmw_fb_set_par(struct fb_info *info)
                 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, info->var.yoffset);
                 vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, info->var.xres);
                 vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, info->var.yres);
-                vmw_write(vmw_priv, SVGA_REG_BYTES_PER_LINE, info->fix.line_length);
                 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
         }