diff options
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 31 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 7 |
2 files changed, 27 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 722cdfc59a9a..b4999b5288e8 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -615,12 +615,20 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) | |||
615 | intel_finish_page_flip_plane(dev, 1); | 615 | intel_finish_page_flip_plane(dev, 1); |
616 | } | 616 | } |
617 | 617 | ||
618 | if (de_iir & DE_PLANEC_FLIP_DONE_IVB) { | ||
619 | intel_prepare_page_flip(dev, 2); | ||
620 | intel_finish_page_flip_plane(dev, 2); | ||
621 | } | ||
622 | |||
618 | if (de_iir & DE_PIPEA_VBLANK_IVB) | 623 | if (de_iir & DE_PIPEA_VBLANK_IVB) |
619 | drm_handle_vblank(dev, 0); | 624 | drm_handle_vblank(dev, 0); |
620 | 625 | ||
621 | if (de_iir & DE_PIPEB_VBLANK_IVB) | 626 | if (de_iir & DE_PIPEB_VBLANK_IVB) |
622 | drm_handle_vblank(dev, 1); | 627 | drm_handle_vblank(dev, 1); |
623 | 628 | ||
629 | if (de_iir & DE_PIPEC_VBLANK_IVB) | ||
630 | drm_handle_vblank(dev, 2); | ||
631 | |||
624 | /* check event from PCH */ | 632 | /* check event from PCH */ |
625 | if (de_iir & DE_PCH_EVENT_IVB) { | 633 | if (de_iir & DE_PCH_EVENT_IVB) { |
626 | if (pch_iir & SDE_HOTPLUG_MASK_CPT) | 634 | if (pch_iir & SDE_HOTPLUG_MASK_CPT) |
@@ -1418,8 +1426,8 @@ static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) | |||
1418 | return -EINVAL; | 1426 | return -EINVAL; |
1419 | 1427 | ||
1420 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | 1428 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
1421 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | 1429 | ironlake_enable_display_irq(dev_priv, |
1422 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); | 1430 | DE_PIPEA_VBLANK_IVB << (5 * pipe)); |
1423 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | 1431 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1424 | 1432 | ||
1425 | return 0; | 1433 | return 0; |
@@ -1486,8 +1494,8 @@ static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) | |||
1486 | unsigned long irqflags; | 1494 | unsigned long irqflags; |
1487 | 1495 | ||
1488 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | 1496 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
1489 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? | 1497 | ironlake_disable_display_irq(dev_priv, |
1490 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); | 1498 | DE_PIPEA_VBLANK_IVB << (pipe * 5)); |
1491 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | 1499 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1492 | } | 1500 | } |
1493 | 1501 | ||
@@ -1802,9 +1810,11 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) | |||
1802 | { | 1810 | { |
1803 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 1811 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1804 | /* enable kind of interrupts always enabled */ | 1812 | /* enable kind of interrupts always enabled */ |
1805 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | 1813 | u32 display_mask = |
1806 | DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB | | 1814 | DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | |
1807 | DE_PLANEB_FLIP_DONE_IVB; | 1815 | DE_PLANEC_FLIP_DONE_IVB | |
1816 | DE_PLANEB_FLIP_DONE_IVB | | ||
1817 | DE_PLANEA_FLIP_DONE_IVB; | ||
1808 | u32 render_irqs; | 1818 | u32 render_irqs; |
1809 | u32 hotplug_mask; | 1819 | u32 hotplug_mask; |
1810 | 1820 | ||
@@ -1813,8 +1823,11 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) | |||
1813 | /* should always can generate irq */ | 1823 | /* should always can generate irq */ |
1814 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | 1824 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
1815 | I915_WRITE(DEIMR, dev_priv->irq_mask); | 1825 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
1816 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB | | 1826 | I915_WRITE(DEIER, |
1817 | DE_PIPEB_VBLANK_IVB); | 1827 | display_mask | |
1828 | DE_PIPEC_VBLANK_IVB | | ||
1829 | DE_PIPEB_VBLANK_IVB | | ||
1830 | DE_PIPEA_VBLANK_IVB); | ||
1818 | POSTING_READ(DEIER); | 1831 | POSTING_READ(DEIER); |
1819 | 1832 | ||
1820 | dev_priv->gt_irq_mask = ~0; | 1833 | dev_priv->gt_irq_mask = ~0; |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3850b7b95167..10e71a9f8bd9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -3221,11 +3221,14 @@ | |||
3221 | #define DE_PCH_EVENT_IVB (1<<28) | 3221 | #define DE_PCH_EVENT_IVB (1<<28) |
3222 | #define DE_DP_A_HOTPLUG_IVB (1<<27) | 3222 | #define DE_DP_A_HOTPLUG_IVB (1<<27) |
3223 | #define DE_AUX_CHANNEL_A_IVB (1<<26) | 3223 | #define DE_AUX_CHANNEL_A_IVB (1<<26) |
3224 | #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) | ||
3225 | #define DE_PLANEC_FLIP_DONE_IVB (1<<13) | ||
3226 | #define DE_PIPEC_VBLANK_IVB (1<<10) | ||
3224 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) | 3227 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
3225 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) | ||
3226 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) | 3228 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
3227 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) | ||
3228 | #define DE_PIPEB_VBLANK_IVB (1<<5) | 3229 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
3230 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) | ||
3231 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) | ||
3229 | #define DE_PIPEA_VBLANK_IVB (1<<0) | 3232 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
3230 | 3233 | ||
3231 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ | 3234 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ |