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-rw-r--r--drivers/gpu/drm/drm_crtc.c3
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c16
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c45
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c11
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h32
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c80
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c19
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c118
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c17
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c2
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c167
-rw-r--r--drivers/gpu/drm/radeon/evergreen_blit_kms.c9
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h4
-rw-r--r--drivers/gpu/drm/radeon/ni.c1
-rw-r--r--drivers/gpu/drm/radeon/nid.h2
-rw-r--r--drivers/gpu/drm/radeon/r600.c1
-rw-r--r--drivers/gpu/drm/radeon/r600d.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c21
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h2
-rw-r--r--drivers/gpu/drm/radeon/rs600.c6
-rw-r--r--drivers/gpu/drm/radeon/rv770.c7
23 files changed, 349 insertions, 224 deletions
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 21058e6ad2b8..82db18506662 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -886,9 +886,6 @@ int drm_mode_group_init(struct drm_device *dev, struct drm_mode_group *group)
886 total_objects += dev->mode_config.num_connector; 886 total_objects += dev->mode_config.num_connector;
887 total_objects += dev->mode_config.num_encoder; 887 total_objects += dev->mode_config.num_encoder;
888 888
889 if (total_objects == 0)
890 return -EINVAL;
891
892 group->id_list = kzalloc(total_objects * sizeof(uint32_t), GFP_KERNEL); 889 group->id_list = kzalloc(total_objects * sizeof(uint32_t), GFP_KERNEL);
893 if (!group->id_list) 890 if (!group->id_list)
894 return -ENOMEM; 891 return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4d46441cbe2d..0a893f7400fa 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1207,13 +1207,17 @@ static int i915_context_status(struct seq_file *m, void *unused)
1207 if (ret) 1207 if (ret)
1208 return ret; 1208 return ret;
1209 1209
1210 seq_printf(m, "power context "); 1210 if (dev_priv->pwrctx) {
1211 describe_obj(m, dev_priv->pwrctx); 1211 seq_printf(m, "power context ");
1212 seq_printf(m, "\n"); 1212 describe_obj(m, dev_priv->pwrctx);
1213 seq_printf(m, "\n");
1214 }
1213 1215
1214 seq_printf(m, "render context "); 1216 if (dev_priv->renderctx) {
1215 describe_obj(m, dev_priv->renderctx); 1217 seq_printf(m, "render context ");
1216 seq_printf(m, "\n"); 1218 describe_obj(m, dev_priv->renderctx);
1219 seq_printf(m, "\n");
1220 }
1217 1221
1218 mutex_unlock(&dev->mode_config.mutex); 1222 mutex_unlock(&dev->mode_config.mutex);
1219 1223
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2b79588541e7..296fbd66f0e1 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1266,30 +1266,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
1266 1266
1267 intel_modeset_gem_init(dev); 1267 intel_modeset_gem_init(dev);
1268 1268
1269 if (IS_IVYBRIDGE(dev)) {
1270 /* Share pre & uninstall handlers with ILK/SNB */
1271 dev->driver->irq_handler = ivybridge_irq_handler;
1272 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1273 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
1274 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1275 dev->driver->enable_vblank = ivybridge_enable_vblank;
1276 dev->driver->disable_vblank = ivybridge_disable_vblank;
1277 } else if (HAS_PCH_SPLIT(dev)) {
1278 dev->driver->irq_handler = ironlake_irq_handler;
1279 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1280 dev->driver->irq_postinstall = ironlake_irq_postinstall;
1281 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1282 dev->driver->enable_vblank = ironlake_enable_vblank;
1283 dev->driver->disable_vblank = ironlake_disable_vblank;
1284 } else {
1285 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
1286 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
1287 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
1288 dev->driver->irq_handler = i915_driver_irq_handler;
1289 dev->driver->enable_vblank = i915_enable_vblank;
1290 dev->driver->disable_vblank = i915_disable_vblank;
1291 }
1292
1293 ret = drm_irq_install(dev); 1269 ret = drm_irq_install(dev);
1294 if (ret) 1270 if (ret)
1295 goto cleanup_gem; 1271 goto cleanup_gem;
@@ -1967,7 +1943,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1967 if (!dev_priv->mm.gtt) { 1943 if (!dev_priv->mm.gtt) {
1968 DRM_ERROR("Failed to initialize GTT\n"); 1944 DRM_ERROR("Failed to initialize GTT\n");
1969 ret = -ENODEV; 1945 ret = -ENODEV;
1970 goto out_iomapfree; 1946 goto out_rmmap;
1971 } 1947 }
1972 1948
1973 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; 1949 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
@@ -2011,18 +1987,13 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2011 if (dev_priv->wq == NULL) { 1987 if (dev_priv->wq == NULL) {
2012 DRM_ERROR("Failed to create our workqueue.\n"); 1988 DRM_ERROR("Failed to create our workqueue.\n");
2013 ret = -ENOMEM; 1989 ret = -ENOMEM;
2014 goto out_iomapfree; 1990 goto out_mtrrfree;
2015 } 1991 }
2016 1992
2017 /* enable GEM by default */ 1993 /* enable GEM by default */
2018 dev_priv->has_gem = 1; 1994 dev_priv->has_gem = 1;
2019 1995
2020 dev->driver->get_vblank_counter = i915_get_vblank_counter; 1996 intel_irq_init(dev);
2021 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2022 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2023 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2024 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2025 }
2026 1997
2027 /* Try to make sure MCHBAR is enabled before poking at it */ 1998 /* Try to make sure MCHBAR is enabled before poking at it */
2028 intel_setup_mchbar(dev); 1999 intel_setup_mchbar(dev);
@@ -2103,13 +2074,21 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2103 return 0; 2074 return 0;
2104 2075
2105out_gem_unload: 2076out_gem_unload:
2077 if (dev_priv->mm.inactive_shrinker.shrink)
2078 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2079
2106 if (dev->pdev->msi_enabled) 2080 if (dev->pdev->msi_enabled)
2107 pci_disable_msi(dev->pdev); 2081 pci_disable_msi(dev->pdev);
2108 2082
2109 intel_teardown_gmbus(dev); 2083 intel_teardown_gmbus(dev);
2110 intel_teardown_mchbar(dev); 2084 intel_teardown_mchbar(dev);
2111 destroy_workqueue(dev_priv->wq); 2085 destroy_workqueue(dev_priv->wq);
2112out_iomapfree: 2086out_mtrrfree:
2087 if (dev_priv->mm.gtt_mtrr >= 0) {
2088 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2089 dev->agp->agp_info.aper_size * 1024 * 1024);
2090 dev_priv->mm.gtt_mtrr = -1;
2091 }
2113 io_mapping_free(dev_priv->mm.gtt_mapping); 2092 io_mapping_free(dev_priv->mm.gtt_mapping);
2114out_rmmap: 2093out_rmmap:
2115 pci_iounmap(dev->pdev, dev_priv->regs); 2094 pci_iounmap(dev->pdev, dev_priv->regs);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 609358faaa90..eb91e2dd7914 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -52,7 +52,7 @@ module_param_named(powersave, i915_powersave, int, 0600);
52unsigned int i915_semaphores = 0; 52unsigned int i915_semaphores = 0;
53module_param_named(semaphores, i915_semaphores, int, 0600); 53module_param_named(semaphores, i915_semaphores, int, 0600);
54 54
55unsigned int i915_enable_rc6 = 1; 55unsigned int i915_enable_rc6 = 0;
56module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); 56module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
57 57
58unsigned int i915_enable_fbc = 0; 58unsigned int i915_enable_fbc = 0;
@@ -577,6 +577,7 @@ int i915_reset(struct drm_device *dev, u8 flags)
577 if (get_seconds() - dev_priv->last_gpu_reset < 5) { 577 if (get_seconds() - dev_priv->last_gpu_reset < 5) {
578 DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); 578 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
579 } else switch (INTEL_INFO(dev)->gen) { 579 } else switch (INTEL_INFO(dev)->gen) {
580 case 7:
580 case 6: 581 case 6:
581 ret = gen6_do_reset(dev, flags); 582 ret = gen6_do_reset(dev, flags);
582 /* If reset with a user forcewake, try to restore */ 583 /* If reset with a user forcewake, try to restore */
@@ -765,14 +766,6 @@ static struct drm_driver driver = {
765 .resume = i915_resume, 766 .resume = i915_resume,
766 767
767 .device_is_agp = i915_driver_device_is_agp, 768 .device_is_agp = i915_driver_device_is_agp,
768 .enable_vblank = i915_enable_vblank,
769 .disable_vblank = i915_disable_vblank,
770 .get_vblank_timestamp = i915_get_vblank_timestamp,
771 .get_scanout_position = i915_get_crtc_scanoutpos,
772 .irq_preinstall = i915_driver_irq_preinstall,
773 .irq_postinstall = i915_driver_irq_postinstall,
774 .irq_uninstall = i915_driver_irq_uninstall,
775 .irq_handler = i915_driver_irq_handler,
776 .reclaim_buffers = drm_core_reclaim_buffers, 769 .reclaim_buffers = drm_core_reclaim_buffers,
777 .master_create = i915_master_create, 770 .master_create = i915_master_create,
778 .master_destroy = i915_master_destroy, 771 .master_destroy = i915_master_destroy,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eddabf68e97a..f245c588ae95 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -997,8 +997,6 @@ extern unsigned int i915_enable_fbc;
997 997
998extern int i915_suspend(struct drm_device *dev, pm_message_t state); 998extern int i915_suspend(struct drm_device *dev, pm_message_t state);
999extern int i915_resume(struct drm_device *dev); 999extern int i915_resume(struct drm_device *dev);
1000extern void i915_save_display(struct drm_device *dev);
1001extern void i915_restore_display(struct drm_device *dev);
1002extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1000extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1003extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1001extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1004 1002
@@ -1033,33 +1031,12 @@ extern int i915_irq_emit(struct drm_device *dev, void *data,
1033extern int i915_irq_wait(struct drm_device *dev, void *data, 1031extern int i915_irq_wait(struct drm_device *dev, void *data,
1034 struct drm_file *file_priv); 1032 struct drm_file *file_priv);
1035 1033
1036extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 1034extern void intel_irq_init(struct drm_device *dev);
1037extern void i915_driver_irq_preinstall(struct drm_device * dev);
1038extern int i915_driver_irq_postinstall(struct drm_device *dev);
1039extern void i915_driver_irq_uninstall(struct drm_device * dev);
1040
1041extern irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS);
1042extern void ironlake_irq_preinstall(struct drm_device *dev);
1043extern int ironlake_irq_postinstall(struct drm_device *dev);
1044extern void ironlake_irq_uninstall(struct drm_device *dev);
1045
1046extern irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS);
1047extern void ivybridge_irq_preinstall(struct drm_device *dev);
1048extern int ivybridge_irq_postinstall(struct drm_device *dev);
1049extern void ivybridge_irq_uninstall(struct drm_device *dev);
1050 1035
1051extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1036extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1052 struct drm_file *file_priv); 1037 struct drm_file *file_priv);
1053extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1038extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1054 struct drm_file *file_priv); 1039 struct drm_file *file_priv);
1055extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1056extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1057extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
1058extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
1059extern int ivybridge_enable_vblank(struct drm_device *dev, int crtc);
1060extern void ivybridge_disable_vblank(struct drm_device *dev, int crtc);
1061extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1062extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1063extern int i915_vblank_swap(struct drm_device *dev, void *data, 1040extern int i915_vblank_swap(struct drm_device *dev, void *data,
1064 struct drm_file *file_priv); 1041 struct drm_file *file_priv);
1065 1042
@@ -1070,13 +1047,6 @@ void
1070i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1047i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1071 1048
1072void intel_enable_asle (struct drm_device *dev); 1049void intel_enable_asle (struct drm_device *dev);
1073int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1074 int *max_error,
1075 struct timeval *vblank_time,
1076 unsigned flags);
1077
1078int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1079 int *vpos, int *hpos);
1080 1050
1081#ifdef CONFIG_DEBUG_FS 1051#ifdef CONFIG_DEBUG_FS
1082extern void i915_destroy_error_state(struct drm_device *dev); 1052extern void i915_destroy_error_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ae2b49969b99..3b03f85ea627 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -152,7 +152,7 @@ i915_pipe_enabled(struct drm_device *dev, int pipe)
152/* Called from drm generic code, passed a 'crtc', which 152/* Called from drm generic code, passed a 'crtc', which
153 * we use as a pipe index 153 * we use as a pipe index
154 */ 154 */
155u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 155static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
156{ 156{
157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
158 unsigned long high_frame; 158 unsigned long high_frame;
@@ -184,7 +184,7 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
184 return (high1 << 8) | low; 184 return (high1 << 8) | low;
185} 185}
186 186
187u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 187static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
188{ 188{
189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
190 int reg = PIPE_FRMCOUNT_GM45(pipe); 190 int reg = PIPE_FRMCOUNT_GM45(pipe);
@@ -198,7 +198,7 @@ u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
198 return I915_READ(reg); 198 return I915_READ(reg);
199} 199}
200 200
201int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 201static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
202 int *vpos, int *hpos) 202 int *vpos, int *hpos)
203{ 203{
204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -264,7 +264,7 @@ int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
264 return ret; 264 return ret;
265} 265}
266 266
267int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 267static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
268 int *max_error, 268 int *max_error,
269 struct timeval *vblank_time, 269 struct timeval *vblank_time,
270 unsigned flags) 270 unsigned flags)
@@ -462,7 +462,7 @@ static void pch_irq_handler(struct drm_device *dev)
462 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 462 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
463} 463}
464 464
465irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) 465static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
466{ 466{
467 struct drm_device *dev = (struct drm_device *) arg; 467 struct drm_device *dev = (struct drm_device *) arg;
468 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 468 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -550,7 +550,7 @@ done:
550 return ret; 550 return ret;
551} 551}
552 552
553irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) 553static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
554{ 554{
555 struct drm_device *dev = (struct drm_device *) arg; 555 struct drm_device *dev = (struct drm_device *) arg;
556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1209,7 +1209,7 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1209 } 1209 }
1210} 1210}
1211 1211
1212irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 1212static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1213{ 1213{
1214 struct drm_device *dev = (struct drm_device *) arg; 1214 struct drm_device *dev = (struct drm_device *) arg;
1215 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1215 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1454,7 +1454,7 @@ int i915_irq_wait(struct drm_device *dev, void *data,
1454/* Called from drm generic code, passed 'crtc' which 1454/* Called from drm generic code, passed 'crtc' which
1455 * we use as a pipe index 1455 * we use as a pipe index
1456 */ 1456 */
1457int i915_enable_vblank(struct drm_device *dev, int pipe) 1457static int i915_enable_vblank(struct drm_device *dev, int pipe)
1458{ 1458{
1459 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1459 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1460 unsigned long irqflags; 1460 unsigned long irqflags;
@@ -1478,7 +1478,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
1478 return 0; 1478 return 0;
1479} 1479}
1480 1480
1481int ironlake_enable_vblank(struct drm_device *dev, int pipe) 1481static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1482{ 1482{
1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1484 unsigned long irqflags; 1484 unsigned long irqflags;
@@ -1494,7 +1494,7 @@ int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1494 return 0; 1494 return 0;
1495} 1495}
1496 1496
1497int ivybridge_enable_vblank(struct drm_device *dev, int pipe) 1497static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1498{ 1498{
1499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1500 unsigned long irqflags; 1500 unsigned long irqflags;
@@ -1513,7 +1513,7 @@ int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1513/* Called from drm generic code, passed 'crtc' which 1513/* Called from drm generic code, passed 'crtc' which
1514 * we use as a pipe index 1514 * we use as a pipe index
1515 */ 1515 */
1516void i915_disable_vblank(struct drm_device *dev, int pipe) 1516static void i915_disable_vblank(struct drm_device *dev, int pipe)
1517{ 1517{
1518 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1518 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1519 unsigned long irqflags; 1519 unsigned long irqflags;
@@ -1529,7 +1529,7 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
1529 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1529 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1530} 1530}
1531 1531
1532void ironlake_disable_vblank(struct drm_device *dev, int pipe) 1532static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1533{ 1533{
1534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1535 unsigned long irqflags; 1535 unsigned long irqflags;
@@ -1540,7 +1540,7 @@ void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1541} 1541}
1542 1542
1543void ivybridge_disable_vblank(struct drm_device *dev, int pipe) 1543static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1544{ 1544{
1545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1546 unsigned long irqflags; 1546 unsigned long irqflags;
@@ -1728,7 +1728,7 @@ repeat:
1728 1728
1729/* drm_dma.h hooks 1729/* drm_dma.h hooks
1730*/ 1730*/
1731void ironlake_irq_preinstall(struct drm_device *dev) 1731static void ironlake_irq_preinstall(struct drm_device *dev)
1732{ 1732{
1733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1734 1734
@@ -1740,7 +1740,7 @@ void ironlake_irq_preinstall(struct drm_device *dev)
1740 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); 1740 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1741 1741
1742 I915_WRITE(HWSTAM, 0xeffe); 1742 I915_WRITE(HWSTAM, 0xeffe);
1743 if (IS_GEN6(dev)) { 1743 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1744 /* Workaround stalls observed on Sandy Bridge GPUs by 1744 /* Workaround stalls observed on Sandy Bridge GPUs by
1745 * making the blitter command streamer generate a 1745 * making the blitter command streamer generate a
1746 * write to the Hardware Status Page for 1746 * write to the Hardware Status Page for
@@ -1769,7 +1769,7 @@ void ironlake_irq_preinstall(struct drm_device *dev)
1769 POSTING_READ(SDEIER); 1769 POSTING_READ(SDEIER);
1770} 1770}
1771 1771
1772int ironlake_irq_postinstall(struct drm_device *dev) 1772static int ironlake_irq_postinstall(struct drm_device *dev)
1773{ 1773{
1774 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1774 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1775 /* enable kind of interrupts always enabled */ 1775 /* enable kind of interrupts always enabled */
@@ -1841,7 +1841,7 @@ int ironlake_irq_postinstall(struct drm_device *dev)
1841 return 0; 1841 return 0;
1842} 1842}
1843 1843
1844int ivybridge_irq_postinstall(struct drm_device *dev) 1844static int ivybridge_irq_postinstall(struct drm_device *dev)
1845{ 1845{
1846 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1846 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1847 /* enable kind of interrupts always enabled */ 1847 /* enable kind of interrupts always enabled */
@@ -1891,7 +1891,7 @@ int ivybridge_irq_postinstall(struct drm_device *dev)
1891 return 0; 1891 return 0;
1892} 1892}
1893 1893
1894void i915_driver_irq_preinstall(struct drm_device * dev) 1894static void i915_driver_irq_preinstall(struct drm_device * dev)
1895{ 1895{
1896 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1896 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1897 int pipe; 1897 int pipe;
@@ -1918,7 +1918,7 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
1918 * Must be called after intel_modeset_init or hotplug interrupts won't be 1918 * Must be called after intel_modeset_init or hotplug interrupts won't be
1919 * enabled correctly. 1919 * enabled correctly.
1920 */ 1920 */
1921int i915_driver_irq_postinstall(struct drm_device *dev) 1921static int i915_driver_irq_postinstall(struct drm_device *dev)
1922{ 1922{
1923 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1923 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1924 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; 1924 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
@@ -1994,7 +1994,7 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
1994 return 0; 1994 return 0;
1995} 1995}
1996 1996
1997void ironlake_irq_uninstall(struct drm_device *dev) 1997static void ironlake_irq_uninstall(struct drm_device *dev)
1998{ 1998{
1999 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1999 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2000 2000
@@ -2014,7 +2014,7 @@ void ironlake_irq_uninstall(struct drm_device *dev)
2014 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2014 I915_WRITE(GTIIR, I915_READ(GTIIR));
2015} 2015}
2016 2016
2017void i915_driver_irq_uninstall(struct drm_device * dev) 2017static void i915_driver_irq_uninstall(struct drm_device * dev)
2018{ 2018{
2019 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2019 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2020 int pipe; 2020 int pipe;
@@ -2040,3 +2040,41 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
2040 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 2040 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2041 I915_WRITE(IIR, I915_READ(IIR)); 2041 I915_WRITE(IIR, I915_READ(IIR));
2042} 2042}
2043
2044void intel_irq_init(struct drm_device *dev)
2045{
2046 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2047 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2048 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2049 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2050 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2051 }
2052
2053
2054 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2055 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2056
2057 if (IS_IVYBRIDGE(dev)) {
2058 /* Share pre & uninstall handlers with ILK/SNB */
2059 dev->driver->irq_handler = ivybridge_irq_handler;
2060 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2061 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2062 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2063 dev->driver->enable_vblank = ivybridge_enable_vblank;
2064 dev->driver->disable_vblank = ivybridge_disable_vblank;
2065 } else if (HAS_PCH_SPLIT(dev)) {
2066 dev->driver->irq_handler = ironlake_irq_handler;
2067 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2068 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2069 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2070 dev->driver->enable_vblank = ironlake_enable_vblank;
2071 dev->driver->disable_vblank = ironlake_disable_vblank;
2072 } else {
2073 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2074 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2075 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2076 dev->driver->irq_handler = i915_driver_irq_handler;
2077 dev->driver->enable_vblank = i915_enable_vblank;
2078 dev->driver->disable_vblank = i915_disable_vblank;
2079 }
2080}
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index e8152d23d5b6..5257cfc34c35 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -597,7 +597,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
597 return; 597 return;
598} 598}
599 599
600void i915_save_display(struct drm_device *dev) 600static void i915_save_display(struct drm_device *dev)
601{ 601{
602 struct drm_i915_private *dev_priv = dev->dev_private; 602 struct drm_i915_private *dev_priv = dev->dev_private;
603 603
@@ -678,7 +678,6 @@ void i915_save_display(struct drm_device *dev)
678 } 678 }
679 679
680 /* VGA state */ 680 /* VGA state */
681 mutex_lock(&dev->struct_mutex);
682 dev_priv->saveVGA0 = I915_READ(VGA0); 681 dev_priv->saveVGA0 = I915_READ(VGA0);
683 dev_priv->saveVGA1 = I915_READ(VGA1); 682 dev_priv->saveVGA1 = I915_READ(VGA1);
684 dev_priv->saveVGA_PD = I915_READ(VGA_PD); 683 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
@@ -688,10 +687,9 @@ void i915_save_display(struct drm_device *dev)
688 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 687 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
689 688
690 i915_save_vga(dev); 689 i915_save_vga(dev);
691 mutex_unlock(&dev->struct_mutex);
692} 690}
693 691
694void i915_restore_display(struct drm_device *dev) 692static void i915_restore_display(struct drm_device *dev)
695{ 693{
696 struct drm_i915_private *dev_priv = dev->dev_private; 694 struct drm_i915_private *dev_priv = dev->dev_private;
697 695
@@ -783,7 +781,6 @@ void i915_restore_display(struct drm_device *dev)
783 else 781 else
784 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 782 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
785 783
786 mutex_lock(&dev->struct_mutex);
787 I915_WRITE(VGA0, dev_priv->saveVGA0); 784 I915_WRITE(VGA0, dev_priv->saveVGA0);
788 I915_WRITE(VGA1, dev_priv->saveVGA1); 785 I915_WRITE(VGA1, dev_priv->saveVGA1);
789 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 786 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
@@ -791,7 +788,6 @@ void i915_restore_display(struct drm_device *dev)
791 udelay(150); 788 udelay(150);
792 789
793 i915_restore_vga(dev); 790 i915_restore_vga(dev);
794 mutex_unlock(&dev->struct_mutex);
795} 791}
796 792
797int i915_save_state(struct drm_device *dev) 793int i915_save_state(struct drm_device *dev)
@@ -801,6 +797,8 @@ int i915_save_state(struct drm_device *dev)
801 797
802 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 798 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
803 799
800 mutex_lock(&dev->struct_mutex);
801
804 /* Hardware status page */ 802 /* Hardware status page */
805 dev_priv->saveHWS = I915_READ(HWS_PGA); 803 dev_priv->saveHWS = I915_READ(HWS_PGA);
806 804
@@ -840,6 +838,8 @@ int i915_save_state(struct drm_device *dev)
840 for (i = 0; i < 3; i++) 838 for (i = 0; i < 3; i++)
841 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); 839 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
842 840
841 mutex_unlock(&dev->struct_mutex);
842
843 return 0; 843 return 0;
844} 844}
845 845
@@ -850,6 +850,8 @@ int i915_restore_state(struct drm_device *dev)
850 850
851 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 851 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
852 852
853 mutex_lock(&dev->struct_mutex);
854
853 /* Hardware status page */ 855 /* Hardware status page */
854 I915_WRITE(HWS_PGA, dev_priv->saveHWS); 856 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
855 857
@@ -867,6 +869,7 @@ int i915_restore_state(struct drm_device *dev)
867 I915_WRITE(IER, dev_priv->saveIER); 869 I915_WRITE(IER, dev_priv->saveIER);
868 I915_WRITE(IMR, dev_priv->saveIMR); 870 I915_WRITE(IMR, dev_priv->saveIMR);
869 } 871 }
872 mutex_unlock(&dev->struct_mutex);
870 873
871 intel_init_clock_gating(dev); 874 intel_init_clock_gating(dev);
872 875
@@ -878,6 +881,8 @@ int i915_restore_state(struct drm_device *dev)
878 if (IS_GEN6(dev)) 881 if (IS_GEN6(dev))
879 gen6_enable_rps(dev_priv); 882 gen6_enable_rps(dev_priv);
880 883
884 mutex_lock(&dev->struct_mutex);
885
881 /* Cache mode state */ 886 /* Cache mode state */
882 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 887 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
883 888
@@ -891,6 +896,8 @@ int i915_restore_state(struct drm_device *dev)
891 for (i = 0; i < 3; i++) 896 for (i = 0; i < 3; i++)
892 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); 897 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
893 898
899 mutex_unlock(&dev->struct_mutex);
900
894 intel_i2c_reset(dev); 901 intel_i2c_reset(dev);
895 902
896 return 0; 903 return 0;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 391b55f1cc74..e2aced6eec4c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -50,7 +50,6 @@ struct intel_dp {
50 bool has_audio; 50 bool has_audio;
51 int force_audio; 51 int force_audio;
52 uint32_t color_range; 52 uint32_t color_range;
53 int dpms_mode;
54 uint8_t link_bw; 53 uint8_t link_bw;
55 uint8_t lane_count; 54 uint8_t lane_count;
56 uint8_t dpcd[4]; 55 uint8_t dpcd[4];
@@ -138,8 +137,8 @@ intel_dp_max_lane_count(struct intel_dp *intel_dp)
138{ 137{
139 int max_lane_count = 4; 138 int max_lane_count = 4;
140 139
141 if (intel_dp->dpcd[0] >= 0x11) { 140 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
142 max_lane_count = intel_dp->dpcd[2] & 0x1f; 141 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
143 switch (max_lane_count) { 142 switch (max_lane_count) {
144 case 1: case 2: case 4: 143 case 1: case 2: case 4:
145 break; 144 break;
@@ -153,7 +152,7 @@ intel_dp_max_lane_count(struct intel_dp *intel_dp)
153static int 152static int
154intel_dp_max_link_bw(struct intel_dp *intel_dp) 153intel_dp_max_link_bw(struct intel_dp *intel_dp)
155{ 154{
156 int max_link_bw = intel_dp->dpcd[1]; 155 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
157 156
158 switch (max_link_bw) { 157 switch (max_link_bw) {
159 case DP_LINK_BW_1_62: 158 case DP_LINK_BW_1_62:
@@ -774,7 +773,8 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
774 /* 773 /*
775 * Check for DPCD version > 1.1 and enhanced framing support 774 * Check for DPCD version > 1.1 and enhanced framing support
776 */ 775 */
777 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { 776 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
777 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
778 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 778 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
779 intel_dp->DP |= DP_ENHANCED_FRAMING; 779 intel_dp->DP |= DP_ENHANCED_FRAMING;
780 } 780 }
@@ -942,11 +942,44 @@ static void ironlake_edp_pll_off(struct drm_encoder *encoder)
942 udelay(200); 942 udelay(200);
943} 943}
944 944
945/* If the sink supports it, try to set the power state appropriately */
946static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
947{
948 int ret, i;
949
950 /* Should have a valid DPCD by this point */
951 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
952 return;
953
954 if (mode != DRM_MODE_DPMS_ON) {
955 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
956 DP_SET_POWER_D3);
957 if (ret != 1)
958 DRM_DEBUG_DRIVER("failed to write sink power state\n");
959 } else {
960 /*
961 * When turning on, we need to retry for 1ms to give the sink
962 * time to wake up.
963 */
964 for (i = 0; i < 3; i++) {
965 ret = intel_dp_aux_native_write_1(intel_dp,
966 DP_SET_POWER,
967 DP_SET_POWER_D0);
968 if (ret == 1)
969 break;
970 msleep(1);
971 }
972 }
973}
974
945static void intel_dp_prepare(struct drm_encoder *encoder) 975static void intel_dp_prepare(struct drm_encoder *encoder)
946{ 976{
947 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 977 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
948 struct drm_device *dev = encoder->dev; 978 struct drm_device *dev = encoder->dev;
949 979
980 /* Wake up the sink first */
981 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
982
950 if (is_edp(intel_dp)) { 983 if (is_edp(intel_dp)) {
951 ironlake_edp_backlight_off(dev); 984 ironlake_edp_backlight_off(dev);
952 ironlake_edp_panel_off(dev); 985 ironlake_edp_panel_off(dev);
@@ -990,6 +1023,7 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
990 if (mode != DRM_MODE_DPMS_ON) { 1023 if (mode != DRM_MODE_DPMS_ON) {
991 if (is_edp(intel_dp)) 1024 if (is_edp(intel_dp))
992 ironlake_edp_backlight_off(dev); 1025 ironlake_edp_backlight_off(dev);
1026 intel_dp_sink_dpms(intel_dp, mode);
993 intel_dp_link_down(intel_dp); 1027 intel_dp_link_down(intel_dp);
994 if (is_edp(intel_dp)) 1028 if (is_edp(intel_dp))
995 ironlake_edp_panel_off(dev); 1029 ironlake_edp_panel_off(dev);
@@ -998,6 +1032,7 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
998 } else { 1032 } else {
999 if (is_edp(intel_dp)) 1033 if (is_edp(intel_dp))
1000 ironlake_edp_panel_vdd_on(intel_dp); 1034 ironlake_edp_panel_vdd_on(intel_dp);
1035 intel_dp_sink_dpms(intel_dp, mode);
1001 if (!(dp_reg & DP_PORT_EN)) { 1036 if (!(dp_reg & DP_PORT_EN)) {
1002 intel_dp_start_link_train(intel_dp); 1037 intel_dp_start_link_train(intel_dp);
1003 if (is_edp(intel_dp)) { 1038 if (is_edp(intel_dp)) {
@@ -1009,7 +1044,31 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
1009 if (is_edp(intel_dp)) 1044 if (is_edp(intel_dp))
1010 ironlake_edp_backlight_on(dev); 1045 ironlake_edp_backlight_on(dev);
1011 } 1046 }
1012 intel_dp->dpms_mode = mode; 1047}
1048
1049/*
1050 * Native read with retry for link status and receiver capability reads for
1051 * cases where the sink may still be asleep.
1052 */
1053static bool
1054intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1055 uint8_t *recv, int recv_bytes)
1056{
1057 int ret, i;
1058
1059 /*
1060 * Sinks are *supposed* to come up within 1ms from an off state,
1061 * but we're also supposed to retry 3 times per the spec.
1062 */
1063 for (i = 0; i < 3; i++) {
1064 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1065 recv_bytes);
1066 if (ret == recv_bytes)
1067 return true;
1068 msleep(1);
1069 }
1070
1071 return false;
1013} 1072}
1014 1073
1015/* 1074/*
@@ -1019,14 +1078,10 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
1019static bool 1078static bool
1020intel_dp_get_link_status(struct intel_dp *intel_dp) 1079intel_dp_get_link_status(struct intel_dp *intel_dp)
1021{ 1080{
1022 int ret; 1081 return intel_dp_aux_native_read_retry(intel_dp,
1023 1082 DP_LANE0_1_STATUS,
1024 ret = intel_dp_aux_native_read(intel_dp, 1083 intel_dp->link_status,
1025 DP_LANE0_1_STATUS, 1084 DP_LINK_STATUS_SIZE);
1026 intel_dp->link_status, DP_LINK_STATUS_SIZE);
1027 if (ret != DP_LINK_STATUS_SIZE)
1028 return false;
1029 return true;
1030} 1085}
1031 1086
1032static uint8_t 1087static uint8_t
@@ -1515,6 +1570,8 @@ intel_dp_link_down(struct intel_dp *intel_dp)
1515static void 1570static void
1516intel_dp_check_link_status(struct intel_dp *intel_dp) 1571intel_dp_check_link_status(struct intel_dp *intel_dp)
1517{ 1572{
1573 int ret;
1574
1518 if (!intel_dp->base.base.crtc) 1575 if (!intel_dp->base.base.crtc)
1519 return; 1576 return;
1520 1577
@@ -1523,6 +1580,15 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
1523 return; 1580 return;
1524 } 1581 }
1525 1582
1583 /* Try to read receiver status if the link appears to be up */
1584 ret = intel_dp_aux_native_read(intel_dp,
1585 0x000, intel_dp->dpcd,
1586 sizeof (intel_dp->dpcd));
1587 if (ret != sizeof(intel_dp->dpcd)) {
1588 intel_dp_link_down(intel_dp);
1589 return;
1590 }
1591
1526 if (!intel_channel_eq_ok(intel_dp)) { 1592 if (!intel_channel_eq_ok(intel_dp)) {
1527 intel_dp_start_link_train(intel_dp); 1593 intel_dp_start_link_train(intel_dp);
1528 intel_dp_complete_link_train(intel_dp); 1594 intel_dp_complete_link_train(intel_dp);
@@ -1533,6 +1599,7 @@ static enum drm_connector_status
1533ironlake_dp_detect(struct intel_dp *intel_dp) 1599ironlake_dp_detect(struct intel_dp *intel_dp)
1534{ 1600{
1535 enum drm_connector_status status; 1601 enum drm_connector_status status;
1602 bool ret;
1536 1603
1537 /* Can't disconnect eDP, but you can close the lid... */ 1604 /* Can't disconnect eDP, but you can close the lid... */
1538 if (is_edp(intel_dp)) { 1605 if (is_edp(intel_dp)) {
@@ -1543,13 +1610,11 @@ ironlake_dp_detect(struct intel_dp *intel_dp)
1543 } 1610 }
1544 1611
1545 status = connector_status_disconnected; 1612 status = connector_status_disconnected;
1546 if (intel_dp_aux_native_read(intel_dp, 1613 ret = intel_dp_aux_native_read_retry(intel_dp,
1547 0x000, intel_dp->dpcd, 1614 0x000, intel_dp->dpcd,
1548 sizeof (intel_dp->dpcd)) 1615 sizeof (intel_dp->dpcd));
1549 == sizeof(intel_dp->dpcd)) { 1616 if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0)
1550 if (intel_dp->dpcd[0] != 0) 1617 status = connector_status_connected;
1551 status = connector_status_connected;
1552 }
1553 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], 1618 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1554 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); 1619 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1555 return status; 1620 return status;
@@ -1586,7 +1651,7 @@ g4x_dp_detect(struct intel_dp *intel_dp)
1586 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd, 1651 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1587 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1652 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1588 { 1653 {
1589 if (intel_dp->dpcd[0] != 0) 1654 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1590 status = connector_status_connected; 1655 status = connector_status_connected;
1591 } 1656 }
1592 1657
@@ -1790,8 +1855,7 @@ intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1790{ 1855{
1791 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 1856 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1792 1857
1793 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) 1858 intel_dp_check_link_status(intel_dp);
1794 intel_dp_check_link_status(intel_dp);
1795} 1859}
1796 1860
1797/* Return which DP Port should be selected for Transcoder DP control */ 1861/* Return which DP Port should be selected for Transcoder DP control */
@@ -1859,7 +1923,6 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1859 return; 1923 return;
1860 1924
1861 intel_dp->output_reg = output_reg; 1925 intel_dp->output_reg = output_reg;
1862 intel_dp->dpms_mode = -1;
1863 1926
1864 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1927 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1865 if (!intel_connector) { 1928 if (!intel_connector) {
@@ -1954,8 +2017,9 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1954 sizeof(intel_dp->dpcd)); 2017 sizeof(intel_dp->dpcd));
1955 ironlake_edp_panel_vdd_off(intel_dp); 2018 ironlake_edp_panel_vdd_off(intel_dp);
1956 if (ret == sizeof(intel_dp->dpcd)) { 2019 if (ret == sizeof(intel_dp->dpcd)) {
1957 if (intel_dp->dpcd[0] >= 0x11) 2020 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
1958 dev_priv->no_aux_handshake = intel_dp->dpcd[3] & 2021 dev_priv->no_aux_handshake =
2022 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
1959 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 2023 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1960 } else { 2024 } else {
1961 /* if this fails, presume the device is a ghost */ 2025 /* if this fails, presume the device is a ghost */
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 56a8e2aea19c..9e2959bc91cd 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1409,6 +1409,11 @@ void intel_setup_overlay(struct drm_device *dev)
1409 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL); 1409 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1410 if (!overlay) 1410 if (!overlay)
1411 return; 1411 return;
1412
1413 mutex_lock(&dev->struct_mutex);
1414 if (WARN_ON(dev_priv->overlay))
1415 goto out_free;
1416
1412 overlay->dev = dev; 1417 overlay->dev = dev;
1413 1418
1414 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE); 1419 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
@@ -1416,8 +1421,6 @@ void intel_setup_overlay(struct drm_device *dev)
1416 goto out_free; 1421 goto out_free;
1417 overlay->reg_bo = reg_bo; 1422 overlay->reg_bo = reg_bo;
1418 1423
1419 mutex_lock(&dev->struct_mutex);
1420
1421 if (OVERLAY_NEEDS_PHYSICAL(dev)) { 1424 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1422 ret = i915_gem_attach_phys_object(dev, reg_bo, 1425 ret = i915_gem_attach_phys_object(dev, reg_bo,
1423 I915_GEM_PHYS_OVERLAY_REGS, 1426 I915_GEM_PHYS_OVERLAY_REGS,
@@ -1442,8 +1445,6 @@ void intel_setup_overlay(struct drm_device *dev)
1442 } 1445 }
1443 } 1446 }
1444 1447
1445 mutex_unlock(&dev->struct_mutex);
1446
1447 /* init all values */ 1448 /* init all values */
1448 overlay->color_key = 0x0101fe; 1449 overlay->color_key = 0x0101fe;
1449 overlay->brightness = -19; 1450 overlay->brightness = -19;
@@ -1452,7 +1453,7 @@ void intel_setup_overlay(struct drm_device *dev)
1452 1453
1453 regs = intel_overlay_map_regs(overlay); 1454 regs = intel_overlay_map_regs(overlay);
1454 if (!regs) 1455 if (!regs)
1455 goto out_free_bo; 1456 goto out_unpin_bo;
1456 1457
1457 memset(regs, 0, sizeof(struct overlay_registers)); 1458 memset(regs, 0, sizeof(struct overlay_registers));
1458 update_polyphase_filter(regs); 1459 update_polyphase_filter(regs);
@@ -1461,15 +1462,17 @@ void intel_setup_overlay(struct drm_device *dev)
1461 intel_overlay_unmap_regs(overlay, regs); 1462 intel_overlay_unmap_regs(overlay, regs);
1462 1463
1463 dev_priv->overlay = overlay; 1464 dev_priv->overlay = overlay;
1465 mutex_unlock(&dev->struct_mutex);
1464 DRM_INFO("initialized overlay support\n"); 1466 DRM_INFO("initialized overlay support\n");
1465 return; 1467 return;
1466 1468
1467out_unpin_bo: 1469out_unpin_bo:
1468 i915_gem_object_unpin(reg_bo); 1470 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1471 i915_gem_object_unpin(reg_bo);
1469out_free_bo: 1472out_free_bo:
1470 drm_gem_object_unreference(&reg_bo->base); 1473 drm_gem_object_unreference(&reg_bo->base);
1471 mutex_unlock(&dev->struct_mutex);
1472out_free: 1474out_free:
1475 mutex_unlock(&dev->struct_mutex);
1473 kfree(overlay); 1476 kfree(overlay);
1474 return; 1477 return;
1475} 1478}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c0e0ee63fbf4..39ac2b634ae5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -165,7 +165,7 @@ void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
165int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); 165int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
166static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring) 166static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring)
167{ 167{
168 return intel_wait_ring_buffer(ring, ring->space - 8); 168 return intel_wait_ring_buffer(ring, ring->size - 8);
169} 169}
170 170
171int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); 171int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 144f79a350ae..731acea865b5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -371,7 +371,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
371 engine->vram.flags_valid = nv50_vram_flags_valid; 371 engine->vram.flags_valid = nv50_vram_flags_valid;
372 break; 372 break;
373 case 0xC0: 373 case 0xC0:
374 case 0xD0:
375 engine->instmem.init = nvc0_instmem_init; 374 engine->instmem.init = nvc0_instmem_init;
376 engine->instmem.takedown = nvc0_instmem_takedown; 375 engine->instmem.takedown = nvc0_instmem_takedown;
377 engine->instmem.suspend = nvc0_instmem_suspend; 376 engine->instmem.suspend = nvc0_instmem_suspend;
@@ -923,7 +922,6 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
923 dev_priv->card_type = NV_50; 922 dev_priv->card_type = NV_50;
924 break; 923 break;
925 case 0xc0: 924 case 0xc0:
926 case 0xd0:
927 dev_priv->card_type = NV_C0; 925 dev_priv->card_type = NV_C0;
928 break; 926 break;
929 default: 927 default:
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 12d2fdc52414..15bd0477a3e8 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -985,17 +985,19 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
985{ 985{
986 save->vga_control[0] = RREG32(D1VGA_CONTROL); 986 save->vga_control[0] = RREG32(D1VGA_CONTROL);
987 save->vga_control[1] = RREG32(D2VGA_CONTROL); 987 save->vga_control[1] = RREG32(D2VGA_CONTROL);
988 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
989 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
990 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
991 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
992 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 988 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
993 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 989 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
994 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 990 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
995 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 991 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
996 if (!(rdev->flags & RADEON_IS_IGP)) { 992 if (rdev->num_crtc >= 4) {
993 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
994 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
997 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 995 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
998 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 996 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
997 }
998 if (rdev->num_crtc >= 6) {
999 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1000 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
999 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 1001 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1000 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 1002 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1001 } 1003 }
@@ -1004,35 +1006,45 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
1004 WREG32(VGA_RENDER_CONTROL, 0); 1006 WREG32(VGA_RENDER_CONTROL, 0);
1005 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1007 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1006 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1007 if (!(rdev->flags & RADEON_IS_IGP)) { 1009 if (rdev->num_crtc >= 4) {
1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1010 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1009 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1011 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1012 }
1013 if (rdev->num_crtc >= 6) {
1010 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1014 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1011 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1012 } 1016 }
1013 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1017 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1014 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1018 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1015 if (!(rdev->flags & RADEON_IS_IGP)) { 1019 if (rdev->num_crtc >= 4) {
1016 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1020 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1017 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1021 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1022 }
1023 if (rdev->num_crtc >= 6) {
1018 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1024 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1019 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1025 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1020 } 1026 }
1021 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1027 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1022 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1028 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1023 if (!(rdev->flags & RADEON_IS_IGP)) { 1029 if (rdev->num_crtc >= 4) {
1024 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1030 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1025 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1031 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1032 }
1033 if (rdev->num_crtc >= 6) {
1026 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1034 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1027 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1035 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1028 } 1036 }
1029 1037
1030 WREG32(D1VGA_CONTROL, 0); 1038 WREG32(D1VGA_CONTROL, 0);
1031 WREG32(D2VGA_CONTROL, 0); 1039 WREG32(D2VGA_CONTROL, 0);
1032 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1040 if (rdev->num_crtc >= 4) {
1033 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1041 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1034 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1042 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1035 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1043 }
1044 if (rdev->num_crtc >= 6) {
1045 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1046 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1047 }
1036} 1048}
1037 1049
1038void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) 1050void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
@@ -1055,7 +1067,7 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1055 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1067 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1056 (u32)rdev->mc.vram_start); 1068 (u32)rdev->mc.vram_start);
1057 1069
1058 if (!(rdev->flags & RADEON_IS_IGP)) { 1070 if (rdev->num_crtc >= 4) {
1059 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1071 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1060 upper_32_bits(rdev->mc.vram_start)); 1072 upper_32_bits(rdev->mc.vram_start));
1061 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1073 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
@@ -1073,7 +1085,8 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1073 (u32)rdev->mc.vram_start); 1085 (u32)rdev->mc.vram_start);
1074 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1086 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1075 (u32)rdev->mc.vram_start); 1087 (u32)rdev->mc.vram_start);
1076 1088 }
1089 if (rdev->num_crtc >= 6) {
1077 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1090 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1078 upper_32_bits(rdev->mc.vram_start)); 1091 upper_32_bits(rdev->mc.vram_start));
1079 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1092 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
@@ -1101,31 +1114,41 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1101 /* Restore video state */ 1114 /* Restore video state */
1102 WREG32(D1VGA_CONTROL, save->vga_control[0]); 1115 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1103 WREG32(D2VGA_CONTROL, save->vga_control[1]); 1116 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1104 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); 1117 if (rdev->num_crtc >= 4) {
1105 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); 1118 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1106 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); 1119 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1107 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); 1120 }
1121 if (rdev->num_crtc >= 6) {
1122 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1123 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1124 }
1108 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1125 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1109 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1126 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1110 if (!(rdev->flags & RADEON_IS_IGP)) { 1127 if (rdev->num_crtc >= 4) {
1111 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1128 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1112 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1129 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1130 }
1131 if (rdev->num_crtc >= 6) {
1113 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1132 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1114 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1133 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1115 } 1134 }
1116 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); 1135 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1117 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); 1136 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1118 if (!(rdev->flags & RADEON_IS_IGP)) { 1137 if (rdev->num_crtc >= 4) {
1119 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); 1138 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1120 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); 1139 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1140 }
1141 if (rdev->num_crtc >= 6) {
1121 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); 1142 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1122 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); 1143 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1123 } 1144 }
1124 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1145 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1125 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1146 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1126 if (!(rdev->flags & RADEON_IS_IGP)) { 1147 if (rdev->num_crtc >= 4) {
1127 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1148 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1128 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1149 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1150 }
1151 if (rdev->num_crtc >= 6) {
1129 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1152 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1130 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1153 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1131 } 1154 }
@@ -1977,7 +2000,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1977 gb_backend_map = 0x66442200; 2000 gb_backend_map = 0x66442200;
1978 break; 2001 break;
1979 case CHIP_JUNIPER: 2002 case CHIP_JUNIPER:
1980 gb_backend_map = 0x00006420; 2003 gb_backend_map = 0x00002200;
1981 break; 2004 break;
1982 default: 2005 default:
1983 gb_backend_map = 2006 gb_backend_map =
@@ -2248,7 +2271,10 @@ int evergreen_mc_init(struct radeon_device *rdev)
2248 2271
2249 /* Get VRAM informations */ 2272 /* Get VRAM informations */
2250 rdev->mc.vram_is_ddr = true; 2273 rdev->mc.vram_is_ddr = true;
2251 tmp = RREG32(MC_ARB_RAMCFG); 2274 if (rdev->flags & RADEON_IS_IGP)
2275 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2276 else
2277 tmp = RREG32(MC_ARB_RAMCFG);
2252 if (tmp & CHANSIZE_OVERRIDE) { 2278 if (tmp & CHANSIZE_OVERRIDE) {
2253 chansize = 16; 2279 chansize = 16;
2254 } else if (tmp & CHANSIZE_MASK) { 2280 } else if (tmp & CHANSIZE_MASK) {
@@ -2414,18 +2440,22 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2414 WREG32(GRBM_INT_CNTL, 0); 2440 WREG32(GRBM_INT_CNTL, 0);
2415 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2441 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2416 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2442 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2417 if (!(rdev->flags & RADEON_IS_IGP)) { 2443 if (rdev->num_crtc >= 4) {
2418 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2444 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2419 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2445 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2446 }
2447 if (rdev->num_crtc >= 6) {
2420 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2448 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2421 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2449 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2422 } 2450 }
2423 2451
2424 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2452 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2425 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2453 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2426 if (!(rdev->flags & RADEON_IS_IGP)) { 2454 if (rdev->num_crtc >= 4) {
2427 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2455 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2428 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2456 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2457 }
2458 if (rdev->num_crtc >= 6) {
2429 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2459 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2430 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2460 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2431 } 2461 }
@@ -2544,19 +2574,25 @@ int evergreen_irq_set(struct radeon_device *rdev)
2544 2574
2545 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2575 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2546 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2576 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2547 if (!(rdev->flags & RADEON_IS_IGP)) { 2577 if (rdev->num_crtc >= 4) {
2548 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2578 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2549 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 2579 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2580 }
2581 if (rdev->num_crtc >= 6) {
2550 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 2582 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2551 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 2583 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2552 } 2584 }
2553 2585
2554 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 2586 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2555 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 2587 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2556 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 2588 if (rdev->num_crtc >= 4) {
2557 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 2589 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2558 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 2590 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2559 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 2591 }
2592 if (rdev->num_crtc >= 6) {
2593 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2594 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2595 }
2560 2596
2561 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2597 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2562 WREG32(DC_HPD2_INT_CONTROL, hpd2); 2598 WREG32(DC_HPD2_INT_CONTROL, hpd2);
@@ -2580,53 +2616,57 @@ static inline void evergreen_irq_ack(struct radeon_device *rdev)
2580 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 2616 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2581 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 2617 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2582 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 2618 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2583 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2619 if (rdev->num_crtc >= 4) {
2584 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2620 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2585 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2621 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2586 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2622 }
2623 if (rdev->num_crtc >= 6) {
2624 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2625 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2626 }
2587 2627
2588 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 2628 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2589 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2629 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2590 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 2630 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2591 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2631 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2592 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2593 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2594 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2595 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2596 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2597 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2598 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2599 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2600
2601 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 2632 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2602 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 2633 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2603 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 2634 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2604 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 2635 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2605
2606 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 2636 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2607 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 2637 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2608 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 2638 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2609 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 2639 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2610 2640
2611 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 2641 if (rdev->num_crtc >= 4) {
2612 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 2642 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2613 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 2643 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2614 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 2644 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2615 2645 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2616 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 2646 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2617 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 2647 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2618 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 2648 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2619 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 2649 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2620 2650 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2621 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 2651 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2622 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 2652 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2623 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 2653 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2624 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 2654 }
2625 2655
2626 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 2656 if (rdev->num_crtc >= 6) {
2627 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 2657 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2628 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 2658 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2629 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 2659 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2660 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2661 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2662 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2663 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2664 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2665 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2666 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2667 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2668 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2669 }
2630 2670
2631 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2671 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2632 tmp = RREG32(DC_HPD1_INT_CONTROL); 2672 tmp = RREG32(DC_HPD1_INT_CONTROL);
@@ -3234,6 +3274,7 @@ void evergreen_fini(struct radeon_device *rdev)
3234 r700_cp_fini(rdev); 3274 r700_cp_fini(rdev);
3235 r600_irq_fini(rdev); 3275 r600_irq_fini(rdev);
3236 radeon_wb_fini(rdev); 3276 radeon_wb_fini(rdev);
3277 radeon_ib_pool_fini(rdev);
3237 radeon_irq_kms_fini(rdev); 3278 radeon_irq_kms_fini(rdev);
3238 evergreen_pcie_gart_fini(rdev); 3279 evergreen_pcie_gart_fini(rdev);
3239 radeon_gem_fini(rdev); 3280 radeon_gem_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index 57f3bc17b87e..2eb251858e72 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -252,7 +252,7 @@ draw_auto(struct radeon_device *rdev)
252 252
253} 253}
254 254
255/* emits 36 */ 255/* emits 39 */
256static void 256static void
257set_default_state(struct radeon_device *rdev) 257set_default_state(struct radeon_device *rdev)
258{ 258{
@@ -531,6 +531,11 @@ set_default_state(struct radeon_device *rdev)
531 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); 531 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
532 radeon_ring_write(rdev, 0); 532 radeon_ring_write(rdev, 0);
533 533
534 /* setup LDS */
535 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
536 radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
537 radeon_ring_write(rdev, 0x10001000);
538
534 /* SQ config */ 539 /* SQ config */
535 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11)); 540 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
536 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); 541 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
@@ -773,7 +778,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
773 /* calculate number of loops correctly */ 778 /* calculate number of loops correctly */
774 ring_size = num_loops * dwords_per_loop; 779 ring_size = num_loops * dwords_per_loop;
775 /* set default + shaders */ 780 /* set default + shaders */
776 ring_size += 52; /* shaders + def state */ 781 ring_size += 55; /* shaders + def state */
777 ring_size += 10; /* fence emit for VB IB */ 782 ring_size += 10; /* fence emit for VB IB */
778 ring_size += 5; /* done copy */ 783 ring_size += 5; /* done copy */
779 ring_size += 10; /* fence emit for done copy */ 784 ring_size += 10; /* fence emit for done copy */
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 1636e3449825..b7b2714f0b32 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -466,7 +466,7 @@
466#define IH_RB_WPTR_ADDR_LO 0x3e14 466#define IH_RB_WPTR_ADDR_LO 0x3e14
467#define IH_CNTL 0x3e18 467#define IH_CNTL 0x3e18
468# define ENABLE_INTR (1 << 0) 468# define ENABLE_INTR (1 << 0)
469# define IH_MC_SWAP(x) ((x) << 2) 469# define IH_MC_SWAP(x) ((x) << 1)
470# define IH_MC_SWAP_NONE 0 470# define IH_MC_SWAP_NONE 0
471# define IH_MC_SWAP_16BIT 1 471# define IH_MC_SWAP_16BIT 1
472# define IH_MC_SWAP_32BIT 2 472# define IH_MC_SWAP_32BIT 2
@@ -547,7 +547,7 @@
547# define LB_D5_VBLANK_INTERRUPT (1 << 3) 547# define LB_D5_VBLANK_INTERRUPT (1 << 3)
548# define DC_HPD5_INTERRUPT (1 << 17) 548# define DC_HPD5_INTERRUPT (1 << 17)
549# define DC_HPD5_RX_INTERRUPT (1 << 18) 549# define DC_HPD5_RX_INTERRUPT (1 << 18)
550#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050 550#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
551# define LB_D6_VLINE_INTERRUPT (1 << 2) 551# define LB_D6_VLINE_INTERRUPT (1 << 2)
552# define LB_D6_VBLANK_INTERRUPT (1 << 3) 552# define LB_D6_VBLANK_INTERRUPT (1 << 3)
553# define DC_HPD6_INTERRUPT (1 << 17) 553# define DC_HPD6_INTERRUPT (1 << 17)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 16caafeadf5e..559dbd412906 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1581,6 +1581,7 @@ void cayman_fini(struct radeon_device *rdev)
1581 cayman_cp_fini(rdev); 1581 cayman_cp_fini(rdev);
1582 r600_irq_fini(rdev); 1582 r600_irq_fini(rdev);
1583 radeon_wb_fini(rdev); 1583 radeon_wb_fini(rdev);
1584 radeon_ib_pool_fini(rdev);
1584 radeon_irq_kms_fini(rdev); 1585 radeon_irq_kms_fini(rdev);
1585 cayman_pcie_gart_fini(rdev); 1586 cayman_pcie_gart_fini(rdev);
1586 radeon_gem_fini(rdev); 1587 radeon_gem_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 9736746da2d6..4672869cdb26 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -320,7 +320,7 @@
320#define CGTS_USER_TCC_DISABLE 0x914C 320#define CGTS_USER_TCC_DISABLE 0x914C
321#define TCC_DISABLE_MASK 0xFFFF0000 321#define TCC_DISABLE_MASK 0xFFFF0000
322#define TCC_DISABLE_SHIFT 16 322#define TCC_DISABLE_SHIFT 16
323#define CGTS_SM_CTRL_REG 0x915C 323#define CGTS_SM_CTRL_REG 0x9150
324#define OVERRIDE (1 << 21) 324#define OVERRIDE (1 << 21)
325 325
326#define TA_CNTL_AUX 0x9508 326#define TA_CNTL_AUX 0x9508
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index f79d2ccb6755..bc54b26cb32f 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2628,6 +2628,7 @@ void r600_fini(struct radeon_device *rdev)
2628 r600_cp_fini(rdev); 2628 r600_cp_fini(rdev);
2629 r600_irq_fini(rdev); 2629 r600_irq_fini(rdev);
2630 radeon_wb_fini(rdev); 2630 radeon_wb_fini(rdev);
2631 radeon_ib_pool_fini(rdev);
2631 radeon_irq_kms_fini(rdev); 2632 radeon_irq_kms_fini(rdev);
2632 r600_pcie_gart_fini(rdev); 2633 r600_pcie_gart_fini(rdev);
2633 radeon_agp_fini(rdev); 2634 radeon_agp_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index f140a0d5cb54..0245ae6c204e 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -536,7 +536,7 @@
536#define IH_RB_WPTR_ADDR_LO 0x3e14 536#define IH_RB_WPTR_ADDR_LO 0x3e14
537#define IH_CNTL 0x3e18 537#define IH_CNTL 0x3e18
538# define ENABLE_INTR (1 << 0) 538# define ENABLE_INTR (1 << 0)
539# define IH_MC_SWAP(x) ((x) << 2) 539# define IH_MC_SWAP(x) ((x) << 1)
540# define IH_MC_SWAP_NONE 0 540# define IH_MC_SWAP_NONE 0
541# define IH_MC_SWAP_16BIT 1 541# define IH_MC_SWAP_16BIT 1
542# define IH_MC_SWAP_32BIT 2 542# define IH_MC_SWAP_32BIT 2
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 3fc5fa1aefd0..229a20f10e2b 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -331,7 +331,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
331 331
332 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 332 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
333 viph_control = RREG32(RADEON_VIPH_CONTROL); 333 viph_control = RREG32(RADEON_VIPH_CONTROL);
334 bus_cntl = RREG32(RADEON_BUS_CNTL); 334 bus_cntl = RREG32(RV370_BUS_CNTL);
335 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 335 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
336 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 336 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
337 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 337 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
@@ -350,7 +350,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
350 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 350 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
351 351
352 /* enable the rom */ 352 /* enable the rom */
353 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 353 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
354 354
355 /* Disable VGA mode */ 355 /* Disable VGA mode */
356 WREG32(AVIVO_D1VGA_CONTROL, 356 WREG32(AVIVO_D1VGA_CONTROL,
@@ -367,7 +367,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
367 /* restore regs */ 367 /* restore regs */
368 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 368 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
369 WREG32(RADEON_VIPH_CONTROL, viph_control); 369 WREG32(RADEON_VIPH_CONTROL, viph_control);
370 WREG32(RADEON_BUS_CNTL, bus_cntl); 370 WREG32(RV370_BUS_CNTL, bus_cntl);
371 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 371 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
372 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 372 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
373 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 373 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
@@ -390,7 +390,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
390 390
391 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 391 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
392 viph_control = RREG32(RADEON_VIPH_CONTROL); 392 viph_control = RREG32(RADEON_VIPH_CONTROL);
393 bus_cntl = RREG32(RADEON_BUS_CNTL); 393 if (rdev->flags & RADEON_IS_PCIE)
394 bus_cntl = RREG32(RV370_BUS_CNTL);
395 else
396 bus_cntl = RREG32(RADEON_BUS_CNTL);
394 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 397 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
395 crtc2_gen_cntl = 0; 398 crtc2_gen_cntl = 0;
396 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 399 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
@@ -412,7 +415,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
412 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 415 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
413 416
414 /* enable the rom */ 417 /* enable the rom */
415 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 418 if (rdev->flags & RADEON_IS_PCIE)
419 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
420 else
421 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
416 422
417 /* Turn off mem requests and CRTC for both controllers */ 423 /* Turn off mem requests and CRTC for both controllers */
418 WREG32(RADEON_CRTC_GEN_CNTL, 424 WREG32(RADEON_CRTC_GEN_CNTL,
@@ -439,7 +445,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
439 /* restore regs */ 445 /* restore regs */
440 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 446 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
441 WREG32(RADEON_VIPH_CONTROL, viph_control); 447 WREG32(RADEON_VIPH_CONTROL, viph_control);
442 WREG32(RADEON_BUS_CNTL, bus_cntl); 448 if (rdev->flags & RADEON_IS_PCIE)
449 WREG32(RV370_BUS_CNTL, bus_cntl);
450 else
451 WREG32(RADEON_BUS_CNTL, bus_cntl);
443 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 452 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
444 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 453 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
445 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 454 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index cbfca3a24fdf..9792d4ffdc86 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -52,6 +52,12 @@ void radeon_connector_hotplug(struct drm_connector *connector)
52 struct radeon_device *rdev = dev->dev_private; 52 struct radeon_device *rdev = dev->dev_private;
53 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 53 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
54 54
55 /* bail if the connector does not have hpd pin, e.g.,
56 * VGA, TV, etc.
57 */
58 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE)
59 return;
60
55 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 61 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
56 62
57 /* powering up/down the eDP panel generates hpd events which 63 /* powering up/down the eDP panel generates hpd events which
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index ec93a75369e6..bc44a3d35ec6 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -300,6 +300,8 @@
300# define RADEON_BUS_READ_BURST (1 << 30) 300# define RADEON_BUS_READ_BURST (1 << 30)
301#define RADEON_BUS_CNTL1 0x0034 301#define RADEON_BUS_CNTL1 0x0034
302# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) 302# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
303#define RV370_BUS_CNTL 0x004c
304# define RV370_BUS_BIOS_DIS_ROM (1 << 2)
303/* rv370/rv380, rv410, r423/r430/r480, r5xx */ 305/* rv370/rv380, rv410, r423/r430/r480, r5xx */
304#define RADEON_MSI_REARM_EN 0x0160 306#define RADEON_MSI_REARM_EN 0x0160
305# define RV370_MSI_REARM_EN (1 << 0) 307# define RV370_MSI_REARM_EN (1 << 0)
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 6e3b11e5abbe..1f5850e473cc 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -426,7 +426,7 @@ int rs600_gart_init(struct radeon_device *rdev)
426 return radeon_gart_table_vram_alloc(rdev); 426 return radeon_gart_table_vram_alloc(rdev);
427} 427}
428 428
429int rs600_gart_enable(struct radeon_device *rdev) 429static int rs600_gart_enable(struct radeon_device *rdev)
430{ 430{
431 u32 tmp; 431 u32 tmp;
432 int r, i; 432 int r, i;
@@ -440,8 +440,8 @@ int rs600_gart_enable(struct radeon_device *rdev)
440 return r; 440 return r;
441 radeon_gart_restore(rdev); 441 radeon_gart_restore(rdev);
442 /* Enable bus master */ 442 /* Enable bus master */
443 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; 443 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
444 WREG32(R_00004C_BUS_CNTL, tmp); 444 WREG32(RADEON_BUS_CNTL, tmp);
445 /* FIXME: setup default page */ 445 /* FIXME: setup default page */
446 WREG32_MC(R_000100_MC_PT0_CNTL, 446 WREG32_MC(R_000100_MC_PT0_CNTL,
447 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 447 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 6f508ffd1035..4de51891aa6d 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -575,6 +575,12 @@ static void rv770_program_channel_remap(struct radeon_device *rdev)
575 else 575 else
576 tcp_chan_steer = 0x00fac688; 576 tcp_chan_steer = 0x00fac688;
577 577
578 /* RV770 CE has special chremap setup */
579 if (rdev->pdev->device == 0x944e) {
580 tcp_chan_steer = 0x00b08b08;
581 mc_shared_chremap = 0x00b08b08;
582 }
583
578 WREG32(TCP_CHAN_STEER, tcp_chan_steer); 584 WREG32(TCP_CHAN_STEER, tcp_chan_steer);
579 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); 585 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
580} 586}
@@ -1362,6 +1368,7 @@ void rv770_fini(struct radeon_device *rdev)
1362 r700_cp_fini(rdev); 1368 r700_cp_fini(rdev);
1363 r600_irq_fini(rdev); 1369 r600_irq_fini(rdev);
1364 radeon_wb_fini(rdev); 1370 radeon_wb_fini(rdev);
1371 radeon_ib_pool_fini(rdev);
1365 radeon_irq_kms_fini(rdev); 1372 radeon_irq_kms_fini(rdev);
1366 rv770_pcie_gart_fini(rdev); 1373 rv770_pcie_gart_fini(rdev);
1367 rv770_vram_scratch_fini(rdev); 1374 rv770_vram_scratch_fini(rdev);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 04:04:14 -0500